projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: reorganize display callbacks
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44{
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48}
49
50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51{
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55}
56
57static void radeon_register_accessor_init(struct radeon_device *rdev)
58{
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
b4df8be1 97 if (rdev->family >= CHIP_R600) {
0a10c851
DV		 98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101}
102
103
104/* helper to disable agp */
105void radeon_agp_disable(struct radeon_device *rdev)
106{
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 117 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 122 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126}
127
128/*
129 * ASIC
130 */
48e7a5f1
DV		 131static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
225758d8 137 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 138 .asic_reset = &r100_asic_reset,
c5b3b850
AD		 139 .gart = {
140 .tlb_flush = &r100_pci_gart_tlb_flush,
141 .set_page = &r100_pci_gart_set_page,
142 },
4c87bc26
CK		 143 .ring = {
144 [RADEON_RING_TYPE_GFX_INDEX] = {
145 .ib_execute = &r100_ring_ib_execute,
146 .emit_fence = &r100_fence_ring_emit,
147 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 148 .cs_parse = &r100_cs_parse,
f712812e
AD		 149 .ring_start = &r100_ring_start,
150 .ring_test = &r100_ring_test,
151 .ib_test = &r100_ib_test,
4c87bc26
CK		 152 }
153 },
b35ea4ab
AD		 154 .irq = {
155 .set = &r100_irq_set,
156 .process = &r100_irq_process,
157 },
c79a49ca
AD		 158 .display = {
159 .bandwidth_update = &r100_bandwidth_update,
160 .get_vblank_counter = &r100_get_vblank_counter,
161 .wait_for_vblank = &r100_wait_for_vblank,
162 },
27cd7769
AD		 163 .copy = {
164 .blit = &r100_copy_blit,
165 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
166 .dma = NULL,
167 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
168 .copy = &r100_copy_blit,
169 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
170 },
48e7a5f1
DV		 171 .get_engine_clock = &radeon_legacy_get_engine_clock,
172 .set_engine_clock = &radeon_legacy_set_engine_clock,
173 .get_memory_clock = &radeon_legacy_get_memory_clock,
174 .set_memory_clock = NULL,
175 .get_pcie_lanes = NULL,
176 .set_pcie_lanes = NULL,
177 .set_clock_gating = &radeon_legacy_set_clock_gating,
178 .set_surface_reg = r100_set_surface_reg,
179 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 180 .hpd = {
181 .init = &r100_hpd_init,
182 .fini = &r100_hpd_fini,
183 .sense = &r100_hpd_sense,
184 .set_polarity = &r100_hpd_set_polarity,
185 },
48e7a5f1 186 .ioctl_wait_idle = NULL,
def9ba9c 187 .gui_idle = &r100_gui_idle,
a02fa397
AD		 188 .pm = {
189 .misc = &r100_pm_misc,
190 .prepare = &r100_pm_prepare,
191 .finish = &r100_pm_finish,
192 .init_profile = &r100_pm_init_profile,
193 .get_dynpm_state = &r100_pm_get_dynpm_state,
194 },
0f9e006c
AD		 195 .pflip = {
196 .pre_page_flip = &r100_pre_page_flip,
197 .page_flip = &r100_page_flip,
198 .post_page_flip = &r100_post_page_flip,
199 },
89e5181f 200 .mc_wait_for_idle = &r100_mc_wait_for_idle,
48e7a5f1
DV		 201};
202
203static struct radeon_asic r200_asic = {
204 .init = &r100_init,
205 .fini = &r100_fini,
206 .suspend = &r100_suspend,
207 .resume = &r100_resume,
208 .vga_set_state = &r100_vga_set_state,
225758d8 209 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 210 .asic_reset = &r100_asic_reset,
c5b3b850
AD		 211 .gart = {
212 .tlb_flush = &r100_pci_gart_tlb_flush,
213 .set_page = &r100_pci_gart_set_page,
214 },
4c87bc26
CK		 215 .ring = {
216 [RADEON_RING_TYPE_GFX_INDEX] = {
217 .ib_execute = &r100_ring_ib_execute,
218 .emit_fence = &r100_fence_ring_emit,
219 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 220 .cs_parse = &r100_cs_parse,
f712812e
AD		 221 .ring_start = &r100_ring_start,
222 .ring_test = &r100_ring_test,
223 .ib_test = &r100_ib_test,
4c87bc26
CK		 224 }
225 },
b35ea4ab
AD		 226 .irq = {
227 .set = &r100_irq_set,
228 .process = &r100_irq_process,
229 },
c79a49ca
AD		 230 .display = {
231 .bandwidth_update = &r100_bandwidth_update,
232 .get_vblank_counter = &r100_get_vblank_counter,
233 .wait_for_vblank = &r100_wait_for_vblank,
234 },
27cd7769
AD		 235 .copy = {
236 .blit = &r100_copy_blit,
237 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
238 .dma = &r200_copy_dma,
239 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
240 .copy = &r100_copy_blit,
241 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
242 },
48e7a5f1
DV		 243 .get_engine_clock = &radeon_legacy_get_engine_clock,
244 .set_engine_clock = &radeon_legacy_set_engine_clock,
245 .get_memory_clock = &radeon_legacy_get_memory_clock,
246 .set_memory_clock = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
249 .set_surface_reg = r100_set_surface_reg,
250 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 251 .hpd = {
252 .init = &r100_hpd_init,
253 .fini = &r100_hpd_fini,
254 .sense = &r100_hpd_sense,
255 .set_polarity = &r100_hpd_set_polarity,
256 },
48e7a5f1 257 .ioctl_wait_idle = NULL,
def9ba9c 258 .gui_idle = &r100_gui_idle,
a02fa397
AD		 259 .pm = {
260 .misc = &r100_pm_misc,
261 .prepare = &r100_pm_prepare,
262 .finish = &r100_pm_finish,
263 .init_profile = &r100_pm_init_profile,
264 .get_dynpm_state = &r100_pm_get_dynpm_state,
265 },
0f9e006c
AD		 266 .pflip = {
267 .pre_page_flip = &r100_pre_page_flip,
268 .page_flip = &r100_page_flip,
269 .post_page_flip = &r100_post_page_flip,
270 },
89e5181f 271 .mc_wait_for_idle = &r100_mc_wait_for_idle,
48e7a5f1
DV		 272};
273
274static struct radeon_asic r300_asic = {
275 .init = &r300_init,
276 .fini = &r300_fini,
277 .suspend = &r300_suspend,
278 .resume = &r300_resume,
279 .vga_set_state = &r100_vga_set_state,
225758d8 280 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 281 .asic_reset = &r300_asic_reset,
c5b3b850
AD		 282 .gart = {
283 .tlb_flush = &r100_pci_gart_tlb_flush,
284 .set_page = &r100_pci_gart_set_page,
285 },
4c87bc26
CK		 286 .ring = {
287 [RADEON_RING_TYPE_GFX_INDEX] = {
288 .ib_execute = &r100_ring_ib_execute,
289 .emit_fence = &r300_fence_ring_emit,
290 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 291 .cs_parse = &r300_cs_parse,
f712812e
AD		 292 .ring_start = &r300_ring_start,
293 .ring_test = &r100_ring_test,
294 .ib_test = &r100_ib_test,
4c87bc26
CK		 295 }
296 },
b35ea4ab
AD		 297 .irq = {
298 .set = &r100_irq_set,
299 .process = &r100_irq_process,
300 },
c79a49ca
AD		 301 .display = {
302 .bandwidth_update = &r100_bandwidth_update,
303 .get_vblank_counter = &r100_get_vblank_counter,
304 .wait_for_vblank = &r100_wait_for_vblank,
305 },
27cd7769
AD		 306 .copy = {
307 .blit = &r100_copy_blit,
308 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
309 .dma = &r200_copy_dma,
310 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
311 .copy = &r100_copy_blit,
312 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
313 },
48e7a5f1
DV		 314 .get_engine_clock = &radeon_legacy_get_engine_clock,
315 .set_engine_clock = &radeon_legacy_set_engine_clock,
316 .get_memory_clock = &radeon_legacy_get_memory_clock,
317 .set_memory_clock = NULL,
318 .get_pcie_lanes = &rv370_get_pcie_lanes,
319 .set_pcie_lanes = &rv370_set_pcie_lanes,
320 .set_clock_gating = &radeon_legacy_set_clock_gating,
321 .set_surface_reg = r100_set_surface_reg,
322 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 323 .hpd = {
324 .init = &r100_hpd_init,
325 .fini = &r100_hpd_fini,
326 .sense = &r100_hpd_sense,
327 .set_polarity = &r100_hpd_set_polarity,
328 },
48e7a5f1 329 .ioctl_wait_idle = NULL,
def9ba9c 330 .gui_idle = &r100_gui_idle,
a02fa397
AD		 331 .pm = {
332 .misc = &r100_pm_misc,
333 .prepare = &r100_pm_prepare,
334 .finish = &r100_pm_finish,
335 .init_profile = &r100_pm_init_profile,
336 .get_dynpm_state = &r100_pm_get_dynpm_state,
337 },
0f9e006c
AD		 338 .pflip = {
339 .pre_page_flip = &r100_pre_page_flip,
340 .page_flip = &r100_page_flip,
341 .post_page_flip = &r100_post_page_flip,
342 },
89e5181f 343 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 344};
345
346static struct radeon_asic r300_asic_pcie = {
347 .init = &r300_init,
348 .fini = &r300_fini,
349 .suspend = &r300_suspend,
350 .resume = &r300_resume,
351 .vga_set_state = &r100_vga_set_state,
225758d8 352 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 353 .asic_reset = &r300_asic_reset,
c5b3b850
AD		 354 .gart = {
355 .tlb_flush = &rv370_pcie_gart_tlb_flush,
356 .set_page = &rv370_pcie_gart_set_page,
357 },
4c87bc26
CK		 358 .ring = {
359 [RADEON_RING_TYPE_GFX_INDEX] = {
360 .ib_execute = &r100_ring_ib_execute,
361 .emit_fence = &r300_fence_ring_emit,
362 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 363 .cs_parse = &r300_cs_parse,
f712812e
AD		 364 .ring_start = &r300_ring_start,
365 .ring_test = &r100_ring_test,
366 .ib_test = &r100_ib_test,
4c87bc26
CK		 367 }
368 },
b35ea4ab
AD		 369 .irq = {
370 .set = &r100_irq_set,
371 .process = &r100_irq_process,
372 },
c79a49ca
AD		 373 .display = {
374 .bandwidth_update = &r100_bandwidth_update,
375 .get_vblank_counter = &r100_get_vblank_counter,
376 .wait_for_vblank = &r100_wait_for_vblank,
377 },
27cd7769
AD		 378 .copy = {
379 .blit = &r100_copy_blit,
380 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
381 .dma = &r200_copy_dma,
382 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
383 .copy = &r100_copy_blit,
384 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
385 },
48e7a5f1
DV		 386 .get_engine_clock = &radeon_legacy_get_engine_clock,
387 .set_engine_clock = &radeon_legacy_set_engine_clock,
388 .get_memory_clock = &radeon_legacy_get_memory_clock,
389 .set_memory_clock = NULL,
390 .set_pcie_lanes = &rv370_set_pcie_lanes,
391 .set_clock_gating = &radeon_legacy_set_clock_gating,
392 .set_surface_reg = r100_set_surface_reg,
393 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 394 .hpd = {
395 .init = &r100_hpd_init,
396 .fini = &r100_hpd_fini,
397 .sense = &r100_hpd_sense,
398 .set_polarity = &r100_hpd_set_polarity,
399 },
48e7a5f1 400 .ioctl_wait_idle = NULL,
def9ba9c 401 .gui_idle = &r100_gui_idle,
a02fa397
AD		 402 .pm = {
403 .misc = &r100_pm_misc,
404 .prepare = &r100_pm_prepare,
405 .finish = &r100_pm_finish,
406 .init_profile = &r100_pm_init_profile,
407 .get_dynpm_state = &r100_pm_get_dynpm_state,
408 },
0f9e006c
AD		 409 .pflip = {
410 .pre_page_flip = &r100_pre_page_flip,
411 .page_flip = &r100_page_flip,
412 .post_page_flip = &r100_post_page_flip,
413 },
89e5181f 414 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 415};
416
417static struct radeon_asic r420_asic = {
418 .init = &r420_init,
419 .fini = &r420_fini,
420 .suspend = &r420_suspend,
421 .resume = &r420_resume,
422 .vga_set_state = &r100_vga_set_state,
225758d8 423 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 424 .asic_reset = &r300_asic_reset,
c5b3b850
AD		 425 .gart = {
426 .tlb_flush = &rv370_pcie_gart_tlb_flush,
427 .set_page = &rv370_pcie_gart_set_page,
428 },
4c87bc26
CK		 429 .ring = {
430 [RADEON_RING_TYPE_GFX_INDEX] = {
431 .ib_execute = &r100_ring_ib_execute,
432 .emit_fence = &r300_fence_ring_emit,
433 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 434 .cs_parse = &r300_cs_parse,
f712812e
AD		 435 .ring_start = &r300_ring_start,
436 .ring_test = &r100_ring_test,
437 .ib_test = &r100_ib_test,
4c87bc26
CK		 438 }
439 },
b35ea4ab
AD		 440 .irq = {
441 .set = &r100_irq_set,
442 .process = &r100_irq_process,
443 },
c79a49ca
AD		 444 .display = {
445 .bandwidth_update = &r100_bandwidth_update,
446 .get_vblank_counter = &r100_get_vblank_counter,
447 .wait_for_vblank = &r100_wait_for_vblank,
448 },
27cd7769
AD		 449 .copy = {
450 .blit = &r100_copy_blit,
451 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
452 .dma = &r200_copy_dma,
453 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
454 .copy = &r100_copy_blit,
455 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
456 },
48e7a5f1
DV		 457 .get_engine_clock = &radeon_atom_get_engine_clock,
458 .set_engine_clock = &radeon_atom_set_engine_clock,
459 .get_memory_clock = &radeon_atom_get_memory_clock,
460 .set_memory_clock = &radeon_atom_set_memory_clock,
461 .get_pcie_lanes = &rv370_get_pcie_lanes,
462 .set_pcie_lanes = &rv370_set_pcie_lanes,
463 .set_clock_gating = &radeon_atom_set_clock_gating,
464 .set_surface_reg = r100_set_surface_reg,
465 .clear_surface_reg = r100_clear_surface_reg,
c79a49ca 466
901ea57d
AD		 467 .hpd = {
468 .init = &r100_hpd_init,
469 .fini = &r100_hpd_fini,
470 .sense = &r100_hpd_sense,
471 .set_polarity = &r100_hpd_set_polarity,
472 },
48e7a5f1 473 .ioctl_wait_idle = NULL,
def9ba9c 474 .gui_idle = &r100_gui_idle,
a02fa397
AD		 475 .pm = {
476 .misc = &r100_pm_misc,
477 .prepare = &r100_pm_prepare,
478 .finish = &r100_pm_finish,
479 .init_profile = &r420_pm_init_profile,
480 .get_dynpm_state = &r100_pm_get_dynpm_state,
481 },
0f9e006c
AD		 482 .pflip = {
483 .pre_page_flip = &r100_pre_page_flip,
484 .page_flip = &r100_page_flip,
485 .post_page_flip = &r100_post_page_flip,
486 },
89e5181f 487 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 488};
489
490static struct radeon_asic rs400_asic = {
491 .init = &rs400_init,
492 .fini = &rs400_fini,
493 .suspend = &rs400_suspend,
494 .resume = &rs400_resume,
495 .vga_set_state = &r100_vga_set_state,
225758d8 496 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 497 .asic_reset = &r300_asic_reset,
c5b3b850
AD		 498 .gart = {
499 .tlb_flush = &rs400_gart_tlb_flush,
500 .set_page = &rs400_gart_set_page,
501 },
4c87bc26
CK		 502 .ring = {
503 [RADEON_RING_TYPE_GFX_INDEX] = {
504 .ib_execute = &r100_ring_ib_execute,
505 .emit_fence = &r300_fence_ring_emit,
506 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 507 .cs_parse = &r300_cs_parse,
f712812e
AD		 508 .ring_start = &r300_ring_start,
509 .ring_test = &r100_ring_test,
510 .ib_test = &r100_ib_test,
4c87bc26
CK		 511 }
512 },
b35ea4ab
AD		 513 .irq = {
514 .set = &r100_irq_set,
515 .process = &r100_irq_process,
516 },
c79a49ca
AD		 517 .display = {
518 .bandwidth_update = &r100_bandwidth_update,
519 .get_vblank_counter = &r100_get_vblank_counter,
520 .wait_for_vblank = &r100_wait_for_vblank,
521 },
27cd7769
AD		 522 .copy = {
523 .blit = &r100_copy_blit,
524 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
525 .dma = &r200_copy_dma,
526 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
527 .copy = &r100_copy_blit,
528 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
529 },
48e7a5f1
DV		 530 .get_engine_clock = &radeon_legacy_get_engine_clock,
531 .set_engine_clock = &radeon_legacy_set_engine_clock,
532 .get_memory_clock = &radeon_legacy_get_memory_clock,
533 .set_memory_clock = NULL,
534 .get_pcie_lanes = NULL,
535 .set_pcie_lanes = NULL,
536 .set_clock_gating = &radeon_legacy_set_clock_gating,
537 .set_surface_reg = r100_set_surface_reg,
538 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 539 .hpd = {
540 .init = &r100_hpd_init,
541 .fini = &r100_hpd_fini,
542 .sense = &r100_hpd_sense,
543 .set_polarity = &r100_hpd_set_polarity,
544 },
48e7a5f1 545 .ioctl_wait_idle = NULL,
def9ba9c 546 .gui_idle = &r100_gui_idle,
a02fa397
AD		 547 .pm = {
548 .misc = &r100_pm_misc,
549 .prepare = &r100_pm_prepare,
550 .finish = &r100_pm_finish,
551 .init_profile = &r100_pm_init_profile,
552 .get_dynpm_state = &r100_pm_get_dynpm_state,
553 },
0f9e006c
AD		 554 .pflip = {
555 .pre_page_flip = &r100_pre_page_flip,
556 .page_flip = &r100_page_flip,
557 .post_page_flip = &r100_post_page_flip,
558 },
89e5181f 559 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
48e7a5f1
DV		 560};
561
562static struct radeon_asic rs600_asic = {
563 .init = &rs600_init,
564 .fini = &rs600_fini,
565 .suspend = &rs600_suspend,
566 .resume = &rs600_resume,
567 .vga_set_state = &r100_vga_set_state,
225758d8 568 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 569 .asic_reset = &rs600_asic_reset,
c5b3b850
AD		 570 .gart = {
571 .tlb_flush = &rs600_gart_tlb_flush,
572 .set_page = &rs600_gart_set_page,
573 },
4c87bc26
CK		 574 .ring = {
575 [RADEON_RING_TYPE_GFX_INDEX] = {
576 .ib_execute = &r100_ring_ib_execute,
577 .emit_fence = &r300_fence_ring_emit,
578 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 579 .cs_parse = &r300_cs_parse,
f712812e
AD		 580 .ring_start = &r300_ring_start,
581 .ring_test = &r100_ring_test,
582 .ib_test = &r100_ib_test,
4c87bc26
CK		 583 }
584 },
b35ea4ab
AD		 585 .irq = {
586 .set = &rs600_irq_set,
587 .process = &rs600_irq_process,
588 },
c79a49ca
AD		 589 .display = {
590 .bandwidth_update = &rs600_bandwidth_update,
591 .get_vblank_counter = &rs600_get_vblank_counter,
592 .wait_for_vblank = &avivo_wait_for_vblank,
593 },
27cd7769
AD		 594 .copy = {
595 .blit = &r100_copy_blit,
596 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
597 .dma = &r200_copy_dma,
598 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
599 .copy = &r100_copy_blit,
600 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
601 },
48e7a5f1
DV		 602 .get_engine_clock = &radeon_atom_get_engine_clock,
603 .set_engine_clock = &radeon_atom_set_engine_clock,
604 .get_memory_clock = &radeon_atom_get_memory_clock,
605 .set_memory_clock = &radeon_atom_set_memory_clock,
606 .get_pcie_lanes = NULL,
607 .set_pcie_lanes = NULL,
608 .set_clock_gating = &radeon_atom_set_clock_gating,
609 .set_surface_reg = r100_set_surface_reg,
610 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 611 .hpd = {
612 .init = &rs600_hpd_init,
613 .fini = &rs600_hpd_fini,
614 .sense = &rs600_hpd_sense,
615 .set_polarity = &rs600_hpd_set_polarity,
616 },
48e7a5f1 617 .ioctl_wait_idle = NULL,
def9ba9c 618 .gui_idle = &r100_gui_idle,
a02fa397
AD		 619 .pm = {
620 .misc = &rs600_pm_misc,
621 .prepare = &rs600_pm_prepare,
622 .finish = &rs600_pm_finish,
623 .init_profile = &r420_pm_init_profile,
624 .get_dynpm_state = &r100_pm_get_dynpm_state,
625 },
0f9e006c
AD		 626 .pflip = {
627 .pre_page_flip = &rs600_pre_page_flip,
628 .page_flip = &rs600_page_flip,
629 .post_page_flip = &rs600_post_page_flip,
630 },
89e5181f 631 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
48e7a5f1
DV		 632};
633
634static struct radeon_asic rs690_asic = {
635 .init = &rs690_init,
636 .fini = &rs690_fini,
637 .suspend = &rs690_suspend,
638 .resume = &rs690_resume,
639 .vga_set_state = &r100_vga_set_state,
225758d8 640 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 641 .asic_reset = &rs600_asic_reset,
c5b3b850
AD		 642 .gart = {
643 .tlb_flush = &rs400_gart_tlb_flush,
644 .set_page = &rs400_gart_set_page,
645 },
4c87bc26
CK		 646 .ring = {
647 [RADEON_RING_TYPE_GFX_INDEX] = {
648 .ib_execute = &r100_ring_ib_execute,
649 .emit_fence = &r300_fence_ring_emit,
650 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 651 .cs_parse = &r300_cs_parse,
f712812e
AD		 652 .ring_start = &r300_ring_start,
653 .ring_test = &r100_ring_test,
654 .ib_test = &r100_ib_test,
4c87bc26
CK		 655 }
656 },
b35ea4ab
AD		 657 .irq = {
658 .set = &rs600_irq_set,
659 .process = &rs600_irq_process,
660 },
c79a49ca
AD		 661 .display = {
662 .get_vblank_counter = &rs600_get_vblank_counter,
663 .bandwidth_update = &rs690_bandwidth_update,
664 .wait_for_vblank = &avivo_wait_for_vblank,
665 },
27cd7769
AD		 666 .copy = {
667 .blit = &r100_copy_blit,
668 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
669 .dma = &r200_copy_dma,
670 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
671 .copy = &r200_copy_dma,
672 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
673 },
48e7a5f1
DV		 674 .get_engine_clock = &radeon_atom_get_engine_clock,
675 .set_engine_clock = &radeon_atom_set_engine_clock,
676 .get_memory_clock = &radeon_atom_get_memory_clock,
677 .set_memory_clock = &radeon_atom_set_memory_clock,
678 .get_pcie_lanes = NULL,
679 .set_pcie_lanes = NULL,
680 .set_clock_gating = &radeon_atom_set_clock_gating,
681 .set_surface_reg = r100_set_surface_reg,
682 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 683 .hpd = {
684 .init = &rs600_hpd_init,
685 .fini = &rs600_hpd_fini,
686 .sense = &rs600_hpd_sense,
687 .set_polarity = &rs600_hpd_set_polarity,
688 },
48e7a5f1 689 .ioctl_wait_idle = NULL,
def9ba9c 690 .gui_idle = &r100_gui_idle,
a02fa397
AD		 691 .pm = {
692 .misc = &rs600_pm_misc,
693 .prepare = &rs600_pm_prepare,
694 .finish = &rs600_pm_finish,
695 .init_profile = &r420_pm_init_profile,
696 .get_dynpm_state = &r100_pm_get_dynpm_state,
697 },
0f9e006c
AD		 698 .pflip = {
699 .pre_page_flip = &rs600_pre_page_flip,
700 .page_flip = &rs600_page_flip,
701 .post_page_flip = &rs600_post_page_flip,
702 },
89e5181f 703 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
48e7a5f1
DV		 704};
705
706static struct radeon_asic rv515_asic = {
707 .init = &rv515_init,
708 .fini = &rv515_fini,
709 .suspend = &rv515_suspend,
710 .resume = &rv515_resume,
711 .vga_set_state = &r100_vga_set_state,
225758d8 712 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 713 .asic_reset = &rs600_asic_reset,
c5b3b850
AD		 714 .gart = {
715 .tlb_flush = &rv370_pcie_gart_tlb_flush,
716 .set_page = &rv370_pcie_gart_set_page,
717 },
4c87bc26
CK		 718 .ring = {
719 [RADEON_RING_TYPE_GFX_INDEX] = {
720 .ib_execute = &r100_ring_ib_execute,
721 .emit_fence = &r300_fence_ring_emit,
722 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 723 .cs_parse = &r300_cs_parse,
f712812e
AD		 724 .ring_start = &rv515_ring_start,
725 .ring_test = &r100_ring_test,
726 .ib_test = &r100_ib_test,
4c87bc26
CK		 727 }
728 },
b35ea4ab
AD		 729 .irq = {
730 .set = &rs600_irq_set,
731 .process = &rs600_irq_process,
732 },
c79a49ca
AD		 733 .display = {
734 .get_vblank_counter = &rs600_get_vblank_counter,
735 .bandwidth_update = &rv515_bandwidth_update,
736 .wait_for_vblank = &avivo_wait_for_vblank,
737 },
27cd7769
AD		 738 .copy = {
739 .blit = &r100_copy_blit,
740 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
741 .dma = &r200_copy_dma,
742 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
743 .copy = &r100_copy_blit,
744 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
745 },
48e7a5f1
DV		 746 .get_engine_clock = &radeon_atom_get_engine_clock,
747 .set_engine_clock = &radeon_atom_set_engine_clock,
748 .get_memory_clock = &radeon_atom_get_memory_clock,
749 .set_memory_clock = &radeon_atom_set_memory_clock,
750 .get_pcie_lanes = &rv370_get_pcie_lanes,
751 .set_pcie_lanes = &rv370_set_pcie_lanes,
752 .set_clock_gating = &radeon_atom_set_clock_gating,
753 .set_surface_reg = r100_set_surface_reg,
754 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 755 .hpd = {
756 .init = &rs600_hpd_init,
757 .fini = &rs600_hpd_fini,
758 .sense = &rs600_hpd_sense,
759 .set_polarity = &rs600_hpd_set_polarity,
760 },
48e7a5f1 761 .ioctl_wait_idle = NULL,
def9ba9c 762 .gui_idle = &r100_gui_idle,
a02fa397
AD		 763 .pm = {
764 .misc = &rs600_pm_misc,
765 .prepare = &rs600_pm_prepare,
766 .finish = &rs600_pm_finish,
767 .init_profile = &r420_pm_init_profile,
768 .get_dynpm_state = &r100_pm_get_dynpm_state,
769 },
0f9e006c
AD		 770 .pflip = {
771 .pre_page_flip = &rs600_pre_page_flip,
772 .page_flip = &rs600_page_flip,
773 .post_page_flip = &rs600_post_page_flip,
774 },
89e5181f 775 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
48e7a5f1
DV		 776};
777
778static struct radeon_asic r520_asic = {
779 .init = &r520_init,
780 .fini = &rv515_fini,
781 .suspend = &rv515_suspend,
782 .resume = &r520_resume,
783 .vga_set_state = &r100_vga_set_state,
225758d8 784 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 785 .asic_reset = &rs600_asic_reset,
c5b3b850
AD		 786 .gart = {
787 .tlb_flush = &rv370_pcie_gart_tlb_flush,
788 .set_page = &rv370_pcie_gart_set_page,
789 },
4c87bc26
CK		 790 .ring = {
791 [RADEON_RING_TYPE_GFX_INDEX] = {
792 .ib_execute = &r100_ring_ib_execute,
793 .emit_fence = &r300_fence_ring_emit,
794 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 795 .cs_parse = &r300_cs_parse,
f712812e
AD		 796 .ring_start = &rv515_ring_start,
797 .ring_test = &r100_ring_test,
798 .ib_test = &r100_ib_test,
4c87bc26
CK		 799 }
800 },
b35ea4ab
AD		 801 .irq = {
802 .set = &rs600_irq_set,
803 .process = &rs600_irq_process,
804 },
c79a49ca
AD		 805 .display = {
806 .bandwidth_update = &rv515_bandwidth_update,
807 .get_vblank_counter = &rs600_get_vblank_counter,
808 .wait_for_vblank = &avivo_wait_for_vblank,
809 },
27cd7769
AD		 810 .copy = {
811 .blit = &r100_copy_blit,
812 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
813 .dma = &r200_copy_dma,
814 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
815 .copy = &r100_copy_blit,
816 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
817 },
48e7a5f1
DV		 818 .get_engine_clock = &radeon_atom_get_engine_clock,
819 .set_engine_clock = &radeon_atom_set_engine_clock,
820 .get_memory_clock = &radeon_atom_get_memory_clock,
821 .set_memory_clock = &radeon_atom_set_memory_clock,
822 .get_pcie_lanes = &rv370_get_pcie_lanes,
823 .set_pcie_lanes = &rv370_set_pcie_lanes,
824 .set_clock_gating = &radeon_atom_set_clock_gating,
825 .set_surface_reg = r100_set_surface_reg,
826 .clear_surface_reg = r100_clear_surface_reg,
901ea57d
AD		 827 .hpd = {
828 .init = &rs600_hpd_init,
829 .fini = &rs600_hpd_fini,
830 .sense = &rs600_hpd_sense,
831 .set_polarity = &rs600_hpd_set_polarity,
832 },
48e7a5f1 833 .ioctl_wait_idle = NULL,
def9ba9c 834 .gui_idle = &r100_gui_idle,
a02fa397
AD		 835 .pm = {
836 .misc = &rs600_pm_misc,
837 .prepare = &rs600_pm_prepare,
838 .finish = &rs600_pm_finish,
839 .init_profile = &r420_pm_init_profile,
840 .get_dynpm_state = &r100_pm_get_dynpm_state,
841 },
0f9e006c
AD		 842 .pflip = {
843 .pre_page_flip = &rs600_pre_page_flip,
844 .page_flip = &rs600_page_flip,
845 .post_page_flip = &rs600_post_page_flip,
846 },
89e5181f 847 .mc_wait_for_idle = &r520_mc_wait_for_idle,
48e7a5f1
DV		 848};
849
850static struct radeon_asic r600_asic = {
851 .init = &r600_init,
852 .fini = &r600_fini,
853 .suspend = &r600_suspend,
854 .resume = &r600_resume,
48e7a5f1 855 .vga_set_state = &r600_vga_set_state,
225758d8 856 .gpu_is_lockup = &r600_gpu_is_lockup,
a2d07b74 857 .asic_reset = &r600_asic_reset,
c5b3b850
AD		 858 .gart = {
859 .tlb_flush = &r600_pcie_gart_tlb_flush,
860 .set_page = &rs600_gart_set_page,
861 },
4c87bc26
CK		 862 .ring = {
863 [RADEON_RING_TYPE_GFX_INDEX] = {
864 .ib_execute = &r600_ring_ib_execute,
865 .emit_fence = &r600_fence_ring_emit,
866 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 867 .cs_parse = &r600_cs_parse,
f712812e
AD		 868 .ring_test = &r600_ring_test,
869 .ib_test = &r600_ib_test,
4c87bc26
CK		 870 }
871 },
b35ea4ab
AD		 872 .irq = {
873 .set = &r600_irq_set,
874 .process = &r600_irq_process,
875 },
c79a49ca
AD		 876 .display = {
877 .bandwidth_update = &rv515_bandwidth_update,
878 .get_vblank_counter = &rs600_get_vblank_counter,
879 .wait_for_vblank = &avivo_wait_for_vblank,
880 },
27cd7769
AD		 881 .copy = {
882 .blit = &r600_copy_blit,
883 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
884 .dma = NULL,
885 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
886 .copy = &r600_copy_blit,
887 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
888 },
48e7a5f1
DV		 889 .get_engine_clock = &radeon_atom_get_engine_clock,
890 .set_engine_clock = &radeon_atom_set_engine_clock,
891 .get_memory_clock = &radeon_atom_get_memory_clock,
892 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 893 .get_pcie_lanes = &r600_get_pcie_lanes,
894 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 895 .set_clock_gating = NULL,
896 .set_surface_reg = r600_set_surface_reg,
897 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 898 .hpd = {
899 .init = &r600_hpd_init,
900 .fini = &r600_hpd_fini,
901 .sense = &r600_hpd_sense,
902 .set_polarity = &r600_hpd_set_polarity,
903 },
48e7a5f1 904 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 905 .gui_idle = &r600_gui_idle,
a02fa397
AD		 906 .pm = {
907 .misc = &r600_pm_misc,
908 .prepare = &rs600_pm_prepare,
909 .finish = &rs600_pm_finish,
910 .init_profile = &r600_pm_init_profile,
911 .get_dynpm_state = &r600_pm_get_dynpm_state,
912 },
0f9e006c
AD		 913 .pflip = {
914 .pre_page_flip = &rs600_pre_page_flip,
915 .page_flip = &rs600_page_flip,
916 .post_page_flip = &rs600_post_page_flip,
917 },
89e5181f 918 .mc_wait_for_idle = &r600_mc_wait_for_idle,
48e7a5f1
DV		 919};
920
f47299c5
AD		 921static struct radeon_asic rs780_asic = {
922 .init = &r600_init,
923 .fini = &r600_fini,
924 .suspend = &r600_suspend,
925 .resume = &r600_resume,
90aca4d2 926 .gpu_is_lockup = &r600_gpu_is_lockup,
f47299c5 927 .vga_set_state = &r600_vga_set_state,
a2d07b74 928 .asic_reset = &r600_asic_reset,
c5b3b850
AD		 929 .gart = {
930 .tlb_flush = &r600_pcie_gart_tlb_flush,
931 .set_page = &rs600_gart_set_page,
932 },
4c87bc26
CK		 933 .ring = {
934 [RADEON_RING_TYPE_GFX_INDEX] = {
935 .ib_execute = &r600_ring_ib_execute,
936 .emit_fence = &r600_fence_ring_emit,
937 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 938 .cs_parse = &r600_cs_parse,
f712812e
AD		 939 .ring_test = &r600_ring_test,
940 .ib_test = &r600_ib_test,
4c87bc26
CK		 941 }
942 },
b35ea4ab
AD		 943 .irq = {
944 .set = &r600_irq_set,
945 .process = &r600_irq_process,
946 },
c79a49ca
AD		 947 .display = {
948 .bandwidth_update = &rs690_bandwidth_update,
949 .get_vblank_counter = &rs600_get_vblank_counter,
950 .wait_for_vblank = &avivo_wait_for_vblank,
951 },
27cd7769
AD		 952 .copy = {
953 .blit = &r600_copy_blit,
954 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
955 .dma = NULL,
956 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
957 .copy = &r600_copy_blit,
958 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
959 },
f47299c5
AD		 960 .get_engine_clock = &radeon_atom_get_engine_clock,
961 .set_engine_clock = &radeon_atom_set_engine_clock,
962 .get_memory_clock = NULL,
963 .set_memory_clock = NULL,
964 .get_pcie_lanes = NULL,
965 .set_pcie_lanes = NULL,
966 .set_clock_gating = NULL,
967 .set_surface_reg = r600_set_surface_reg,
968 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 969 .hpd = {
970 .init = &r600_hpd_init,
971 .fini = &r600_hpd_fini,
972 .sense = &r600_hpd_sense,
973 .set_polarity = &r600_hpd_set_polarity,
974 },
f47299c5 975 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 976 .gui_idle = &r600_gui_idle,
a02fa397
AD		 977 .pm = {
978 .misc = &r600_pm_misc,
979 .prepare = &rs600_pm_prepare,
980 .finish = &rs600_pm_finish,
981 .init_profile = &rs780_pm_init_profile,
982 .get_dynpm_state = &r600_pm_get_dynpm_state,
983 },
0f9e006c
AD		 984 .pflip = {
985 .pre_page_flip = &rs600_pre_page_flip,
986 .page_flip = &rs600_page_flip,
987 .post_page_flip = &rs600_post_page_flip,
988 },
89e5181f 989 .mc_wait_for_idle = &r600_mc_wait_for_idle,
f47299c5
AD		 990};
991
48e7a5f1
DV		 992static struct radeon_asic rv770_asic = {
993 .init = &rv770_init,
994 .fini = &rv770_fini,
995 .suspend = &rv770_suspend,
996 .resume = &rv770_resume,
a2d07b74 997 .asic_reset = &r600_asic_reset,
225758d8 998 .gpu_is_lockup = &r600_gpu_is_lockup,
48e7a5f1 999 .vga_set_state = &r600_vga_set_state,
c5b3b850
AD		 1000 .gart = {
1001 .tlb_flush = &r600_pcie_gart_tlb_flush,
1002 .set_page = &rs600_gart_set_page,
1003 },
4c87bc26
CK		 1004 .ring = {
1005 [RADEON_RING_TYPE_GFX_INDEX] = {
1006 .ib_execute = &r600_ring_ib_execute,
1007 .emit_fence = &r600_fence_ring_emit,
1008 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1009 .cs_parse = &r600_cs_parse,
f712812e
AD		 1010 .ring_test = &r600_ring_test,
1011 .ib_test = &r600_ib_test,
4c87bc26
CK		 1012 }
1013 },
b35ea4ab
AD		 1014 .irq = {
1015 .set = &r600_irq_set,
1016 .process = &r600_irq_process,
1017 },
c79a49ca
AD		 1018 .display = {
1019 .bandwidth_update = &rv515_bandwidth_update,
1020 .get_vblank_counter = &rs600_get_vblank_counter,
1021 .wait_for_vblank = &avivo_wait_for_vblank,
1022 },
27cd7769
AD		 1023 .copy = {
1024 .blit = &r600_copy_blit,
1025 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1026 .dma = NULL,
1027 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1028 .copy = &r600_copy_blit,
1029 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1030 },
48e7a5f1
DV		 1031 .get_engine_clock = &radeon_atom_get_engine_clock,
1032 .set_engine_clock = &radeon_atom_set_engine_clock,
1033 .get_memory_clock = &radeon_atom_get_memory_clock,
1034 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 1035 .get_pcie_lanes = &r600_get_pcie_lanes,
1036 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 1037 .set_clock_gating = &radeon_atom_set_clock_gating,
1038 .set_surface_reg = r600_set_surface_reg,
1039 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 1040 .hpd = {
1041 .init = &r600_hpd_init,
1042 .fini = &r600_hpd_fini,
1043 .sense = &r600_hpd_sense,
1044 .set_polarity = &r600_hpd_set_polarity,
1045 },
48e7a5f1 1046 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 1047 .gui_idle = &r600_gui_idle,
a02fa397
AD		 1048 .pm = {
1049 .misc = &rv770_pm_misc,
1050 .prepare = &rs600_pm_prepare,
1051 .finish = &rs600_pm_finish,
1052 .init_profile = &r600_pm_init_profile,
1053 .get_dynpm_state = &r600_pm_get_dynpm_state,
1054 },
0f9e006c
AD		 1055 .pflip = {
1056 .pre_page_flip = &rs600_pre_page_flip,
1057 .page_flip = &rv770_page_flip,
1058 .post_page_flip = &rs600_post_page_flip,
1059 },
89e5181f 1060 .mc_wait_for_idle = &r600_mc_wait_for_idle,
48e7a5f1
DV		 1061};
1062
1063static struct radeon_asic evergreen_asic = {
1064 .init = &evergreen_init,
1065 .fini = &evergreen_fini,
1066 .suspend = &evergreen_suspend,
1067 .resume = &evergreen_resume,
225758d8 1068 .gpu_is_lockup = &evergreen_gpu_is_lockup,
a2d07b74 1069 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1070 .vga_set_state = &r600_vga_set_state,
c5b3b850
AD		 1071 .gart = {
1072 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1073 .set_page = &rs600_gart_set_page,
1074 },
4c87bc26
CK		 1075 .ring = {
1076 [RADEON_RING_TYPE_GFX_INDEX] = {
1077 .ib_execute = &evergreen_ring_ib_execute,
1078 .emit_fence = &r600_fence_ring_emit,
1079 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1080 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1081 .ring_test = &r600_ring_test,
1082 .ib_test = &r600_ib_test,
4c87bc26
CK		 1083 }
1084 },
b35ea4ab
AD		 1085 .irq = {
1086 .set = &evergreen_irq_set,
1087 .process = &evergreen_irq_process,
1088 },
c79a49ca
AD		 1089 .display = {
1090 .bandwidth_update = &evergreen_bandwidth_update,
1091 .get_vblank_counter = &evergreen_get_vblank_counter,
1092 .wait_for_vblank = &dce4_wait_for_vblank,
1093 },
27cd7769
AD		 1094 .copy = {
1095 .blit = &r600_copy_blit,
1096 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1097 .dma = NULL,
1098 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1099 .copy = &r600_copy_blit,
1100 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1101 },
48e7a5f1
DV		 1102 .get_engine_clock = &radeon_atom_get_engine_clock,
1103 .set_engine_clock = &radeon_atom_set_engine_clock,
1104 .get_memory_clock = &radeon_atom_get_memory_clock,
1105 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 1106 .get_pcie_lanes = &r600_get_pcie_lanes,
1107 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 1108 .set_clock_gating = NULL,
1109 .set_surface_reg = r600_set_surface_reg,
1110 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 1111 .hpd = {
1112 .init = &evergreen_hpd_init,
1113 .fini = &evergreen_hpd_fini,
1114 .sense = &evergreen_hpd_sense,
1115 .set_polarity = &evergreen_hpd_set_polarity,
1116 },
97bfd0ac 1117 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 1118 .gui_idle = &r600_gui_idle,
a02fa397
AD		 1119 .pm = {
1120 .misc = &evergreen_pm_misc,
1121 .prepare = &evergreen_pm_prepare,
1122 .finish = &evergreen_pm_finish,
1123 .init_profile = &r600_pm_init_profile,
1124 .get_dynpm_state = &r600_pm_get_dynpm_state,
1125 },
0f9e006c
AD		 1126 .pflip = {
1127 .pre_page_flip = &evergreen_pre_page_flip,
1128 .page_flip = &evergreen_page_flip,
1129 .post_page_flip = &evergreen_post_page_flip,
1130 },
89e5181f 1131 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
48e7a5f1
DV		 1132};
1133
958261d1
AD		 1134static struct radeon_asic sumo_asic = {
1135 .init = &evergreen_init,
1136 .fini = &evergreen_fini,
1137 .suspend = &evergreen_suspend,
1138 .resume = &evergreen_resume,
958261d1
AD		 1139 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1140 .asic_reset = &evergreen_asic_reset,
1141 .vga_set_state = &r600_vga_set_state,
c5b3b850
AD		 1142 .gart = {
1143 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1144 .set_page = &rs600_gart_set_page,
1145 },
4c87bc26
CK		 1146 .ring = {
1147 [RADEON_RING_TYPE_GFX_INDEX] = {
1148 .ib_execute = &evergreen_ring_ib_execute,
1149 .emit_fence = &r600_fence_ring_emit,
1150 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1151 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1152 .ring_test = &r600_ring_test,
1153 .ib_test = &r600_ib_test,
eb0c19c5 1154 },
4c87bc26 1155 },
b35ea4ab
AD		 1156 .irq = {
1157 .set = &evergreen_irq_set,
1158 .process = &evergreen_irq_process,
1159 },
c79a49ca
AD		 1160 .display = {
1161 .bandwidth_update = &evergreen_bandwidth_update,
1162 .get_vblank_counter = &evergreen_get_vblank_counter,
1163 .wait_for_vblank = &dce4_wait_for_vblank,
1164 },
27cd7769
AD		 1165 .copy = {
1166 .blit = &r600_copy_blit,
1167 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1168 .dma = NULL,
1169 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1170 .copy = &r600_copy_blit,
1171 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1172 },
958261d1
AD		 1173 .get_engine_clock = &radeon_atom_get_engine_clock,
1174 .set_engine_clock = &radeon_atom_set_engine_clock,
1175 .get_memory_clock = NULL,
1176 .set_memory_clock = NULL,
1177 .get_pcie_lanes = NULL,
1178 .set_pcie_lanes = NULL,
1179 .set_clock_gating = NULL,
1180 .set_surface_reg = r600_set_surface_reg,
1181 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 1182 .hpd = {
1183 .init = &evergreen_hpd_init,
1184 .fini = &evergreen_hpd_fini,
1185 .sense = &evergreen_hpd_sense,
1186 .set_polarity = &evergreen_hpd_set_polarity,
1187 },
97bfd0ac 1188 .ioctl_wait_idle = r600_ioctl_wait_idle,
958261d1 1189 .gui_idle = &r600_gui_idle,
a02fa397
AD		 1190 .pm = {
1191 .misc = &evergreen_pm_misc,
1192 .prepare = &evergreen_pm_prepare,
1193 .finish = &evergreen_pm_finish,
1194 .init_profile = &sumo_pm_init_profile,
1195 .get_dynpm_state = &r600_pm_get_dynpm_state,
1196 },
0f9e006c
AD		 1197 .pflip = {
1198 .pre_page_flip = &evergreen_pre_page_flip,
1199 .page_flip = &evergreen_page_flip,
1200 .post_page_flip = &evergreen_post_page_flip,
1201 },
89e5181f 1202 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
958261d1
AD		 1203};
1204
a43b7665
AD		 1205static struct radeon_asic btc_asic = {
1206 .init = &evergreen_init,
1207 .fini = &evergreen_fini,
1208 .suspend = &evergreen_suspend,
1209 .resume = &evergreen_resume,
a43b7665
AD		 1210 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1211 .asic_reset = &evergreen_asic_reset,
1212 .vga_set_state = &r600_vga_set_state,
c5b3b850
AD		 1213 .gart = {
1214 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1215 .set_page = &rs600_gart_set_page,
1216 },
4c87bc26
CK		 1217 .ring = {
1218 [RADEON_RING_TYPE_GFX_INDEX] = {
1219 .ib_execute = &evergreen_ring_ib_execute,
1220 .emit_fence = &r600_fence_ring_emit,
1221 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1222 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1223 .ring_test = &r600_ring_test,
1224 .ib_test = &r600_ib_test,
4c87bc26
CK		 1225 }
1226 },
b35ea4ab
AD		 1227 .irq = {
1228 .set = &evergreen_irq_set,
1229 .process = &evergreen_irq_process,
1230 },
c79a49ca
AD		 1231 .display = {
1232 .bandwidth_update = &evergreen_bandwidth_update,
1233 .get_vblank_counter = &evergreen_get_vblank_counter,
1234 .wait_for_vblank = &dce4_wait_for_vblank,
1235 },
27cd7769
AD		 1236 .copy = {
1237 .blit = &r600_copy_blit,
1238 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1239 .dma = NULL,
1240 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1241 .copy = &r600_copy_blit,
1242 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1243 },
a43b7665
AD		 1244 .get_engine_clock = &radeon_atom_get_engine_clock,
1245 .set_engine_clock = &radeon_atom_set_engine_clock,
1246 .get_memory_clock = &radeon_atom_get_memory_clock,
1247 .set_memory_clock = &radeon_atom_set_memory_clock,
1248 .get_pcie_lanes = NULL,
1249 .set_pcie_lanes = NULL,
1250 .set_clock_gating = NULL,
1251 .set_surface_reg = r600_set_surface_reg,
1252 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 1253 .hpd = {
1254 .init = &evergreen_hpd_init,
1255 .fini = &evergreen_hpd_fini,
1256 .sense = &evergreen_hpd_sense,
1257 .set_polarity = &evergreen_hpd_set_polarity,
1258 },
97bfd0ac 1259 .ioctl_wait_idle = r600_ioctl_wait_idle,
a43b7665 1260 .gui_idle = &r600_gui_idle,
a02fa397
AD		 1261 .pm = {
1262 .misc = &evergreen_pm_misc,
1263 .prepare = &evergreen_pm_prepare,
1264 .finish = &evergreen_pm_finish,
1265 .init_profile = &r600_pm_init_profile,
1266 .get_dynpm_state = &r600_pm_get_dynpm_state,
1267 },
0f9e006c
AD		 1268 .pflip = {
1269 .pre_page_flip = &evergreen_pre_page_flip,
1270 .page_flip = &evergreen_page_flip,
1271 .post_page_flip = &evergreen_post_page_flip,
1272 },
89e5181f 1273 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
a43b7665
AD		 1274};
1275
721604a1
JG		 1276static const struct radeon_vm_funcs cayman_vm_funcs = {
1277 .init = &cayman_vm_init,
1278 .fini = &cayman_vm_fini,
1279 .bind = &cayman_vm_bind,
1280 .unbind = &cayman_vm_unbind,
1281 .tlb_flush = &cayman_vm_tlb_flush,
1282 .page_flags = &cayman_vm_page_flags,
1283 .set_page = &cayman_vm_set_page,
1284};
1285
e3487629
AD		 1286static struct radeon_asic cayman_asic = {
1287 .init = &cayman_init,
1288 .fini = &cayman_fini,
1289 .suspend = &cayman_suspend,
1290 .resume = &cayman_resume,
e3487629
AD		 1291 .gpu_is_lockup = &cayman_gpu_is_lockup,
1292 .asic_reset = &cayman_asic_reset,
1293 .vga_set_state = &r600_vga_set_state,
c5b3b850
AD		 1294 .gart = {
1295 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1296 .set_page = &rs600_gart_set_page,
1297 },
4c87bc26
CK		 1298 .ring = {
1299 [RADEON_RING_TYPE_GFX_INDEX] = {
721604a1
JG		 1300 .ib_execute = &cayman_ring_ib_execute,
1301 .ib_parse = &evergreen_ib_parse,
b40e7e16 1302 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1303 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1304 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1305 .ring_test = &r600_ring_test,
1306 .ib_test = &r600_ib_test,
4c87bc26
CK		 1307 },
1308 [CAYMAN_RING_TYPE_CP1_INDEX] = {
721604a1
JG		 1309 .ib_execute = &cayman_ring_ib_execute,
1310 .ib_parse = &evergreen_ib_parse,
b40e7e16 1311 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1312 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1313 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1314 .ring_test = &r600_ring_test,
1315 .ib_test = &r600_ib_test,
4c87bc26
CK		 1316 },
1317 [CAYMAN_RING_TYPE_CP2_INDEX] = {
721604a1
JG		 1318 .ib_execute = &cayman_ring_ib_execute,
1319 .ib_parse = &evergreen_ib_parse,
b40e7e16 1320 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1321 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1322 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1323 .ring_test = &r600_ring_test,
1324 .ib_test = &r600_ib_test,
4c87bc26
CK		 1325 }
1326 },
b35ea4ab
AD		 1327 .irq = {
1328 .set = &evergreen_irq_set,
1329 .process = &evergreen_irq_process,
1330 },
c79a49ca
AD		 1331 .display = {
1332 .bandwidth_update = &evergreen_bandwidth_update,
1333 .get_vblank_counter = &evergreen_get_vblank_counter,
1334 .wait_for_vblank = &dce4_wait_for_vblank,
1335 },
27cd7769
AD		 1336 .copy = {
1337 .blit = &r600_copy_blit,
1338 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1339 .dma = NULL,
1340 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1341 .copy = &r600_copy_blit,
1342 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1343 },
e3487629
AD		 1344 .get_engine_clock = &radeon_atom_get_engine_clock,
1345 .set_engine_clock = &radeon_atom_set_engine_clock,
1346 .get_memory_clock = &radeon_atom_get_memory_clock,
1347 .set_memory_clock = &radeon_atom_set_memory_clock,
1348 .get_pcie_lanes = NULL,
1349 .set_pcie_lanes = NULL,
1350 .set_clock_gating = NULL,
1351 .set_surface_reg = r600_set_surface_reg,
1352 .clear_surface_reg = r600_clear_surface_reg,
901ea57d
AD		 1353 .hpd = {
1354 .init = &evergreen_hpd_init,
1355 .fini = &evergreen_hpd_fini,
1356 .sense = &evergreen_hpd_sense,
1357 .set_polarity = &evergreen_hpd_set_polarity,
1358 },
97bfd0ac 1359 .ioctl_wait_idle = r600_ioctl_wait_idle,
e3487629 1360 .gui_idle = &r600_gui_idle,
a02fa397
AD		 1361 .pm = {
1362 .misc = &evergreen_pm_misc,
1363 .prepare = &evergreen_pm_prepare,
1364 .finish = &evergreen_pm_finish,
1365 .init_profile = &r600_pm_init_profile,
1366 .get_dynpm_state = &r600_pm_get_dynpm_state,
1367 },
0f9e006c
AD		 1368 .pflip = {
1369 .pre_page_flip = &evergreen_pre_page_flip,
1370 .page_flip = &evergreen_page_flip,
1371 .post_page_flip = &evergreen_post_page_flip,
1372 },
89e5181f 1373 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
e3487629
AD		 1374};
1375
0a10c851
DV		 1376int radeon_asic_init(struct radeon_device *rdev)
1377{
1378 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 1379
1380 /* set the number of crtcs */
1381 if (rdev->flags & RADEON_SINGLE_CRTC)
1382 rdev->num_crtc = 1;
1383 else
1384 rdev->num_crtc = 2;
1385
0a10c851
DV		 1386 switch (rdev->family) {
1387 case CHIP_R100:
1388 case CHIP_RV100:
1389 case CHIP_RS100:
1390 case CHIP_RV200:
1391 case CHIP_RS200:
1392 rdev->asic = &r100_asic;
1393 break;
1394 case CHIP_R200:
1395 case CHIP_RV250:
1396 case CHIP_RS300:
1397 case CHIP_RV280:
1398 rdev->asic = &r200_asic;
1399 break;
1400 case CHIP_R300:
1401 case CHIP_R350:
1402 case CHIP_RV350:
1403 case CHIP_RV380:
1404 if (rdev->flags & RADEON_IS_PCIE)
1405 rdev->asic = &r300_asic_pcie;
1406 else
1407 rdev->asic = &r300_asic;
1408 break;
1409 case CHIP_R420:
1410 case CHIP_R423:
1411 case CHIP_RV410:
1412 rdev->asic = &r420_asic;
07bb084c
AD		 1413 /* handle macs */
1414 if (rdev->bios == NULL) {
1415 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
1416 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
1417 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
1418 rdev->asic->set_memory_clock = NULL;
1419 }
0a10c851
DV		 1420 break;
1421 case CHIP_RS400:
1422 case CHIP_RS480:
1423 rdev->asic = &rs400_asic;
1424 break;
1425 case CHIP_RS600:
1426 rdev->asic = &rs600_asic;
1427 break;
1428 case CHIP_RS690:
1429 case CHIP_RS740:
1430 rdev->asic = &rs690_asic;
1431 break;
1432 case CHIP_RV515:
1433 rdev->asic = &rv515_asic;
1434 break;
1435 case CHIP_R520:
1436 case CHIP_RV530:
1437 case CHIP_RV560:
1438 case CHIP_RV570:
1439 case CHIP_R580:
1440 rdev->asic = &r520_asic;
1441 break;
1442 case CHIP_R600:
1443 case CHIP_RV610:
1444 case CHIP_RV630:
1445 case CHIP_RV620:
1446 case CHIP_RV635:
1447 case CHIP_RV670:
f47299c5
AD		 1448 rdev->asic = &r600_asic;
1449 break;
0a10c851
DV		 1450 case CHIP_RS780:
1451 case CHIP_RS880:
f47299c5 1452 rdev->asic = &rs780_asic;
0a10c851
DV		 1453 break;
1454 case CHIP_RV770:
1455 case CHIP_RV730:
1456 case CHIP_RV710:
1457 case CHIP_RV740:
1458 rdev->asic = &rv770_asic;
1459 break;
1460 case CHIP_CEDAR:
1461 case CHIP_REDWOOD:
1462 case CHIP_JUNIPER:
1463 case CHIP_CYPRESS:
1464 case CHIP_HEMLOCK:
ba7e05e9
AD		 1465 /* set num crtcs */
1466 if (rdev->family == CHIP_CEDAR)
1467 rdev->num_crtc = 4;
1468 else
1469 rdev->num_crtc = 6;
0a10c851
DV		 1470 rdev->asic = &evergreen_asic;
1471 break;
958261d1 1472 case CHIP_PALM:
89da5a37
AD		 1473 case CHIP_SUMO:
1474 case CHIP_SUMO2:
958261d1
AD		 1475 rdev->asic = &sumo_asic;
1476 break;
a43b7665
AD		 1477 case CHIP_BARTS:
1478 case CHIP_TURKS:
1479 case CHIP_CAICOS:
ba7e05e9
AD		 1480 /* set num crtcs */
1481 if (rdev->family == CHIP_CAICOS)
1482 rdev->num_crtc = 4;
1483 else
1484 rdev->num_crtc = 6;
a43b7665
AD		 1485 rdev->asic = &btc_asic;
1486 break;
e3487629
AD		 1487 case CHIP_CAYMAN:
1488 rdev->asic = &cayman_asic;
ba7e05e9
AD		 1489 /* set num crtcs */
1490 rdev->num_crtc = 6;
721604a1 1491 rdev->vm_manager.funcs = &cayman_vm_funcs;
e3487629 1492 break;
0a10c851
DV		 1493 default:
1494 /* FIXME: not supported yet */
1495 return -EINVAL;
1496 }
1497
1498 if (rdev->flags & RADEON_IS_IGP) {
1499 rdev->asic->get_memory_clock = NULL;
1500 rdev->asic->set_memory_clock = NULL;
1501 }
1502
1503 return 0;
1504}
1505
Linux kernel - Deliverables
This page took 0.190417 seconds and 5 git commands to generate.