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drm/radeon/rv6xx: implement get_current_sclk/mclk
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
cb658906 162 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
c5b3b850 163 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 164 } else {
165 DRM_INFO("Forcing AGP to PCI mode\n");
166 rdev->flags |= RADEON_IS_PCI;
c5b3b850 167 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
cb658906 168 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
c5b3b850 169 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 170 }
171 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
172}
173
174/*
175 * ASIC
176 */
76a0df85
CK		 177
178static struct radeon_asic_ring r100_gfx_ring = {
179 .ib_execute = &r100_ring_ib_execute,
180 .emit_fence = &r100_fence_ring_emit,
181 .emit_semaphore = &r100_semaphore_ring_emit,
182 .cs_parse = &r100_cs_parse,
183 .ring_start = &r100_ring_start,
184 .ring_test = &r100_ring_test,
185 .ib_test = &r100_ib_test,
186 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 187 .get_rptr = &r100_gfx_get_rptr,
188 .get_wptr = &r100_gfx_get_wptr,
189 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 190};
191
48e7a5f1
DV		 192static struct radeon_asic r100_asic = {
193 .init = &r100_init,
194 .fini = &r100_fini,
195 .suspend = &r100_suspend,
196 .resume = &r100_resume,
197 .vga_set_state = &r100_vga_set_state,
a2d07b74 198 .asic_reset = &r100_asic_reset,
124764f1 199 .mmio_hdp_flush = NULL,
54e88e06
AD		 200 .gui_idle = &r100_gui_idle,
201 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 202 .gart = {
203 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 204 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 205 .set_page = &r100_pci_gart_set_page,
206 },
4c87bc26 207 .ring = {
76a0df85 208 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 209 },
b35ea4ab
AD		 210 .irq = {
211 .set = &r100_irq_set,
212 .process = &r100_irq_process,
213 },
c79a49ca
AD		 214 .display = {
215 .bandwidth_update = &r100_bandwidth_update,
216 .get_vblank_counter = &r100_get_vblank_counter,
217 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 218 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 219 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 220 },
27cd7769
AD		 221 .copy = {
222 .blit = &r100_copy_blit,
223 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
224 .dma = NULL,
225 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
226 .copy = &r100_copy_blit,
227 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
228 },
9e6f3d02
AD		 229 .surface = {
230 .set_reg = r100_set_surface_reg,
231 .clear_reg = r100_clear_surface_reg,
232 },
901ea57d
AD		 233 .hpd = {
234 .init = &r100_hpd_init,
235 .fini = &r100_hpd_fini,
236 .sense = &r100_hpd_sense,
237 .set_polarity = &r100_hpd_set_polarity,
238 },
a02fa397
AD		 239 .pm = {
240 .misc = &r100_pm_misc,
241 .prepare = &r100_pm_prepare,
242 .finish = &r100_pm_finish,
243 .init_profile = &r100_pm_init_profile,
244 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 245 .get_engine_clock = &radeon_legacy_get_engine_clock,
246 .set_engine_clock = &radeon_legacy_set_engine_clock,
247 .get_memory_clock = &radeon_legacy_get_memory_clock,
248 .set_memory_clock = NULL,
249 .get_pcie_lanes = NULL,
250 .set_pcie_lanes = NULL,
251 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 252 },
0f9e006c 253 .pflip = {
0f9e006c 254 .page_flip = &r100_page_flip,
157fa14d 255 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 256 },
48e7a5f1
DV		 257};
258
259static struct radeon_asic r200_asic = {
260 .init = &r100_init,
261 .fini = &r100_fini,
262 .suspend = &r100_suspend,
263 .resume = &r100_resume,
264 .vga_set_state = &r100_vga_set_state,
a2d07b74 265 .asic_reset = &r100_asic_reset,
124764f1 266 .mmio_hdp_flush = NULL,
54e88e06
AD		 267 .gui_idle = &r100_gui_idle,
268 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 269 .gart = {
270 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 271 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 272 .set_page = &r100_pci_gart_set_page,
273 },
4c87bc26 274 .ring = {
76a0df85 275 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 276 },
b35ea4ab
AD		 277 .irq = {
278 .set = &r100_irq_set,
279 .process = &r100_irq_process,
280 },
c79a49ca
AD		 281 .display = {
282 .bandwidth_update = &r100_bandwidth_update,
283 .get_vblank_counter = &r100_get_vblank_counter,
284 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 285 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 286 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 287 },
27cd7769
AD		 288 .copy = {
289 .blit = &r100_copy_blit,
290 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291 .dma = &r200_copy_dma,
292 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
293 .copy = &r100_copy_blit,
294 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
295 },
9e6f3d02
AD		 296 .surface = {
297 .set_reg = r100_set_surface_reg,
298 .clear_reg = r100_clear_surface_reg,
299 },
901ea57d
AD		 300 .hpd = {
301 .init = &r100_hpd_init,
302 .fini = &r100_hpd_fini,
303 .sense = &r100_hpd_sense,
304 .set_polarity = &r100_hpd_set_polarity,
305 },
a02fa397
AD		 306 .pm = {
307 .misc = &r100_pm_misc,
308 .prepare = &r100_pm_prepare,
309 .finish = &r100_pm_finish,
310 .init_profile = &r100_pm_init_profile,
311 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 312 .get_engine_clock = &radeon_legacy_get_engine_clock,
313 .set_engine_clock = &radeon_legacy_set_engine_clock,
314 .get_memory_clock = &radeon_legacy_get_memory_clock,
315 .set_memory_clock = NULL,
316 .get_pcie_lanes = NULL,
317 .set_pcie_lanes = NULL,
318 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 319 },
0f9e006c 320 .pflip = {
0f9e006c 321 .page_flip = &r100_page_flip,
157fa14d 322 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 323 },
48e7a5f1
DV		 324};
325
76a0df85
CK		 326static struct radeon_asic_ring r300_gfx_ring = {
327 .ib_execute = &r100_ring_ib_execute,
328 .emit_fence = &r300_fence_ring_emit,
329 .emit_semaphore = &r100_semaphore_ring_emit,
330 .cs_parse = &r300_cs_parse,
331 .ring_start = &r300_ring_start,
332 .ring_test = &r100_ring_test,
333 .ib_test = &r100_ib_test,
334 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 335 .get_rptr = &r100_gfx_get_rptr,
336 .get_wptr = &r100_gfx_get_wptr,
337 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 338};
339
d8a74e18
AD		 340static struct radeon_asic_ring rv515_gfx_ring = {
341 .ib_execute = &r100_ring_ib_execute,
342 .emit_fence = &r300_fence_ring_emit,
343 .emit_semaphore = &r100_semaphore_ring_emit,
344 .cs_parse = &r300_cs_parse,
345 .ring_start = &rv515_ring_start,
346 .ring_test = &r100_ring_test,
347 .ib_test = &r100_ib_test,
348 .is_lockup = &r100_gpu_is_lockup,
349 .get_rptr = &r100_gfx_get_rptr,
350 .get_wptr = &r100_gfx_get_wptr,
351 .set_wptr = &r100_gfx_set_wptr,
352};
353
48e7a5f1
DV		 354static struct radeon_asic r300_asic = {
355 .init = &r300_init,
356 .fini = &r300_fini,
357 .suspend = &r300_suspend,
358 .resume = &r300_resume,
359 .vga_set_state = &r100_vga_set_state,
a2d07b74 360 .asic_reset = &r300_asic_reset,
124764f1 361 .mmio_hdp_flush = NULL,
54e88e06
AD		 362 .gui_idle = &r100_gui_idle,
363 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 364 .gart = {
365 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 366 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 367 .set_page = &r100_pci_gart_set_page,
368 },
4c87bc26 369 .ring = {
76a0df85 370 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 371 },
b35ea4ab
AD		 372 .irq = {
373 .set = &r100_irq_set,
374 .process = &r100_irq_process,
375 },
c79a49ca
AD		 376 .display = {
377 .bandwidth_update = &r100_bandwidth_update,
378 .get_vblank_counter = &r100_get_vblank_counter,
379 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 380 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 381 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 382 },
27cd7769
AD		 383 .copy = {
384 .blit = &r100_copy_blit,
385 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
386 .dma = &r200_copy_dma,
387 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
388 .copy = &r100_copy_blit,
389 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
390 },
9e6f3d02
AD		 391 .surface = {
392 .set_reg = r100_set_surface_reg,
393 .clear_reg = r100_clear_surface_reg,
394 },
901ea57d
AD		 395 .hpd = {
396 .init = &r100_hpd_init,
397 .fini = &r100_hpd_fini,
398 .sense = &r100_hpd_sense,
399 .set_polarity = &r100_hpd_set_polarity,
400 },
a02fa397
AD		 401 .pm = {
402 .misc = &r100_pm_misc,
403 .prepare = &r100_pm_prepare,
404 .finish = &r100_pm_finish,
405 .init_profile = &r100_pm_init_profile,
406 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 407 .get_engine_clock = &radeon_legacy_get_engine_clock,
408 .set_engine_clock = &radeon_legacy_set_engine_clock,
409 .get_memory_clock = &radeon_legacy_get_memory_clock,
410 .set_memory_clock = NULL,
411 .get_pcie_lanes = &rv370_get_pcie_lanes,
412 .set_pcie_lanes = &rv370_set_pcie_lanes,
413 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 414 },
0f9e006c 415 .pflip = {
0f9e006c 416 .page_flip = &r100_page_flip,
157fa14d 417 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 418 },
48e7a5f1
DV		 419};
420
421static struct radeon_asic r300_asic_pcie = {
422 .init = &r300_init,
423 .fini = &r300_fini,
424 .suspend = &r300_suspend,
425 .resume = &r300_resume,
426 .vga_set_state = &r100_vga_set_state,
a2d07b74 427 .asic_reset = &r300_asic_reset,
124764f1 428 .mmio_hdp_flush = NULL,
54e88e06
AD		 429 .gui_idle = &r100_gui_idle,
430 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 431 .gart = {
432 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 433 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 434 .set_page = &rv370_pcie_gart_set_page,
435 },
4c87bc26 436 .ring = {
76a0df85 437 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 438 },
b35ea4ab
AD		 439 .irq = {
440 .set = &r100_irq_set,
441 .process = &r100_irq_process,
442 },
c79a49ca
AD		 443 .display = {
444 .bandwidth_update = &r100_bandwidth_update,
445 .get_vblank_counter = &r100_get_vblank_counter,
446 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 447 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 448 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 449 },
27cd7769
AD		 450 .copy = {
451 .blit = &r100_copy_blit,
452 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
453 .dma = &r200_copy_dma,
454 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .copy = &r100_copy_blit,
456 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 },
9e6f3d02
AD		 458 .surface = {
459 .set_reg = r100_set_surface_reg,
460 .clear_reg = r100_clear_surface_reg,
461 },
901ea57d
AD		 462 .hpd = {
463 .init = &r100_hpd_init,
464 .fini = &r100_hpd_fini,
465 .sense = &r100_hpd_sense,
466 .set_polarity = &r100_hpd_set_polarity,
467 },
a02fa397
AD		 468 .pm = {
469 .misc = &r100_pm_misc,
470 .prepare = &r100_pm_prepare,
471 .finish = &r100_pm_finish,
472 .init_profile = &r100_pm_init_profile,
473 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 474 .get_engine_clock = &radeon_legacy_get_engine_clock,
475 .set_engine_clock = &radeon_legacy_set_engine_clock,
476 .get_memory_clock = &radeon_legacy_get_memory_clock,
477 .set_memory_clock = NULL,
478 .get_pcie_lanes = &rv370_get_pcie_lanes,
479 .set_pcie_lanes = &rv370_set_pcie_lanes,
480 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 481 },
0f9e006c 482 .pflip = {
0f9e006c 483 .page_flip = &r100_page_flip,
157fa14d 484 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 485 },
48e7a5f1
DV		 486};
487
488static struct radeon_asic r420_asic = {
489 .init = &r420_init,
490 .fini = &r420_fini,
491 .suspend = &r420_suspend,
492 .resume = &r420_resume,
493 .vga_set_state = &r100_vga_set_state,
a2d07b74 494 .asic_reset = &r300_asic_reset,
124764f1 495 .mmio_hdp_flush = NULL,
54e88e06
AD		 496 .gui_idle = &r100_gui_idle,
497 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 498 .gart = {
499 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 500 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 501 .set_page = &rv370_pcie_gart_set_page,
502 },
4c87bc26 503 .ring = {
76a0df85 504 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 505 },
b35ea4ab
AD		 506 .irq = {
507 .set = &r100_irq_set,
508 .process = &r100_irq_process,
509 },
c79a49ca
AD		 510 .display = {
511 .bandwidth_update = &r100_bandwidth_update,
512 .get_vblank_counter = &r100_get_vblank_counter,
513 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 514 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 515 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 516 },
27cd7769
AD		 517 .copy = {
518 .blit = &r100_copy_blit,
519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
520 .dma = &r200_copy_dma,
521 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
522 .copy = &r100_copy_blit,
523 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
524 },
9e6f3d02
AD		 525 .surface = {
526 .set_reg = r100_set_surface_reg,
527 .clear_reg = r100_clear_surface_reg,
528 },
901ea57d
AD		 529 .hpd = {
530 .init = &r100_hpd_init,
531 .fini = &r100_hpd_fini,
532 .sense = &r100_hpd_sense,
533 .set_polarity = &r100_hpd_set_polarity,
534 },
a02fa397
AD		 535 .pm = {
536 .misc = &r100_pm_misc,
537 .prepare = &r100_pm_prepare,
538 .finish = &r100_pm_finish,
539 .init_profile = &r420_pm_init_profile,
540 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 541 .get_engine_clock = &radeon_atom_get_engine_clock,
542 .set_engine_clock = &radeon_atom_set_engine_clock,
543 .get_memory_clock = &radeon_atom_get_memory_clock,
544 .set_memory_clock = &radeon_atom_set_memory_clock,
545 .get_pcie_lanes = &rv370_get_pcie_lanes,
546 .set_pcie_lanes = &rv370_set_pcie_lanes,
547 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 548 },
0f9e006c 549 .pflip = {
0f9e006c 550 .page_flip = &r100_page_flip,
157fa14d 551 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 552 },
48e7a5f1
DV		 553};
554
555static struct radeon_asic rs400_asic = {
556 .init = &rs400_init,
557 .fini = &rs400_fini,
558 .suspend = &rs400_suspend,
559 .resume = &rs400_resume,
560 .vga_set_state = &r100_vga_set_state,
a2d07b74 561 .asic_reset = &r300_asic_reset,
124764f1 562 .mmio_hdp_flush = NULL,
54e88e06
AD		 563 .gui_idle = &r100_gui_idle,
564 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 565 .gart = {
566 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 567 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 568 .set_page = &rs400_gart_set_page,
569 },
4c87bc26 570 .ring = {
76a0df85 571 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 572 },
b35ea4ab
AD		 573 .irq = {
574 .set = &r100_irq_set,
575 .process = &r100_irq_process,
576 },
c79a49ca
AD		 577 .display = {
578 .bandwidth_update = &r100_bandwidth_update,
579 .get_vblank_counter = &r100_get_vblank_counter,
580 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 581 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 582 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 583 },
27cd7769
AD		 584 .copy = {
585 .blit = &r100_copy_blit,
586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587 .dma = &r200_copy_dma,
588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589 .copy = &r100_copy_blit,
590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
591 },
9e6f3d02
AD		 592 .surface = {
593 .set_reg = r100_set_surface_reg,
594 .clear_reg = r100_clear_surface_reg,
595 },
901ea57d
AD		 596 .hpd = {
597 .init = &r100_hpd_init,
598 .fini = &r100_hpd_fini,
599 .sense = &r100_hpd_sense,
600 .set_polarity = &r100_hpd_set_polarity,
601 },
a02fa397
AD		 602 .pm = {
603 .misc = &r100_pm_misc,
604 .prepare = &r100_pm_prepare,
605 .finish = &r100_pm_finish,
606 .init_profile = &r100_pm_init_profile,
607 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 608 .get_engine_clock = &radeon_legacy_get_engine_clock,
609 .set_engine_clock = &radeon_legacy_set_engine_clock,
610 .get_memory_clock = &radeon_legacy_get_memory_clock,
611 .set_memory_clock = NULL,
612 .get_pcie_lanes = NULL,
613 .set_pcie_lanes = NULL,
614 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 615 },
0f9e006c 616 .pflip = {
0f9e006c 617 .page_flip = &r100_page_flip,
157fa14d 618 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 619 },
48e7a5f1
DV		 620};
621
622static struct radeon_asic rs600_asic = {
623 .init = &rs600_init,
624 .fini = &rs600_fini,
625 .suspend = &rs600_suspend,
626 .resume = &rs600_resume,
627 .vga_set_state = &r100_vga_set_state,
90aca4d2 628 .asic_reset = &rs600_asic_reset,
124764f1 629 .mmio_hdp_flush = NULL,
54e88e06
AD		 630 .gui_idle = &r100_gui_idle,
631 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 632 .gart = {
633 .tlb_flush = &rs600_gart_tlb_flush,
cb658906 634 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 635 .set_page = &rs600_gart_set_page,
636 },
4c87bc26 637 .ring = {
76a0df85 638 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 639 },
b35ea4ab
AD		 640 .irq = {
641 .set = &rs600_irq_set,
642 .process = &rs600_irq_process,
643 },
c79a49ca
AD		 644 .display = {
645 .bandwidth_update = &rs600_bandwidth_update,
646 .get_vblank_counter = &rs600_get_vblank_counter,
647 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 648 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 649 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 650 },
27cd7769
AD		 651 .copy = {
652 .blit = &r100_copy_blit,
653 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
654 .dma = &r200_copy_dma,
655 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
656 .copy = &r100_copy_blit,
657 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
658 },
9e6f3d02
AD		 659 .surface = {
660 .set_reg = r100_set_surface_reg,
661 .clear_reg = r100_clear_surface_reg,
662 },
901ea57d
AD		 663 .hpd = {
664 .init = &rs600_hpd_init,
665 .fini = &rs600_hpd_fini,
666 .sense = &rs600_hpd_sense,
667 .set_polarity = &rs600_hpd_set_polarity,
668 },
a02fa397
AD		 669 .pm = {
670 .misc = &rs600_pm_misc,
671 .prepare = &rs600_pm_prepare,
672 .finish = &rs600_pm_finish,
673 .init_profile = &r420_pm_init_profile,
674 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 675 .get_engine_clock = &radeon_atom_get_engine_clock,
676 .set_engine_clock = &radeon_atom_set_engine_clock,
677 .get_memory_clock = &radeon_atom_get_memory_clock,
678 .set_memory_clock = &radeon_atom_set_memory_clock,
679 .get_pcie_lanes = NULL,
680 .set_pcie_lanes = NULL,
681 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 682 },
0f9e006c 683 .pflip = {
0f9e006c 684 .page_flip = &rs600_page_flip,
157fa14d 685 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 686 },
48e7a5f1
DV		 687};
688
689static struct radeon_asic rs690_asic = {
690 .init = &rs690_init,
691 .fini = &rs690_fini,
692 .suspend = &rs690_suspend,
693 .resume = &rs690_resume,
694 .vga_set_state = &r100_vga_set_state,
90aca4d2 695 .asic_reset = &rs600_asic_reset,
124764f1 696 .mmio_hdp_flush = NULL,
54e88e06
AD		 697 .gui_idle = &r100_gui_idle,
698 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 699 .gart = {
700 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 701 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 702 .set_page = &rs400_gart_set_page,
703 },
4c87bc26 704 .ring = {
76a0df85 705 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 706 },
b35ea4ab
AD		 707 .irq = {
708 .set = &rs600_irq_set,
709 .process = &rs600_irq_process,
710 },
c79a49ca
AD		 711 .display = {
712 .get_vblank_counter = &rs600_get_vblank_counter,
713 .bandwidth_update = &rs690_bandwidth_update,
714 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 715 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 716 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 717 },
27cd7769
AD		 718 .copy = {
719 .blit = &r100_copy_blit,
720 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
721 .dma = &r200_copy_dma,
722 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
723 .copy = &r200_copy_dma,
724 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
725 },
9e6f3d02
AD		 726 .surface = {
727 .set_reg = r100_set_surface_reg,
728 .clear_reg = r100_clear_surface_reg,
729 },
901ea57d
AD		 730 .hpd = {
731 .init = &rs600_hpd_init,
732 .fini = &rs600_hpd_fini,
733 .sense = &rs600_hpd_sense,
734 .set_polarity = &rs600_hpd_set_polarity,
735 },
a02fa397
AD		 736 .pm = {
737 .misc = &rs600_pm_misc,
738 .prepare = &rs600_pm_prepare,
739 .finish = &rs600_pm_finish,
740 .init_profile = &r420_pm_init_profile,
741 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 742 .get_engine_clock = &radeon_atom_get_engine_clock,
743 .set_engine_clock = &radeon_atom_set_engine_clock,
744 .get_memory_clock = &radeon_atom_get_memory_clock,
745 .set_memory_clock = &radeon_atom_set_memory_clock,
746 .get_pcie_lanes = NULL,
747 .set_pcie_lanes = NULL,
748 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 749 },
0f9e006c 750 .pflip = {
0f9e006c 751 .page_flip = &rs600_page_flip,
157fa14d 752 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 753 },
48e7a5f1
DV		 754};
755
756static struct radeon_asic rv515_asic = {
757 .init = &rv515_init,
758 .fini = &rv515_fini,
759 .suspend = &rv515_suspend,
760 .resume = &rv515_resume,
761 .vga_set_state = &r100_vga_set_state,
90aca4d2 762 .asic_reset = &rs600_asic_reset,
124764f1 763 .mmio_hdp_flush = NULL,
54e88e06
AD		 764 .gui_idle = &r100_gui_idle,
765 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 766 .gart = {
767 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 768 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 769 .set_page = &rv370_pcie_gart_set_page,
770 },
4c87bc26 771 .ring = {
d8a74e18 772 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 773 },
b35ea4ab
AD		 774 .irq = {
775 .set = &rs600_irq_set,
776 .process = &rs600_irq_process,
777 },
c79a49ca
AD		 778 .display = {
779 .get_vblank_counter = &rs600_get_vblank_counter,
780 .bandwidth_update = &rv515_bandwidth_update,
781 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 782 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 783 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 784 },
27cd7769
AD		 785 .copy = {
786 .blit = &r100_copy_blit,
787 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
788 .dma = &r200_copy_dma,
789 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
790 .copy = &r100_copy_blit,
791 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
792 },
9e6f3d02
AD		 793 .surface = {
794 .set_reg = r100_set_surface_reg,
795 .clear_reg = r100_clear_surface_reg,
796 },
901ea57d
AD		 797 .hpd = {
798 .init = &rs600_hpd_init,
799 .fini = &rs600_hpd_fini,
800 .sense = &rs600_hpd_sense,
801 .set_polarity = &rs600_hpd_set_polarity,
802 },
a02fa397
AD		 803 .pm = {
804 .misc = &rs600_pm_misc,
805 .prepare = &rs600_pm_prepare,
806 .finish = &rs600_pm_finish,
807 .init_profile = &r420_pm_init_profile,
808 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 809 .get_engine_clock = &radeon_atom_get_engine_clock,
810 .set_engine_clock = &radeon_atom_set_engine_clock,
811 .get_memory_clock = &radeon_atom_get_memory_clock,
812 .set_memory_clock = &radeon_atom_set_memory_clock,
813 .get_pcie_lanes = &rv370_get_pcie_lanes,
814 .set_pcie_lanes = &rv370_set_pcie_lanes,
815 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 816 },
0f9e006c 817 .pflip = {
0f9e006c 818 .page_flip = &rs600_page_flip,
157fa14d 819 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 820 },
48e7a5f1
DV		 821};
822
823static struct radeon_asic r520_asic = {
824 .init = &r520_init,
825 .fini = &rv515_fini,
826 .suspend = &rv515_suspend,
827 .resume = &r520_resume,
828 .vga_set_state = &r100_vga_set_state,
90aca4d2 829 .asic_reset = &rs600_asic_reset,
124764f1 830 .mmio_hdp_flush = NULL,
54e88e06
AD		 831 .gui_idle = &r100_gui_idle,
832 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 833 .gart = {
834 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 835 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 836 .set_page = &rv370_pcie_gart_set_page,
837 },
4c87bc26 838 .ring = {
d8a74e18 839 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 840 },
b35ea4ab
AD		 841 .irq = {
842 .set = &rs600_irq_set,
843 .process = &rs600_irq_process,
844 },
c79a49ca
AD		 845 .display = {
846 .bandwidth_update = &rv515_bandwidth_update,
847 .get_vblank_counter = &rs600_get_vblank_counter,
848 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 849 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 850 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 851 },
27cd7769
AD		 852 .copy = {
853 .blit = &r100_copy_blit,
854 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
855 .dma = &r200_copy_dma,
856 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
857 .copy = &r100_copy_blit,
858 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
859 },
9e6f3d02
AD		 860 .surface = {
861 .set_reg = r100_set_surface_reg,
862 .clear_reg = r100_clear_surface_reg,
863 },
901ea57d
AD		 864 .hpd = {
865 .init = &rs600_hpd_init,
866 .fini = &rs600_hpd_fini,
867 .sense = &rs600_hpd_sense,
868 .set_polarity = &rs600_hpd_set_polarity,
869 },
a02fa397
AD		 870 .pm = {
871 .misc = &rs600_pm_misc,
872 .prepare = &rs600_pm_prepare,
873 .finish = &rs600_pm_finish,
874 .init_profile = &r420_pm_init_profile,
875 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 876 .get_engine_clock = &radeon_atom_get_engine_clock,
877 .set_engine_clock = &radeon_atom_set_engine_clock,
878 .get_memory_clock = &radeon_atom_get_memory_clock,
879 .set_memory_clock = &radeon_atom_set_memory_clock,
880 .get_pcie_lanes = &rv370_get_pcie_lanes,
881 .set_pcie_lanes = &rv370_set_pcie_lanes,
882 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 883 },
0f9e006c 884 .pflip = {
0f9e006c 885 .page_flip = &rs600_page_flip,
157fa14d 886 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 887 },
48e7a5f1
DV		 888};
889
76a0df85
CK		 890static struct radeon_asic_ring r600_gfx_ring = {
891 .ib_execute = &r600_ring_ib_execute,
892 .emit_fence = &r600_fence_ring_emit,
893 .emit_semaphore = &r600_semaphore_ring_emit,
894 .cs_parse = &r600_cs_parse,
895 .ring_test = &r600_ring_test,
896 .ib_test = &r600_ib_test,
897 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 898 .get_rptr = &r600_gfx_get_rptr,
899 .get_wptr = &r600_gfx_get_wptr,
900 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 901};
902
903static struct radeon_asic_ring r600_dma_ring = {
904 .ib_execute = &r600_dma_ring_ib_execute,
905 .emit_fence = &r600_dma_fence_ring_emit,
906 .emit_semaphore = &r600_dma_semaphore_ring_emit,
907 .cs_parse = &r600_dma_cs_parse,
908 .ring_test = &r600_dma_ring_test,
909 .ib_test = &r600_dma_ib_test,
910 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 911 .get_rptr = &r600_dma_get_rptr,
912 .get_wptr = &r600_dma_get_wptr,
913 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 914};
915
48e7a5f1
DV		 916static struct radeon_asic r600_asic = {
917 .init = &r600_init,
918 .fini = &r600_fini,
919 .suspend = &r600_suspend,
920 .resume = &r600_resume,
48e7a5f1 921 .vga_set_state = &r600_vga_set_state,
a2d07b74 922 .asic_reset = &r600_asic_reset,
124764f1 923 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 924 .gui_idle = &r600_gui_idle,
925 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 926 .get_xclk = &r600_get_xclk,
d0418894 927 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 928 .gart = {
929 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 930 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 931 .set_page = &rs600_gart_set_page,
932 },
4c87bc26 933 .ring = {
76a0df85
CK		 934 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
935 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 936 },
b35ea4ab
AD		 937 .irq = {
938 .set = &r600_irq_set,
939 .process = &r600_irq_process,
940 },
c79a49ca
AD		 941 .display = {
942 .bandwidth_update = &rv515_bandwidth_update,
943 .get_vblank_counter = &rs600_get_vblank_counter,
944 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 945 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 946 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 947 },
27cd7769 948 .copy = {
8dddb993 949 .blit = &r600_copy_cpdma,
27cd7769 950 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 951 .dma = &r600_copy_dma,
952 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 953 .copy = &r600_copy_cpdma,
aeea40cb 954 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 955 },
9e6f3d02
AD		 956 .surface = {
957 .set_reg = r600_set_surface_reg,
958 .clear_reg = r600_clear_surface_reg,
959 },
901ea57d
AD		 960 .hpd = {
961 .init = &r600_hpd_init,
962 .fini = &r600_hpd_fini,
963 .sense = &r600_hpd_sense,
964 .set_polarity = &r600_hpd_set_polarity,
965 },
a02fa397
AD		 966 .pm = {
967 .misc = &r600_pm_misc,
968 .prepare = &rs600_pm_prepare,
969 .finish = &rs600_pm_finish,
970 .init_profile = &r600_pm_init_profile,
971 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 972 .get_engine_clock = &radeon_atom_get_engine_clock,
973 .set_engine_clock = &radeon_atom_set_engine_clock,
974 .get_memory_clock = &radeon_atom_get_memory_clock,
975 .set_memory_clock = &radeon_atom_set_memory_clock,
976 .get_pcie_lanes = &r600_get_pcie_lanes,
977 .set_pcie_lanes = &r600_set_pcie_lanes,
978 .set_clock_gating = NULL,
6bd1c385 979 .get_temperature = &rv6xx_get_temp,
a02fa397 980 },
0f9e006c 981 .pflip = {
0f9e006c 982 .page_flip = &rs600_page_flip,
157fa14d 983 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 984 },
48e7a5f1
DV		 985};
986
856754c3
CK		 987static struct radeon_asic_ring rv6xx_uvd_ring = {
988 .ib_execute = &uvd_v1_0_ib_execute,
989 .emit_fence = &uvd_v1_0_fence_emit,
990 .emit_semaphore = &uvd_v1_0_semaphore_emit,
991 .cs_parse = &radeon_uvd_cs_parse,
992 .ring_test = &uvd_v1_0_ring_test,
993 .ib_test = &uvd_v1_0_ib_test,
994 .is_lockup = &radeon_ring_test_lockup,
995 .get_rptr = &uvd_v1_0_get_rptr,
996 .get_wptr = &uvd_v1_0_get_wptr,
997 .set_wptr = &uvd_v1_0_set_wptr,
998};
999
ca361b65
AD		 1000static struct radeon_asic rv6xx_asic = {
1001 .init = &r600_init,
1002 .fini = &r600_fini,
1003 .suspend = &r600_suspend,
1004 .resume = &r600_resume,
1005 .vga_set_state = &r600_vga_set_state,
1006 .asic_reset = &r600_asic_reset,
124764f1 1007 .mmio_hdp_flush = r600_mmio_hdp_flush,
ca361b65
AD		 1008 .gui_idle = &r600_gui_idle,
1009 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1010 .get_xclk = &r600_get_xclk,
1011 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1012 .gart = {
1013 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1014 .get_page_entry = &rs600_gart_get_page_entry,
ca361b65
AD		 1015 .set_page = &rs600_gart_set_page,
1016 },
1017 .ring = {
76a0df85
CK		 1018 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1019 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1020 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
ca361b65
AD		 1021 },
1022 .irq = {
1023 .set = &r600_irq_set,
1024 .process = &r600_irq_process,
1025 },
1026 .display = {
1027 .bandwidth_update = &rv515_bandwidth_update,
1028 .get_vblank_counter = &rs600_get_vblank_counter,
1029 .wait_for_vblank = &avivo_wait_for_vblank,
1030 .set_backlight_level = &atombios_set_backlight_level,
1031 .get_backlight_level = &atombios_get_backlight_level,
1032 },
1033 .copy = {
8dddb993 1034 .blit = &r600_copy_cpdma,
ca361b65
AD		 1035 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1036 .dma = &r600_copy_dma,
1037 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1038 .copy = &r600_copy_cpdma,
aeea40cb 1039 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1040 },
1041 .surface = {
1042 .set_reg = r600_set_surface_reg,
1043 .clear_reg = r600_clear_surface_reg,
1044 },
1045 .hpd = {
1046 .init = &r600_hpd_init,
1047 .fini = &r600_hpd_fini,
1048 .sense = &r600_hpd_sense,
1049 .set_polarity = &r600_hpd_set_polarity,
1050 },
1051 .pm = {
1052 .misc = &r600_pm_misc,
1053 .prepare = &rs600_pm_prepare,
1054 .finish = &rs600_pm_finish,
1055 .init_profile = &r600_pm_init_profile,
1056 .get_dynpm_state = &r600_pm_get_dynpm_state,
1057 .get_engine_clock = &radeon_atom_get_engine_clock,
1058 .set_engine_clock = &radeon_atom_set_engine_clock,
1059 .get_memory_clock = &radeon_atom_get_memory_clock,
1060 .set_memory_clock = &radeon_atom_set_memory_clock,
1061 .get_pcie_lanes = &r600_get_pcie_lanes,
1062 .set_pcie_lanes = &r600_set_pcie_lanes,
1063 .set_clock_gating = NULL,
1064 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1065 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1066 },
4a6369e9
AD		 1067 .dpm = {
1068 .init = &rv6xx_dpm_init,
1069 .setup_asic = &rv6xx_setup_asic,
1070 .enable = &rv6xx_dpm_enable,
a4643ba3 1071 .late_enable = &r600_dpm_late_enable,
4a6369e9 1072 .disable = &rv6xx_dpm_disable,
98243917 1073 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1074 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1075 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1076 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1077 .fini = &rv6xx_dpm_fini,
1078 .get_sclk = &rv6xx_dpm_get_sclk,
1079 .get_mclk = &rv6xx_dpm_get_mclk,
1080 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1081 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1082 .force_performance_level = &rv6xx_dpm_force_performance_level,
d0a04d3b
AD		 1083 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1084 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
4a6369e9 1085 },
ca361b65 1086 .pflip = {
ca361b65 1087 .page_flip = &rs600_page_flip,
157fa14d 1088 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1089 },
1090};
1091
f47299c5
AD		 1092static struct radeon_asic rs780_asic = {
1093 .init = &r600_init,
1094 .fini = &r600_fini,
1095 .suspend = &r600_suspend,
1096 .resume = &r600_resume,
f47299c5 1097 .vga_set_state = &r600_vga_set_state,
a2d07b74 1098 .asic_reset = &r600_asic_reset,
124764f1 1099 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1100 .gui_idle = &r600_gui_idle,
1101 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1102 .get_xclk = &r600_get_xclk,
d0418894 1103 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1104 .gart = {
1105 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1106 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1107 .set_page = &rs600_gart_set_page,
1108 },
4c87bc26 1109 .ring = {
76a0df85
CK		 1110 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1111 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1112 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
4c87bc26 1113 },
b35ea4ab
AD		 1114 .irq = {
1115 .set = &r600_irq_set,
1116 .process = &r600_irq_process,
1117 },
c79a49ca
AD		 1118 .display = {
1119 .bandwidth_update = &rs690_bandwidth_update,
1120 .get_vblank_counter = &rs600_get_vblank_counter,
1121 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1122 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1123 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1124 },
27cd7769 1125 .copy = {
8dddb993 1126 .blit = &r600_copy_cpdma,
27cd7769 1127 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1128 .dma = &r600_copy_dma,
1129 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1130 .copy = &r600_copy_cpdma,
aeea40cb 1131 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1132 },
9e6f3d02
AD		 1133 .surface = {
1134 .set_reg = r600_set_surface_reg,
1135 .clear_reg = r600_clear_surface_reg,
1136 },
901ea57d
AD		 1137 .hpd = {
1138 .init = &r600_hpd_init,
1139 .fini = &r600_hpd_fini,
1140 .sense = &r600_hpd_sense,
1141 .set_polarity = &r600_hpd_set_polarity,
1142 },
a02fa397
AD		 1143 .pm = {
1144 .misc = &r600_pm_misc,
1145 .prepare = &rs600_pm_prepare,
1146 .finish = &rs600_pm_finish,
1147 .init_profile = &rs780_pm_init_profile,
1148 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1149 .get_engine_clock = &radeon_atom_get_engine_clock,
1150 .set_engine_clock = &radeon_atom_set_engine_clock,
1151 .get_memory_clock = NULL,
1152 .set_memory_clock = NULL,
1153 .get_pcie_lanes = NULL,
1154 .set_pcie_lanes = NULL,
1155 .set_clock_gating = NULL,
6bd1c385 1156 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1157 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1158 },
9d67006e
AD		 1159 .dpm = {
1160 .init = &rs780_dpm_init,
1161 .setup_asic = &rs780_dpm_setup_asic,
1162 .enable = &rs780_dpm_enable,
a4643ba3 1163 .late_enable = &r600_dpm_late_enable,
9d67006e 1164 .disable = &rs780_dpm_disable,
98243917 1165 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1166 .set_power_state = &rs780_dpm_set_power_state,
98243917 1167 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1168 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1169 .fini = &rs780_dpm_fini,
1170 .get_sclk = &rs780_dpm_get_sclk,
1171 .get_mclk = &rs780_dpm_get_mclk,
1172 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1173 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1174 .force_performance_level = &rs780_dpm_force_performance_level,
3c94566c
AD		 1175 .get_current_sclk = &rs780_dpm_get_current_sclk,
1176 .get_current_mclk = &rs780_dpm_get_current_mclk,
9d67006e 1177 },
0f9e006c 1178 .pflip = {
0f9e006c 1179 .page_flip = &rs600_page_flip,
157fa14d 1180 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1181 },
f47299c5
AD		 1182};
1183
76a0df85 1184static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1185 .ib_execute = &uvd_v1_0_ib_execute,
1186 .emit_fence = &uvd_v2_2_fence_emit,
1187 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1188 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1189 .ring_test = &uvd_v1_0_ring_test,
1190 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1191 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1192 .get_rptr = &uvd_v1_0_get_rptr,
1193 .get_wptr = &uvd_v1_0_get_wptr,
1194 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1195};
1196
48e7a5f1
DV		 1197static struct radeon_asic rv770_asic = {
1198 .init = &rv770_init,
1199 .fini = &rv770_fini,
1200 .suspend = &rv770_suspend,
1201 .resume = &rv770_resume,
a2d07b74 1202 .asic_reset = &r600_asic_reset,
48e7a5f1 1203 .vga_set_state = &r600_vga_set_state,
124764f1 1204 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1205 .gui_idle = &r600_gui_idle,
1206 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1207 .get_xclk = &rv770_get_xclk,
d0418894 1208 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1209 .gart = {
1210 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1211 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1212 .set_page = &rs600_gart_set_page,
1213 },
4c87bc26 1214 .ring = {
76a0df85
CK		 1215 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1216 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1217 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1218 },
b35ea4ab
AD		 1219 .irq = {
1220 .set = &r600_irq_set,
1221 .process = &r600_irq_process,
1222 },
c79a49ca
AD		 1223 .display = {
1224 .bandwidth_update = &rv515_bandwidth_update,
1225 .get_vblank_counter = &rs600_get_vblank_counter,
1226 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1227 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1228 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1229 },
27cd7769 1230 .copy = {
8dddb993 1231 .blit = &r600_copy_cpdma,
27cd7769 1232 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1233 .dma = &rv770_copy_dma,
4d75658b 1234 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1235 .copy = &rv770_copy_dma,
2d6cc729 1236 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1237 },
9e6f3d02
AD		 1238 .surface = {
1239 .set_reg = r600_set_surface_reg,
1240 .clear_reg = r600_clear_surface_reg,
1241 },
901ea57d
AD		 1242 .hpd = {
1243 .init = &r600_hpd_init,
1244 .fini = &r600_hpd_fini,
1245 .sense = &r600_hpd_sense,
1246 .set_polarity = &r600_hpd_set_polarity,
1247 },
a02fa397
AD		 1248 .pm = {
1249 .misc = &rv770_pm_misc,
1250 .prepare = &rs600_pm_prepare,
1251 .finish = &rs600_pm_finish,
1252 .init_profile = &r600_pm_init_profile,
1253 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1254 .get_engine_clock = &radeon_atom_get_engine_clock,
1255 .set_engine_clock = &radeon_atom_set_engine_clock,
1256 .get_memory_clock = &radeon_atom_get_memory_clock,
1257 .set_memory_clock = &radeon_atom_set_memory_clock,
1258 .get_pcie_lanes = &r600_get_pcie_lanes,
1259 .set_pcie_lanes = &r600_set_pcie_lanes,
1260 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1261 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1262 .get_temperature = &rv770_get_temp,
a02fa397 1263 },
66229b20
AD		 1264 .dpm = {
1265 .init = &rv770_dpm_init,
1266 .setup_asic = &rv770_dpm_setup_asic,
1267 .enable = &rv770_dpm_enable,
a3f11245 1268 .late_enable = &rv770_dpm_late_enable,
66229b20 1269 .disable = &rv770_dpm_disable,
98243917 1270 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1271 .set_power_state = &rv770_dpm_set_power_state,
98243917 1272 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1273 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1274 .fini = &rv770_dpm_fini,
1275 .get_sclk = &rv770_dpm_get_sclk,
1276 .get_mclk = &rv770_dpm_get_mclk,
1277 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1278 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1279 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1280 .vblank_too_short = &rv770_dpm_vblank_too_short,
66229b20 1281 },
0f9e006c 1282 .pflip = {
0f9e006c 1283 .page_flip = &rv770_page_flip,
157fa14d 1284 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1285 },
48e7a5f1
DV		 1286};
1287
76a0df85
CK		 1288static struct radeon_asic_ring evergreen_gfx_ring = {
1289 .ib_execute = &evergreen_ring_ib_execute,
1290 .emit_fence = &r600_fence_ring_emit,
1291 .emit_semaphore = &r600_semaphore_ring_emit,
1292 .cs_parse = &evergreen_cs_parse,
1293 .ring_test = &r600_ring_test,
1294 .ib_test = &r600_ib_test,
1295 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1296 .get_rptr = &r600_gfx_get_rptr,
1297 .get_wptr = &r600_gfx_get_wptr,
1298 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1299};
1300
1301static struct radeon_asic_ring evergreen_dma_ring = {
1302 .ib_execute = &evergreen_dma_ring_ib_execute,
1303 .emit_fence = &evergreen_dma_fence_ring_emit,
1304 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1305 .cs_parse = &evergreen_dma_cs_parse,
1306 .ring_test = &r600_dma_ring_test,
1307 .ib_test = &r600_dma_ib_test,
1308 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1309 .get_rptr = &r600_dma_get_rptr,
1310 .get_wptr = &r600_dma_get_wptr,
1311 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1312};
1313
48e7a5f1
DV		 1314static struct radeon_asic evergreen_asic = {
1315 .init = &evergreen_init,
1316 .fini = &evergreen_fini,
1317 .suspend = &evergreen_suspend,
1318 .resume = &evergreen_resume,
a2d07b74 1319 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1320 .vga_set_state = &r600_vga_set_state,
124764f1 1321 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1322 .gui_idle = &r600_gui_idle,
1323 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1324 .get_xclk = &rv770_get_xclk,
d0418894 1325 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1326 .gart = {
1327 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1328 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1329 .set_page = &rs600_gart_set_page,
1330 },
4c87bc26 1331 .ring = {
76a0df85
CK		 1332 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1333 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1334 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1335 },
b35ea4ab
AD		 1336 .irq = {
1337 .set = &evergreen_irq_set,
1338 .process = &evergreen_irq_process,
1339 },
c79a49ca
AD		 1340 .display = {
1341 .bandwidth_update = &evergreen_bandwidth_update,
1342 .get_vblank_counter = &evergreen_get_vblank_counter,
1343 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1344 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1345 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1346 },
27cd7769 1347 .copy = {
8dddb993 1348 .blit = &r600_copy_cpdma,
27cd7769 1349 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1350 .dma = &evergreen_copy_dma,
1351 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1352 .copy = &evergreen_copy_dma,
1353 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1354 },
9e6f3d02
AD		 1355 .surface = {
1356 .set_reg = r600_set_surface_reg,
1357 .clear_reg = r600_clear_surface_reg,
1358 },
901ea57d
AD		 1359 .hpd = {
1360 .init = &evergreen_hpd_init,
1361 .fini = &evergreen_hpd_fini,
1362 .sense = &evergreen_hpd_sense,
1363 .set_polarity = &evergreen_hpd_set_polarity,
1364 },
a02fa397
AD		 1365 .pm = {
1366 .misc = &evergreen_pm_misc,
1367 .prepare = &evergreen_pm_prepare,
1368 .finish = &evergreen_pm_finish,
1369 .init_profile = &r600_pm_init_profile,
1370 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1371 .get_engine_clock = &radeon_atom_get_engine_clock,
1372 .set_engine_clock = &radeon_atom_set_engine_clock,
1373 .get_memory_clock = &radeon_atom_get_memory_clock,
1374 .set_memory_clock = &radeon_atom_set_memory_clock,
1375 .get_pcie_lanes = &r600_get_pcie_lanes,
1376 .set_pcie_lanes = &r600_set_pcie_lanes,
1377 .set_clock_gating = NULL,
a8b4925c 1378 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1379 .get_temperature = &evergreen_get_temp,
a02fa397 1380 },
dc50ba7f
AD		 1381 .dpm = {
1382 .init = &cypress_dpm_init,
1383 .setup_asic = &cypress_dpm_setup_asic,
1384 .enable = &cypress_dpm_enable,
a3f11245 1385 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1386 .disable = &cypress_dpm_disable,
98243917 1387 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1388 .set_power_state = &cypress_dpm_set_power_state,
98243917 1389 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1390 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1391 .fini = &cypress_dpm_fini,
1392 .get_sclk = &rv770_dpm_get_sclk,
1393 .get_mclk = &rv770_dpm_get_mclk,
1394 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1395 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1396 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1397 .vblank_too_short = &cypress_dpm_vblank_too_short,
dc50ba7f 1398 },
0f9e006c 1399 .pflip = {
0f9e006c 1400 .page_flip = &evergreen_page_flip,
157fa14d 1401 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1402 },
48e7a5f1
DV		 1403};
1404
958261d1
AD		 1405static struct radeon_asic sumo_asic = {
1406 .init = &evergreen_init,
1407 .fini = &evergreen_fini,
1408 .suspend = &evergreen_suspend,
1409 .resume = &evergreen_resume,
958261d1
AD		 1410 .asic_reset = &evergreen_asic_reset,
1411 .vga_set_state = &r600_vga_set_state,
124764f1 1412 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1413 .gui_idle = &r600_gui_idle,
1414 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1415 .get_xclk = &r600_get_xclk,
d0418894 1416 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1417 .gart = {
1418 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1419 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1420 .set_page = &rs600_gart_set_page,
1421 },
4c87bc26 1422 .ring = {
76a0df85
CK		 1423 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1424 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1425 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1426 },
b35ea4ab
AD		 1427 .irq = {
1428 .set = &evergreen_irq_set,
1429 .process = &evergreen_irq_process,
1430 },
c79a49ca
AD		 1431 .display = {
1432 .bandwidth_update = &evergreen_bandwidth_update,
1433 .get_vblank_counter = &evergreen_get_vblank_counter,
1434 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1435 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1436 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1437 },
27cd7769 1438 .copy = {
8dddb993 1439 .blit = &r600_copy_cpdma,
27cd7769 1440 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1441 .dma = &evergreen_copy_dma,
1442 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1443 .copy = &evergreen_copy_dma,
1444 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1445 },
9e6f3d02
AD		 1446 .surface = {
1447 .set_reg = r600_set_surface_reg,
1448 .clear_reg = r600_clear_surface_reg,
1449 },
901ea57d
AD		 1450 .hpd = {
1451 .init = &evergreen_hpd_init,
1452 .fini = &evergreen_hpd_fini,
1453 .sense = &evergreen_hpd_sense,
1454 .set_polarity = &evergreen_hpd_set_polarity,
1455 },
a02fa397
AD		 1456 .pm = {
1457 .misc = &evergreen_pm_misc,
1458 .prepare = &evergreen_pm_prepare,
1459 .finish = &evergreen_pm_finish,
1460 .init_profile = &sumo_pm_init_profile,
1461 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1462 .get_engine_clock = &radeon_atom_get_engine_clock,
1463 .set_engine_clock = &radeon_atom_set_engine_clock,
1464 .get_memory_clock = NULL,
1465 .set_memory_clock = NULL,
1466 .get_pcie_lanes = NULL,
1467 .set_pcie_lanes = NULL,
1468 .set_clock_gating = NULL,
23d33ba3 1469 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1470 .get_temperature = &sumo_get_temp,
a02fa397 1471 },
80ea2c12
AD		 1472 .dpm = {
1473 .init = &sumo_dpm_init,
1474 .setup_asic = &sumo_dpm_setup_asic,
1475 .enable = &sumo_dpm_enable,
14ec9fab 1476 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1477 .disable = &sumo_dpm_disable,
422a56bc 1478 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1479 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1480 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1481 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1482 .fini = &sumo_dpm_fini,
1483 .get_sclk = &sumo_dpm_get_sclk,
1484 .get_mclk = &sumo_dpm_get_mclk,
1485 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1486 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1487 .force_performance_level = &sumo_dpm_force_performance_level,
80ea2c12 1488 },
0f9e006c 1489 .pflip = {
0f9e006c 1490 .page_flip = &evergreen_page_flip,
157fa14d 1491 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1492 },
958261d1
AD		 1493};
1494
a43b7665
AD		 1495static struct radeon_asic btc_asic = {
1496 .init = &evergreen_init,
1497 .fini = &evergreen_fini,
1498 .suspend = &evergreen_suspend,
1499 .resume = &evergreen_resume,
a43b7665
AD		 1500 .asic_reset = &evergreen_asic_reset,
1501 .vga_set_state = &r600_vga_set_state,
124764f1 1502 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1503 .gui_idle = &r600_gui_idle,
1504 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1505 .get_xclk = &rv770_get_xclk,
d0418894 1506 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1507 .gart = {
1508 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1509 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1510 .set_page = &rs600_gart_set_page,
1511 },
4c87bc26 1512 .ring = {
76a0df85
CK		 1513 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1514 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1515 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1516 },
b35ea4ab
AD		 1517 .irq = {
1518 .set = &evergreen_irq_set,
1519 .process = &evergreen_irq_process,
1520 },
c79a49ca
AD		 1521 .display = {
1522 .bandwidth_update = &evergreen_bandwidth_update,
1523 .get_vblank_counter = &evergreen_get_vblank_counter,
1524 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1525 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1526 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1527 },
27cd7769 1528 .copy = {
8dddb993 1529 .blit = &r600_copy_cpdma,
27cd7769 1530 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1531 .dma = &evergreen_copy_dma,
1532 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1533 .copy = &evergreen_copy_dma,
1534 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1535 },
9e6f3d02
AD		 1536 .surface = {
1537 .set_reg = r600_set_surface_reg,
1538 .clear_reg = r600_clear_surface_reg,
1539 },
901ea57d
AD		 1540 .hpd = {
1541 .init = &evergreen_hpd_init,
1542 .fini = &evergreen_hpd_fini,
1543 .sense = &evergreen_hpd_sense,
1544 .set_polarity = &evergreen_hpd_set_polarity,
1545 },
a02fa397
AD		 1546 .pm = {
1547 .misc = &evergreen_pm_misc,
1548 .prepare = &evergreen_pm_prepare,
1549 .finish = &evergreen_pm_finish,
27810fb2 1550 .init_profile = &btc_pm_init_profile,
a02fa397 1551 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1552 .get_engine_clock = &radeon_atom_get_engine_clock,
1553 .set_engine_clock = &radeon_atom_set_engine_clock,
1554 .get_memory_clock = &radeon_atom_get_memory_clock,
1555 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1556 .get_pcie_lanes = &r600_get_pcie_lanes,
1557 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1558 .set_clock_gating = NULL,
a8b4925c 1559 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1560 .get_temperature = &evergreen_get_temp,
a02fa397 1561 },
6596afd4
AD		 1562 .dpm = {
1563 .init = &btc_dpm_init,
1564 .setup_asic = &btc_dpm_setup_asic,
1565 .enable = &btc_dpm_enable,
a3f11245 1566 .late_enable = &rv770_dpm_late_enable,
6596afd4 1567 .disable = &btc_dpm_disable,
e8a9539f 1568 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1569 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1570 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1571 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1572 .fini = &btc_dpm_fini,
e8a9539f
AD		 1573 .get_sclk = &btc_dpm_get_sclk,
1574 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1575 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1576 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1577 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1578 .vblank_too_short = &btc_dpm_vblank_too_short,
6596afd4 1579 },
0f9e006c 1580 .pflip = {
0f9e006c 1581 .page_flip = &evergreen_page_flip,
157fa14d 1582 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1583 },
a43b7665
AD		 1584};
1585
76a0df85
CK		 1586static struct radeon_asic_ring cayman_gfx_ring = {
1587 .ib_execute = &cayman_ring_ib_execute,
1588 .ib_parse = &evergreen_ib_parse,
1589 .emit_fence = &cayman_fence_ring_emit,
1590 .emit_semaphore = &r600_semaphore_ring_emit,
1591 .cs_parse = &evergreen_cs_parse,
1592 .ring_test = &r600_ring_test,
1593 .ib_test = &r600_ib_test,
1594 .is_lockup = &cayman_gfx_is_lockup,
1595 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1596 .get_rptr = &cayman_gfx_get_rptr,
1597 .get_wptr = &cayman_gfx_get_wptr,
1598 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1599};
1600
1601static struct radeon_asic_ring cayman_dma_ring = {
1602 .ib_execute = &cayman_dma_ring_ib_execute,
1603 .ib_parse = &evergreen_dma_ib_parse,
1604 .emit_fence = &evergreen_dma_fence_ring_emit,
1605 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1606 .cs_parse = &evergreen_dma_cs_parse,
1607 .ring_test = &r600_dma_ring_test,
1608 .ib_test = &r600_dma_ib_test,
1609 .is_lockup = &cayman_dma_is_lockup,
1610 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1611 .get_rptr = &cayman_dma_get_rptr,
1612 .get_wptr = &cayman_dma_get_wptr,
1613 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1614};
1615
1616static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1617 .ib_execute = &uvd_v1_0_ib_execute,
1618 .emit_fence = &uvd_v2_2_fence_emit,
1619 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1620 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1621 .ring_test = &uvd_v1_0_ring_test,
1622 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1623 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1624 .get_rptr = &uvd_v1_0_get_rptr,
1625 .get_wptr = &uvd_v1_0_get_wptr,
1626 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1627};
1628
e3487629
AD		 1629static struct radeon_asic cayman_asic = {
1630 .init = &cayman_init,
1631 .fini = &cayman_fini,
1632 .suspend = &cayman_suspend,
1633 .resume = &cayman_resume,
e3487629
AD		 1634 .asic_reset = &cayman_asic_reset,
1635 .vga_set_state = &r600_vga_set_state,
124764f1 1636 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1637 .gui_idle = &r600_gui_idle,
1638 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1639 .get_xclk = &rv770_get_xclk,
d0418894 1640 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1641 .gart = {
1642 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1643 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1644 .set_page = &rs600_gart_set_page,
1645 },
05b07147
CK		 1646 .vm = {
1647 .init = &cayman_vm_init,
1648 .fini = &cayman_vm_fini,
03f62abd
CK		 1649 .copy_pages = &cayman_dma_vm_copy_pages,
1650 .write_pages = &cayman_dma_vm_write_pages,
1651 .set_pages = &cayman_dma_vm_set_pages,
1652 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1653 },
4c87bc26 1654 .ring = {
76a0df85
CK		 1655 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1656 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1657 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1658 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1659 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1660 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1661 },
b35ea4ab
AD		 1662 .irq = {
1663 .set = &evergreen_irq_set,
1664 .process = &evergreen_irq_process,
1665 },
c79a49ca
AD		 1666 .display = {
1667 .bandwidth_update = &evergreen_bandwidth_update,
1668 .get_vblank_counter = &evergreen_get_vblank_counter,
1669 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1670 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1671 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1672 },
27cd7769 1673 .copy = {
8dddb993 1674 .blit = &r600_copy_cpdma,
27cd7769 1675 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1676 .dma = &evergreen_copy_dma,
1677 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1678 .copy = &evergreen_copy_dma,
1679 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1680 },
9e6f3d02
AD		 1681 .surface = {
1682 .set_reg = r600_set_surface_reg,
1683 .clear_reg = r600_clear_surface_reg,
1684 },
901ea57d
AD		 1685 .hpd = {
1686 .init = &evergreen_hpd_init,
1687 .fini = &evergreen_hpd_fini,
1688 .sense = &evergreen_hpd_sense,
1689 .set_polarity = &evergreen_hpd_set_polarity,
1690 },
a02fa397
AD		 1691 .pm = {
1692 .misc = &evergreen_pm_misc,
1693 .prepare = &evergreen_pm_prepare,
1694 .finish = &evergreen_pm_finish,
27810fb2 1695 .init_profile = &btc_pm_init_profile,
a02fa397 1696 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1697 .get_engine_clock = &radeon_atom_get_engine_clock,
1698 .set_engine_clock = &radeon_atom_set_engine_clock,
1699 .get_memory_clock = &radeon_atom_get_memory_clock,
1700 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1701 .get_pcie_lanes = &r600_get_pcie_lanes,
1702 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1703 .set_clock_gating = NULL,
a8b4925c 1704 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1705 .get_temperature = &evergreen_get_temp,
a02fa397 1706 },
69e0b57a
AD		 1707 .dpm = {
1708 .init = &ni_dpm_init,
1709 .setup_asic = &ni_dpm_setup_asic,
1710 .enable = &ni_dpm_enable,
a3f11245 1711 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1712 .disable = &ni_dpm_disable,
fee3d744 1713 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1714 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1715 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1716 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1717 .fini = &ni_dpm_fini,
1718 .get_sclk = &ni_dpm_get_sclk,
1719 .get_mclk = &ni_dpm_get_mclk,
1720 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1721 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1722 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1723 .vblank_too_short = &ni_dpm_vblank_too_short,
69e0b57a 1724 },
0f9e006c 1725 .pflip = {
0f9e006c 1726 .page_flip = &evergreen_page_flip,
157fa14d 1727 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1728 },
e3487629
AD		 1729};
1730
be63fe8c
AD		 1731static struct radeon_asic trinity_asic = {
1732 .init = &cayman_init,
1733 .fini = &cayman_fini,
1734 .suspend = &cayman_suspend,
1735 .resume = &cayman_resume,
be63fe8c
AD		 1736 .asic_reset = &cayman_asic_reset,
1737 .vga_set_state = &r600_vga_set_state,
124764f1 1738 .mmio_hdp_flush = r600_mmio_hdp_flush,
be63fe8c
AD		 1739 .gui_idle = &r600_gui_idle,
1740 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1741 .get_xclk = &r600_get_xclk,
d0418894 1742 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1743 .gart = {
1744 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1745 .get_page_entry = &rs600_gart_get_page_entry,
be63fe8c
AD		 1746 .set_page = &rs600_gart_set_page,
1747 },
05b07147
CK		 1748 .vm = {
1749 .init = &cayman_vm_init,
1750 .fini = &cayman_vm_fini,
03f62abd
CK		 1751 .copy_pages = &cayman_dma_vm_copy_pages,
1752 .write_pages = &cayman_dma_vm_write_pages,
1753 .set_pages = &cayman_dma_vm_set_pages,
1754 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1755 },
be63fe8c 1756 .ring = {
76a0df85
CK		 1757 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1758 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1759 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1760 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1761 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1762 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1763 },
1764 .irq = {
1765 .set = &evergreen_irq_set,
1766 .process = &evergreen_irq_process,
1767 },
1768 .display = {
1769 .bandwidth_update = &dce6_bandwidth_update,
1770 .get_vblank_counter = &evergreen_get_vblank_counter,
1771 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1772 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1773 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 1774 },
1775 .copy = {
8dddb993 1776 .blit = &r600_copy_cpdma,
be63fe8c 1777 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1778 .dma = &evergreen_copy_dma,
1779 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1780 .copy = &evergreen_copy_dma,
1781 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1782 },
1783 .surface = {
1784 .set_reg = r600_set_surface_reg,
1785 .clear_reg = r600_clear_surface_reg,
1786 },
1787 .hpd = {
1788 .init = &evergreen_hpd_init,
1789 .fini = &evergreen_hpd_fini,
1790 .sense = &evergreen_hpd_sense,
1791 .set_polarity = &evergreen_hpd_set_polarity,
1792 },
1793 .pm = {
1794 .misc = &evergreen_pm_misc,
1795 .prepare = &evergreen_pm_prepare,
1796 .finish = &evergreen_pm_finish,
1797 .init_profile = &sumo_pm_init_profile,
1798 .get_dynpm_state = &r600_pm_get_dynpm_state,
1799 .get_engine_clock = &radeon_atom_get_engine_clock,
1800 .set_engine_clock = &radeon_atom_set_engine_clock,
1801 .get_memory_clock = NULL,
1802 .set_memory_clock = NULL,
1803 .get_pcie_lanes = NULL,
1804 .set_pcie_lanes = NULL,
1805 .set_clock_gating = NULL,
23d33ba3 1806 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1807 .get_temperature = &tn_get_temp,
be63fe8c 1808 },
d70229f7
AD		 1809 .dpm = {
1810 .init = &trinity_dpm_init,
1811 .setup_asic = &trinity_dpm_setup_asic,
1812 .enable = &trinity_dpm_enable,
bda44c1a 1813 .late_enable = &trinity_dpm_late_enable,
d70229f7 1814 .disable = &trinity_dpm_disable,
a284c48a 1815 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1816 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1817 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1818 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1819 .fini = &trinity_dpm_fini,
1820 .get_sclk = &trinity_dpm_get_sclk,
1821 .get_mclk = &trinity_dpm_get_mclk,
1822 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1823 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1824 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1825 .enable_bapm = &trinity_dpm_enable_bapm,
d70229f7 1826 },
be63fe8c 1827 .pflip = {
be63fe8c 1828 .page_flip = &evergreen_page_flip,
157fa14d 1829 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1830 },
1831};
1832
76a0df85
CK		 1833static struct radeon_asic_ring si_gfx_ring = {
1834 .ib_execute = &si_ring_ib_execute,
1835 .ib_parse = &si_ib_parse,
1836 .emit_fence = &si_fence_ring_emit,
1837 .emit_semaphore = &r600_semaphore_ring_emit,
1838 .cs_parse = NULL,
1839 .ring_test = &r600_ring_test,
1840 .ib_test = &r600_ib_test,
1841 .is_lockup = &si_gfx_is_lockup,
1842 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1843 .get_rptr = &cayman_gfx_get_rptr,
1844 .get_wptr = &cayman_gfx_get_wptr,
1845 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1846};
1847
1848static struct radeon_asic_ring si_dma_ring = {
1849 .ib_execute = &cayman_dma_ring_ib_execute,
1850 .ib_parse = &evergreen_dma_ib_parse,
1851 .emit_fence = &evergreen_dma_fence_ring_emit,
1852 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1853 .cs_parse = NULL,
1854 .ring_test = &r600_dma_ring_test,
1855 .ib_test = &r600_dma_ib_test,
1856 .is_lockup = &si_dma_is_lockup,
1857 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1858 .get_rptr = &cayman_dma_get_rptr,
1859 .get_wptr = &cayman_dma_get_wptr,
1860 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1861};
1862
02779c08
AD		 1863static struct radeon_asic si_asic = {
1864 .init = &si_init,
1865 .fini = &si_fini,
1866 .suspend = &si_suspend,
1867 .resume = &si_resume,
02779c08
AD		 1868 .asic_reset = &si_asic_reset,
1869 .vga_set_state = &r600_vga_set_state,
124764f1 1870 .mmio_hdp_flush = r600_mmio_hdp_flush,
02779c08
AD		 1871 .gui_idle = &r600_gui_idle,
1872 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1873 .get_xclk = &si_get_xclk,
d0418894 1874 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1875 .gart = {
1876 .tlb_flush = &si_pcie_gart_tlb_flush,
cb658906 1877 .get_page_entry = &rs600_gart_get_page_entry,
02779c08
AD		 1878 .set_page = &rs600_gart_set_page,
1879 },
05b07147
CK		 1880 .vm = {
1881 .init = &si_vm_init,
1882 .fini = &si_vm_fini,
03f62abd
CK		 1883 .copy_pages = &si_dma_vm_copy_pages,
1884 .write_pages = &si_dma_vm_write_pages,
1885 .set_pages = &si_dma_vm_set_pages,
1886 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1887 },
02779c08 1888 .ring = {
76a0df85
CK		 1889 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1890 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1891 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1892 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1893 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1894 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1895 },
1896 .irq = {
1897 .set = &si_irq_set,
1898 .process = &si_irq_process,
1899 },
1900 .display = {
1901 .bandwidth_update = &dce6_bandwidth_update,
1902 .get_vblank_counter = &evergreen_get_vblank_counter,
1903 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1904 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1905 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 1906 },
1907 .copy = {
5c722739 1908 .blit = &r600_copy_cpdma,
02779c08 1909 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1910 .dma = &si_copy_dma,
1911 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1912 .copy = &si_copy_dma,
1913 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1914 },
1915 .surface = {
1916 .set_reg = r600_set_surface_reg,
1917 .clear_reg = r600_clear_surface_reg,
1918 },
1919 .hpd = {
1920 .init = &evergreen_hpd_init,
1921 .fini = &evergreen_hpd_fini,
1922 .sense = &evergreen_hpd_sense,
1923 .set_polarity = &evergreen_hpd_set_polarity,
1924 },
1925 .pm = {
1926 .misc = &evergreen_pm_misc,
1927 .prepare = &evergreen_pm_prepare,
1928 .finish = &evergreen_pm_finish,
1929 .init_profile = &sumo_pm_init_profile,
1930 .get_dynpm_state = &r600_pm_get_dynpm_state,
1931 .get_engine_clock = &radeon_atom_get_engine_clock,
1932 .set_engine_clock = &radeon_atom_set_engine_clock,
1933 .get_memory_clock = &radeon_atom_get_memory_clock,
1934 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1935 .get_pcie_lanes = &r600_get_pcie_lanes,
1936 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1937 .set_clock_gating = NULL,
2539eb02 1938 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1939 .get_temperature = &si_get_temp,
02779c08 1940 },
a9e61410
AD		 1941 .dpm = {
1942 .init = &si_dpm_init,
1943 .setup_asic = &si_dpm_setup_asic,
1944 .enable = &si_dpm_enable,
963c115d 1945 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1946 .disable = &si_dpm_disable,
1947 .pre_set_power_state = &si_dpm_pre_set_power_state,
1948 .set_power_state = &si_dpm_set_power_state,
1949 .post_set_power_state = &si_dpm_post_set_power_state,
1950 .display_configuration_changed = &si_dpm_display_configuration_changed,
1951 .fini = &si_dpm_fini,
1952 .get_sclk = &ni_dpm_get_sclk,
1953 .get_mclk = &ni_dpm_get_mclk,
1954 .print_power_state = &ni_dpm_print_power_state,
7982128c 1955 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1956 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1957 .vblank_too_short = &ni_dpm_vblank_too_short,
5e8150a6
AD		 1958 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1959 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1960 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1961 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
a9e61410 1962 },
02779c08 1963 .pflip = {
02779c08 1964 .page_flip = &evergreen_page_flip,
157fa14d 1965 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 1966 },
1967};
1968
76a0df85
CK		 1969static struct radeon_asic_ring ci_gfx_ring = {
1970 .ib_execute = &cik_ring_ib_execute,
1971 .ib_parse = &cik_ib_parse,
1972 .emit_fence = &cik_fence_gfx_ring_emit,
1973 .emit_semaphore = &cik_semaphore_ring_emit,
1974 .cs_parse = NULL,
1975 .ring_test = &cik_ring_test,
1976 .ib_test = &cik_ib_test,
1977 .is_lockup = &cik_gfx_is_lockup,
1978 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1979 .get_rptr = &cik_gfx_get_rptr,
1980 .get_wptr = &cik_gfx_get_wptr,
1981 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 1982};
1983
1984static struct radeon_asic_ring ci_cp_ring = {
1985 .ib_execute = &cik_ring_ib_execute,
1986 .ib_parse = &cik_ib_parse,
1987 .emit_fence = &cik_fence_compute_ring_emit,
1988 .emit_semaphore = &cik_semaphore_ring_emit,
1989 .cs_parse = NULL,
1990 .ring_test = &cik_ring_test,
1991 .ib_test = &cik_ib_test,
1992 .is_lockup = &cik_gfx_is_lockup,
1993 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1994 .get_rptr = &cik_compute_get_rptr,
1995 .get_wptr = &cik_compute_get_wptr,
1996 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 1997};
1998
1999static struct radeon_asic_ring ci_dma_ring = {
2000 .ib_execute = &cik_sdma_ring_ib_execute,
2001 .ib_parse = &cik_ib_parse,
2002 .emit_fence = &cik_sdma_fence_ring_emit,
2003 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2004 .cs_parse = NULL,
2005 .ring_test = &cik_sdma_ring_test,
2006 .ib_test = &cik_sdma_ib_test,
2007 .is_lockup = &cik_sdma_is_lockup,
2008 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 2009 .get_rptr = &cik_sdma_get_rptr,
2010 .get_wptr = &cik_sdma_get_wptr,
2011 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 2012};
2013
d93f7937
CK		 2014static struct radeon_asic_ring ci_vce_ring = {
2015 .ib_execute = &radeon_vce_ib_execute,
2016 .emit_fence = &radeon_vce_fence_emit,
2017 .emit_semaphore = &radeon_vce_semaphore_emit,
2018 .cs_parse = &radeon_vce_cs_parse,
2019 .ring_test = &radeon_vce_ring_test,
2020 .ib_test = &radeon_vce_ib_test,
2021 .is_lockup = &radeon_ring_test_lockup,
2022 .get_rptr = &vce_v1_0_get_rptr,
2023 .get_wptr = &vce_v1_0_get_wptr,
2024 .set_wptr = &vce_v1_0_set_wptr,
2025};
2026
0672e27b
AD		 2027static struct radeon_asic ci_asic = {
2028 .init = &cik_init,
2029 .fini = &cik_fini,
2030 .suspend = &cik_suspend,
2031 .resume = &cik_resume,
2032 .asic_reset = &cik_asic_reset,
2033 .vga_set_state = &r600_vga_set_state,
72a9987e 2034 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2035 .gui_idle = &r600_gui_idle,
2036 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2037 .get_xclk = &cik_get_xclk,
2038 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2039 .gart = {
2040 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2041 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2042 .set_page = &rs600_gart_set_page,
2043 },
2044 .vm = {
2045 .init = &cik_vm_init,
2046 .fini = &cik_vm_fini,
03f62abd
CK		 2047 .copy_pages = &cik_sdma_vm_copy_pages,
2048 .write_pages = &cik_sdma_vm_write_pages,
2049 .set_pages = &cik_sdma_vm_set_pages,
2050 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2051 },
2052 .ring = {
76a0df85
CK		 2053 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2054 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2055 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2056 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2057 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2058 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2059 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2060 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2061 },
2062 .irq = {
2063 .set = &cik_irq_set,
2064 .process = &cik_irq_process,
2065 },
2066 .display = {
2067 .bandwidth_update = &dce8_bandwidth_update,
2068 .get_vblank_counter = &evergreen_get_vblank_counter,
2069 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2070 .set_backlight_level = &atombios_set_backlight_level,
2071 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2072 },
2073 .copy = {
7819678f 2074 .blit = &cik_copy_cpdma,
0672e27b
AD		 2075 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2076 .dma = &cik_copy_dma,
2077 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2078 .copy = &cik_copy_dma,
2079 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2080 },
2081 .surface = {
2082 .set_reg = r600_set_surface_reg,
2083 .clear_reg = r600_clear_surface_reg,
2084 },
2085 .hpd = {
2086 .init = &evergreen_hpd_init,
2087 .fini = &evergreen_hpd_fini,
2088 .sense = &evergreen_hpd_sense,
2089 .set_polarity = &evergreen_hpd_set_polarity,
2090 },
2091 .pm = {
2092 .misc = &evergreen_pm_misc,
2093 .prepare = &evergreen_pm_prepare,
2094 .finish = &evergreen_pm_finish,
2095 .init_profile = &sumo_pm_init_profile,
2096 .get_dynpm_state = &r600_pm_get_dynpm_state,
2097 .get_engine_clock = &radeon_atom_get_engine_clock,
2098 .set_engine_clock = &radeon_atom_set_engine_clock,
2099 .get_memory_clock = &radeon_atom_get_memory_clock,
2100 .set_memory_clock = &radeon_atom_set_memory_clock,
2101 .get_pcie_lanes = NULL,
2102 .set_pcie_lanes = NULL,
2103 .set_clock_gating = NULL,
2104 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2105 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2106 .get_temperature = &ci_get_temp,
0672e27b 2107 },
cc8dbbb4
AD		 2108 .dpm = {
2109 .init = &ci_dpm_init,
2110 .setup_asic = &ci_dpm_setup_asic,
2111 .enable = &ci_dpm_enable,
90208427 2112 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2113 .disable = &ci_dpm_disable,
2114 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2115 .set_power_state = &ci_dpm_set_power_state,
2116 .post_set_power_state = &ci_dpm_post_set_power_state,
2117 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2118 .fini = &ci_dpm_fini,
2119 .get_sclk = &ci_dpm_get_sclk,
2120 .get_mclk = &ci_dpm_get_mclk,
2121 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2122 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2123 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2124 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2125 .powergate_uvd = &ci_dpm_powergate_uvd,
36689e57
OC		 2126 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2127 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2128 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2129 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
cc8dbbb4 2130 },
0672e27b 2131 .pflip = {
0672e27b 2132 .page_flip = &evergreen_page_flip,
157fa14d 2133 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2134 },
2135};
2136
2137static struct radeon_asic kv_asic = {
2138 .init = &cik_init,
2139 .fini = &cik_fini,
2140 .suspend = &cik_suspend,
2141 .resume = &cik_resume,
2142 .asic_reset = &cik_asic_reset,
2143 .vga_set_state = &r600_vga_set_state,
72a9987e 2144 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2145 .gui_idle = &r600_gui_idle,
2146 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2147 .get_xclk = &cik_get_xclk,
2148 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2149 .gart = {
2150 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2151 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2152 .set_page = &rs600_gart_set_page,
2153 },
2154 .vm = {
2155 .init = &cik_vm_init,
2156 .fini = &cik_vm_fini,
03f62abd
CK		 2157 .copy_pages = &cik_sdma_vm_copy_pages,
2158 .write_pages = &cik_sdma_vm_write_pages,
2159 .set_pages = &cik_sdma_vm_set_pages,
2160 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2161 },
2162 .ring = {
76a0df85
CK		 2163 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2164 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2165 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2166 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2167 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2168 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2169 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2170 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2171 },
2172 .irq = {
2173 .set = &cik_irq_set,
2174 .process = &cik_irq_process,
2175 },
2176 .display = {
2177 .bandwidth_update = &dce8_bandwidth_update,
2178 .get_vblank_counter = &evergreen_get_vblank_counter,
2179 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2180 .set_backlight_level = &atombios_set_backlight_level,
2181 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2182 },
2183 .copy = {
7819678f 2184 .blit = &cik_copy_cpdma,
0672e27b
AD		 2185 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2186 .dma = &cik_copy_dma,
2187 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2188 .copy = &cik_copy_dma,
2189 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2190 },
2191 .surface = {
2192 .set_reg = r600_set_surface_reg,
2193 .clear_reg = r600_clear_surface_reg,
2194 },
2195 .hpd = {
2196 .init = &evergreen_hpd_init,
2197 .fini = &evergreen_hpd_fini,
2198 .sense = &evergreen_hpd_sense,
2199 .set_polarity = &evergreen_hpd_set_polarity,
2200 },
2201 .pm = {
2202 .misc = &evergreen_pm_misc,
2203 .prepare = &evergreen_pm_prepare,
2204 .finish = &evergreen_pm_finish,
2205 .init_profile = &sumo_pm_init_profile,
2206 .get_dynpm_state = &r600_pm_get_dynpm_state,
2207 .get_engine_clock = &radeon_atom_get_engine_clock,
2208 .set_engine_clock = &radeon_atom_set_engine_clock,
2209 .get_memory_clock = &radeon_atom_get_memory_clock,
2210 .set_memory_clock = &radeon_atom_set_memory_clock,
2211 .get_pcie_lanes = NULL,
2212 .set_pcie_lanes = NULL,
2213 .set_clock_gating = NULL,
2214 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2215 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2216 .get_temperature = &kv_get_temp,
0672e27b 2217 },
41a524ab
AD		 2218 .dpm = {
2219 .init = &kv_dpm_init,
2220 .setup_asic = &kv_dpm_setup_asic,
2221 .enable = &kv_dpm_enable,
d8852c34 2222 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2223 .disable = &kv_dpm_disable,
2224 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2225 .set_power_state = &kv_dpm_set_power_state,
2226 .post_set_power_state = &kv_dpm_post_set_power_state,
2227 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2228 .fini = &kv_dpm_fini,
2229 .get_sclk = &kv_dpm_get_sclk,
2230 .get_mclk = &kv_dpm_get_mclk,
2231 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2232 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2233 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2234 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2235 .enable_bapm = &kv_dpm_enable_bapm,
41a524ab 2236 },
0672e27b 2237 .pflip = {
0672e27b 2238 .page_flip = &evergreen_page_flip,
157fa14d 2239 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2240 },
2241};
2242
abf1dc67
AD		 2243/**
2244 * radeon_asic_init - register asic specific callbacks
2245 *
2246 * @rdev: radeon device pointer
2247 *
2248 * Registers the appropriate asic specific callbacks for each
2249 * chip family. Also sets other asics specific info like the number
2250 * of crtcs and the register aperture accessors (all asics).
2251 * Returns 0 for success.
2252 */
0a10c851
DV		 2253int radeon_asic_init(struct radeon_device *rdev)
2254{
2255 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2256
2257 /* set the number of crtcs */
2258 if (rdev->flags & RADEON_SINGLE_CRTC)
2259 rdev->num_crtc = 1;
2260 else
2261 rdev->num_crtc = 2;
2262
948bee3f
AD		 2263 rdev->has_uvd = false;
2264
0a10c851
DV		 2265 switch (rdev->family) {
2266 case CHIP_R100:
2267 case CHIP_RV100:
2268 case CHIP_RS100:
2269 case CHIP_RV200:
2270 case CHIP_RS200:
2271 rdev->asic = &r100_asic;
2272 break;
2273 case CHIP_R200:
2274 case CHIP_RV250:
2275 case CHIP_RS300:
2276 case CHIP_RV280:
2277 rdev->asic = &r200_asic;
2278 break;
2279 case CHIP_R300:
2280 case CHIP_R350:
2281 case CHIP_RV350:
2282 case CHIP_RV380:
2283 if (rdev->flags & RADEON_IS_PCIE)
2284 rdev->asic = &r300_asic_pcie;
2285 else
2286 rdev->asic = &r300_asic;
2287 break;
2288 case CHIP_R420:
2289 case CHIP_R423:
2290 case CHIP_RV410:
2291 rdev->asic = &r420_asic;
07bb084c
AD		 2292 /* handle macs */
2293 if (rdev->bios == NULL) {
798bcf73
AD		 2294 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2295 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2296 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2297 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2298 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2299 }
0a10c851
DV		 2300 break;
2301 case CHIP_RS400:
2302 case CHIP_RS480:
2303 rdev->asic = &rs400_asic;
2304 break;
2305 case CHIP_RS600:
2306 rdev->asic = &rs600_asic;
2307 break;
2308 case CHIP_RS690:
2309 case CHIP_RS740:
2310 rdev->asic = &rs690_asic;
2311 break;
2312 case CHIP_RV515:
2313 rdev->asic = &rv515_asic;
2314 break;
2315 case CHIP_R520:
2316 case CHIP_RV530:
2317 case CHIP_RV560:
2318 case CHIP_RV570:
2319 case CHIP_R580:
2320 rdev->asic = &r520_asic;
2321 break;
2322 case CHIP_R600:
ca361b65
AD		 2323 rdev->asic = &r600_asic;
2324 break;
0a10c851
DV		 2325 case CHIP_RV610:
2326 case CHIP_RV630:
2327 case CHIP_RV620:
2328 case CHIP_RV635:
2329 case CHIP_RV670:
ca361b65
AD		 2330 rdev->asic = &rv6xx_asic;
2331 rdev->has_uvd = true;
f47299c5 2332 break;
0a10c851
DV		 2333 case CHIP_RS780:
2334 case CHIP_RS880:
f47299c5 2335 rdev->asic = &rs780_asic;
bdc99722
AD		 2336 /* 760G/780V/880V don't have UVD */
2337 if ((rdev->pdev->device == 0x9616)||
2338 (rdev->pdev->device == 0x9611)||
2339 (rdev->pdev->device == 0x9613)||
2340 (rdev->pdev->device == 0x9711)||
2341 (rdev->pdev->device == 0x9713))
2342 rdev->has_uvd = false;
2343 else
2344 rdev->has_uvd = true;
0a10c851
DV		 2345 break;
2346 case CHIP_RV770:
2347 case CHIP_RV730:
2348 case CHIP_RV710:
2349 case CHIP_RV740:
2350 rdev->asic = &rv770_asic;
948bee3f 2351 rdev->has_uvd = true;
0a10c851
DV		 2352 break;
2353 case CHIP_CEDAR:
2354 case CHIP_REDWOOD:
2355 case CHIP_JUNIPER:
2356 case CHIP_CYPRESS:
2357 case CHIP_HEMLOCK:
ba7e05e9
AD		 2358 /* set num crtcs */
2359 if (rdev->family == CHIP_CEDAR)
2360 rdev->num_crtc = 4;
2361 else
2362 rdev->num_crtc = 6;
0a10c851 2363 rdev->asic = &evergreen_asic;
948bee3f 2364 rdev->has_uvd = true;
0a10c851 2365 break;
958261d1 2366 case CHIP_PALM:
89da5a37
AD		 2367 case CHIP_SUMO:
2368 case CHIP_SUMO2:
958261d1 2369 rdev->asic = &sumo_asic;
948bee3f 2370 rdev->has_uvd = true;
958261d1 2371 break;
a43b7665
AD		 2372 case CHIP_BARTS:
2373 case CHIP_TURKS:
2374 case CHIP_CAICOS:
ba7e05e9
AD		 2375 /* set num crtcs */
2376 if (rdev->family == CHIP_CAICOS)
2377 rdev->num_crtc = 4;
2378 else
2379 rdev->num_crtc = 6;
a43b7665 2380 rdev->asic = &btc_asic;
948bee3f 2381 rdev->has_uvd = true;
a43b7665 2382 break;
e3487629
AD		 2383 case CHIP_CAYMAN:
2384 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2385 /* set num crtcs */
2386 rdev->num_crtc = 6;
948bee3f 2387 rdev->has_uvd = true;
e3487629 2388 break;
be63fe8c
AD		 2389 case CHIP_ARUBA:
2390 rdev->asic = &trinity_asic;
2391 /* set num crtcs */
2392 rdev->num_crtc = 4;
948bee3f 2393 rdev->has_uvd = true;
be63fe8c 2394 break;
02779c08
AD		 2395 case CHIP_TAHITI:
2396 case CHIP_PITCAIRN:
2397 case CHIP_VERDE:
e737a14c 2398 case CHIP_OLAND:
86a45cac 2399 case CHIP_HAINAN:
02779c08
AD		 2400 rdev->asic = &si_asic;
2401 /* set num crtcs */
86a45cac
AD		 2402 if (rdev->family == CHIP_HAINAN)
2403 rdev->num_crtc = 0;
2404 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2405 rdev->num_crtc = 2;
2406 else
2407 rdev->num_crtc = 6;
948bee3f
AD		 2408 if (rdev->family == CHIP_HAINAN)
2409 rdev->has_uvd = false;
2410 else
2411 rdev->has_uvd = true;
0116e1ef
AD		 2412 switch (rdev->family) {
2413 case CHIP_TAHITI:
2414 rdev->cg_flags =
090f4b6a 2415 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2416 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2417 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2418 RADEON_CG_SUPPORT_GFX_CGLS |
2419 RADEON_CG_SUPPORT_GFX_CGTS |
2420 RADEON_CG_SUPPORT_GFX_CP_LS |
2421 RADEON_CG_SUPPORT_MC_MGCG |
2422 RADEON_CG_SUPPORT_SDMA_MGCG |
2423 RADEON_CG_SUPPORT_BIF_LS |
2424 RADEON_CG_SUPPORT_VCE_MGCG |
2425 RADEON_CG_SUPPORT_UVD_MGCG |
2426 RADEON_CG_SUPPORT_HDP_LS |
2427 RADEON_CG_SUPPORT_HDP_MGCG;
2428 rdev->pg_flags = 0;
2429 break;
2430 case CHIP_PITCAIRN:
2431 rdev->cg_flags =
090f4b6a 2432 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2433 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2434 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2435 RADEON_CG_SUPPORT_GFX_CGLS |
2436 RADEON_CG_SUPPORT_GFX_CGTS |
2437 RADEON_CG_SUPPORT_GFX_CP_LS |
2438 RADEON_CG_SUPPORT_GFX_RLC_LS |
2439 RADEON_CG_SUPPORT_MC_LS |
2440 RADEON_CG_SUPPORT_MC_MGCG |
2441 RADEON_CG_SUPPORT_SDMA_MGCG |
2442 RADEON_CG_SUPPORT_BIF_LS |
2443 RADEON_CG_SUPPORT_VCE_MGCG |
2444 RADEON_CG_SUPPORT_UVD_MGCG |
2445 RADEON_CG_SUPPORT_HDP_LS |
2446 RADEON_CG_SUPPORT_HDP_MGCG;
2447 rdev->pg_flags = 0;
2448 break;
2449 case CHIP_VERDE:
2450 rdev->cg_flags =
090f4b6a 2451 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2452 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2453 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2454 RADEON_CG_SUPPORT_GFX_CGLS |
2455 RADEON_CG_SUPPORT_GFX_CGTS |
2456 RADEON_CG_SUPPORT_GFX_CP_LS |
2457 RADEON_CG_SUPPORT_GFX_RLC_LS |
2458 RADEON_CG_SUPPORT_MC_LS |
2459 RADEON_CG_SUPPORT_MC_MGCG |
2460 RADEON_CG_SUPPORT_SDMA_MGCG |
2461 RADEON_CG_SUPPORT_BIF_LS |
2462 RADEON_CG_SUPPORT_VCE_MGCG |
2463 RADEON_CG_SUPPORT_UVD_MGCG |
2464 RADEON_CG_SUPPORT_HDP_LS |
2465 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2466 rdev->pg_flags = 0 |
2b19d17f 2467 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2468 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2469 break;
2470 case CHIP_OLAND:
2471 rdev->cg_flags =
090f4b6a 2472 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2473 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2474 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2475 RADEON_CG_SUPPORT_GFX_CGLS |
2476 RADEON_CG_SUPPORT_GFX_CGTS |
2477 RADEON_CG_SUPPORT_GFX_CP_LS |
2478 RADEON_CG_SUPPORT_GFX_RLC_LS |
2479 RADEON_CG_SUPPORT_MC_LS |
2480 RADEON_CG_SUPPORT_MC_MGCG |
2481 RADEON_CG_SUPPORT_SDMA_MGCG |
2482 RADEON_CG_SUPPORT_BIF_LS |
2483 RADEON_CG_SUPPORT_UVD_MGCG |
2484 RADEON_CG_SUPPORT_HDP_LS |
2485 RADEON_CG_SUPPORT_HDP_MGCG;
2486 rdev->pg_flags = 0;
2487 break;
2488 case CHIP_HAINAN:
2489 rdev->cg_flags =
090f4b6a 2490 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2491 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2492 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2493 RADEON_CG_SUPPORT_GFX_CGLS |
2494 RADEON_CG_SUPPORT_GFX_CGTS |
2495 RADEON_CG_SUPPORT_GFX_CP_LS |
2496 RADEON_CG_SUPPORT_GFX_RLC_LS |
2497 RADEON_CG_SUPPORT_MC_LS |
2498 RADEON_CG_SUPPORT_MC_MGCG |
2499 RADEON_CG_SUPPORT_SDMA_MGCG |
2500 RADEON_CG_SUPPORT_BIF_LS |
2501 RADEON_CG_SUPPORT_HDP_LS |
2502 RADEON_CG_SUPPORT_HDP_MGCG;
2503 rdev->pg_flags = 0;
2504 break;
2505 default:
2506 rdev->cg_flags = 0;
2507 rdev->pg_flags = 0;
2508 break;
2509 }
02779c08 2510 break;
0672e27b 2511 case CHIP_BONAIRE:
41971b37 2512 case CHIP_HAWAII:
0672e27b
AD		 2513 rdev->asic = &ci_asic;
2514 rdev->num_crtc = 6;
22c775ce 2515 rdev->has_uvd = true;
41971b37
AD		 2516 if (rdev->family == CHIP_BONAIRE) {
2517 rdev->cg_flags =
2518 RADEON_CG_SUPPORT_GFX_MGCG |
2519 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2520 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2521 RADEON_CG_SUPPORT_GFX_CGLS |
2522 RADEON_CG_SUPPORT_GFX_CGTS |
2523 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2524 RADEON_CG_SUPPORT_GFX_CP_LS |
2525 RADEON_CG_SUPPORT_MC_LS |
2526 RADEON_CG_SUPPORT_MC_MGCG |
2527 RADEON_CG_SUPPORT_SDMA_MGCG |
2528 RADEON_CG_SUPPORT_SDMA_LS |
2529 RADEON_CG_SUPPORT_BIF_LS |
2530 RADEON_CG_SUPPORT_VCE_MGCG |
2531 RADEON_CG_SUPPORT_UVD_MGCG |
2532 RADEON_CG_SUPPORT_HDP_LS |
2533 RADEON_CG_SUPPORT_HDP_MGCG;
2534 rdev->pg_flags = 0;
2535 } else {
2536 rdev->cg_flags =
2537 RADEON_CG_SUPPORT_GFX_MGCG |
2538 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2539 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2540 RADEON_CG_SUPPORT_GFX_CGLS |
2541 RADEON_CG_SUPPORT_GFX_CGTS |
2542 RADEON_CG_SUPPORT_GFX_CP_LS |
2543 RADEON_CG_SUPPORT_MC_LS |
2544 RADEON_CG_SUPPORT_MC_MGCG |
2545 RADEON_CG_SUPPORT_SDMA_MGCG |
2546 RADEON_CG_SUPPORT_SDMA_LS |
2547 RADEON_CG_SUPPORT_BIF_LS |
2548 RADEON_CG_SUPPORT_VCE_MGCG |
2549 RADEON_CG_SUPPORT_UVD_MGCG |
2550 RADEON_CG_SUPPORT_HDP_LS |
2551 RADEON_CG_SUPPORT_HDP_MGCG;
2552 rdev->pg_flags = 0;
2553 }
0672e27b
AD		 2554 break;
2555 case CHIP_KAVERI:
2556 case CHIP_KABINI:
b0a9f22a 2557 case CHIP_MULLINS:
0672e27b
AD		 2558 rdev->asic = &kv_asic;
2559 /* set num crtcs */
473359bc 2560 if (rdev->family == CHIP_KAVERI) {
0672e27b 2561 rdev->num_crtc = 4;
473359bc 2562 rdev->cg_flags =
773dc10a 2563 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2564 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2565 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2566 RADEON_CG_SUPPORT_GFX_CGLS |
2567 RADEON_CG_SUPPORT_GFX_CGTS |
2568 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2569 RADEON_CG_SUPPORT_GFX_CP_LS |
2570 RADEON_CG_SUPPORT_SDMA_MGCG |
2571 RADEON_CG_SUPPORT_SDMA_LS |
2572 RADEON_CG_SUPPORT_BIF_LS |
2573 RADEON_CG_SUPPORT_VCE_MGCG |
2574 RADEON_CG_SUPPORT_UVD_MGCG |
2575 RADEON_CG_SUPPORT_HDP_LS |
2576 RADEON_CG_SUPPORT_HDP_MGCG;
2577 rdev->pg_flags = 0;
2b19d17f 2578 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2579 RADEON_PG_SUPPORT_GFX_SMG |
2580 RADEON_PG_SUPPORT_GFX_DMG |
2581 RADEON_PG_SUPPORT_UVD |
2582 RADEON_PG_SUPPORT_VCE |
2583 RADEON_PG_SUPPORT_CP |
2584 RADEON_PG_SUPPORT_GDS |
2585 RADEON_PG_SUPPORT_RLC_SMU_HS |
2586 RADEON_PG_SUPPORT_ACP |
2587 RADEON_PG_SUPPORT_SAMU;*/
2588 } else {
0672e27b 2589 rdev->num_crtc = 2;
473359bc 2590 rdev->cg_flags =
773dc10a 2591 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2592 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2593 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2594 RADEON_CG_SUPPORT_GFX_CGLS |
2595 RADEON_CG_SUPPORT_GFX_CGTS |
2596 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2597 RADEON_CG_SUPPORT_GFX_CP_LS |
2598 RADEON_CG_SUPPORT_SDMA_MGCG |
2599 RADEON_CG_SUPPORT_SDMA_LS |
2600 RADEON_CG_SUPPORT_BIF_LS |
2601 RADEON_CG_SUPPORT_VCE_MGCG |
2602 RADEON_CG_SUPPORT_UVD_MGCG |
2603 RADEON_CG_SUPPORT_HDP_LS |
2604 RADEON_CG_SUPPORT_HDP_MGCG;
2605 rdev->pg_flags = 0;
2b19d17f 2606 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2607 RADEON_PG_SUPPORT_GFX_SMG |
2608 RADEON_PG_SUPPORT_UVD |
2609 RADEON_PG_SUPPORT_VCE |
2610 RADEON_PG_SUPPORT_CP |
2611 RADEON_PG_SUPPORT_GDS |
2612 RADEON_PG_SUPPORT_RLC_SMU_HS |
2613 RADEON_PG_SUPPORT_SAMU;*/
2614 }
22c775ce 2615 rdev->has_uvd = true;
0672e27b 2616 break;
0a10c851
DV		 2617 default:
2618 /* FIXME: not supported yet */
2619 return -EINVAL;
2620 }
2621
2622 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2623 rdev->asic->pm.get_memory_clock = NULL;
2624 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2625 }
2626
2627 return 0;
2628}
2629
Linux kernel - Deliverables
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