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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
b4df8be1 | 125 | if (rdev->family >= CHIP_R600) { |
0a10c851 DV |
126 | rdev->pciep_rreg = &r600_pciep_rreg; |
127 | rdev->pciep_wreg = &r600_pciep_wreg; | |
128 | } | |
129 | } | |
130 | ||
131 | ||
132 | /* helper to disable agp */ | |
abf1dc67 AD |
133 | /** |
134 | * radeon_agp_disable - AGP disable helper function | |
135 | * | |
136 | * @rdev: radeon device pointer | |
137 | * | |
138 | * Removes AGP flags and changes the gart callbacks on AGP | |
139 | * cards when using the internal gart rather than AGP (all asics). | |
140 | */ | |
0a10c851 DV |
141 | void radeon_agp_disable(struct radeon_device *rdev) |
142 | { | |
143 | rdev->flags &= ~RADEON_IS_AGP; | |
144 | if (rdev->family >= CHIP_R600) { | |
145 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
146 | rdev->flags |= RADEON_IS_PCIE; | |
147 | } else if (rdev->family >= CHIP_RV515 || | |
148 | rdev->family == CHIP_RV380 || | |
149 | rdev->family == CHIP_RV410 || | |
150 | rdev->family == CHIP_R423) { | |
151 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
152 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
153 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
154 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
155 | } else { |
156 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
157 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
158 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
159 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
160 | } |
161 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
162 | } | |
163 | ||
164 | /* | |
165 | * ASIC | |
166 | */ | |
48e7a5f1 DV |
167 | static struct radeon_asic r100_asic = { |
168 | .init = &r100_init, | |
169 | .fini = &r100_fini, | |
170 | .suspend = &r100_suspend, | |
171 | .resume = &r100_resume, | |
172 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 173 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
174 | .ioctl_wait_idle = NULL, |
175 | .gui_idle = &r100_gui_idle, | |
176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
177 | .gart = { |
178 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
179 | .set_page = &r100_pci_gart_set_page, | |
180 | }, | |
4c87bc26 CK |
181 | .ring = { |
182 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
183 | .ib_execute = &r100_ring_ib_execute, | |
184 | .emit_fence = &r100_fence_ring_emit, | |
185 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 186 | .cs_parse = &r100_cs_parse, |
f712812e AD |
187 | .ring_start = &r100_ring_start, |
188 | .ring_test = &r100_ring_test, | |
189 | .ib_test = &r100_ib_test, | |
312c4a8c | 190 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
191 | } |
192 | }, | |
b35ea4ab AD |
193 | .irq = { |
194 | .set = &r100_irq_set, | |
195 | .process = &r100_irq_process, | |
196 | }, | |
c79a49ca AD |
197 | .display = { |
198 | .bandwidth_update = &r100_bandwidth_update, | |
199 | .get_vblank_counter = &r100_get_vblank_counter, | |
200 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 201 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
c79a49ca | 202 | }, |
27cd7769 AD |
203 | .copy = { |
204 | .blit = &r100_copy_blit, | |
205 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
206 | .dma = NULL, | |
207 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
208 | .copy = &r100_copy_blit, | |
209 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
210 | }, | |
9e6f3d02 AD |
211 | .surface = { |
212 | .set_reg = r100_set_surface_reg, | |
213 | .clear_reg = r100_clear_surface_reg, | |
214 | }, | |
901ea57d AD |
215 | .hpd = { |
216 | .init = &r100_hpd_init, | |
217 | .fini = &r100_hpd_fini, | |
218 | .sense = &r100_hpd_sense, | |
219 | .set_polarity = &r100_hpd_set_polarity, | |
220 | }, | |
a02fa397 AD |
221 | .pm = { |
222 | .misc = &r100_pm_misc, | |
223 | .prepare = &r100_pm_prepare, | |
224 | .finish = &r100_pm_finish, | |
225 | .init_profile = &r100_pm_init_profile, | |
226 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
227 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
228 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
229 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
230 | .set_memory_clock = NULL, | |
231 | .get_pcie_lanes = NULL, | |
232 | .set_pcie_lanes = NULL, | |
233 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 234 | }, |
0f9e006c AD |
235 | .pflip = { |
236 | .pre_page_flip = &r100_pre_page_flip, | |
237 | .page_flip = &r100_page_flip, | |
238 | .post_page_flip = &r100_post_page_flip, | |
239 | }, | |
48e7a5f1 DV |
240 | }; |
241 | ||
242 | static struct radeon_asic r200_asic = { | |
243 | .init = &r100_init, | |
244 | .fini = &r100_fini, | |
245 | .suspend = &r100_suspend, | |
246 | .resume = &r100_resume, | |
247 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 248 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
249 | .ioctl_wait_idle = NULL, |
250 | .gui_idle = &r100_gui_idle, | |
251 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
252 | .gart = { |
253 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
254 | .set_page = &r100_pci_gart_set_page, | |
255 | }, | |
4c87bc26 CK |
256 | .ring = { |
257 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
258 | .ib_execute = &r100_ring_ib_execute, | |
259 | .emit_fence = &r100_fence_ring_emit, | |
260 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 261 | .cs_parse = &r100_cs_parse, |
f712812e AD |
262 | .ring_start = &r100_ring_start, |
263 | .ring_test = &r100_ring_test, | |
264 | .ib_test = &r100_ib_test, | |
312c4a8c | 265 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
266 | } |
267 | }, | |
b35ea4ab AD |
268 | .irq = { |
269 | .set = &r100_irq_set, | |
270 | .process = &r100_irq_process, | |
271 | }, | |
c79a49ca AD |
272 | .display = { |
273 | .bandwidth_update = &r100_bandwidth_update, | |
274 | .get_vblank_counter = &r100_get_vblank_counter, | |
275 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 276 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
c79a49ca | 277 | }, |
27cd7769 AD |
278 | .copy = { |
279 | .blit = &r100_copy_blit, | |
280 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
281 | .dma = &r200_copy_dma, | |
282 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
283 | .copy = &r100_copy_blit, | |
284 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
285 | }, | |
9e6f3d02 AD |
286 | .surface = { |
287 | .set_reg = r100_set_surface_reg, | |
288 | .clear_reg = r100_clear_surface_reg, | |
289 | }, | |
901ea57d AD |
290 | .hpd = { |
291 | .init = &r100_hpd_init, | |
292 | .fini = &r100_hpd_fini, | |
293 | .sense = &r100_hpd_sense, | |
294 | .set_polarity = &r100_hpd_set_polarity, | |
295 | }, | |
a02fa397 AD |
296 | .pm = { |
297 | .misc = &r100_pm_misc, | |
298 | .prepare = &r100_pm_prepare, | |
299 | .finish = &r100_pm_finish, | |
300 | .init_profile = &r100_pm_init_profile, | |
301 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
302 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
303 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
304 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
305 | .set_memory_clock = NULL, | |
306 | .get_pcie_lanes = NULL, | |
307 | .set_pcie_lanes = NULL, | |
308 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 309 | }, |
0f9e006c AD |
310 | .pflip = { |
311 | .pre_page_flip = &r100_pre_page_flip, | |
312 | .page_flip = &r100_page_flip, | |
313 | .post_page_flip = &r100_post_page_flip, | |
314 | }, | |
48e7a5f1 DV |
315 | }; |
316 | ||
317 | static struct radeon_asic r300_asic = { | |
318 | .init = &r300_init, | |
319 | .fini = &r300_fini, | |
320 | .suspend = &r300_suspend, | |
321 | .resume = &r300_resume, | |
322 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 323 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
324 | .ioctl_wait_idle = NULL, |
325 | .gui_idle = &r100_gui_idle, | |
326 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
327 | .gart = { |
328 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
329 | .set_page = &r100_pci_gart_set_page, | |
330 | }, | |
4c87bc26 CK |
331 | .ring = { |
332 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
333 | .ib_execute = &r100_ring_ib_execute, | |
334 | .emit_fence = &r300_fence_ring_emit, | |
335 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 336 | .cs_parse = &r300_cs_parse, |
f712812e AD |
337 | .ring_start = &r300_ring_start, |
338 | .ring_test = &r100_ring_test, | |
339 | .ib_test = &r100_ib_test, | |
8ba957b5 | 340 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
341 | } |
342 | }, | |
b35ea4ab AD |
343 | .irq = { |
344 | .set = &r100_irq_set, | |
345 | .process = &r100_irq_process, | |
346 | }, | |
c79a49ca AD |
347 | .display = { |
348 | .bandwidth_update = &r100_bandwidth_update, | |
349 | .get_vblank_counter = &r100_get_vblank_counter, | |
350 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 351 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
c79a49ca | 352 | }, |
27cd7769 AD |
353 | .copy = { |
354 | .blit = &r100_copy_blit, | |
355 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
356 | .dma = &r200_copy_dma, | |
357 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
358 | .copy = &r100_copy_blit, | |
359 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
360 | }, | |
9e6f3d02 AD |
361 | .surface = { |
362 | .set_reg = r100_set_surface_reg, | |
363 | .clear_reg = r100_clear_surface_reg, | |
364 | }, | |
901ea57d AD |
365 | .hpd = { |
366 | .init = &r100_hpd_init, | |
367 | .fini = &r100_hpd_fini, | |
368 | .sense = &r100_hpd_sense, | |
369 | .set_polarity = &r100_hpd_set_polarity, | |
370 | }, | |
a02fa397 AD |
371 | .pm = { |
372 | .misc = &r100_pm_misc, | |
373 | .prepare = &r100_pm_prepare, | |
374 | .finish = &r100_pm_finish, | |
375 | .init_profile = &r100_pm_init_profile, | |
376 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
377 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
378 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
379 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
380 | .set_memory_clock = NULL, | |
381 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
382 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
383 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 384 | }, |
0f9e006c AD |
385 | .pflip = { |
386 | .pre_page_flip = &r100_pre_page_flip, | |
387 | .page_flip = &r100_page_flip, | |
388 | .post_page_flip = &r100_post_page_flip, | |
389 | }, | |
48e7a5f1 DV |
390 | }; |
391 | ||
392 | static struct radeon_asic r300_asic_pcie = { | |
393 | .init = &r300_init, | |
394 | .fini = &r300_fini, | |
395 | .suspend = &r300_suspend, | |
396 | .resume = &r300_resume, | |
397 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 398 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
399 | .ioctl_wait_idle = NULL, |
400 | .gui_idle = &r100_gui_idle, | |
401 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
402 | .gart = { |
403 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
404 | .set_page = &rv370_pcie_gart_set_page, | |
405 | }, | |
4c87bc26 CK |
406 | .ring = { |
407 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
408 | .ib_execute = &r100_ring_ib_execute, | |
409 | .emit_fence = &r300_fence_ring_emit, | |
410 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 411 | .cs_parse = &r300_cs_parse, |
f712812e AD |
412 | .ring_start = &r300_ring_start, |
413 | .ring_test = &r100_ring_test, | |
414 | .ib_test = &r100_ib_test, | |
8ba957b5 | 415 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
416 | } |
417 | }, | |
b35ea4ab AD |
418 | .irq = { |
419 | .set = &r100_irq_set, | |
420 | .process = &r100_irq_process, | |
421 | }, | |
c79a49ca AD |
422 | .display = { |
423 | .bandwidth_update = &r100_bandwidth_update, | |
424 | .get_vblank_counter = &r100_get_vblank_counter, | |
425 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 426 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
c79a49ca | 427 | }, |
27cd7769 AD |
428 | .copy = { |
429 | .blit = &r100_copy_blit, | |
430 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
431 | .dma = &r200_copy_dma, | |
432 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
433 | .copy = &r100_copy_blit, | |
434 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
435 | }, | |
9e6f3d02 AD |
436 | .surface = { |
437 | .set_reg = r100_set_surface_reg, | |
438 | .clear_reg = r100_clear_surface_reg, | |
439 | }, | |
901ea57d AD |
440 | .hpd = { |
441 | .init = &r100_hpd_init, | |
442 | .fini = &r100_hpd_fini, | |
443 | .sense = &r100_hpd_sense, | |
444 | .set_polarity = &r100_hpd_set_polarity, | |
445 | }, | |
a02fa397 AD |
446 | .pm = { |
447 | .misc = &r100_pm_misc, | |
448 | .prepare = &r100_pm_prepare, | |
449 | .finish = &r100_pm_finish, | |
450 | .init_profile = &r100_pm_init_profile, | |
451 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
452 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
453 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
454 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
455 | .set_memory_clock = NULL, | |
456 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
457 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
458 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 459 | }, |
0f9e006c AD |
460 | .pflip = { |
461 | .pre_page_flip = &r100_pre_page_flip, | |
462 | .page_flip = &r100_page_flip, | |
463 | .post_page_flip = &r100_post_page_flip, | |
464 | }, | |
48e7a5f1 DV |
465 | }; |
466 | ||
467 | static struct radeon_asic r420_asic = { | |
468 | .init = &r420_init, | |
469 | .fini = &r420_fini, | |
470 | .suspend = &r420_suspend, | |
471 | .resume = &r420_resume, | |
472 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 473 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
474 | .ioctl_wait_idle = NULL, |
475 | .gui_idle = &r100_gui_idle, | |
476 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
477 | .gart = { |
478 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
479 | .set_page = &rv370_pcie_gart_set_page, | |
480 | }, | |
4c87bc26 CK |
481 | .ring = { |
482 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
483 | .ib_execute = &r100_ring_ib_execute, | |
484 | .emit_fence = &r300_fence_ring_emit, | |
485 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 486 | .cs_parse = &r300_cs_parse, |
f712812e AD |
487 | .ring_start = &r300_ring_start, |
488 | .ring_test = &r100_ring_test, | |
489 | .ib_test = &r100_ib_test, | |
8ba957b5 | 490 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
491 | } |
492 | }, | |
b35ea4ab AD |
493 | .irq = { |
494 | .set = &r100_irq_set, | |
495 | .process = &r100_irq_process, | |
496 | }, | |
c79a49ca AD |
497 | .display = { |
498 | .bandwidth_update = &r100_bandwidth_update, | |
499 | .get_vblank_counter = &r100_get_vblank_counter, | |
500 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 501 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 502 | }, |
27cd7769 AD |
503 | .copy = { |
504 | .blit = &r100_copy_blit, | |
505 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
506 | .dma = &r200_copy_dma, | |
507 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
508 | .copy = &r100_copy_blit, | |
509 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
510 | }, | |
9e6f3d02 AD |
511 | .surface = { |
512 | .set_reg = r100_set_surface_reg, | |
513 | .clear_reg = r100_clear_surface_reg, | |
514 | }, | |
901ea57d AD |
515 | .hpd = { |
516 | .init = &r100_hpd_init, | |
517 | .fini = &r100_hpd_fini, | |
518 | .sense = &r100_hpd_sense, | |
519 | .set_polarity = &r100_hpd_set_polarity, | |
520 | }, | |
a02fa397 AD |
521 | .pm = { |
522 | .misc = &r100_pm_misc, | |
523 | .prepare = &r100_pm_prepare, | |
524 | .finish = &r100_pm_finish, | |
525 | .init_profile = &r420_pm_init_profile, | |
526 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
527 | .get_engine_clock = &radeon_atom_get_engine_clock, |
528 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
529 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
530 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
531 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
532 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
533 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 534 | }, |
0f9e006c AD |
535 | .pflip = { |
536 | .pre_page_flip = &r100_pre_page_flip, | |
537 | .page_flip = &r100_page_flip, | |
538 | .post_page_flip = &r100_post_page_flip, | |
539 | }, | |
48e7a5f1 DV |
540 | }; |
541 | ||
542 | static struct radeon_asic rs400_asic = { | |
543 | .init = &rs400_init, | |
544 | .fini = &rs400_fini, | |
545 | .suspend = &rs400_suspend, | |
546 | .resume = &rs400_resume, | |
547 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 548 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
549 | .ioctl_wait_idle = NULL, |
550 | .gui_idle = &r100_gui_idle, | |
551 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
552 | .gart = { |
553 | .tlb_flush = &rs400_gart_tlb_flush, | |
554 | .set_page = &rs400_gart_set_page, | |
555 | }, | |
4c87bc26 CK |
556 | .ring = { |
557 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
558 | .ib_execute = &r100_ring_ib_execute, | |
559 | .emit_fence = &r300_fence_ring_emit, | |
560 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 561 | .cs_parse = &r300_cs_parse, |
f712812e AD |
562 | .ring_start = &r300_ring_start, |
563 | .ring_test = &r100_ring_test, | |
564 | .ib_test = &r100_ib_test, | |
8ba957b5 | 565 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
566 | } |
567 | }, | |
b35ea4ab AD |
568 | .irq = { |
569 | .set = &r100_irq_set, | |
570 | .process = &r100_irq_process, | |
571 | }, | |
c79a49ca AD |
572 | .display = { |
573 | .bandwidth_update = &r100_bandwidth_update, | |
574 | .get_vblank_counter = &r100_get_vblank_counter, | |
575 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 576 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
c79a49ca | 577 | }, |
27cd7769 AD |
578 | .copy = { |
579 | .blit = &r100_copy_blit, | |
580 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
581 | .dma = &r200_copy_dma, | |
582 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
583 | .copy = &r100_copy_blit, | |
584 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
585 | }, | |
9e6f3d02 AD |
586 | .surface = { |
587 | .set_reg = r100_set_surface_reg, | |
588 | .clear_reg = r100_clear_surface_reg, | |
589 | }, | |
901ea57d AD |
590 | .hpd = { |
591 | .init = &r100_hpd_init, | |
592 | .fini = &r100_hpd_fini, | |
593 | .sense = &r100_hpd_sense, | |
594 | .set_polarity = &r100_hpd_set_polarity, | |
595 | }, | |
a02fa397 AD |
596 | .pm = { |
597 | .misc = &r100_pm_misc, | |
598 | .prepare = &r100_pm_prepare, | |
599 | .finish = &r100_pm_finish, | |
600 | .init_profile = &r100_pm_init_profile, | |
601 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
602 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
603 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
604 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
605 | .set_memory_clock = NULL, | |
606 | .get_pcie_lanes = NULL, | |
607 | .set_pcie_lanes = NULL, | |
608 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 609 | }, |
0f9e006c AD |
610 | .pflip = { |
611 | .pre_page_flip = &r100_pre_page_flip, | |
612 | .page_flip = &r100_page_flip, | |
613 | .post_page_flip = &r100_post_page_flip, | |
614 | }, | |
48e7a5f1 DV |
615 | }; |
616 | ||
617 | static struct radeon_asic rs600_asic = { | |
618 | .init = &rs600_init, | |
619 | .fini = &rs600_fini, | |
620 | .suspend = &rs600_suspend, | |
621 | .resume = &rs600_resume, | |
622 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 623 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
624 | .ioctl_wait_idle = NULL, |
625 | .gui_idle = &r100_gui_idle, | |
626 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
627 | .gart = { |
628 | .tlb_flush = &rs600_gart_tlb_flush, | |
629 | .set_page = &rs600_gart_set_page, | |
630 | }, | |
4c87bc26 CK |
631 | .ring = { |
632 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
633 | .ib_execute = &r100_ring_ib_execute, | |
634 | .emit_fence = &r300_fence_ring_emit, | |
635 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 636 | .cs_parse = &r300_cs_parse, |
f712812e AD |
637 | .ring_start = &r300_ring_start, |
638 | .ring_test = &r100_ring_test, | |
639 | .ib_test = &r100_ib_test, | |
8ba957b5 | 640 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
641 | } |
642 | }, | |
b35ea4ab AD |
643 | .irq = { |
644 | .set = &rs600_irq_set, | |
645 | .process = &rs600_irq_process, | |
646 | }, | |
c79a49ca AD |
647 | .display = { |
648 | .bandwidth_update = &rs600_bandwidth_update, | |
649 | .get_vblank_counter = &rs600_get_vblank_counter, | |
650 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 651 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 652 | }, |
27cd7769 AD |
653 | .copy = { |
654 | .blit = &r100_copy_blit, | |
655 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
656 | .dma = &r200_copy_dma, | |
657 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
658 | .copy = &r100_copy_blit, | |
659 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
660 | }, | |
9e6f3d02 AD |
661 | .surface = { |
662 | .set_reg = r100_set_surface_reg, | |
663 | .clear_reg = r100_clear_surface_reg, | |
664 | }, | |
901ea57d AD |
665 | .hpd = { |
666 | .init = &rs600_hpd_init, | |
667 | .fini = &rs600_hpd_fini, | |
668 | .sense = &rs600_hpd_sense, | |
669 | .set_polarity = &rs600_hpd_set_polarity, | |
670 | }, | |
a02fa397 AD |
671 | .pm = { |
672 | .misc = &rs600_pm_misc, | |
673 | .prepare = &rs600_pm_prepare, | |
674 | .finish = &rs600_pm_finish, | |
675 | .init_profile = &r420_pm_init_profile, | |
676 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
677 | .get_engine_clock = &radeon_atom_get_engine_clock, |
678 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
679 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
680 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
681 | .get_pcie_lanes = NULL, | |
682 | .set_pcie_lanes = NULL, | |
683 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 684 | }, |
0f9e006c AD |
685 | .pflip = { |
686 | .pre_page_flip = &rs600_pre_page_flip, | |
687 | .page_flip = &rs600_page_flip, | |
688 | .post_page_flip = &rs600_post_page_flip, | |
689 | }, | |
48e7a5f1 DV |
690 | }; |
691 | ||
692 | static struct radeon_asic rs690_asic = { | |
693 | .init = &rs690_init, | |
694 | .fini = &rs690_fini, | |
695 | .suspend = &rs690_suspend, | |
696 | .resume = &rs690_resume, | |
697 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 698 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
699 | .ioctl_wait_idle = NULL, |
700 | .gui_idle = &r100_gui_idle, | |
701 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
702 | .gart = { |
703 | .tlb_flush = &rs400_gart_tlb_flush, | |
704 | .set_page = &rs400_gart_set_page, | |
705 | }, | |
4c87bc26 CK |
706 | .ring = { |
707 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
708 | .ib_execute = &r100_ring_ib_execute, | |
709 | .emit_fence = &r300_fence_ring_emit, | |
710 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 711 | .cs_parse = &r300_cs_parse, |
f712812e AD |
712 | .ring_start = &r300_ring_start, |
713 | .ring_test = &r100_ring_test, | |
714 | .ib_test = &r100_ib_test, | |
8ba957b5 | 715 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
716 | } |
717 | }, | |
b35ea4ab AD |
718 | .irq = { |
719 | .set = &rs600_irq_set, | |
720 | .process = &rs600_irq_process, | |
721 | }, | |
c79a49ca AD |
722 | .display = { |
723 | .get_vblank_counter = &rs600_get_vblank_counter, | |
724 | .bandwidth_update = &rs690_bandwidth_update, | |
725 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 726 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 727 | }, |
27cd7769 AD |
728 | .copy = { |
729 | .blit = &r100_copy_blit, | |
730 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
731 | .dma = &r200_copy_dma, | |
732 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
733 | .copy = &r200_copy_dma, | |
734 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
735 | }, | |
9e6f3d02 AD |
736 | .surface = { |
737 | .set_reg = r100_set_surface_reg, | |
738 | .clear_reg = r100_clear_surface_reg, | |
739 | }, | |
901ea57d AD |
740 | .hpd = { |
741 | .init = &rs600_hpd_init, | |
742 | .fini = &rs600_hpd_fini, | |
743 | .sense = &rs600_hpd_sense, | |
744 | .set_polarity = &rs600_hpd_set_polarity, | |
745 | }, | |
a02fa397 AD |
746 | .pm = { |
747 | .misc = &rs600_pm_misc, | |
748 | .prepare = &rs600_pm_prepare, | |
749 | .finish = &rs600_pm_finish, | |
750 | .init_profile = &r420_pm_init_profile, | |
751 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
752 | .get_engine_clock = &radeon_atom_get_engine_clock, |
753 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
754 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
755 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
756 | .get_pcie_lanes = NULL, | |
757 | .set_pcie_lanes = NULL, | |
758 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 759 | }, |
0f9e006c AD |
760 | .pflip = { |
761 | .pre_page_flip = &rs600_pre_page_flip, | |
762 | .page_flip = &rs600_page_flip, | |
763 | .post_page_flip = &rs600_post_page_flip, | |
764 | }, | |
48e7a5f1 DV |
765 | }; |
766 | ||
767 | static struct radeon_asic rv515_asic = { | |
768 | .init = &rv515_init, | |
769 | .fini = &rv515_fini, | |
770 | .suspend = &rv515_suspend, | |
771 | .resume = &rv515_resume, | |
772 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 773 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
774 | .ioctl_wait_idle = NULL, |
775 | .gui_idle = &r100_gui_idle, | |
776 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
777 | .gart = { |
778 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
779 | .set_page = &rv370_pcie_gart_set_page, | |
780 | }, | |
4c87bc26 CK |
781 | .ring = { |
782 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
783 | .ib_execute = &r100_ring_ib_execute, | |
784 | .emit_fence = &r300_fence_ring_emit, | |
785 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 786 | .cs_parse = &r300_cs_parse, |
f712812e AD |
787 | .ring_start = &rv515_ring_start, |
788 | .ring_test = &r100_ring_test, | |
789 | .ib_test = &r100_ib_test, | |
8ba957b5 | 790 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
791 | } |
792 | }, | |
b35ea4ab AD |
793 | .irq = { |
794 | .set = &rs600_irq_set, | |
795 | .process = &rs600_irq_process, | |
796 | }, | |
c79a49ca AD |
797 | .display = { |
798 | .get_vblank_counter = &rs600_get_vblank_counter, | |
799 | .bandwidth_update = &rv515_bandwidth_update, | |
800 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 801 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 802 | }, |
27cd7769 AD |
803 | .copy = { |
804 | .blit = &r100_copy_blit, | |
805 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
806 | .dma = &r200_copy_dma, | |
807 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
808 | .copy = &r100_copy_blit, | |
809 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
810 | }, | |
9e6f3d02 AD |
811 | .surface = { |
812 | .set_reg = r100_set_surface_reg, | |
813 | .clear_reg = r100_clear_surface_reg, | |
814 | }, | |
901ea57d AD |
815 | .hpd = { |
816 | .init = &rs600_hpd_init, | |
817 | .fini = &rs600_hpd_fini, | |
818 | .sense = &rs600_hpd_sense, | |
819 | .set_polarity = &rs600_hpd_set_polarity, | |
820 | }, | |
a02fa397 AD |
821 | .pm = { |
822 | .misc = &rs600_pm_misc, | |
823 | .prepare = &rs600_pm_prepare, | |
824 | .finish = &rs600_pm_finish, | |
825 | .init_profile = &r420_pm_init_profile, | |
826 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
827 | .get_engine_clock = &radeon_atom_get_engine_clock, |
828 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
829 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
830 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
831 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
832 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
833 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 834 | }, |
0f9e006c AD |
835 | .pflip = { |
836 | .pre_page_flip = &rs600_pre_page_flip, | |
837 | .page_flip = &rs600_page_flip, | |
838 | .post_page_flip = &rs600_post_page_flip, | |
839 | }, | |
48e7a5f1 DV |
840 | }; |
841 | ||
842 | static struct radeon_asic r520_asic = { | |
843 | .init = &r520_init, | |
844 | .fini = &rv515_fini, | |
845 | .suspend = &rv515_suspend, | |
846 | .resume = &r520_resume, | |
847 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 848 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
849 | .ioctl_wait_idle = NULL, |
850 | .gui_idle = &r100_gui_idle, | |
851 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
852 | .gart = { |
853 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
854 | .set_page = &rv370_pcie_gart_set_page, | |
855 | }, | |
4c87bc26 CK |
856 | .ring = { |
857 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
858 | .ib_execute = &r100_ring_ib_execute, | |
859 | .emit_fence = &r300_fence_ring_emit, | |
860 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 861 | .cs_parse = &r300_cs_parse, |
f712812e AD |
862 | .ring_start = &rv515_ring_start, |
863 | .ring_test = &r100_ring_test, | |
864 | .ib_test = &r100_ib_test, | |
8ba957b5 | 865 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
866 | } |
867 | }, | |
b35ea4ab AD |
868 | .irq = { |
869 | .set = &rs600_irq_set, | |
870 | .process = &rs600_irq_process, | |
871 | }, | |
c79a49ca AD |
872 | .display = { |
873 | .bandwidth_update = &rv515_bandwidth_update, | |
874 | .get_vblank_counter = &rs600_get_vblank_counter, | |
875 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 876 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 877 | }, |
27cd7769 AD |
878 | .copy = { |
879 | .blit = &r100_copy_blit, | |
880 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
881 | .dma = &r200_copy_dma, | |
882 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
883 | .copy = &r100_copy_blit, | |
884 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
885 | }, | |
9e6f3d02 AD |
886 | .surface = { |
887 | .set_reg = r100_set_surface_reg, | |
888 | .clear_reg = r100_clear_surface_reg, | |
889 | }, | |
901ea57d AD |
890 | .hpd = { |
891 | .init = &rs600_hpd_init, | |
892 | .fini = &rs600_hpd_fini, | |
893 | .sense = &rs600_hpd_sense, | |
894 | .set_polarity = &rs600_hpd_set_polarity, | |
895 | }, | |
a02fa397 AD |
896 | .pm = { |
897 | .misc = &rs600_pm_misc, | |
898 | .prepare = &rs600_pm_prepare, | |
899 | .finish = &rs600_pm_finish, | |
900 | .init_profile = &r420_pm_init_profile, | |
901 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
902 | .get_engine_clock = &radeon_atom_get_engine_clock, |
903 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
904 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
905 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
906 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
907 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
908 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 909 | }, |
0f9e006c AD |
910 | .pflip = { |
911 | .pre_page_flip = &rs600_pre_page_flip, | |
912 | .page_flip = &rs600_page_flip, | |
913 | .post_page_flip = &rs600_post_page_flip, | |
914 | }, | |
48e7a5f1 DV |
915 | }; |
916 | ||
917 | static struct radeon_asic r600_asic = { | |
918 | .init = &r600_init, | |
919 | .fini = &r600_fini, | |
920 | .suspend = &r600_suspend, | |
921 | .resume = &r600_resume, | |
48e7a5f1 | 922 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 923 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
924 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
925 | .gui_idle = &r600_gui_idle, | |
926 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
927 | .gart = { |
928 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
929 | .set_page = &rs600_gart_set_page, | |
930 | }, | |
4c87bc26 CK |
931 | .ring = { |
932 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
933 | .ib_execute = &r600_ring_ib_execute, | |
934 | .emit_fence = &r600_fence_ring_emit, | |
935 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 936 | .cs_parse = &r600_cs_parse, |
f712812e AD |
937 | .ring_test = &r600_ring_test, |
938 | .ib_test = &r600_ib_test, | |
312c4a8c | 939 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
940 | } |
941 | }, | |
b35ea4ab AD |
942 | .irq = { |
943 | .set = &r600_irq_set, | |
944 | .process = &r600_irq_process, | |
945 | }, | |
c79a49ca AD |
946 | .display = { |
947 | .bandwidth_update = &rv515_bandwidth_update, | |
948 | .get_vblank_counter = &rs600_get_vblank_counter, | |
949 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 950 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 951 | }, |
27cd7769 AD |
952 | .copy = { |
953 | .blit = &r600_copy_blit, | |
954 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
955 | .dma = NULL, | |
956 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
957 | .copy = &r600_copy_blit, | |
958 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
959 | }, | |
9e6f3d02 AD |
960 | .surface = { |
961 | .set_reg = r600_set_surface_reg, | |
962 | .clear_reg = r600_clear_surface_reg, | |
963 | }, | |
901ea57d AD |
964 | .hpd = { |
965 | .init = &r600_hpd_init, | |
966 | .fini = &r600_hpd_fini, | |
967 | .sense = &r600_hpd_sense, | |
968 | .set_polarity = &r600_hpd_set_polarity, | |
969 | }, | |
a02fa397 AD |
970 | .pm = { |
971 | .misc = &r600_pm_misc, | |
972 | .prepare = &rs600_pm_prepare, | |
973 | .finish = &rs600_pm_finish, | |
974 | .init_profile = &r600_pm_init_profile, | |
975 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
976 | .get_engine_clock = &radeon_atom_get_engine_clock, |
977 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
978 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
979 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
980 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
981 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
982 | .set_clock_gating = NULL, | |
a02fa397 | 983 | }, |
0f9e006c AD |
984 | .pflip = { |
985 | .pre_page_flip = &rs600_pre_page_flip, | |
986 | .page_flip = &rs600_page_flip, | |
987 | .post_page_flip = &rs600_post_page_flip, | |
988 | }, | |
48e7a5f1 DV |
989 | }; |
990 | ||
f47299c5 AD |
991 | static struct radeon_asic rs780_asic = { |
992 | .init = &r600_init, | |
993 | .fini = &r600_fini, | |
994 | .suspend = &r600_suspend, | |
995 | .resume = &r600_resume, | |
f47299c5 | 996 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 997 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
998 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
999 | .gui_idle = &r600_gui_idle, | |
1000 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
1001 | .gart = { |
1002 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1003 | .set_page = &rs600_gart_set_page, | |
1004 | }, | |
4c87bc26 CK |
1005 | .ring = { |
1006 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1007 | .ib_execute = &r600_ring_ib_execute, | |
1008 | .emit_fence = &r600_fence_ring_emit, | |
1009 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1010 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1011 | .ring_test = &r600_ring_test, |
1012 | .ib_test = &r600_ib_test, | |
312c4a8c | 1013 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
1014 | } |
1015 | }, | |
b35ea4ab AD |
1016 | .irq = { |
1017 | .set = &r600_irq_set, | |
1018 | .process = &r600_irq_process, | |
1019 | }, | |
c79a49ca AD |
1020 | .display = { |
1021 | .bandwidth_update = &rs690_bandwidth_update, | |
1022 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1023 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1024 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1025 | }, |
27cd7769 AD |
1026 | .copy = { |
1027 | .blit = &r600_copy_blit, | |
1028 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1029 | .dma = NULL, | |
1030 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1031 | .copy = &r600_copy_blit, | |
1032 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1033 | }, | |
9e6f3d02 AD |
1034 | .surface = { |
1035 | .set_reg = r600_set_surface_reg, | |
1036 | .clear_reg = r600_clear_surface_reg, | |
1037 | }, | |
901ea57d AD |
1038 | .hpd = { |
1039 | .init = &r600_hpd_init, | |
1040 | .fini = &r600_hpd_fini, | |
1041 | .sense = &r600_hpd_sense, | |
1042 | .set_polarity = &r600_hpd_set_polarity, | |
1043 | }, | |
a02fa397 AD |
1044 | .pm = { |
1045 | .misc = &r600_pm_misc, | |
1046 | .prepare = &rs600_pm_prepare, | |
1047 | .finish = &rs600_pm_finish, | |
1048 | .init_profile = &rs780_pm_init_profile, | |
1049 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1050 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1051 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1052 | .get_memory_clock = NULL, | |
1053 | .set_memory_clock = NULL, | |
1054 | .get_pcie_lanes = NULL, | |
1055 | .set_pcie_lanes = NULL, | |
1056 | .set_clock_gating = NULL, | |
a02fa397 | 1057 | }, |
0f9e006c AD |
1058 | .pflip = { |
1059 | .pre_page_flip = &rs600_pre_page_flip, | |
1060 | .page_flip = &rs600_page_flip, | |
1061 | .post_page_flip = &rs600_post_page_flip, | |
1062 | }, | |
f47299c5 AD |
1063 | }; |
1064 | ||
48e7a5f1 DV |
1065 | static struct radeon_asic rv770_asic = { |
1066 | .init = &rv770_init, | |
1067 | .fini = &rv770_fini, | |
1068 | .suspend = &rv770_suspend, | |
1069 | .resume = &rv770_resume, | |
a2d07b74 | 1070 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1071 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1072 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1073 | .gui_idle = &r600_gui_idle, | |
1074 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
1075 | .gart = { |
1076 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1077 | .set_page = &rs600_gart_set_page, | |
1078 | }, | |
4c87bc26 CK |
1079 | .ring = { |
1080 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1081 | .ib_execute = &r600_ring_ib_execute, | |
1082 | .emit_fence = &r600_fence_ring_emit, | |
1083 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1084 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1085 | .ring_test = &r600_ring_test, |
1086 | .ib_test = &r600_ib_test, | |
312c4a8c | 1087 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
1088 | } |
1089 | }, | |
b35ea4ab AD |
1090 | .irq = { |
1091 | .set = &r600_irq_set, | |
1092 | .process = &r600_irq_process, | |
1093 | }, | |
c79a49ca AD |
1094 | .display = { |
1095 | .bandwidth_update = &rv515_bandwidth_update, | |
1096 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1097 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1098 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1099 | }, |
27cd7769 AD |
1100 | .copy = { |
1101 | .blit = &r600_copy_blit, | |
1102 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1103 | .dma = NULL, | |
1104 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1105 | .copy = &r600_copy_blit, | |
1106 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1107 | }, | |
9e6f3d02 AD |
1108 | .surface = { |
1109 | .set_reg = r600_set_surface_reg, | |
1110 | .clear_reg = r600_clear_surface_reg, | |
1111 | }, | |
901ea57d AD |
1112 | .hpd = { |
1113 | .init = &r600_hpd_init, | |
1114 | .fini = &r600_hpd_fini, | |
1115 | .sense = &r600_hpd_sense, | |
1116 | .set_polarity = &r600_hpd_set_polarity, | |
1117 | }, | |
a02fa397 AD |
1118 | .pm = { |
1119 | .misc = &rv770_pm_misc, | |
1120 | .prepare = &rs600_pm_prepare, | |
1121 | .finish = &rs600_pm_finish, | |
1122 | .init_profile = &r600_pm_init_profile, | |
1123 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1124 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1125 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1126 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1127 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1128 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1129 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1130 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 1131 | }, |
0f9e006c AD |
1132 | .pflip = { |
1133 | .pre_page_flip = &rs600_pre_page_flip, | |
1134 | .page_flip = &rv770_page_flip, | |
1135 | .post_page_flip = &rs600_post_page_flip, | |
1136 | }, | |
48e7a5f1 DV |
1137 | }; |
1138 | ||
1139 | static struct radeon_asic evergreen_asic = { | |
1140 | .init = &evergreen_init, | |
1141 | .fini = &evergreen_fini, | |
1142 | .suspend = &evergreen_suspend, | |
1143 | .resume = &evergreen_resume, | |
a2d07b74 | 1144 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1145 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1146 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1147 | .gui_idle = &r600_gui_idle, | |
1148 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1149 | .gart = { |
1150 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1151 | .set_page = &rs600_gart_set_page, | |
1152 | }, | |
4c87bc26 CK |
1153 | .ring = { |
1154 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1155 | .ib_execute = &evergreen_ring_ib_execute, | |
1156 | .emit_fence = &r600_fence_ring_emit, | |
1157 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1158 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1159 | .ring_test = &r600_ring_test, |
1160 | .ib_test = &r600_ib_test, | |
312c4a8c | 1161 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1162 | } |
1163 | }, | |
b35ea4ab AD |
1164 | .irq = { |
1165 | .set = &evergreen_irq_set, | |
1166 | .process = &evergreen_irq_process, | |
1167 | }, | |
c79a49ca AD |
1168 | .display = { |
1169 | .bandwidth_update = &evergreen_bandwidth_update, | |
1170 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1171 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1172 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1173 | }, |
27cd7769 AD |
1174 | .copy = { |
1175 | .blit = &r600_copy_blit, | |
1176 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1177 | .dma = NULL, | |
1178 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1179 | .copy = &r600_copy_blit, | |
1180 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1181 | }, | |
9e6f3d02 AD |
1182 | .surface = { |
1183 | .set_reg = r600_set_surface_reg, | |
1184 | .clear_reg = r600_clear_surface_reg, | |
1185 | }, | |
901ea57d AD |
1186 | .hpd = { |
1187 | .init = &evergreen_hpd_init, | |
1188 | .fini = &evergreen_hpd_fini, | |
1189 | .sense = &evergreen_hpd_sense, | |
1190 | .set_polarity = &evergreen_hpd_set_polarity, | |
1191 | }, | |
a02fa397 AD |
1192 | .pm = { |
1193 | .misc = &evergreen_pm_misc, | |
1194 | .prepare = &evergreen_pm_prepare, | |
1195 | .finish = &evergreen_pm_finish, | |
1196 | .init_profile = &r600_pm_init_profile, | |
1197 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1198 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1199 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1200 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1201 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1202 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1203 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1204 | .set_clock_gating = NULL, | |
a02fa397 | 1205 | }, |
0f9e006c AD |
1206 | .pflip = { |
1207 | .pre_page_flip = &evergreen_pre_page_flip, | |
1208 | .page_flip = &evergreen_page_flip, | |
1209 | .post_page_flip = &evergreen_post_page_flip, | |
1210 | }, | |
48e7a5f1 DV |
1211 | }; |
1212 | ||
958261d1 AD |
1213 | static struct radeon_asic sumo_asic = { |
1214 | .init = &evergreen_init, | |
1215 | .fini = &evergreen_fini, | |
1216 | .suspend = &evergreen_suspend, | |
1217 | .resume = &evergreen_resume, | |
958261d1 AD |
1218 | .asic_reset = &evergreen_asic_reset, |
1219 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1220 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1221 | .gui_idle = &r600_gui_idle, | |
1222 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1223 | .gart = { |
1224 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1225 | .set_page = &rs600_gart_set_page, | |
1226 | }, | |
4c87bc26 CK |
1227 | .ring = { |
1228 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1229 | .ib_execute = &evergreen_ring_ib_execute, | |
1230 | .emit_fence = &r600_fence_ring_emit, | |
1231 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1232 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1233 | .ring_test = &r600_ring_test, |
1234 | .ib_test = &r600_ib_test, | |
312c4a8c | 1235 | .is_lockup = &evergreen_gpu_is_lockup, |
eb0c19c5 | 1236 | }, |
4c87bc26 | 1237 | }, |
b35ea4ab AD |
1238 | .irq = { |
1239 | .set = &evergreen_irq_set, | |
1240 | .process = &evergreen_irq_process, | |
1241 | }, | |
c79a49ca AD |
1242 | .display = { |
1243 | .bandwidth_update = &evergreen_bandwidth_update, | |
1244 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1245 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1246 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1247 | }, |
27cd7769 AD |
1248 | .copy = { |
1249 | .blit = &r600_copy_blit, | |
1250 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1251 | .dma = NULL, | |
1252 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1253 | .copy = &r600_copy_blit, | |
1254 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1255 | }, | |
9e6f3d02 AD |
1256 | .surface = { |
1257 | .set_reg = r600_set_surface_reg, | |
1258 | .clear_reg = r600_clear_surface_reg, | |
1259 | }, | |
901ea57d AD |
1260 | .hpd = { |
1261 | .init = &evergreen_hpd_init, | |
1262 | .fini = &evergreen_hpd_fini, | |
1263 | .sense = &evergreen_hpd_sense, | |
1264 | .set_polarity = &evergreen_hpd_set_polarity, | |
1265 | }, | |
a02fa397 AD |
1266 | .pm = { |
1267 | .misc = &evergreen_pm_misc, | |
1268 | .prepare = &evergreen_pm_prepare, | |
1269 | .finish = &evergreen_pm_finish, | |
1270 | .init_profile = &sumo_pm_init_profile, | |
1271 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1272 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1273 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1274 | .get_memory_clock = NULL, | |
1275 | .set_memory_clock = NULL, | |
1276 | .get_pcie_lanes = NULL, | |
1277 | .set_pcie_lanes = NULL, | |
1278 | .set_clock_gating = NULL, | |
a02fa397 | 1279 | }, |
0f9e006c AD |
1280 | .pflip = { |
1281 | .pre_page_flip = &evergreen_pre_page_flip, | |
1282 | .page_flip = &evergreen_page_flip, | |
1283 | .post_page_flip = &evergreen_post_page_flip, | |
1284 | }, | |
958261d1 AD |
1285 | }; |
1286 | ||
a43b7665 AD |
1287 | static struct radeon_asic btc_asic = { |
1288 | .init = &evergreen_init, | |
1289 | .fini = &evergreen_fini, | |
1290 | .suspend = &evergreen_suspend, | |
1291 | .resume = &evergreen_resume, | |
a43b7665 AD |
1292 | .asic_reset = &evergreen_asic_reset, |
1293 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1294 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1295 | .gui_idle = &r600_gui_idle, | |
1296 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1297 | .gart = { |
1298 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1299 | .set_page = &rs600_gart_set_page, | |
1300 | }, | |
4c87bc26 CK |
1301 | .ring = { |
1302 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1303 | .ib_execute = &evergreen_ring_ib_execute, | |
1304 | .emit_fence = &r600_fence_ring_emit, | |
1305 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1306 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1307 | .ring_test = &r600_ring_test, |
1308 | .ib_test = &r600_ib_test, | |
312c4a8c | 1309 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1310 | } |
1311 | }, | |
b35ea4ab AD |
1312 | .irq = { |
1313 | .set = &evergreen_irq_set, | |
1314 | .process = &evergreen_irq_process, | |
1315 | }, | |
c79a49ca AD |
1316 | .display = { |
1317 | .bandwidth_update = &evergreen_bandwidth_update, | |
1318 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1319 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1320 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1321 | }, |
27cd7769 AD |
1322 | .copy = { |
1323 | .blit = &r600_copy_blit, | |
1324 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1325 | .dma = NULL, | |
1326 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1327 | .copy = &r600_copy_blit, | |
1328 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1329 | }, | |
9e6f3d02 AD |
1330 | .surface = { |
1331 | .set_reg = r600_set_surface_reg, | |
1332 | .clear_reg = r600_clear_surface_reg, | |
1333 | }, | |
901ea57d AD |
1334 | .hpd = { |
1335 | .init = &evergreen_hpd_init, | |
1336 | .fini = &evergreen_hpd_fini, | |
1337 | .sense = &evergreen_hpd_sense, | |
1338 | .set_polarity = &evergreen_hpd_set_polarity, | |
1339 | }, | |
a02fa397 AD |
1340 | .pm = { |
1341 | .misc = &evergreen_pm_misc, | |
1342 | .prepare = &evergreen_pm_prepare, | |
1343 | .finish = &evergreen_pm_finish, | |
1344 | .init_profile = &r600_pm_init_profile, | |
1345 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1346 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1347 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1348 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1349 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1350 | .get_pcie_lanes = NULL, | |
1351 | .set_pcie_lanes = NULL, | |
1352 | .set_clock_gating = NULL, | |
a02fa397 | 1353 | }, |
0f9e006c AD |
1354 | .pflip = { |
1355 | .pre_page_flip = &evergreen_pre_page_flip, | |
1356 | .page_flip = &evergreen_page_flip, | |
1357 | .post_page_flip = &evergreen_post_page_flip, | |
1358 | }, | |
a43b7665 AD |
1359 | }; |
1360 | ||
e3487629 AD |
1361 | static struct radeon_asic cayman_asic = { |
1362 | .init = &cayman_init, | |
1363 | .fini = &cayman_fini, | |
1364 | .suspend = &cayman_suspend, | |
1365 | .resume = &cayman_resume, | |
e3487629 AD |
1366 | .asic_reset = &cayman_asic_reset, |
1367 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1368 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1369 | .gui_idle = &r600_gui_idle, | |
1370 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1371 | .gart = { |
1372 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1373 | .set_page = &rs600_gart_set_page, | |
1374 | }, | |
05b07147 CK |
1375 | .vm = { |
1376 | .init = &cayman_vm_init, | |
1377 | .fini = &cayman_vm_fini, | |
1378 | .bind = &cayman_vm_bind, | |
05b07147 CK |
1379 | .tlb_flush = &cayman_vm_tlb_flush, |
1380 | .page_flags = &cayman_vm_page_flags, | |
1381 | .set_page = &cayman_vm_set_page, | |
1382 | }, | |
4c87bc26 CK |
1383 | .ring = { |
1384 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
1385 | .ib_execute = &cayman_ring_ib_execute, |
1386 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1387 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1388 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1389 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1390 | .ring_test = &r600_ring_test, |
1391 | .ib_test = &r600_ib_test, | |
abfaa44b | 1392 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1393 | }, |
1394 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1395 | .ib_execute = &cayman_ring_ib_execute, |
1396 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1397 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1398 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1399 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1400 | .ring_test = &r600_ring_test, |
1401 | .ib_test = &r600_ib_test, | |
abfaa44b | 1402 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1403 | }, |
1404 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1405 | .ib_execute = &cayman_ring_ib_execute, |
1406 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1407 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1408 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1409 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1410 | .ring_test = &r600_ring_test, |
1411 | .ib_test = &r600_ib_test, | |
abfaa44b | 1412 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1413 | } |
1414 | }, | |
b35ea4ab AD |
1415 | .irq = { |
1416 | .set = &evergreen_irq_set, | |
1417 | .process = &evergreen_irq_process, | |
1418 | }, | |
c79a49ca AD |
1419 | .display = { |
1420 | .bandwidth_update = &evergreen_bandwidth_update, | |
1421 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1422 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1423 | .set_backlight_level = &atombios_set_backlight_level, |
c79a49ca | 1424 | }, |
27cd7769 AD |
1425 | .copy = { |
1426 | .blit = &r600_copy_blit, | |
1427 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1428 | .dma = NULL, | |
1429 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1430 | .copy = &r600_copy_blit, | |
1431 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1432 | }, | |
9e6f3d02 AD |
1433 | .surface = { |
1434 | .set_reg = r600_set_surface_reg, | |
1435 | .clear_reg = r600_clear_surface_reg, | |
1436 | }, | |
901ea57d AD |
1437 | .hpd = { |
1438 | .init = &evergreen_hpd_init, | |
1439 | .fini = &evergreen_hpd_fini, | |
1440 | .sense = &evergreen_hpd_sense, | |
1441 | .set_polarity = &evergreen_hpd_set_polarity, | |
1442 | }, | |
a02fa397 AD |
1443 | .pm = { |
1444 | .misc = &evergreen_pm_misc, | |
1445 | .prepare = &evergreen_pm_prepare, | |
1446 | .finish = &evergreen_pm_finish, | |
1447 | .init_profile = &r600_pm_init_profile, | |
1448 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1449 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1450 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1451 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1452 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1453 | .get_pcie_lanes = NULL, | |
1454 | .set_pcie_lanes = NULL, | |
1455 | .set_clock_gating = NULL, | |
a02fa397 | 1456 | }, |
0f9e006c AD |
1457 | .pflip = { |
1458 | .pre_page_flip = &evergreen_pre_page_flip, | |
1459 | .page_flip = &evergreen_page_flip, | |
1460 | .post_page_flip = &evergreen_post_page_flip, | |
1461 | }, | |
e3487629 AD |
1462 | }; |
1463 | ||
be63fe8c AD |
1464 | static struct radeon_asic trinity_asic = { |
1465 | .init = &cayman_init, | |
1466 | .fini = &cayman_fini, | |
1467 | .suspend = &cayman_suspend, | |
1468 | .resume = &cayman_resume, | |
be63fe8c AD |
1469 | .asic_reset = &cayman_asic_reset, |
1470 | .vga_set_state = &r600_vga_set_state, | |
1471 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1472 | .gui_idle = &r600_gui_idle, | |
1473 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
1474 | .gart = { | |
1475 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1476 | .set_page = &rs600_gart_set_page, | |
1477 | }, | |
05b07147 CK |
1478 | .vm = { |
1479 | .init = &cayman_vm_init, | |
1480 | .fini = &cayman_vm_fini, | |
1481 | .bind = &cayman_vm_bind, | |
05b07147 CK |
1482 | .tlb_flush = &cayman_vm_tlb_flush, |
1483 | .page_flags = &cayman_vm_page_flags, | |
1484 | .set_page = &cayman_vm_set_page, | |
1485 | }, | |
be63fe8c AD |
1486 | .ring = { |
1487 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1488 | .ib_execute = &cayman_ring_ib_execute, | |
1489 | .ib_parse = &evergreen_ib_parse, | |
1490 | .emit_fence = &cayman_fence_ring_emit, | |
1491 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1492 | .cs_parse = &evergreen_cs_parse, | |
1493 | .ring_test = &r600_ring_test, | |
1494 | .ib_test = &r600_ib_test, | |
abfaa44b | 1495 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1496 | }, |
1497 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
1498 | .ib_execute = &cayman_ring_ib_execute, | |
1499 | .ib_parse = &evergreen_ib_parse, | |
1500 | .emit_fence = &cayman_fence_ring_emit, | |
1501 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1502 | .cs_parse = &evergreen_cs_parse, | |
1503 | .ring_test = &r600_ring_test, | |
1504 | .ib_test = &r600_ib_test, | |
abfaa44b | 1505 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1506 | }, |
1507 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
1508 | .ib_execute = &cayman_ring_ib_execute, | |
1509 | .ib_parse = &evergreen_ib_parse, | |
1510 | .emit_fence = &cayman_fence_ring_emit, | |
1511 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1512 | .cs_parse = &evergreen_cs_parse, | |
1513 | .ring_test = &r600_ring_test, | |
1514 | .ib_test = &r600_ib_test, | |
abfaa44b | 1515 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1516 | } |
1517 | }, | |
1518 | .irq = { | |
1519 | .set = &evergreen_irq_set, | |
1520 | .process = &evergreen_irq_process, | |
1521 | }, | |
1522 | .display = { | |
1523 | .bandwidth_update = &dce6_bandwidth_update, | |
1524 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1525 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1526 | .set_backlight_level = &atombios_set_backlight_level, |
be63fe8c AD |
1527 | }, |
1528 | .copy = { | |
1529 | .blit = &r600_copy_blit, | |
1530 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1531 | .dma = NULL, | |
1532 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1533 | .copy = &r600_copy_blit, | |
1534 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1535 | }, | |
1536 | .surface = { | |
1537 | .set_reg = r600_set_surface_reg, | |
1538 | .clear_reg = r600_clear_surface_reg, | |
1539 | }, | |
1540 | .hpd = { | |
1541 | .init = &evergreen_hpd_init, | |
1542 | .fini = &evergreen_hpd_fini, | |
1543 | .sense = &evergreen_hpd_sense, | |
1544 | .set_polarity = &evergreen_hpd_set_polarity, | |
1545 | }, | |
1546 | .pm = { | |
1547 | .misc = &evergreen_pm_misc, | |
1548 | .prepare = &evergreen_pm_prepare, | |
1549 | .finish = &evergreen_pm_finish, | |
1550 | .init_profile = &sumo_pm_init_profile, | |
1551 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1552 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1553 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1554 | .get_memory_clock = NULL, | |
1555 | .set_memory_clock = NULL, | |
1556 | .get_pcie_lanes = NULL, | |
1557 | .set_pcie_lanes = NULL, | |
1558 | .set_clock_gating = NULL, | |
1559 | }, | |
1560 | .pflip = { | |
1561 | .pre_page_flip = &evergreen_pre_page_flip, | |
1562 | .page_flip = &evergreen_page_flip, | |
1563 | .post_page_flip = &evergreen_post_page_flip, | |
1564 | }, | |
1565 | }; | |
1566 | ||
02779c08 AD |
1567 | static struct radeon_asic si_asic = { |
1568 | .init = &si_init, | |
1569 | .fini = &si_fini, | |
1570 | .suspend = &si_suspend, | |
1571 | .resume = &si_resume, | |
02779c08 AD |
1572 | .asic_reset = &si_asic_reset, |
1573 | .vga_set_state = &r600_vga_set_state, | |
1574 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1575 | .gui_idle = &r600_gui_idle, | |
1576 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
1577 | .gart = { | |
1578 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
1579 | .set_page = &rs600_gart_set_page, | |
1580 | }, | |
05b07147 CK |
1581 | .vm = { |
1582 | .init = &si_vm_init, | |
1583 | .fini = &si_vm_fini, | |
1584 | .bind = &si_vm_bind, | |
05b07147 CK |
1585 | .tlb_flush = &si_vm_tlb_flush, |
1586 | .page_flags = &cayman_vm_page_flags, | |
1587 | .set_page = &cayman_vm_set_page, | |
1588 | }, | |
02779c08 AD |
1589 | .ring = { |
1590 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1591 | .ib_execute = &si_ring_ib_execute, | |
1592 | .ib_parse = &si_ib_parse, | |
1593 | .emit_fence = &si_fence_ring_emit, | |
1594 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1595 | .cs_parse = NULL, | |
1596 | .ring_test = &r600_ring_test, | |
1597 | .ib_test = &r600_ib_test, | |
312c4a8c | 1598 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1599 | }, |
1600 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
1601 | .ib_execute = &si_ring_ib_execute, | |
1602 | .ib_parse = &si_ib_parse, | |
1603 | .emit_fence = &si_fence_ring_emit, | |
1604 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1605 | .cs_parse = NULL, | |
1606 | .ring_test = &r600_ring_test, | |
1607 | .ib_test = &r600_ib_test, | |
312c4a8c | 1608 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1609 | }, |
1610 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
1611 | .ib_execute = &si_ring_ib_execute, | |
1612 | .ib_parse = &si_ib_parse, | |
1613 | .emit_fence = &si_fence_ring_emit, | |
1614 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1615 | .cs_parse = NULL, | |
1616 | .ring_test = &r600_ring_test, | |
1617 | .ib_test = &r600_ib_test, | |
312c4a8c | 1618 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1619 | } |
1620 | }, | |
1621 | .irq = { | |
1622 | .set = &si_irq_set, | |
1623 | .process = &si_irq_process, | |
1624 | }, | |
1625 | .display = { | |
1626 | .bandwidth_update = &dce6_bandwidth_update, | |
1627 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1628 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1629 | .set_backlight_level = &atombios_set_backlight_level, |
02779c08 AD |
1630 | }, |
1631 | .copy = { | |
1632 | .blit = NULL, | |
1633 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1634 | .dma = NULL, | |
1635 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1636 | .copy = NULL, | |
1637 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1638 | }, | |
1639 | .surface = { | |
1640 | .set_reg = r600_set_surface_reg, | |
1641 | .clear_reg = r600_clear_surface_reg, | |
1642 | }, | |
1643 | .hpd = { | |
1644 | .init = &evergreen_hpd_init, | |
1645 | .fini = &evergreen_hpd_fini, | |
1646 | .sense = &evergreen_hpd_sense, | |
1647 | .set_polarity = &evergreen_hpd_set_polarity, | |
1648 | }, | |
1649 | .pm = { | |
1650 | .misc = &evergreen_pm_misc, | |
1651 | .prepare = &evergreen_pm_prepare, | |
1652 | .finish = &evergreen_pm_finish, | |
1653 | .init_profile = &sumo_pm_init_profile, | |
1654 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1655 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1656 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1657 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1658 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1659 | .get_pcie_lanes = NULL, | |
1660 | .set_pcie_lanes = NULL, | |
1661 | .set_clock_gating = NULL, | |
1662 | }, | |
1663 | .pflip = { | |
1664 | .pre_page_flip = &evergreen_pre_page_flip, | |
1665 | .page_flip = &evergreen_page_flip, | |
1666 | .post_page_flip = &evergreen_post_page_flip, | |
1667 | }, | |
1668 | }; | |
1669 | ||
abf1dc67 AD |
1670 | /** |
1671 | * radeon_asic_init - register asic specific callbacks | |
1672 | * | |
1673 | * @rdev: radeon device pointer | |
1674 | * | |
1675 | * Registers the appropriate asic specific callbacks for each | |
1676 | * chip family. Also sets other asics specific info like the number | |
1677 | * of crtcs and the register aperture accessors (all asics). | |
1678 | * Returns 0 for success. | |
1679 | */ | |
0a10c851 DV |
1680 | int radeon_asic_init(struct radeon_device *rdev) |
1681 | { | |
1682 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
1683 | |
1684 | /* set the number of crtcs */ | |
1685 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
1686 | rdev->num_crtc = 1; | |
1687 | else | |
1688 | rdev->num_crtc = 2; | |
1689 | ||
0a10c851 DV |
1690 | switch (rdev->family) { |
1691 | case CHIP_R100: | |
1692 | case CHIP_RV100: | |
1693 | case CHIP_RS100: | |
1694 | case CHIP_RV200: | |
1695 | case CHIP_RS200: | |
1696 | rdev->asic = &r100_asic; | |
1697 | break; | |
1698 | case CHIP_R200: | |
1699 | case CHIP_RV250: | |
1700 | case CHIP_RS300: | |
1701 | case CHIP_RV280: | |
1702 | rdev->asic = &r200_asic; | |
1703 | break; | |
1704 | case CHIP_R300: | |
1705 | case CHIP_R350: | |
1706 | case CHIP_RV350: | |
1707 | case CHIP_RV380: | |
1708 | if (rdev->flags & RADEON_IS_PCIE) | |
1709 | rdev->asic = &r300_asic_pcie; | |
1710 | else | |
1711 | rdev->asic = &r300_asic; | |
1712 | break; | |
1713 | case CHIP_R420: | |
1714 | case CHIP_R423: | |
1715 | case CHIP_RV410: | |
1716 | rdev->asic = &r420_asic; | |
07bb084c AD |
1717 | /* handle macs */ |
1718 | if (rdev->bios == NULL) { | |
798bcf73 AD |
1719 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
1720 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
1721 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
1722 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 1723 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 1724 | } |
0a10c851 DV |
1725 | break; |
1726 | case CHIP_RS400: | |
1727 | case CHIP_RS480: | |
1728 | rdev->asic = &rs400_asic; | |
1729 | break; | |
1730 | case CHIP_RS600: | |
1731 | rdev->asic = &rs600_asic; | |
1732 | break; | |
1733 | case CHIP_RS690: | |
1734 | case CHIP_RS740: | |
1735 | rdev->asic = &rs690_asic; | |
1736 | break; | |
1737 | case CHIP_RV515: | |
1738 | rdev->asic = &rv515_asic; | |
1739 | break; | |
1740 | case CHIP_R520: | |
1741 | case CHIP_RV530: | |
1742 | case CHIP_RV560: | |
1743 | case CHIP_RV570: | |
1744 | case CHIP_R580: | |
1745 | rdev->asic = &r520_asic; | |
1746 | break; | |
1747 | case CHIP_R600: | |
1748 | case CHIP_RV610: | |
1749 | case CHIP_RV630: | |
1750 | case CHIP_RV620: | |
1751 | case CHIP_RV635: | |
1752 | case CHIP_RV670: | |
f47299c5 AD |
1753 | rdev->asic = &r600_asic; |
1754 | break; | |
0a10c851 DV |
1755 | case CHIP_RS780: |
1756 | case CHIP_RS880: | |
f47299c5 | 1757 | rdev->asic = &rs780_asic; |
0a10c851 DV |
1758 | break; |
1759 | case CHIP_RV770: | |
1760 | case CHIP_RV730: | |
1761 | case CHIP_RV710: | |
1762 | case CHIP_RV740: | |
1763 | rdev->asic = &rv770_asic; | |
1764 | break; | |
1765 | case CHIP_CEDAR: | |
1766 | case CHIP_REDWOOD: | |
1767 | case CHIP_JUNIPER: | |
1768 | case CHIP_CYPRESS: | |
1769 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
1770 | /* set num crtcs */ |
1771 | if (rdev->family == CHIP_CEDAR) | |
1772 | rdev->num_crtc = 4; | |
1773 | else | |
1774 | rdev->num_crtc = 6; | |
0a10c851 DV |
1775 | rdev->asic = &evergreen_asic; |
1776 | break; | |
958261d1 | 1777 | case CHIP_PALM: |
89da5a37 AD |
1778 | case CHIP_SUMO: |
1779 | case CHIP_SUMO2: | |
958261d1 AD |
1780 | rdev->asic = &sumo_asic; |
1781 | break; | |
a43b7665 AD |
1782 | case CHIP_BARTS: |
1783 | case CHIP_TURKS: | |
1784 | case CHIP_CAICOS: | |
ba7e05e9 AD |
1785 | /* set num crtcs */ |
1786 | if (rdev->family == CHIP_CAICOS) | |
1787 | rdev->num_crtc = 4; | |
1788 | else | |
1789 | rdev->num_crtc = 6; | |
a43b7665 AD |
1790 | rdev->asic = &btc_asic; |
1791 | break; | |
e3487629 AD |
1792 | case CHIP_CAYMAN: |
1793 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
1794 | /* set num crtcs */ |
1795 | rdev->num_crtc = 6; | |
e3487629 | 1796 | break; |
be63fe8c AD |
1797 | case CHIP_ARUBA: |
1798 | rdev->asic = &trinity_asic; | |
1799 | /* set num crtcs */ | |
1800 | rdev->num_crtc = 4; | |
be63fe8c | 1801 | break; |
02779c08 AD |
1802 | case CHIP_TAHITI: |
1803 | case CHIP_PITCAIRN: | |
1804 | case CHIP_VERDE: | |
1805 | rdev->asic = &si_asic; | |
1806 | /* set num crtcs */ | |
1807 | rdev->num_crtc = 6; | |
02779c08 | 1808 | break; |
0a10c851 DV |
1809 | default: |
1810 | /* FIXME: not supported yet */ | |
1811 | return -EINVAL; | |
1812 | } | |
1813 | ||
1814 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
1815 | rdev->asic->pm.get_memory_clock = NULL; |
1816 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
1817 | } |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 |