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drm/radeon/kms: add gui_idle callback
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44{
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48}
49
50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51{
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55}
56
57static void radeon_register_accessor_init(struct radeon_device *rdev)
58{
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101}
102
103
104/* helper to disable agp */
105void radeon_agp_disable(struct radeon_device *rdev)
106{
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126}
127
128/*
129 * ASIC
130 */
48e7a5f1
DV		 131static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
225758d8 137 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 138 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 139 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
140 .gart_set_page = &r100_pci_gart_set_page,
141 .cp_commit = &r100_cp_commit,
142 .ring_start = &r100_ring_start,
143 .ring_test = &r100_ring_test,
144 .ring_ib_execute = &r100_ring_ib_execute,
145 .irq_set = &r100_irq_set,
146 .irq_process = &r100_irq_process,
147 .get_vblank_counter = &r100_get_vblank_counter,
148 .fence_ring_emit = &r100_fence_ring_emit,
149 .cs_parse = &r100_cs_parse,
150 .copy_blit = &r100_copy_blit,
151 .copy_dma = NULL,
152 .copy = &r100_copy_blit,
153 .get_engine_clock = &radeon_legacy_get_engine_clock,
154 .set_engine_clock = &radeon_legacy_set_engine_clock,
155 .get_memory_clock = &radeon_legacy_get_memory_clock,
156 .set_memory_clock = NULL,
157 .get_pcie_lanes = NULL,
158 .set_pcie_lanes = NULL,
159 .set_clock_gating = &radeon_legacy_set_clock_gating,
160 .set_surface_reg = r100_set_surface_reg,
161 .clear_surface_reg = r100_clear_surface_reg,
162 .bandwidth_update = &r100_bandwidth_update,
163 .hpd_init = &r100_hpd_init,
164 .hpd_fini = &r100_hpd_fini,
165 .hpd_sense = &r100_hpd_sense,
166 .hpd_set_polarity = &r100_hpd_set_polarity,
167 .ioctl_wait_idle = NULL,
def9ba9c 168 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 169};
170
171static struct radeon_asic r200_asic = {
172 .init = &r100_init,
173 .fini = &r100_fini,
174 .suspend = &r100_suspend,
175 .resume = &r100_resume,
176 .vga_set_state = &r100_vga_set_state,
225758d8 177 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 178 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 179 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
180 .gart_set_page = &r100_pci_gart_set_page,
181 .cp_commit = &r100_cp_commit,
182 .ring_start = &r100_ring_start,
183 .ring_test = &r100_ring_test,
184 .ring_ib_execute = &r100_ring_ib_execute,
185 .irq_set = &r100_irq_set,
186 .irq_process = &r100_irq_process,
187 .get_vblank_counter = &r100_get_vblank_counter,
188 .fence_ring_emit = &r100_fence_ring_emit,
189 .cs_parse = &r100_cs_parse,
190 .copy_blit = &r100_copy_blit,
191 .copy_dma = &r200_copy_dma,
192 .copy = &r100_copy_blit,
193 .get_engine_clock = &radeon_legacy_get_engine_clock,
194 .set_engine_clock = &radeon_legacy_set_engine_clock,
195 .get_memory_clock = &radeon_legacy_get_memory_clock,
196 .set_memory_clock = NULL,
197 .set_pcie_lanes = NULL,
198 .set_clock_gating = &radeon_legacy_set_clock_gating,
199 .set_surface_reg = r100_set_surface_reg,
200 .clear_surface_reg = r100_clear_surface_reg,
201 .bandwidth_update = &r100_bandwidth_update,
202 .hpd_init = &r100_hpd_init,
203 .hpd_fini = &r100_hpd_fini,
204 .hpd_sense = &r100_hpd_sense,
205 .hpd_set_polarity = &r100_hpd_set_polarity,
206 .ioctl_wait_idle = NULL,
def9ba9c 207 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 208};
209
210static struct radeon_asic r300_asic = {
211 .init = &r300_init,
212 .fini = &r300_fini,
213 .suspend = &r300_suspend,
214 .resume = &r300_resume,
215 .vga_set_state = &r100_vga_set_state,
225758d8 216 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 217 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 218 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
219 .gart_set_page = &r100_pci_gart_set_page,
220 .cp_commit = &r100_cp_commit,
221 .ring_start = &r300_ring_start,
222 .ring_test = &r100_ring_test,
223 .ring_ib_execute = &r100_ring_ib_execute,
224 .irq_set = &r100_irq_set,
225 .irq_process = &r100_irq_process,
226 .get_vblank_counter = &r100_get_vblank_counter,
227 .fence_ring_emit = &r300_fence_ring_emit,
228 .cs_parse = &r300_cs_parse,
229 .copy_blit = &r100_copy_blit,
230 .copy_dma = &r200_copy_dma,
231 .copy = &r100_copy_blit,
232 .get_engine_clock = &radeon_legacy_get_engine_clock,
233 .set_engine_clock = &radeon_legacy_set_engine_clock,
234 .get_memory_clock = &radeon_legacy_get_memory_clock,
235 .set_memory_clock = NULL,
236 .get_pcie_lanes = &rv370_get_pcie_lanes,
237 .set_pcie_lanes = &rv370_set_pcie_lanes,
238 .set_clock_gating = &radeon_legacy_set_clock_gating,
239 .set_surface_reg = r100_set_surface_reg,
240 .clear_surface_reg = r100_clear_surface_reg,
241 .bandwidth_update = &r100_bandwidth_update,
242 .hpd_init = &r100_hpd_init,
243 .hpd_fini = &r100_hpd_fini,
244 .hpd_sense = &r100_hpd_sense,
245 .hpd_set_polarity = &r100_hpd_set_polarity,
246 .ioctl_wait_idle = NULL,
def9ba9c 247 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 248};
249
250static struct radeon_asic r300_asic_pcie = {
251 .init = &r300_init,
252 .fini = &r300_fini,
253 .suspend = &r300_suspend,
254 .resume = &r300_resume,
255 .vga_set_state = &r100_vga_set_state,
225758d8 256 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 257 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 258 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
259 .gart_set_page = &rv370_pcie_gart_set_page,
260 .cp_commit = &r100_cp_commit,
261 .ring_start = &r300_ring_start,
262 .ring_test = &r100_ring_test,
263 .ring_ib_execute = &r100_ring_ib_execute,
264 .irq_set = &r100_irq_set,
265 .irq_process = &r100_irq_process,
266 .get_vblank_counter = &r100_get_vblank_counter,
267 .fence_ring_emit = &r300_fence_ring_emit,
268 .cs_parse = &r300_cs_parse,
269 .copy_blit = &r100_copy_blit,
270 .copy_dma = &r200_copy_dma,
271 .copy = &r100_copy_blit,
272 .get_engine_clock = &radeon_legacy_get_engine_clock,
273 .set_engine_clock = &radeon_legacy_set_engine_clock,
274 .get_memory_clock = &radeon_legacy_get_memory_clock,
275 .set_memory_clock = NULL,
276 .set_pcie_lanes = &rv370_set_pcie_lanes,
277 .set_clock_gating = &radeon_legacy_set_clock_gating,
278 .set_surface_reg = r100_set_surface_reg,
279 .clear_surface_reg = r100_clear_surface_reg,
280 .bandwidth_update = &r100_bandwidth_update,
281 .hpd_init = &r100_hpd_init,
282 .hpd_fini = &r100_hpd_fini,
283 .hpd_sense = &r100_hpd_sense,
284 .hpd_set_polarity = &r100_hpd_set_polarity,
285 .ioctl_wait_idle = NULL,
def9ba9c 286 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 287};
288
289static struct radeon_asic r420_asic = {
290 .init = &r420_init,
291 .fini = &r420_fini,
292 .suspend = &r420_suspend,
293 .resume = &r420_resume,
294 .vga_set_state = &r100_vga_set_state,
225758d8 295 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 296 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 297 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
298 .gart_set_page = &rv370_pcie_gart_set_page,
299 .cp_commit = &r100_cp_commit,
300 .ring_start = &r300_ring_start,
301 .ring_test = &r100_ring_test,
302 .ring_ib_execute = &r100_ring_ib_execute,
303 .irq_set = &r100_irq_set,
304 .irq_process = &r100_irq_process,
305 .get_vblank_counter = &r100_get_vblank_counter,
306 .fence_ring_emit = &r300_fence_ring_emit,
307 .cs_parse = &r300_cs_parse,
308 .copy_blit = &r100_copy_blit,
309 .copy_dma = &r200_copy_dma,
310 .copy = &r100_copy_blit,
311 .get_engine_clock = &radeon_atom_get_engine_clock,
312 .set_engine_clock = &radeon_atom_set_engine_clock,
313 .get_memory_clock = &radeon_atom_get_memory_clock,
314 .set_memory_clock = &radeon_atom_set_memory_clock,
315 .get_pcie_lanes = &rv370_get_pcie_lanes,
316 .set_pcie_lanes = &rv370_set_pcie_lanes,
317 .set_clock_gating = &radeon_atom_set_clock_gating,
318 .set_surface_reg = r100_set_surface_reg,
319 .clear_surface_reg = r100_clear_surface_reg,
320 .bandwidth_update = &r100_bandwidth_update,
321 .hpd_init = &r100_hpd_init,
322 .hpd_fini = &r100_hpd_fini,
323 .hpd_sense = &r100_hpd_sense,
324 .hpd_set_polarity = &r100_hpd_set_polarity,
325 .ioctl_wait_idle = NULL,
def9ba9c 326 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 327};
328
329static struct radeon_asic rs400_asic = {
330 .init = &rs400_init,
331 .fini = &rs400_fini,
332 .suspend = &rs400_suspend,
333 .resume = &rs400_resume,
334 .vga_set_state = &r100_vga_set_state,
225758d8 335 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 336 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 337 .gart_tlb_flush = &rs400_gart_tlb_flush,
338 .gart_set_page = &rs400_gart_set_page,
339 .cp_commit = &r100_cp_commit,
340 .ring_start = &r300_ring_start,
341 .ring_test = &r100_ring_test,
342 .ring_ib_execute = &r100_ring_ib_execute,
343 .irq_set = &r100_irq_set,
344 .irq_process = &r100_irq_process,
345 .get_vblank_counter = &r100_get_vblank_counter,
346 .fence_ring_emit = &r300_fence_ring_emit,
347 .cs_parse = &r300_cs_parse,
348 .copy_blit = &r100_copy_blit,
349 .copy_dma = &r200_copy_dma,
350 .copy = &r100_copy_blit,
351 .get_engine_clock = &radeon_legacy_get_engine_clock,
352 .set_engine_clock = &radeon_legacy_set_engine_clock,
353 .get_memory_clock = &radeon_legacy_get_memory_clock,
354 .set_memory_clock = NULL,
355 .get_pcie_lanes = NULL,
356 .set_pcie_lanes = NULL,
357 .set_clock_gating = &radeon_legacy_set_clock_gating,
358 .set_surface_reg = r100_set_surface_reg,
359 .clear_surface_reg = r100_clear_surface_reg,
360 .bandwidth_update = &r100_bandwidth_update,
361 .hpd_init = &r100_hpd_init,
362 .hpd_fini = &r100_hpd_fini,
363 .hpd_sense = &r100_hpd_sense,
364 .hpd_set_polarity = &r100_hpd_set_polarity,
365 .ioctl_wait_idle = NULL,
def9ba9c 366 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 367};
368
369static struct radeon_asic rs600_asic = {
370 .init = &rs600_init,
371 .fini = &rs600_fini,
372 .suspend = &rs600_suspend,
373 .resume = &rs600_resume,
374 .vga_set_state = &r100_vga_set_state,
225758d8 375 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 376 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 377 .gart_tlb_flush = &rs600_gart_tlb_flush,
378 .gart_set_page = &rs600_gart_set_page,
379 .cp_commit = &r100_cp_commit,
380 .ring_start = &r300_ring_start,
381 .ring_test = &r100_ring_test,
382 .ring_ib_execute = &r100_ring_ib_execute,
383 .irq_set = &rs600_irq_set,
384 .irq_process = &rs600_irq_process,
385 .get_vblank_counter = &rs600_get_vblank_counter,
386 .fence_ring_emit = &r300_fence_ring_emit,
387 .cs_parse = &r300_cs_parse,
388 .copy_blit = &r100_copy_blit,
389 .copy_dma = &r200_copy_dma,
390 .copy = &r100_copy_blit,
391 .get_engine_clock = &radeon_atom_get_engine_clock,
392 .set_engine_clock = &radeon_atom_set_engine_clock,
393 .get_memory_clock = &radeon_atom_get_memory_clock,
394 .set_memory_clock = &radeon_atom_set_memory_clock,
395 .get_pcie_lanes = NULL,
396 .set_pcie_lanes = NULL,
397 .set_clock_gating = &radeon_atom_set_clock_gating,
398 .set_surface_reg = r100_set_surface_reg,
399 .clear_surface_reg = r100_clear_surface_reg,
400 .bandwidth_update = &rs600_bandwidth_update,
401 .hpd_init = &rs600_hpd_init,
402 .hpd_fini = &rs600_hpd_fini,
403 .hpd_sense = &rs600_hpd_sense,
404 .hpd_set_polarity = &rs600_hpd_set_polarity,
405 .ioctl_wait_idle = NULL,
def9ba9c 406 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 407};
408
409static struct radeon_asic rs690_asic = {
410 .init = &rs690_init,
411 .fini = &rs690_fini,
412 .suspend = &rs690_suspend,
413 .resume = &rs690_resume,
414 .vga_set_state = &r100_vga_set_state,
225758d8 415 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 416 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 417 .gart_tlb_flush = &rs400_gart_tlb_flush,
418 .gart_set_page = &rs400_gart_set_page,
419 .cp_commit = &r100_cp_commit,
420 .ring_start = &r300_ring_start,
421 .ring_test = &r100_ring_test,
422 .ring_ib_execute = &r100_ring_ib_execute,
423 .irq_set = &rs600_irq_set,
424 .irq_process = &rs600_irq_process,
425 .get_vblank_counter = &rs600_get_vblank_counter,
426 .fence_ring_emit = &r300_fence_ring_emit,
427 .cs_parse = &r300_cs_parse,
428 .copy_blit = &r100_copy_blit,
429 .copy_dma = &r200_copy_dma,
430 .copy = &r200_copy_dma,
431 .get_engine_clock = &radeon_atom_get_engine_clock,
432 .set_engine_clock = &radeon_atom_set_engine_clock,
433 .get_memory_clock = &radeon_atom_get_memory_clock,
434 .set_memory_clock = &radeon_atom_set_memory_clock,
435 .get_pcie_lanes = NULL,
436 .set_pcie_lanes = NULL,
437 .set_clock_gating = &radeon_atom_set_clock_gating,
438 .set_surface_reg = r100_set_surface_reg,
439 .clear_surface_reg = r100_clear_surface_reg,
440 .bandwidth_update = &rs690_bandwidth_update,
441 .hpd_init = &rs600_hpd_init,
442 .hpd_fini = &rs600_hpd_fini,
443 .hpd_sense = &rs600_hpd_sense,
444 .hpd_set_polarity = &rs600_hpd_set_polarity,
445 .ioctl_wait_idle = NULL,
def9ba9c 446 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 447};
448
449static struct radeon_asic rv515_asic = {
450 .init = &rv515_init,
451 .fini = &rv515_fini,
452 .suspend = &rv515_suspend,
453 .resume = &rv515_resume,
454 .vga_set_state = &r100_vga_set_state,
225758d8 455 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 456 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 457 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
458 .gart_set_page = &rv370_pcie_gart_set_page,
459 .cp_commit = &r100_cp_commit,
460 .ring_start = &rv515_ring_start,
461 .ring_test = &r100_ring_test,
462 .ring_ib_execute = &r100_ring_ib_execute,
463 .irq_set = &rs600_irq_set,
464 .irq_process = &rs600_irq_process,
465 .get_vblank_counter = &rs600_get_vblank_counter,
466 .fence_ring_emit = &r300_fence_ring_emit,
467 .cs_parse = &r300_cs_parse,
468 .copy_blit = &r100_copy_blit,
469 .copy_dma = &r200_copy_dma,
470 .copy = &r100_copy_blit,
471 .get_engine_clock = &radeon_atom_get_engine_clock,
472 .set_engine_clock = &radeon_atom_set_engine_clock,
473 .get_memory_clock = &radeon_atom_get_memory_clock,
474 .set_memory_clock = &radeon_atom_set_memory_clock,
475 .get_pcie_lanes = &rv370_get_pcie_lanes,
476 .set_pcie_lanes = &rv370_set_pcie_lanes,
477 .set_clock_gating = &radeon_atom_set_clock_gating,
478 .set_surface_reg = r100_set_surface_reg,
479 .clear_surface_reg = r100_clear_surface_reg,
480 .bandwidth_update = &rv515_bandwidth_update,
481 .hpd_init = &rs600_hpd_init,
482 .hpd_fini = &rs600_hpd_fini,
483 .hpd_sense = &rs600_hpd_sense,
484 .hpd_set_polarity = &rs600_hpd_set_polarity,
485 .ioctl_wait_idle = NULL,
def9ba9c 486 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 487};
488
489static struct radeon_asic r520_asic = {
490 .init = &r520_init,
491 .fini = &rv515_fini,
492 .suspend = &rv515_suspend,
493 .resume = &r520_resume,
494 .vga_set_state = &r100_vga_set_state,
225758d8 495 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 496 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 497 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
498 .gart_set_page = &rv370_pcie_gart_set_page,
499 .cp_commit = &r100_cp_commit,
500 .ring_start = &rv515_ring_start,
501 .ring_test = &r100_ring_test,
502 .ring_ib_execute = &r100_ring_ib_execute,
503 .irq_set = &rs600_irq_set,
504 .irq_process = &rs600_irq_process,
505 .get_vblank_counter = &rs600_get_vblank_counter,
506 .fence_ring_emit = &r300_fence_ring_emit,
507 .cs_parse = &r300_cs_parse,
508 .copy_blit = &r100_copy_blit,
509 .copy_dma = &r200_copy_dma,
510 .copy = &r100_copy_blit,
511 .get_engine_clock = &radeon_atom_get_engine_clock,
512 .set_engine_clock = &radeon_atom_set_engine_clock,
513 .get_memory_clock = &radeon_atom_get_memory_clock,
514 .set_memory_clock = &radeon_atom_set_memory_clock,
515 .get_pcie_lanes = &rv370_get_pcie_lanes,
516 .set_pcie_lanes = &rv370_set_pcie_lanes,
517 .set_clock_gating = &radeon_atom_set_clock_gating,
518 .set_surface_reg = r100_set_surface_reg,
519 .clear_surface_reg = r100_clear_surface_reg,
520 .bandwidth_update = &rv515_bandwidth_update,
521 .hpd_init = &rs600_hpd_init,
522 .hpd_fini = &rs600_hpd_fini,
523 .hpd_sense = &rs600_hpd_sense,
524 .hpd_set_polarity = &rs600_hpd_set_polarity,
525 .ioctl_wait_idle = NULL,
def9ba9c 526 .gui_idle = &r100_gui_idle,
48e7a5f1
DV		 527};
528
529static struct radeon_asic r600_asic = {
530 .init = &r600_init,
531 .fini = &r600_fini,
532 .suspend = &r600_suspend,
533 .resume = &r600_resume,
534 .cp_commit = &r600_cp_commit,
535 .vga_set_state = &r600_vga_set_state,
225758d8 536 .gpu_is_lockup = &r600_gpu_is_lockup,
a2d07b74 537 .asic_reset = &r600_asic_reset,
48e7a5f1
DV		 538 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
539 .gart_set_page = &rs600_gart_set_page,
540 .ring_test = &r600_ring_test,
541 .ring_ib_execute = &r600_ring_ib_execute,
542 .irq_set = &r600_irq_set,
543 .irq_process = &r600_irq_process,
544 .get_vblank_counter = &rs600_get_vblank_counter,
545 .fence_ring_emit = &r600_fence_ring_emit,
546 .cs_parse = &r600_cs_parse,
547 .copy_blit = &r600_copy_blit,
548 .copy_dma = &r600_copy_blit,
549 .copy = &r600_copy_blit,
550 .get_engine_clock = &radeon_atom_get_engine_clock,
551 .set_engine_clock = &radeon_atom_set_engine_clock,
552 .get_memory_clock = &radeon_atom_get_memory_clock,
553 .set_memory_clock = &radeon_atom_set_memory_clock,
554 .get_pcie_lanes = &rv370_get_pcie_lanes,
555 .set_pcie_lanes = NULL,
556 .set_clock_gating = NULL,
557 .set_surface_reg = r600_set_surface_reg,
558 .clear_surface_reg = r600_clear_surface_reg,
559 .bandwidth_update = &rv515_bandwidth_update,
560 .hpd_init = &r600_hpd_init,
561 .hpd_fini = &r600_hpd_fini,
562 .hpd_sense = &r600_hpd_sense,
563 .hpd_set_polarity = &r600_hpd_set_polarity,
564 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 565 .gui_idle = &r600_gui_idle,
48e7a5f1
DV		 566};
567
f47299c5
AD		 568static struct radeon_asic rs780_asic = {
569 .init = &r600_init,
570 .fini = &r600_fini,
571 .suspend = &r600_suspend,
572 .resume = &r600_resume,
573 .cp_commit = &r600_cp_commit,
90aca4d2 574 .gpu_is_lockup = &r600_gpu_is_lockup,
f47299c5 575 .vga_set_state = &r600_vga_set_state,
a2d07b74 576 .asic_reset = &r600_asic_reset,
f47299c5
AD		 577 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
578 .gart_set_page = &rs600_gart_set_page,
579 .ring_test = &r600_ring_test,
580 .ring_ib_execute = &r600_ring_ib_execute,
581 .irq_set = &r600_irq_set,
582 .irq_process = &r600_irq_process,
583 .get_vblank_counter = &rs600_get_vblank_counter,
584 .fence_ring_emit = &r600_fence_ring_emit,
585 .cs_parse = &r600_cs_parse,
586 .copy_blit = &r600_copy_blit,
587 .copy_dma = &r600_copy_blit,
588 .copy = &r600_copy_blit,
589 .get_engine_clock = &radeon_atom_get_engine_clock,
590 .set_engine_clock = &radeon_atom_set_engine_clock,
591 .get_memory_clock = NULL,
592 .set_memory_clock = NULL,
593 .get_pcie_lanes = NULL,
594 .set_pcie_lanes = NULL,
595 .set_clock_gating = NULL,
596 .set_surface_reg = r600_set_surface_reg,
597 .clear_surface_reg = r600_clear_surface_reg,
598 .bandwidth_update = &rs690_bandwidth_update,
599 .hpd_init = &r600_hpd_init,
600 .hpd_fini = &r600_hpd_fini,
601 .hpd_sense = &r600_hpd_sense,
602 .hpd_set_polarity = &r600_hpd_set_polarity,
603 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 604 .gui_idle = &r600_gui_idle,
f47299c5
AD		 605};
606
48e7a5f1
DV		 607static struct radeon_asic rv770_asic = {
608 .init = &rv770_init,
609 .fini = &rv770_fini,
610 .suspend = &rv770_suspend,
611 .resume = &rv770_resume,
612 .cp_commit = &r600_cp_commit,
a2d07b74 613 .asic_reset = &r600_asic_reset,
225758d8 614 .gpu_is_lockup = &r600_gpu_is_lockup,
48e7a5f1
DV		 615 .vga_set_state = &r600_vga_set_state,
616 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
617 .gart_set_page = &rs600_gart_set_page,
618 .ring_test = &r600_ring_test,
619 .ring_ib_execute = &r600_ring_ib_execute,
620 .irq_set = &r600_irq_set,
621 .irq_process = &r600_irq_process,
622 .get_vblank_counter = &rs600_get_vblank_counter,
623 .fence_ring_emit = &r600_fence_ring_emit,
624 .cs_parse = &r600_cs_parse,
625 .copy_blit = &r600_copy_blit,
626 .copy_dma = &r600_copy_blit,
627 .copy = &r600_copy_blit,
628 .get_engine_clock = &radeon_atom_get_engine_clock,
629 .set_engine_clock = &radeon_atom_set_engine_clock,
630 .get_memory_clock = &radeon_atom_get_memory_clock,
631 .set_memory_clock = &radeon_atom_set_memory_clock,
632 .get_pcie_lanes = &rv370_get_pcie_lanes,
633 .set_pcie_lanes = NULL,
634 .set_clock_gating = &radeon_atom_set_clock_gating,
635 .set_surface_reg = r600_set_surface_reg,
636 .clear_surface_reg = r600_clear_surface_reg,
637 .bandwidth_update = &rv515_bandwidth_update,
638 .hpd_init = &r600_hpd_init,
639 .hpd_fini = &r600_hpd_fini,
640 .hpd_sense = &r600_hpd_sense,
641 .hpd_set_polarity = &r600_hpd_set_polarity,
642 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 643 .gui_idle = &r600_gui_idle,
48e7a5f1
DV		 644};
645
646static struct radeon_asic evergreen_asic = {
647 .init = &evergreen_init,
648 .fini = &evergreen_fini,
649 .suspend = &evergreen_suspend,
650 .resume = &evergreen_resume,
fe251e2f 651 .cp_commit = &r600_cp_commit,
225758d8 652 .gpu_is_lockup = &evergreen_gpu_is_lockup,
a2d07b74 653 .asic_reset = &evergreen_asic_reset,
48e7a5f1 654 .vga_set_state = &r600_vga_set_state,
0fcdb61e 655 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
48e7a5f1 656 .gart_set_page = &rs600_gart_set_page,
fe251e2f
AD		 657 .ring_test = &r600_ring_test,
658 .ring_ib_execute = &r600_ring_ib_execute,
45f9a39b
AD		 659 .irq_set = &evergreen_irq_set,
660 .irq_process = &evergreen_irq_process,
661 .get_vblank_counter = &evergreen_get_vblank_counter,
48e7a5f1
DV		 662 .fence_ring_emit = NULL,
663 .cs_parse = NULL,
664 .copy_blit = NULL,
665 .copy_dma = NULL,
666 .copy = NULL,
667 .get_engine_clock = &radeon_atom_get_engine_clock,
668 .set_engine_clock = &radeon_atom_set_engine_clock,
669 .get_memory_clock = &radeon_atom_get_memory_clock,
670 .set_memory_clock = &radeon_atom_set_memory_clock,
671 .set_pcie_lanes = NULL,
672 .set_clock_gating = NULL,
673 .set_surface_reg = r600_set_surface_reg,
674 .clear_surface_reg = r600_clear_surface_reg,
675 .bandwidth_update = &evergreen_bandwidth_update,
676 .hpd_init = &evergreen_hpd_init,
677 .hpd_fini = &evergreen_hpd_fini,
678 .hpd_sense = &evergreen_hpd_sense,
679 .hpd_set_polarity = &evergreen_hpd_set_polarity,
def9ba9c 680 .gui_idle = &r600_gui_idle,
48e7a5f1
DV		 681};
682
0a10c851
DV		 683int radeon_asic_init(struct radeon_device *rdev)
684{
685 radeon_register_accessor_init(rdev);
686 switch (rdev->family) {
687 case CHIP_R100:
688 case CHIP_RV100:
689 case CHIP_RS100:
690 case CHIP_RV200:
691 case CHIP_RS200:
692 rdev->asic = &r100_asic;
693 break;
694 case CHIP_R200:
695 case CHIP_RV250:
696 case CHIP_RS300:
697 case CHIP_RV280:
698 rdev->asic = &r200_asic;
699 break;
700 case CHIP_R300:
701 case CHIP_R350:
702 case CHIP_RV350:
703 case CHIP_RV380:
704 if (rdev->flags & RADEON_IS_PCIE)
705 rdev->asic = &r300_asic_pcie;
706 else
707 rdev->asic = &r300_asic;
708 break;
709 case CHIP_R420:
710 case CHIP_R423:
711 case CHIP_RV410:
712 rdev->asic = &r420_asic;
713 break;
714 case CHIP_RS400:
715 case CHIP_RS480:
716 rdev->asic = &rs400_asic;
717 break;
718 case CHIP_RS600:
719 rdev->asic = &rs600_asic;
720 break;
721 case CHIP_RS690:
722 case CHIP_RS740:
723 rdev->asic = &rs690_asic;
724 break;
725 case CHIP_RV515:
726 rdev->asic = &rv515_asic;
727 break;
728 case CHIP_R520:
729 case CHIP_RV530:
730 case CHIP_RV560:
731 case CHIP_RV570:
732 case CHIP_R580:
733 rdev->asic = &r520_asic;
734 break;
735 case CHIP_R600:
736 case CHIP_RV610:
737 case CHIP_RV630:
738 case CHIP_RV620:
739 case CHIP_RV635:
740 case CHIP_RV670:
f47299c5
AD		 741 rdev->asic = &r600_asic;
742 break;
0a10c851
DV		 743 case CHIP_RS780:
744 case CHIP_RS880:
f47299c5 745 rdev->asic = &rs780_asic;
0a10c851
DV		 746 break;
747 case CHIP_RV770:
748 case CHIP_RV730:
749 case CHIP_RV710:
750 case CHIP_RV740:
751 rdev->asic = &rv770_asic;
752 break;
753 case CHIP_CEDAR:
754 case CHIP_REDWOOD:
755 case CHIP_JUNIPER:
756 case CHIP_CYPRESS:
757 case CHIP_HEMLOCK:
758 rdev->asic = &evergreen_asic;
759 break;
760 default:
761 /* FIXME: not supported yet */
762 return -EINVAL;
763 }
764
765 if (rdev->flags & RADEON_IS_IGP) {
766 rdev->asic->get_memory_clock = NULL;
767 rdev->asic->set_memory_clock = NULL;
768 }
769
9e7b414e
AD		 770 /* set the number of crtcs */
771 if (rdev->flags & RADEON_SINGLE_CRTC)
772 rdev->num_crtc = 1;
773 else {
774 if (ASIC_IS_DCE4(rdev))
775 rdev->num_crtc = 6;
776 else
777 rdev->num_crtc = 2;
778 }
779
0a10c851
DV		 780 return 0;
781}
782
783/*
784 * Wrapper around modesetting bits. Move to radeon_clocks.c?
785 */
786int radeon_clocks_init(struct radeon_device *rdev)
787{
788 int r;
789
790 r = radeon_static_clocks_init(rdev->ddev);
791 if (r) {
792 return r;
793 }
794 DRM_INFO("Clocks initialized !\n");
795 return 0;
796}
797
798void radeon_clocks_fini(struct radeon_device *rdev)
799{
800}
Linux kernel - Deliverables
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