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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
b4df8be1 | 125 | if (rdev->family >= CHIP_R600) { |
0a10c851 DV |
126 | rdev->pciep_rreg = &r600_pciep_rreg; |
127 | rdev->pciep_wreg = &r600_pciep_wreg; | |
128 | } | |
129 | } | |
130 | ||
131 | ||
132 | /* helper to disable agp */ | |
abf1dc67 AD |
133 | /** |
134 | * radeon_agp_disable - AGP disable helper function | |
135 | * | |
136 | * @rdev: radeon device pointer | |
137 | * | |
138 | * Removes AGP flags and changes the gart callbacks on AGP | |
139 | * cards when using the internal gart rather than AGP (all asics). | |
140 | */ | |
0a10c851 DV |
141 | void radeon_agp_disable(struct radeon_device *rdev) |
142 | { | |
143 | rdev->flags &= ~RADEON_IS_AGP; | |
144 | if (rdev->family >= CHIP_R600) { | |
145 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
146 | rdev->flags |= RADEON_IS_PCIE; | |
147 | } else if (rdev->family >= CHIP_RV515 || | |
148 | rdev->family == CHIP_RV380 || | |
149 | rdev->family == CHIP_RV410 || | |
150 | rdev->family == CHIP_R423) { | |
151 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
152 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
153 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
154 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
155 | } else { |
156 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
157 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
158 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
159 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
160 | } |
161 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
162 | } | |
163 | ||
164 | /* | |
165 | * ASIC | |
166 | */ | |
48e7a5f1 DV |
167 | static struct radeon_asic r100_asic = { |
168 | .init = &r100_init, | |
169 | .fini = &r100_fini, | |
170 | .suspend = &r100_suspend, | |
171 | .resume = &r100_resume, | |
172 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 173 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
174 | .ioctl_wait_idle = NULL, |
175 | .gui_idle = &r100_gui_idle, | |
176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
177 | .gart = { |
178 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
179 | .set_page = &r100_pci_gart_set_page, | |
180 | }, | |
4c87bc26 CK |
181 | .ring = { |
182 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
183 | .ib_execute = &r100_ring_ib_execute, | |
184 | .emit_fence = &r100_fence_ring_emit, | |
185 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 186 | .cs_parse = &r100_cs_parse, |
f712812e AD |
187 | .ring_start = &r100_ring_start, |
188 | .ring_test = &r100_ring_test, | |
189 | .ib_test = &r100_ib_test, | |
312c4a8c | 190 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
191 | } |
192 | }, | |
b35ea4ab AD |
193 | .irq = { |
194 | .set = &r100_irq_set, | |
195 | .process = &r100_irq_process, | |
196 | }, | |
c79a49ca AD |
197 | .display = { |
198 | .bandwidth_update = &r100_bandwidth_update, | |
199 | .get_vblank_counter = &r100_get_vblank_counter, | |
200 | .wait_for_vblank = &r100_wait_for_vblank, | |
201 | }, | |
27cd7769 AD |
202 | .copy = { |
203 | .blit = &r100_copy_blit, | |
204 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
205 | .dma = NULL, | |
206 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
207 | .copy = &r100_copy_blit, | |
208 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
209 | }, | |
9e6f3d02 AD |
210 | .surface = { |
211 | .set_reg = r100_set_surface_reg, | |
212 | .clear_reg = r100_clear_surface_reg, | |
213 | }, | |
901ea57d AD |
214 | .hpd = { |
215 | .init = &r100_hpd_init, | |
216 | .fini = &r100_hpd_fini, | |
217 | .sense = &r100_hpd_sense, | |
218 | .set_polarity = &r100_hpd_set_polarity, | |
219 | }, | |
a02fa397 AD |
220 | .pm = { |
221 | .misc = &r100_pm_misc, | |
222 | .prepare = &r100_pm_prepare, | |
223 | .finish = &r100_pm_finish, | |
224 | .init_profile = &r100_pm_init_profile, | |
225 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
226 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
227 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
228 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
229 | .set_memory_clock = NULL, | |
230 | .get_pcie_lanes = NULL, | |
231 | .set_pcie_lanes = NULL, | |
232 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 233 | }, |
0f9e006c AD |
234 | .pflip = { |
235 | .pre_page_flip = &r100_pre_page_flip, | |
236 | .page_flip = &r100_page_flip, | |
237 | .post_page_flip = &r100_post_page_flip, | |
238 | }, | |
48e7a5f1 DV |
239 | }; |
240 | ||
241 | static struct radeon_asic r200_asic = { | |
242 | .init = &r100_init, | |
243 | .fini = &r100_fini, | |
244 | .suspend = &r100_suspend, | |
245 | .resume = &r100_resume, | |
246 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 247 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
248 | .ioctl_wait_idle = NULL, |
249 | .gui_idle = &r100_gui_idle, | |
250 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
251 | .gart = { |
252 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
253 | .set_page = &r100_pci_gart_set_page, | |
254 | }, | |
4c87bc26 CK |
255 | .ring = { |
256 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
257 | .ib_execute = &r100_ring_ib_execute, | |
258 | .emit_fence = &r100_fence_ring_emit, | |
259 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 260 | .cs_parse = &r100_cs_parse, |
f712812e AD |
261 | .ring_start = &r100_ring_start, |
262 | .ring_test = &r100_ring_test, | |
263 | .ib_test = &r100_ib_test, | |
312c4a8c | 264 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
265 | } |
266 | }, | |
b35ea4ab AD |
267 | .irq = { |
268 | .set = &r100_irq_set, | |
269 | .process = &r100_irq_process, | |
270 | }, | |
c79a49ca AD |
271 | .display = { |
272 | .bandwidth_update = &r100_bandwidth_update, | |
273 | .get_vblank_counter = &r100_get_vblank_counter, | |
274 | .wait_for_vblank = &r100_wait_for_vblank, | |
275 | }, | |
27cd7769 AD |
276 | .copy = { |
277 | .blit = &r100_copy_blit, | |
278 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
279 | .dma = &r200_copy_dma, | |
280 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
281 | .copy = &r100_copy_blit, | |
282 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
283 | }, | |
9e6f3d02 AD |
284 | .surface = { |
285 | .set_reg = r100_set_surface_reg, | |
286 | .clear_reg = r100_clear_surface_reg, | |
287 | }, | |
901ea57d AD |
288 | .hpd = { |
289 | .init = &r100_hpd_init, | |
290 | .fini = &r100_hpd_fini, | |
291 | .sense = &r100_hpd_sense, | |
292 | .set_polarity = &r100_hpd_set_polarity, | |
293 | }, | |
a02fa397 AD |
294 | .pm = { |
295 | .misc = &r100_pm_misc, | |
296 | .prepare = &r100_pm_prepare, | |
297 | .finish = &r100_pm_finish, | |
298 | .init_profile = &r100_pm_init_profile, | |
299 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
300 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
301 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
302 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
303 | .set_memory_clock = NULL, | |
304 | .get_pcie_lanes = NULL, | |
305 | .set_pcie_lanes = NULL, | |
306 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 307 | }, |
0f9e006c AD |
308 | .pflip = { |
309 | .pre_page_flip = &r100_pre_page_flip, | |
310 | .page_flip = &r100_page_flip, | |
311 | .post_page_flip = &r100_post_page_flip, | |
312 | }, | |
48e7a5f1 DV |
313 | }; |
314 | ||
315 | static struct radeon_asic r300_asic = { | |
316 | .init = &r300_init, | |
317 | .fini = &r300_fini, | |
318 | .suspend = &r300_suspend, | |
319 | .resume = &r300_resume, | |
320 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 321 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
322 | .ioctl_wait_idle = NULL, |
323 | .gui_idle = &r100_gui_idle, | |
324 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
325 | .gart = { |
326 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
327 | .set_page = &r100_pci_gart_set_page, | |
328 | }, | |
4c87bc26 CK |
329 | .ring = { |
330 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
331 | .ib_execute = &r100_ring_ib_execute, | |
332 | .emit_fence = &r300_fence_ring_emit, | |
333 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 334 | .cs_parse = &r300_cs_parse, |
f712812e AD |
335 | .ring_start = &r300_ring_start, |
336 | .ring_test = &r100_ring_test, | |
337 | .ib_test = &r100_ib_test, | |
8ba957b5 | 338 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
339 | } |
340 | }, | |
b35ea4ab AD |
341 | .irq = { |
342 | .set = &r100_irq_set, | |
343 | .process = &r100_irq_process, | |
344 | }, | |
c79a49ca AD |
345 | .display = { |
346 | .bandwidth_update = &r100_bandwidth_update, | |
347 | .get_vblank_counter = &r100_get_vblank_counter, | |
348 | .wait_for_vblank = &r100_wait_for_vblank, | |
349 | }, | |
27cd7769 AD |
350 | .copy = { |
351 | .blit = &r100_copy_blit, | |
352 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
353 | .dma = &r200_copy_dma, | |
354 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
355 | .copy = &r100_copy_blit, | |
356 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
357 | }, | |
9e6f3d02 AD |
358 | .surface = { |
359 | .set_reg = r100_set_surface_reg, | |
360 | .clear_reg = r100_clear_surface_reg, | |
361 | }, | |
901ea57d AD |
362 | .hpd = { |
363 | .init = &r100_hpd_init, | |
364 | .fini = &r100_hpd_fini, | |
365 | .sense = &r100_hpd_sense, | |
366 | .set_polarity = &r100_hpd_set_polarity, | |
367 | }, | |
a02fa397 AD |
368 | .pm = { |
369 | .misc = &r100_pm_misc, | |
370 | .prepare = &r100_pm_prepare, | |
371 | .finish = &r100_pm_finish, | |
372 | .init_profile = &r100_pm_init_profile, | |
373 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
374 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
375 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
376 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
377 | .set_memory_clock = NULL, | |
378 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
379 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
380 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 381 | }, |
0f9e006c AD |
382 | .pflip = { |
383 | .pre_page_flip = &r100_pre_page_flip, | |
384 | .page_flip = &r100_page_flip, | |
385 | .post_page_flip = &r100_post_page_flip, | |
386 | }, | |
48e7a5f1 DV |
387 | }; |
388 | ||
389 | static struct radeon_asic r300_asic_pcie = { | |
390 | .init = &r300_init, | |
391 | .fini = &r300_fini, | |
392 | .suspend = &r300_suspend, | |
393 | .resume = &r300_resume, | |
394 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 395 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
396 | .ioctl_wait_idle = NULL, |
397 | .gui_idle = &r100_gui_idle, | |
398 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
399 | .gart = { |
400 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
401 | .set_page = &rv370_pcie_gart_set_page, | |
402 | }, | |
4c87bc26 CK |
403 | .ring = { |
404 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
405 | .ib_execute = &r100_ring_ib_execute, | |
406 | .emit_fence = &r300_fence_ring_emit, | |
407 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 408 | .cs_parse = &r300_cs_parse, |
f712812e AD |
409 | .ring_start = &r300_ring_start, |
410 | .ring_test = &r100_ring_test, | |
411 | .ib_test = &r100_ib_test, | |
8ba957b5 | 412 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
413 | } |
414 | }, | |
b35ea4ab AD |
415 | .irq = { |
416 | .set = &r100_irq_set, | |
417 | .process = &r100_irq_process, | |
418 | }, | |
c79a49ca AD |
419 | .display = { |
420 | .bandwidth_update = &r100_bandwidth_update, | |
421 | .get_vblank_counter = &r100_get_vblank_counter, | |
422 | .wait_for_vblank = &r100_wait_for_vblank, | |
423 | }, | |
27cd7769 AD |
424 | .copy = { |
425 | .blit = &r100_copy_blit, | |
426 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
427 | .dma = &r200_copy_dma, | |
428 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
429 | .copy = &r100_copy_blit, | |
430 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
431 | }, | |
9e6f3d02 AD |
432 | .surface = { |
433 | .set_reg = r100_set_surface_reg, | |
434 | .clear_reg = r100_clear_surface_reg, | |
435 | }, | |
901ea57d AD |
436 | .hpd = { |
437 | .init = &r100_hpd_init, | |
438 | .fini = &r100_hpd_fini, | |
439 | .sense = &r100_hpd_sense, | |
440 | .set_polarity = &r100_hpd_set_polarity, | |
441 | }, | |
a02fa397 AD |
442 | .pm = { |
443 | .misc = &r100_pm_misc, | |
444 | .prepare = &r100_pm_prepare, | |
445 | .finish = &r100_pm_finish, | |
446 | .init_profile = &r100_pm_init_profile, | |
447 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
448 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
449 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
450 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
451 | .set_memory_clock = NULL, | |
452 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
453 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
454 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 455 | }, |
0f9e006c AD |
456 | .pflip = { |
457 | .pre_page_flip = &r100_pre_page_flip, | |
458 | .page_flip = &r100_page_flip, | |
459 | .post_page_flip = &r100_post_page_flip, | |
460 | }, | |
48e7a5f1 DV |
461 | }; |
462 | ||
463 | static struct radeon_asic r420_asic = { | |
464 | .init = &r420_init, | |
465 | .fini = &r420_fini, | |
466 | .suspend = &r420_suspend, | |
467 | .resume = &r420_resume, | |
468 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 469 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
470 | .ioctl_wait_idle = NULL, |
471 | .gui_idle = &r100_gui_idle, | |
472 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
473 | .gart = { |
474 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
475 | .set_page = &rv370_pcie_gart_set_page, | |
476 | }, | |
4c87bc26 CK |
477 | .ring = { |
478 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
479 | .ib_execute = &r100_ring_ib_execute, | |
480 | .emit_fence = &r300_fence_ring_emit, | |
481 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 482 | .cs_parse = &r300_cs_parse, |
f712812e AD |
483 | .ring_start = &r300_ring_start, |
484 | .ring_test = &r100_ring_test, | |
485 | .ib_test = &r100_ib_test, | |
8ba957b5 | 486 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
487 | } |
488 | }, | |
b35ea4ab AD |
489 | .irq = { |
490 | .set = &r100_irq_set, | |
491 | .process = &r100_irq_process, | |
492 | }, | |
c79a49ca AD |
493 | .display = { |
494 | .bandwidth_update = &r100_bandwidth_update, | |
495 | .get_vblank_counter = &r100_get_vblank_counter, | |
496 | .wait_for_vblank = &r100_wait_for_vblank, | |
497 | }, | |
27cd7769 AD |
498 | .copy = { |
499 | .blit = &r100_copy_blit, | |
500 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
501 | .dma = &r200_copy_dma, | |
502 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
503 | .copy = &r100_copy_blit, | |
504 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
505 | }, | |
9e6f3d02 AD |
506 | .surface = { |
507 | .set_reg = r100_set_surface_reg, | |
508 | .clear_reg = r100_clear_surface_reg, | |
509 | }, | |
901ea57d AD |
510 | .hpd = { |
511 | .init = &r100_hpd_init, | |
512 | .fini = &r100_hpd_fini, | |
513 | .sense = &r100_hpd_sense, | |
514 | .set_polarity = &r100_hpd_set_polarity, | |
515 | }, | |
a02fa397 AD |
516 | .pm = { |
517 | .misc = &r100_pm_misc, | |
518 | .prepare = &r100_pm_prepare, | |
519 | .finish = &r100_pm_finish, | |
520 | .init_profile = &r420_pm_init_profile, | |
521 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
522 | .get_engine_clock = &radeon_atom_get_engine_clock, |
523 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
524 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
525 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
526 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
527 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
528 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 529 | }, |
0f9e006c AD |
530 | .pflip = { |
531 | .pre_page_flip = &r100_pre_page_flip, | |
532 | .page_flip = &r100_page_flip, | |
533 | .post_page_flip = &r100_post_page_flip, | |
534 | }, | |
48e7a5f1 DV |
535 | }; |
536 | ||
537 | static struct radeon_asic rs400_asic = { | |
538 | .init = &rs400_init, | |
539 | .fini = &rs400_fini, | |
540 | .suspend = &rs400_suspend, | |
541 | .resume = &rs400_resume, | |
542 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 543 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
544 | .ioctl_wait_idle = NULL, |
545 | .gui_idle = &r100_gui_idle, | |
546 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
547 | .gart = { |
548 | .tlb_flush = &rs400_gart_tlb_flush, | |
549 | .set_page = &rs400_gart_set_page, | |
550 | }, | |
4c87bc26 CK |
551 | .ring = { |
552 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
553 | .ib_execute = &r100_ring_ib_execute, | |
554 | .emit_fence = &r300_fence_ring_emit, | |
555 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 556 | .cs_parse = &r300_cs_parse, |
f712812e AD |
557 | .ring_start = &r300_ring_start, |
558 | .ring_test = &r100_ring_test, | |
559 | .ib_test = &r100_ib_test, | |
8ba957b5 | 560 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
561 | } |
562 | }, | |
b35ea4ab AD |
563 | .irq = { |
564 | .set = &r100_irq_set, | |
565 | .process = &r100_irq_process, | |
566 | }, | |
c79a49ca AD |
567 | .display = { |
568 | .bandwidth_update = &r100_bandwidth_update, | |
569 | .get_vblank_counter = &r100_get_vblank_counter, | |
570 | .wait_for_vblank = &r100_wait_for_vblank, | |
571 | }, | |
27cd7769 AD |
572 | .copy = { |
573 | .blit = &r100_copy_blit, | |
574 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
575 | .dma = &r200_copy_dma, | |
576 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
577 | .copy = &r100_copy_blit, | |
578 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
579 | }, | |
9e6f3d02 AD |
580 | .surface = { |
581 | .set_reg = r100_set_surface_reg, | |
582 | .clear_reg = r100_clear_surface_reg, | |
583 | }, | |
901ea57d AD |
584 | .hpd = { |
585 | .init = &r100_hpd_init, | |
586 | .fini = &r100_hpd_fini, | |
587 | .sense = &r100_hpd_sense, | |
588 | .set_polarity = &r100_hpd_set_polarity, | |
589 | }, | |
a02fa397 AD |
590 | .pm = { |
591 | .misc = &r100_pm_misc, | |
592 | .prepare = &r100_pm_prepare, | |
593 | .finish = &r100_pm_finish, | |
594 | .init_profile = &r100_pm_init_profile, | |
595 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
596 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
597 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
598 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
599 | .set_memory_clock = NULL, | |
600 | .get_pcie_lanes = NULL, | |
601 | .set_pcie_lanes = NULL, | |
602 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 603 | }, |
0f9e006c AD |
604 | .pflip = { |
605 | .pre_page_flip = &r100_pre_page_flip, | |
606 | .page_flip = &r100_page_flip, | |
607 | .post_page_flip = &r100_post_page_flip, | |
608 | }, | |
48e7a5f1 DV |
609 | }; |
610 | ||
611 | static struct radeon_asic rs600_asic = { | |
612 | .init = &rs600_init, | |
613 | .fini = &rs600_fini, | |
614 | .suspend = &rs600_suspend, | |
615 | .resume = &rs600_resume, | |
616 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 617 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
618 | .ioctl_wait_idle = NULL, |
619 | .gui_idle = &r100_gui_idle, | |
620 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
621 | .gart = { |
622 | .tlb_flush = &rs600_gart_tlb_flush, | |
623 | .set_page = &rs600_gart_set_page, | |
624 | }, | |
4c87bc26 CK |
625 | .ring = { |
626 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
627 | .ib_execute = &r100_ring_ib_execute, | |
628 | .emit_fence = &r300_fence_ring_emit, | |
629 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 630 | .cs_parse = &r300_cs_parse, |
f712812e AD |
631 | .ring_start = &r300_ring_start, |
632 | .ring_test = &r100_ring_test, | |
633 | .ib_test = &r100_ib_test, | |
8ba957b5 | 634 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
635 | } |
636 | }, | |
b35ea4ab AD |
637 | .irq = { |
638 | .set = &rs600_irq_set, | |
639 | .process = &rs600_irq_process, | |
640 | }, | |
c79a49ca AD |
641 | .display = { |
642 | .bandwidth_update = &rs600_bandwidth_update, | |
643 | .get_vblank_counter = &rs600_get_vblank_counter, | |
644 | .wait_for_vblank = &avivo_wait_for_vblank, | |
645 | }, | |
27cd7769 AD |
646 | .copy = { |
647 | .blit = &r100_copy_blit, | |
648 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
649 | .dma = &r200_copy_dma, | |
650 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
651 | .copy = &r100_copy_blit, | |
652 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
653 | }, | |
9e6f3d02 AD |
654 | .surface = { |
655 | .set_reg = r100_set_surface_reg, | |
656 | .clear_reg = r100_clear_surface_reg, | |
657 | }, | |
901ea57d AD |
658 | .hpd = { |
659 | .init = &rs600_hpd_init, | |
660 | .fini = &rs600_hpd_fini, | |
661 | .sense = &rs600_hpd_sense, | |
662 | .set_polarity = &rs600_hpd_set_polarity, | |
663 | }, | |
a02fa397 AD |
664 | .pm = { |
665 | .misc = &rs600_pm_misc, | |
666 | .prepare = &rs600_pm_prepare, | |
667 | .finish = &rs600_pm_finish, | |
668 | .init_profile = &r420_pm_init_profile, | |
669 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
670 | .get_engine_clock = &radeon_atom_get_engine_clock, |
671 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
672 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
673 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
674 | .get_pcie_lanes = NULL, | |
675 | .set_pcie_lanes = NULL, | |
676 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 677 | }, |
0f9e006c AD |
678 | .pflip = { |
679 | .pre_page_flip = &rs600_pre_page_flip, | |
680 | .page_flip = &rs600_page_flip, | |
681 | .post_page_flip = &rs600_post_page_flip, | |
682 | }, | |
48e7a5f1 DV |
683 | }; |
684 | ||
685 | static struct radeon_asic rs690_asic = { | |
686 | .init = &rs690_init, | |
687 | .fini = &rs690_fini, | |
688 | .suspend = &rs690_suspend, | |
689 | .resume = &rs690_resume, | |
690 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 691 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
692 | .ioctl_wait_idle = NULL, |
693 | .gui_idle = &r100_gui_idle, | |
694 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
695 | .gart = { |
696 | .tlb_flush = &rs400_gart_tlb_flush, | |
697 | .set_page = &rs400_gart_set_page, | |
698 | }, | |
4c87bc26 CK |
699 | .ring = { |
700 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
701 | .ib_execute = &r100_ring_ib_execute, | |
702 | .emit_fence = &r300_fence_ring_emit, | |
703 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 704 | .cs_parse = &r300_cs_parse, |
f712812e AD |
705 | .ring_start = &r300_ring_start, |
706 | .ring_test = &r100_ring_test, | |
707 | .ib_test = &r100_ib_test, | |
8ba957b5 | 708 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
709 | } |
710 | }, | |
b35ea4ab AD |
711 | .irq = { |
712 | .set = &rs600_irq_set, | |
713 | .process = &rs600_irq_process, | |
714 | }, | |
c79a49ca AD |
715 | .display = { |
716 | .get_vblank_counter = &rs600_get_vblank_counter, | |
717 | .bandwidth_update = &rs690_bandwidth_update, | |
718 | .wait_for_vblank = &avivo_wait_for_vblank, | |
719 | }, | |
27cd7769 AD |
720 | .copy = { |
721 | .blit = &r100_copy_blit, | |
722 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
723 | .dma = &r200_copy_dma, | |
724 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
725 | .copy = &r200_copy_dma, | |
726 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
727 | }, | |
9e6f3d02 AD |
728 | .surface = { |
729 | .set_reg = r100_set_surface_reg, | |
730 | .clear_reg = r100_clear_surface_reg, | |
731 | }, | |
901ea57d AD |
732 | .hpd = { |
733 | .init = &rs600_hpd_init, | |
734 | .fini = &rs600_hpd_fini, | |
735 | .sense = &rs600_hpd_sense, | |
736 | .set_polarity = &rs600_hpd_set_polarity, | |
737 | }, | |
a02fa397 AD |
738 | .pm = { |
739 | .misc = &rs600_pm_misc, | |
740 | .prepare = &rs600_pm_prepare, | |
741 | .finish = &rs600_pm_finish, | |
742 | .init_profile = &r420_pm_init_profile, | |
743 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
744 | .get_engine_clock = &radeon_atom_get_engine_clock, |
745 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
746 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
747 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
748 | .get_pcie_lanes = NULL, | |
749 | .set_pcie_lanes = NULL, | |
750 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 751 | }, |
0f9e006c AD |
752 | .pflip = { |
753 | .pre_page_flip = &rs600_pre_page_flip, | |
754 | .page_flip = &rs600_page_flip, | |
755 | .post_page_flip = &rs600_post_page_flip, | |
756 | }, | |
48e7a5f1 DV |
757 | }; |
758 | ||
759 | static struct radeon_asic rv515_asic = { | |
760 | .init = &rv515_init, | |
761 | .fini = &rv515_fini, | |
762 | .suspend = &rv515_suspend, | |
763 | .resume = &rv515_resume, | |
764 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 765 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
766 | .ioctl_wait_idle = NULL, |
767 | .gui_idle = &r100_gui_idle, | |
768 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
769 | .gart = { |
770 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
771 | .set_page = &rv370_pcie_gart_set_page, | |
772 | }, | |
4c87bc26 CK |
773 | .ring = { |
774 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
775 | .ib_execute = &r100_ring_ib_execute, | |
776 | .emit_fence = &r300_fence_ring_emit, | |
777 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 778 | .cs_parse = &r300_cs_parse, |
f712812e AD |
779 | .ring_start = &rv515_ring_start, |
780 | .ring_test = &r100_ring_test, | |
781 | .ib_test = &r100_ib_test, | |
8ba957b5 | 782 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
783 | } |
784 | }, | |
b35ea4ab AD |
785 | .irq = { |
786 | .set = &rs600_irq_set, | |
787 | .process = &rs600_irq_process, | |
788 | }, | |
c79a49ca AD |
789 | .display = { |
790 | .get_vblank_counter = &rs600_get_vblank_counter, | |
791 | .bandwidth_update = &rv515_bandwidth_update, | |
792 | .wait_for_vblank = &avivo_wait_for_vblank, | |
793 | }, | |
27cd7769 AD |
794 | .copy = { |
795 | .blit = &r100_copy_blit, | |
796 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
797 | .dma = &r200_copy_dma, | |
798 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
799 | .copy = &r100_copy_blit, | |
800 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
801 | }, | |
9e6f3d02 AD |
802 | .surface = { |
803 | .set_reg = r100_set_surface_reg, | |
804 | .clear_reg = r100_clear_surface_reg, | |
805 | }, | |
901ea57d AD |
806 | .hpd = { |
807 | .init = &rs600_hpd_init, | |
808 | .fini = &rs600_hpd_fini, | |
809 | .sense = &rs600_hpd_sense, | |
810 | .set_polarity = &rs600_hpd_set_polarity, | |
811 | }, | |
a02fa397 AD |
812 | .pm = { |
813 | .misc = &rs600_pm_misc, | |
814 | .prepare = &rs600_pm_prepare, | |
815 | .finish = &rs600_pm_finish, | |
816 | .init_profile = &r420_pm_init_profile, | |
817 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
818 | .get_engine_clock = &radeon_atom_get_engine_clock, |
819 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
820 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
821 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
822 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
823 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
824 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 825 | }, |
0f9e006c AD |
826 | .pflip = { |
827 | .pre_page_flip = &rs600_pre_page_flip, | |
828 | .page_flip = &rs600_page_flip, | |
829 | .post_page_flip = &rs600_post_page_flip, | |
830 | }, | |
48e7a5f1 DV |
831 | }; |
832 | ||
833 | static struct radeon_asic r520_asic = { | |
834 | .init = &r520_init, | |
835 | .fini = &rv515_fini, | |
836 | .suspend = &rv515_suspend, | |
837 | .resume = &r520_resume, | |
838 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 839 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
840 | .ioctl_wait_idle = NULL, |
841 | .gui_idle = &r100_gui_idle, | |
842 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
843 | .gart = { |
844 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
845 | .set_page = &rv370_pcie_gart_set_page, | |
846 | }, | |
4c87bc26 CK |
847 | .ring = { |
848 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
849 | .ib_execute = &r100_ring_ib_execute, | |
850 | .emit_fence = &r300_fence_ring_emit, | |
851 | .emit_semaphore = &r100_semaphore_ring_emit, | |
eb0c19c5 | 852 | .cs_parse = &r300_cs_parse, |
f712812e AD |
853 | .ring_start = &rv515_ring_start, |
854 | .ring_test = &r100_ring_test, | |
855 | .ib_test = &r100_ib_test, | |
8ba957b5 | 856 | .is_lockup = &r100_gpu_is_lockup, |
4c87bc26 CK |
857 | } |
858 | }, | |
b35ea4ab AD |
859 | .irq = { |
860 | .set = &rs600_irq_set, | |
861 | .process = &rs600_irq_process, | |
862 | }, | |
c79a49ca AD |
863 | .display = { |
864 | .bandwidth_update = &rv515_bandwidth_update, | |
865 | .get_vblank_counter = &rs600_get_vblank_counter, | |
866 | .wait_for_vblank = &avivo_wait_for_vblank, | |
867 | }, | |
27cd7769 AD |
868 | .copy = { |
869 | .blit = &r100_copy_blit, | |
870 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
871 | .dma = &r200_copy_dma, | |
872 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
873 | .copy = &r100_copy_blit, | |
874 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
875 | }, | |
9e6f3d02 AD |
876 | .surface = { |
877 | .set_reg = r100_set_surface_reg, | |
878 | .clear_reg = r100_clear_surface_reg, | |
879 | }, | |
901ea57d AD |
880 | .hpd = { |
881 | .init = &rs600_hpd_init, | |
882 | .fini = &rs600_hpd_fini, | |
883 | .sense = &rs600_hpd_sense, | |
884 | .set_polarity = &rs600_hpd_set_polarity, | |
885 | }, | |
a02fa397 AD |
886 | .pm = { |
887 | .misc = &rs600_pm_misc, | |
888 | .prepare = &rs600_pm_prepare, | |
889 | .finish = &rs600_pm_finish, | |
890 | .init_profile = &r420_pm_init_profile, | |
891 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
892 | .get_engine_clock = &radeon_atom_get_engine_clock, |
893 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
894 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
895 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
896 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
897 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
898 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 899 | }, |
0f9e006c AD |
900 | .pflip = { |
901 | .pre_page_flip = &rs600_pre_page_flip, | |
902 | .page_flip = &rs600_page_flip, | |
903 | .post_page_flip = &rs600_post_page_flip, | |
904 | }, | |
48e7a5f1 DV |
905 | }; |
906 | ||
907 | static struct radeon_asic r600_asic = { | |
908 | .init = &r600_init, | |
909 | .fini = &r600_fini, | |
910 | .suspend = &r600_suspend, | |
911 | .resume = &r600_resume, | |
48e7a5f1 | 912 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 913 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
914 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
915 | .gui_idle = &r600_gui_idle, | |
916 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
917 | .gart = { |
918 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
919 | .set_page = &rs600_gart_set_page, | |
920 | }, | |
4c87bc26 CK |
921 | .ring = { |
922 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
923 | .ib_execute = &r600_ring_ib_execute, | |
924 | .emit_fence = &r600_fence_ring_emit, | |
925 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 926 | .cs_parse = &r600_cs_parse, |
f712812e AD |
927 | .ring_test = &r600_ring_test, |
928 | .ib_test = &r600_ib_test, | |
312c4a8c | 929 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
930 | } |
931 | }, | |
b35ea4ab AD |
932 | .irq = { |
933 | .set = &r600_irq_set, | |
934 | .process = &r600_irq_process, | |
935 | }, | |
c79a49ca AD |
936 | .display = { |
937 | .bandwidth_update = &rv515_bandwidth_update, | |
938 | .get_vblank_counter = &rs600_get_vblank_counter, | |
939 | .wait_for_vblank = &avivo_wait_for_vblank, | |
940 | }, | |
27cd7769 AD |
941 | .copy = { |
942 | .blit = &r600_copy_blit, | |
943 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
944 | .dma = NULL, | |
945 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
946 | .copy = &r600_copy_blit, | |
947 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
948 | }, | |
9e6f3d02 AD |
949 | .surface = { |
950 | .set_reg = r600_set_surface_reg, | |
951 | .clear_reg = r600_clear_surface_reg, | |
952 | }, | |
901ea57d AD |
953 | .hpd = { |
954 | .init = &r600_hpd_init, | |
955 | .fini = &r600_hpd_fini, | |
956 | .sense = &r600_hpd_sense, | |
957 | .set_polarity = &r600_hpd_set_polarity, | |
958 | }, | |
a02fa397 AD |
959 | .pm = { |
960 | .misc = &r600_pm_misc, | |
961 | .prepare = &rs600_pm_prepare, | |
962 | .finish = &rs600_pm_finish, | |
963 | .init_profile = &r600_pm_init_profile, | |
964 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
965 | .get_engine_clock = &radeon_atom_get_engine_clock, |
966 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
967 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
968 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
969 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
970 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
971 | .set_clock_gating = NULL, | |
a02fa397 | 972 | }, |
0f9e006c AD |
973 | .pflip = { |
974 | .pre_page_flip = &rs600_pre_page_flip, | |
975 | .page_flip = &rs600_page_flip, | |
976 | .post_page_flip = &rs600_post_page_flip, | |
977 | }, | |
48e7a5f1 DV |
978 | }; |
979 | ||
f47299c5 AD |
980 | static struct radeon_asic rs780_asic = { |
981 | .init = &r600_init, | |
982 | .fini = &r600_fini, | |
983 | .suspend = &r600_suspend, | |
984 | .resume = &r600_resume, | |
f47299c5 | 985 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 986 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
987 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
988 | .gui_idle = &r600_gui_idle, | |
989 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
990 | .gart = { |
991 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
992 | .set_page = &rs600_gart_set_page, | |
993 | }, | |
4c87bc26 CK |
994 | .ring = { |
995 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
996 | .ib_execute = &r600_ring_ib_execute, | |
997 | .emit_fence = &r600_fence_ring_emit, | |
998 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 999 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1000 | .ring_test = &r600_ring_test, |
1001 | .ib_test = &r600_ib_test, | |
312c4a8c | 1002 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
1003 | } |
1004 | }, | |
b35ea4ab AD |
1005 | .irq = { |
1006 | .set = &r600_irq_set, | |
1007 | .process = &r600_irq_process, | |
1008 | }, | |
c79a49ca AD |
1009 | .display = { |
1010 | .bandwidth_update = &rs690_bandwidth_update, | |
1011 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1012 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1013 | }, | |
27cd7769 AD |
1014 | .copy = { |
1015 | .blit = &r600_copy_blit, | |
1016 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1017 | .dma = NULL, | |
1018 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1019 | .copy = &r600_copy_blit, | |
1020 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1021 | }, | |
9e6f3d02 AD |
1022 | .surface = { |
1023 | .set_reg = r600_set_surface_reg, | |
1024 | .clear_reg = r600_clear_surface_reg, | |
1025 | }, | |
901ea57d AD |
1026 | .hpd = { |
1027 | .init = &r600_hpd_init, | |
1028 | .fini = &r600_hpd_fini, | |
1029 | .sense = &r600_hpd_sense, | |
1030 | .set_polarity = &r600_hpd_set_polarity, | |
1031 | }, | |
a02fa397 AD |
1032 | .pm = { |
1033 | .misc = &r600_pm_misc, | |
1034 | .prepare = &rs600_pm_prepare, | |
1035 | .finish = &rs600_pm_finish, | |
1036 | .init_profile = &rs780_pm_init_profile, | |
1037 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1038 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1039 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1040 | .get_memory_clock = NULL, | |
1041 | .set_memory_clock = NULL, | |
1042 | .get_pcie_lanes = NULL, | |
1043 | .set_pcie_lanes = NULL, | |
1044 | .set_clock_gating = NULL, | |
a02fa397 | 1045 | }, |
0f9e006c AD |
1046 | .pflip = { |
1047 | .pre_page_flip = &rs600_pre_page_flip, | |
1048 | .page_flip = &rs600_page_flip, | |
1049 | .post_page_flip = &rs600_post_page_flip, | |
1050 | }, | |
f47299c5 AD |
1051 | }; |
1052 | ||
48e7a5f1 DV |
1053 | static struct radeon_asic rv770_asic = { |
1054 | .init = &rv770_init, | |
1055 | .fini = &rv770_fini, | |
1056 | .suspend = &rv770_suspend, | |
1057 | .resume = &rv770_resume, | |
a2d07b74 | 1058 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1059 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1060 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1061 | .gui_idle = &r600_gui_idle, | |
1062 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
c5b3b850 AD |
1063 | .gart = { |
1064 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1065 | .set_page = &rs600_gart_set_page, | |
1066 | }, | |
4c87bc26 CK |
1067 | .ring = { |
1068 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1069 | .ib_execute = &r600_ring_ib_execute, | |
1070 | .emit_fence = &r600_fence_ring_emit, | |
1071 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1072 | .cs_parse = &r600_cs_parse, |
f712812e AD |
1073 | .ring_test = &r600_ring_test, |
1074 | .ib_test = &r600_ib_test, | |
312c4a8c | 1075 | .is_lockup = &r600_gpu_is_lockup, |
4c87bc26 CK |
1076 | } |
1077 | }, | |
b35ea4ab AD |
1078 | .irq = { |
1079 | .set = &r600_irq_set, | |
1080 | .process = &r600_irq_process, | |
1081 | }, | |
c79a49ca AD |
1082 | .display = { |
1083 | .bandwidth_update = &rv515_bandwidth_update, | |
1084 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1085 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1086 | }, | |
27cd7769 AD |
1087 | .copy = { |
1088 | .blit = &r600_copy_blit, | |
1089 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1090 | .dma = NULL, | |
1091 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1092 | .copy = &r600_copy_blit, | |
1093 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1094 | }, | |
9e6f3d02 AD |
1095 | .surface = { |
1096 | .set_reg = r600_set_surface_reg, | |
1097 | .clear_reg = r600_clear_surface_reg, | |
1098 | }, | |
901ea57d AD |
1099 | .hpd = { |
1100 | .init = &r600_hpd_init, | |
1101 | .fini = &r600_hpd_fini, | |
1102 | .sense = &r600_hpd_sense, | |
1103 | .set_polarity = &r600_hpd_set_polarity, | |
1104 | }, | |
a02fa397 AD |
1105 | .pm = { |
1106 | .misc = &rv770_pm_misc, | |
1107 | .prepare = &rs600_pm_prepare, | |
1108 | .finish = &rs600_pm_finish, | |
1109 | .init_profile = &r600_pm_init_profile, | |
1110 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1111 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1112 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1113 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1114 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1115 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1116 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1117 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 1118 | }, |
0f9e006c AD |
1119 | .pflip = { |
1120 | .pre_page_flip = &rs600_pre_page_flip, | |
1121 | .page_flip = &rv770_page_flip, | |
1122 | .post_page_flip = &rs600_post_page_flip, | |
1123 | }, | |
48e7a5f1 DV |
1124 | }; |
1125 | ||
1126 | static struct radeon_asic evergreen_asic = { | |
1127 | .init = &evergreen_init, | |
1128 | .fini = &evergreen_fini, | |
1129 | .suspend = &evergreen_suspend, | |
1130 | .resume = &evergreen_resume, | |
a2d07b74 | 1131 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1132 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1133 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1134 | .gui_idle = &r600_gui_idle, | |
1135 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1136 | .gart = { |
1137 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1138 | .set_page = &rs600_gart_set_page, | |
1139 | }, | |
4c87bc26 CK |
1140 | .ring = { |
1141 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1142 | .ib_execute = &evergreen_ring_ib_execute, | |
1143 | .emit_fence = &r600_fence_ring_emit, | |
1144 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1145 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1146 | .ring_test = &r600_ring_test, |
1147 | .ib_test = &r600_ib_test, | |
312c4a8c | 1148 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1149 | } |
1150 | }, | |
b35ea4ab AD |
1151 | .irq = { |
1152 | .set = &evergreen_irq_set, | |
1153 | .process = &evergreen_irq_process, | |
1154 | }, | |
c79a49ca AD |
1155 | .display = { |
1156 | .bandwidth_update = &evergreen_bandwidth_update, | |
1157 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1158 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1159 | }, | |
27cd7769 AD |
1160 | .copy = { |
1161 | .blit = &r600_copy_blit, | |
1162 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1163 | .dma = NULL, | |
1164 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1165 | .copy = &r600_copy_blit, | |
1166 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1167 | }, | |
9e6f3d02 AD |
1168 | .surface = { |
1169 | .set_reg = r600_set_surface_reg, | |
1170 | .clear_reg = r600_clear_surface_reg, | |
1171 | }, | |
901ea57d AD |
1172 | .hpd = { |
1173 | .init = &evergreen_hpd_init, | |
1174 | .fini = &evergreen_hpd_fini, | |
1175 | .sense = &evergreen_hpd_sense, | |
1176 | .set_polarity = &evergreen_hpd_set_polarity, | |
1177 | }, | |
a02fa397 AD |
1178 | .pm = { |
1179 | .misc = &evergreen_pm_misc, | |
1180 | .prepare = &evergreen_pm_prepare, | |
1181 | .finish = &evergreen_pm_finish, | |
1182 | .init_profile = &r600_pm_init_profile, | |
1183 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1184 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1185 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1186 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1187 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1188 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1189 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1190 | .set_clock_gating = NULL, | |
a02fa397 | 1191 | }, |
0f9e006c AD |
1192 | .pflip = { |
1193 | .pre_page_flip = &evergreen_pre_page_flip, | |
1194 | .page_flip = &evergreen_page_flip, | |
1195 | .post_page_flip = &evergreen_post_page_flip, | |
1196 | }, | |
48e7a5f1 DV |
1197 | }; |
1198 | ||
958261d1 AD |
1199 | static struct radeon_asic sumo_asic = { |
1200 | .init = &evergreen_init, | |
1201 | .fini = &evergreen_fini, | |
1202 | .suspend = &evergreen_suspend, | |
1203 | .resume = &evergreen_resume, | |
958261d1 AD |
1204 | .asic_reset = &evergreen_asic_reset, |
1205 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1206 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1207 | .gui_idle = &r600_gui_idle, | |
1208 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1209 | .gart = { |
1210 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1211 | .set_page = &rs600_gart_set_page, | |
1212 | }, | |
4c87bc26 CK |
1213 | .ring = { |
1214 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1215 | .ib_execute = &evergreen_ring_ib_execute, | |
1216 | .emit_fence = &r600_fence_ring_emit, | |
1217 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1218 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1219 | .ring_test = &r600_ring_test, |
1220 | .ib_test = &r600_ib_test, | |
312c4a8c | 1221 | .is_lockup = &evergreen_gpu_is_lockup, |
eb0c19c5 | 1222 | }, |
4c87bc26 | 1223 | }, |
b35ea4ab AD |
1224 | .irq = { |
1225 | .set = &evergreen_irq_set, | |
1226 | .process = &evergreen_irq_process, | |
1227 | }, | |
c79a49ca AD |
1228 | .display = { |
1229 | .bandwidth_update = &evergreen_bandwidth_update, | |
1230 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1231 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1232 | }, | |
27cd7769 AD |
1233 | .copy = { |
1234 | .blit = &r600_copy_blit, | |
1235 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1236 | .dma = NULL, | |
1237 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1238 | .copy = &r600_copy_blit, | |
1239 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1240 | }, | |
9e6f3d02 AD |
1241 | .surface = { |
1242 | .set_reg = r600_set_surface_reg, | |
1243 | .clear_reg = r600_clear_surface_reg, | |
1244 | }, | |
901ea57d AD |
1245 | .hpd = { |
1246 | .init = &evergreen_hpd_init, | |
1247 | .fini = &evergreen_hpd_fini, | |
1248 | .sense = &evergreen_hpd_sense, | |
1249 | .set_polarity = &evergreen_hpd_set_polarity, | |
1250 | }, | |
a02fa397 AD |
1251 | .pm = { |
1252 | .misc = &evergreen_pm_misc, | |
1253 | .prepare = &evergreen_pm_prepare, | |
1254 | .finish = &evergreen_pm_finish, | |
1255 | .init_profile = &sumo_pm_init_profile, | |
1256 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1257 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1258 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1259 | .get_memory_clock = NULL, | |
1260 | .set_memory_clock = NULL, | |
1261 | .get_pcie_lanes = NULL, | |
1262 | .set_pcie_lanes = NULL, | |
1263 | .set_clock_gating = NULL, | |
a02fa397 | 1264 | }, |
0f9e006c AD |
1265 | .pflip = { |
1266 | .pre_page_flip = &evergreen_pre_page_flip, | |
1267 | .page_flip = &evergreen_page_flip, | |
1268 | .post_page_flip = &evergreen_post_page_flip, | |
1269 | }, | |
958261d1 AD |
1270 | }; |
1271 | ||
a43b7665 AD |
1272 | static struct radeon_asic btc_asic = { |
1273 | .init = &evergreen_init, | |
1274 | .fini = &evergreen_fini, | |
1275 | .suspend = &evergreen_suspend, | |
1276 | .resume = &evergreen_resume, | |
a43b7665 AD |
1277 | .asic_reset = &evergreen_asic_reset, |
1278 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1279 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1280 | .gui_idle = &r600_gui_idle, | |
1281 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1282 | .gart = { |
1283 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1284 | .set_page = &rs600_gart_set_page, | |
1285 | }, | |
4c87bc26 CK |
1286 | .ring = { |
1287 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1288 | .ib_execute = &evergreen_ring_ib_execute, | |
1289 | .emit_fence = &r600_fence_ring_emit, | |
1290 | .emit_semaphore = &r600_semaphore_ring_emit, | |
eb0c19c5 | 1291 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1292 | .ring_test = &r600_ring_test, |
1293 | .ib_test = &r600_ib_test, | |
312c4a8c | 1294 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1295 | } |
1296 | }, | |
b35ea4ab AD |
1297 | .irq = { |
1298 | .set = &evergreen_irq_set, | |
1299 | .process = &evergreen_irq_process, | |
1300 | }, | |
c79a49ca AD |
1301 | .display = { |
1302 | .bandwidth_update = &evergreen_bandwidth_update, | |
1303 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1304 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1305 | }, | |
27cd7769 AD |
1306 | .copy = { |
1307 | .blit = &r600_copy_blit, | |
1308 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1309 | .dma = NULL, | |
1310 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1311 | .copy = &r600_copy_blit, | |
1312 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1313 | }, | |
9e6f3d02 AD |
1314 | .surface = { |
1315 | .set_reg = r600_set_surface_reg, | |
1316 | .clear_reg = r600_clear_surface_reg, | |
1317 | }, | |
901ea57d AD |
1318 | .hpd = { |
1319 | .init = &evergreen_hpd_init, | |
1320 | .fini = &evergreen_hpd_fini, | |
1321 | .sense = &evergreen_hpd_sense, | |
1322 | .set_polarity = &evergreen_hpd_set_polarity, | |
1323 | }, | |
a02fa397 AD |
1324 | .pm = { |
1325 | .misc = &evergreen_pm_misc, | |
1326 | .prepare = &evergreen_pm_prepare, | |
1327 | .finish = &evergreen_pm_finish, | |
1328 | .init_profile = &r600_pm_init_profile, | |
1329 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1330 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1331 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1332 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1333 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1334 | .get_pcie_lanes = NULL, | |
1335 | .set_pcie_lanes = NULL, | |
1336 | .set_clock_gating = NULL, | |
a02fa397 | 1337 | }, |
0f9e006c AD |
1338 | .pflip = { |
1339 | .pre_page_flip = &evergreen_pre_page_flip, | |
1340 | .page_flip = &evergreen_page_flip, | |
1341 | .post_page_flip = &evergreen_post_page_flip, | |
1342 | }, | |
a43b7665 AD |
1343 | }; |
1344 | ||
721604a1 JG |
1345 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
1346 | .init = &cayman_vm_init, | |
1347 | .fini = &cayman_vm_fini, | |
1348 | .bind = &cayman_vm_bind, | |
1349 | .unbind = &cayman_vm_unbind, | |
1350 | .tlb_flush = &cayman_vm_tlb_flush, | |
1351 | .page_flags = &cayman_vm_page_flags, | |
1352 | .set_page = &cayman_vm_set_page, | |
1353 | }; | |
1354 | ||
e3487629 AD |
1355 | static struct radeon_asic cayman_asic = { |
1356 | .init = &cayman_init, | |
1357 | .fini = &cayman_fini, | |
1358 | .suspend = &cayman_suspend, | |
1359 | .resume = &cayman_resume, | |
e3487629 AD |
1360 | .asic_reset = &cayman_asic_reset, |
1361 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1362 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1363 | .gui_idle = &r600_gui_idle, | |
1364 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
c5b3b850 AD |
1365 | .gart = { |
1366 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1367 | .set_page = &rs600_gart_set_page, | |
1368 | }, | |
4c87bc26 CK |
1369 | .ring = { |
1370 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
1371 | .ib_execute = &cayman_ring_ib_execute, |
1372 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1373 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1374 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1375 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1376 | .ring_test = &r600_ring_test, |
1377 | .ib_test = &r600_ib_test, | |
abfaa44b | 1378 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1379 | }, |
1380 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1381 | .ib_execute = &cayman_ring_ib_execute, |
1382 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1383 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1384 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1385 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1386 | .ring_test = &r600_ring_test, |
1387 | .ib_test = &r600_ib_test, | |
abfaa44b | 1388 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1389 | }, |
1390 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1391 | .ib_execute = &cayman_ring_ib_execute, |
1392 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1393 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 | 1394 | .emit_semaphore = &r600_semaphore_ring_emit, |
eb0c19c5 | 1395 | .cs_parse = &evergreen_cs_parse, |
f712812e AD |
1396 | .ring_test = &r600_ring_test, |
1397 | .ib_test = &r600_ib_test, | |
abfaa44b | 1398 | .is_lockup = &evergreen_gpu_is_lockup, |
4c87bc26 CK |
1399 | } |
1400 | }, | |
b35ea4ab AD |
1401 | .irq = { |
1402 | .set = &evergreen_irq_set, | |
1403 | .process = &evergreen_irq_process, | |
1404 | }, | |
c79a49ca AD |
1405 | .display = { |
1406 | .bandwidth_update = &evergreen_bandwidth_update, | |
1407 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1408 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1409 | }, | |
27cd7769 AD |
1410 | .copy = { |
1411 | .blit = &r600_copy_blit, | |
1412 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1413 | .dma = NULL, | |
1414 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1415 | .copy = &r600_copy_blit, | |
1416 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1417 | }, | |
9e6f3d02 AD |
1418 | .surface = { |
1419 | .set_reg = r600_set_surface_reg, | |
1420 | .clear_reg = r600_clear_surface_reg, | |
1421 | }, | |
901ea57d AD |
1422 | .hpd = { |
1423 | .init = &evergreen_hpd_init, | |
1424 | .fini = &evergreen_hpd_fini, | |
1425 | .sense = &evergreen_hpd_sense, | |
1426 | .set_polarity = &evergreen_hpd_set_polarity, | |
1427 | }, | |
a02fa397 AD |
1428 | .pm = { |
1429 | .misc = &evergreen_pm_misc, | |
1430 | .prepare = &evergreen_pm_prepare, | |
1431 | .finish = &evergreen_pm_finish, | |
1432 | .init_profile = &r600_pm_init_profile, | |
1433 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1434 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1435 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1436 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1437 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1438 | .get_pcie_lanes = NULL, | |
1439 | .set_pcie_lanes = NULL, | |
1440 | .set_clock_gating = NULL, | |
a02fa397 | 1441 | }, |
0f9e006c AD |
1442 | .pflip = { |
1443 | .pre_page_flip = &evergreen_pre_page_flip, | |
1444 | .page_flip = &evergreen_page_flip, | |
1445 | .post_page_flip = &evergreen_post_page_flip, | |
1446 | }, | |
e3487629 AD |
1447 | }; |
1448 | ||
be63fe8c AD |
1449 | static struct radeon_asic trinity_asic = { |
1450 | .init = &cayman_init, | |
1451 | .fini = &cayman_fini, | |
1452 | .suspend = &cayman_suspend, | |
1453 | .resume = &cayman_resume, | |
be63fe8c AD |
1454 | .asic_reset = &cayman_asic_reset, |
1455 | .vga_set_state = &r600_vga_set_state, | |
1456 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1457 | .gui_idle = &r600_gui_idle, | |
1458 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
1459 | .gart = { | |
1460 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1461 | .set_page = &rs600_gart_set_page, | |
1462 | }, | |
1463 | .ring = { | |
1464 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1465 | .ib_execute = &cayman_ring_ib_execute, | |
1466 | .ib_parse = &evergreen_ib_parse, | |
1467 | .emit_fence = &cayman_fence_ring_emit, | |
1468 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1469 | .cs_parse = &evergreen_cs_parse, | |
1470 | .ring_test = &r600_ring_test, | |
1471 | .ib_test = &r600_ib_test, | |
abfaa44b | 1472 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1473 | }, |
1474 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
1475 | .ib_execute = &cayman_ring_ib_execute, | |
1476 | .ib_parse = &evergreen_ib_parse, | |
1477 | .emit_fence = &cayman_fence_ring_emit, | |
1478 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1479 | .cs_parse = &evergreen_cs_parse, | |
1480 | .ring_test = &r600_ring_test, | |
1481 | .ib_test = &r600_ib_test, | |
abfaa44b | 1482 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1483 | }, |
1484 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
1485 | .ib_execute = &cayman_ring_ib_execute, | |
1486 | .ib_parse = &evergreen_ib_parse, | |
1487 | .emit_fence = &cayman_fence_ring_emit, | |
1488 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1489 | .cs_parse = &evergreen_cs_parse, | |
1490 | .ring_test = &r600_ring_test, | |
1491 | .ib_test = &r600_ib_test, | |
abfaa44b | 1492 | .is_lockup = &evergreen_gpu_is_lockup, |
be63fe8c AD |
1493 | } |
1494 | }, | |
1495 | .irq = { | |
1496 | .set = &evergreen_irq_set, | |
1497 | .process = &evergreen_irq_process, | |
1498 | }, | |
1499 | .display = { | |
1500 | .bandwidth_update = &dce6_bandwidth_update, | |
1501 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1502 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1503 | }, | |
1504 | .copy = { | |
1505 | .blit = &r600_copy_blit, | |
1506 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1507 | .dma = NULL, | |
1508 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1509 | .copy = &r600_copy_blit, | |
1510 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1511 | }, | |
1512 | .surface = { | |
1513 | .set_reg = r600_set_surface_reg, | |
1514 | .clear_reg = r600_clear_surface_reg, | |
1515 | }, | |
1516 | .hpd = { | |
1517 | .init = &evergreen_hpd_init, | |
1518 | .fini = &evergreen_hpd_fini, | |
1519 | .sense = &evergreen_hpd_sense, | |
1520 | .set_polarity = &evergreen_hpd_set_polarity, | |
1521 | }, | |
1522 | .pm = { | |
1523 | .misc = &evergreen_pm_misc, | |
1524 | .prepare = &evergreen_pm_prepare, | |
1525 | .finish = &evergreen_pm_finish, | |
1526 | .init_profile = &sumo_pm_init_profile, | |
1527 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1528 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1529 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1530 | .get_memory_clock = NULL, | |
1531 | .set_memory_clock = NULL, | |
1532 | .get_pcie_lanes = NULL, | |
1533 | .set_pcie_lanes = NULL, | |
1534 | .set_clock_gating = NULL, | |
1535 | }, | |
1536 | .pflip = { | |
1537 | .pre_page_flip = &evergreen_pre_page_flip, | |
1538 | .page_flip = &evergreen_page_flip, | |
1539 | .post_page_flip = &evergreen_post_page_flip, | |
1540 | }, | |
1541 | }; | |
1542 | ||
02779c08 AD |
1543 | static const struct radeon_vm_funcs si_vm_funcs = { |
1544 | .init = &si_vm_init, | |
1545 | .fini = &si_vm_fini, | |
1546 | .bind = &si_vm_bind, | |
1547 | .unbind = &si_vm_unbind, | |
1548 | .tlb_flush = &si_vm_tlb_flush, | |
1549 | .page_flags = &cayman_vm_page_flags, | |
1550 | .set_page = &cayman_vm_set_page, | |
1551 | }; | |
1552 | ||
1553 | static struct radeon_asic si_asic = { | |
1554 | .init = &si_init, | |
1555 | .fini = &si_fini, | |
1556 | .suspend = &si_suspend, | |
1557 | .resume = &si_resume, | |
02779c08 AD |
1558 | .asic_reset = &si_asic_reset, |
1559 | .vga_set_state = &r600_vga_set_state, | |
1560 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1561 | .gui_idle = &r600_gui_idle, | |
1562 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
1563 | .gart = { | |
1564 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
1565 | .set_page = &rs600_gart_set_page, | |
1566 | }, | |
1567 | .ring = { | |
1568 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
1569 | .ib_execute = &si_ring_ib_execute, | |
1570 | .ib_parse = &si_ib_parse, | |
1571 | .emit_fence = &si_fence_ring_emit, | |
1572 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1573 | .cs_parse = NULL, | |
1574 | .ring_test = &r600_ring_test, | |
1575 | .ib_test = &r600_ib_test, | |
312c4a8c | 1576 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1577 | }, |
1578 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
1579 | .ib_execute = &si_ring_ib_execute, | |
1580 | .ib_parse = &si_ib_parse, | |
1581 | .emit_fence = &si_fence_ring_emit, | |
1582 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1583 | .cs_parse = NULL, | |
1584 | .ring_test = &r600_ring_test, | |
1585 | .ib_test = &r600_ib_test, | |
312c4a8c | 1586 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1587 | }, |
1588 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
1589 | .ib_execute = &si_ring_ib_execute, | |
1590 | .ib_parse = &si_ib_parse, | |
1591 | .emit_fence = &si_fence_ring_emit, | |
1592 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1593 | .cs_parse = NULL, | |
1594 | .ring_test = &r600_ring_test, | |
1595 | .ib_test = &r600_ib_test, | |
312c4a8c | 1596 | .is_lockup = &si_gpu_is_lockup, |
02779c08 AD |
1597 | } |
1598 | }, | |
1599 | .irq = { | |
1600 | .set = &si_irq_set, | |
1601 | .process = &si_irq_process, | |
1602 | }, | |
1603 | .display = { | |
1604 | .bandwidth_update = &dce6_bandwidth_update, | |
1605 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1606 | .wait_for_vblank = &dce4_wait_for_vblank, | |
1607 | }, | |
1608 | .copy = { | |
1609 | .blit = NULL, | |
1610 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1611 | .dma = NULL, | |
1612 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1613 | .copy = NULL, | |
1614 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
1615 | }, | |
1616 | .surface = { | |
1617 | .set_reg = r600_set_surface_reg, | |
1618 | .clear_reg = r600_clear_surface_reg, | |
1619 | }, | |
1620 | .hpd = { | |
1621 | .init = &evergreen_hpd_init, | |
1622 | .fini = &evergreen_hpd_fini, | |
1623 | .sense = &evergreen_hpd_sense, | |
1624 | .set_polarity = &evergreen_hpd_set_polarity, | |
1625 | }, | |
1626 | .pm = { | |
1627 | .misc = &evergreen_pm_misc, | |
1628 | .prepare = &evergreen_pm_prepare, | |
1629 | .finish = &evergreen_pm_finish, | |
1630 | .init_profile = &sumo_pm_init_profile, | |
1631 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1632 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1633 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1634 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1635 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1636 | .get_pcie_lanes = NULL, | |
1637 | .set_pcie_lanes = NULL, | |
1638 | .set_clock_gating = NULL, | |
1639 | }, | |
1640 | .pflip = { | |
1641 | .pre_page_flip = &evergreen_pre_page_flip, | |
1642 | .page_flip = &evergreen_page_flip, | |
1643 | .post_page_flip = &evergreen_post_page_flip, | |
1644 | }, | |
1645 | }; | |
1646 | ||
abf1dc67 AD |
1647 | /** |
1648 | * radeon_asic_init - register asic specific callbacks | |
1649 | * | |
1650 | * @rdev: radeon device pointer | |
1651 | * | |
1652 | * Registers the appropriate asic specific callbacks for each | |
1653 | * chip family. Also sets other asics specific info like the number | |
1654 | * of crtcs and the register aperture accessors (all asics). | |
1655 | * Returns 0 for success. | |
1656 | */ | |
0a10c851 DV |
1657 | int radeon_asic_init(struct radeon_device *rdev) |
1658 | { | |
1659 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
1660 | |
1661 | /* set the number of crtcs */ | |
1662 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
1663 | rdev->num_crtc = 1; | |
1664 | else | |
1665 | rdev->num_crtc = 2; | |
1666 | ||
0a10c851 DV |
1667 | switch (rdev->family) { |
1668 | case CHIP_R100: | |
1669 | case CHIP_RV100: | |
1670 | case CHIP_RS100: | |
1671 | case CHIP_RV200: | |
1672 | case CHIP_RS200: | |
1673 | rdev->asic = &r100_asic; | |
1674 | break; | |
1675 | case CHIP_R200: | |
1676 | case CHIP_RV250: | |
1677 | case CHIP_RS300: | |
1678 | case CHIP_RV280: | |
1679 | rdev->asic = &r200_asic; | |
1680 | break; | |
1681 | case CHIP_R300: | |
1682 | case CHIP_R350: | |
1683 | case CHIP_RV350: | |
1684 | case CHIP_RV380: | |
1685 | if (rdev->flags & RADEON_IS_PCIE) | |
1686 | rdev->asic = &r300_asic_pcie; | |
1687 | else | |
1688 | rdev->asic = &r300_asic; | |
1689 | break; | |
1690 | case CHIP_R420: | |
1691 | case CHIP_R423: | |
1692 | case CHIP_RV410: | |
1693 | rdev->asic = &r420_asic; | |
07bb084c AD |
1694 | /* handle macs */ |
1695 | if (rdev->bios == NULL) { | |
798bcf73 AD |
1696 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
1697 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
1698 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
1699 | rdev->asic->pm.set_memory_clock = NULL; | |
07bb084c | 1700 | } |
0a10c851 DV |
1701 | break; |
1702 | case CHIP_RS400: | |
1703 | case CHIP_RS480: | |
1704 | rdev->asic = &rs400_asic; | |
1705 | break; | |
1706 | case CHIP_RS600: | |
1707 | rdev->asic = &rs600_asic; | |
1708 | break; | |
1709 | case CHIP_RS690: | |
1710 | case CHIP_RS740: | |
1711 | rdev->asic = &rs690_asic; | |
1712 | break; | |
1713 | case CHIP_RV515: | |
1714 | rdev->asic = &rv515_asic; | |
1715 | break; | |
1716 | case CHIP_R520: | |
1717 | case CHIP_RV530: | |
1718 | case CHIP_RV560: | |
1719 | case CHIP_RV570: | |
1720 | case CHIP_R580: | |
1721 | rdev->asic = &r520_asic; | |
1722 | break; | |
1723 | case CHIP_R600: | |
1724 | case CHIP_RV610: | |
1725 | case CHIP_RV630: | |
1726 | case CHIP_RV620: | |
1727 | case CHIP_RV635: | |
1728 | case CHIP_RV670: | |
f47299c5 AD |
1729 | rdev->asic = &r600_asic; |
1730 | break; | |
0a10c851 DV |
1731 | case CHIP_RS780: |
1732 | case CHIP_RS880: | |
f47299c5 | 1733 | rdev->asic = &rs780_asic; |
0a10c851 DV |
1734 | break; |
1735 | case CHIP_RV770: | |
1736 | case CHIP_RV730: | |
1737 | case CHIP_RV710: | |
1738 | case CHIP_RV740: | |
1739 | rdev->asic = &rv770_asic; | |
1740 | break; | |
1741 | case CHIP_CEDAR: | |
1742 | case CHIP_REDWOOD: | |
1743 | case CHIP_JUNIPER: | |
1744 | case CHIP_CYPRESS: | |
1745 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
1746 | /* set num crtcs */ |
1747 | if (rdev->family == CHIP_CEDAR) | |
1748 | rdev->num_crtc = 4; | |
1749 | else | |
1750 | rdev->num_crtc = 6; | |
0a10c851 DV |
1751 | rdev->asic = &evergreen_asic; |
1752 | break; | |
958261d1 | 1753 | case CHIP_PALM: |
89da5a37 AD |
1754 | case CHIP_SUMO: |
1755 | case CHIP_SUMO2: | |
958261d1 AD |
1756 | rdev->asic = &sumo_asic; |
1757 | break; | |
a43b7665 AD |
1758 | case CHIP_BARTS: |
1759 | case CHIP_TURKS: | |
1760 | case CHIP_CAICOS: | |
ba7e05e9 AD |
1761 | /* set num crtcs */ |
1762 | if (rdev->family == CHIP_CAICOS) | |
1763 | rdev->num_crtc = 4; | |
1764 | else | |
1765 | rdev->num_crtc = 6; | |
a43b7665 AD |
1766 | rdev->asic = &btc_asic; |
1767 | break; | |
e3487629 AD |
1768 | case CHIP_CAYMAN: |
1769 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
1770 | /* set num crtcs */ |
1771 | rdev->num_crtc = 6; | |
721604a1 | 1772 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
e3487629 | 1773 | break; |
be63fe8c AD |
1774 | case CHIP_ARUBA: |
1775 | rdev->asic = &trinity_asic; | |
1776 | /* set num crtcs */ | |
1777 | rdev->num_crtc = 4; | |
1778 | rdev->vm_manager.funcs = &cayman_vm_funcs; | |
1779 | break; | |
02779c08 AD |
1780 | case CHIP_TAHITI: |
1781 | case CHIP_PITCAIRN: | |
1782 | case CHIP_VERDE: | |
1783 | rdev->asic = &si_asic; | |
1784 | /* set num crtcs */ | |
1785 | rdev->num_crtc = 6; | |
1786 | rdev->vm_manager.funcs = &si_vm_funcs; | |
1787 | break; | |
0a10c851 DV |
1788 | default: |
1789 | /* FIXME: not supported yet */ | |
1790 | return -EINVAL; | |
1791 | } | |
1792 | ||
1793 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
1794 | rdev->asic->pm.get_memory_clock = NULL; |
1795 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
1796 | } |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 |