projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 37e9b6a6 | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 AD |
49 | |
| 50 | ||
| 771fe6b9 | 51 | /* |
| 44ca7478 | 52 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 53 | */ |
| 2b497502 DV |
54 | struct r100_mc_save { |
| 55 | u32 GENMO_WT; | |
| 56 | u32 CRTC_EXT_CNTL; | |
| 57 | u32 CRTC_GEN_CNTL; | |
| 58 | u32 CRTC2_GEN_CNTL; | |
| 59 | u32 CUR_OFFSET; | |
| 60 | u32 CUR2_OFFSET; | |
| 61 | }; | |
| 62 | int r100_init(struct radeon_device *rdev); | |
| 63 | void r100_fini(struct radeon_device *rdev); | |
| 64 | int r100_suspend(struct radeon_device *rdev); | |
| 65 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 66 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| e32eb50d | 67 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 68 | int r100_asic_reset(struct radeon_device *rdev); |
| 7ed220d7 | 69 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
70 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 71 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| f712812e | 72 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 771fe6b9 JG |
73 | int r100_irq_set(struct radeon_device *rdev); |
| 74 | int r100_irq_process(struct radeon_device *rdev); | |
| 75 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 76 | struct radeon_fence *fence); | |
| 15d3332f | 77 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 78 | struct radeon_ring *cp, |
| 15d3332f | 79 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 80 | bool emit_wait); |
| 771fe6b9 JG |
81 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 82 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 83 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 84 | int r100_copy_blit(struct radeon_device *rdev, | |
| 85 | uint64_t src_offset, | |
| 86 | uint64_t dst_offset, | |
| 003cefe0 | 87 | unsigned num_gpu_pages, |
| 876dc9f3 | 88 | struct radeon_fence **fence); |
| e024e110 DA |
89 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 90 | uint32_t tiling_flags, uint32_t pitch, | |
| 91 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 92 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 93 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 94 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 95 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 429770b3 AD |
96 | void r100_hpd_init(struct radeon_device *rdev); |
| 97 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 98 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 99 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 100 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
101 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 102 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 103 | void r100_cp_disable(struct radeon_device *rdev); | |
| 104 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 105 | void r100_cp_fini(struct radeon_device *rdev); | |
| 106 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 107 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 108 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 109 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 110 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 111 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| f712812e | 112 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 2b497502 DV |
113 | void r100_irq_disable(struct radeon_device *rdev); |
| 114 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 115 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 116 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
117 | int r100_cp_reset(struct radeon_device *rdev); |
| 118 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 119 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
120 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 121 | struct radeon_cs_packet *pkt, | |
| 122 | struct radeon_bo *robj); | |
| 123 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 124 | struct radeon_cs_packet *pkt, | |
| 125 | const unsigned *auth, unsigned n, | |
| 126 | radeon_packet0_check_t check); | |
| 127 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 128 | struct radeon_cs_packet *pkt, | |
| 129 | unsigned idx); | |
| 130 | void r100_enable_bm(struct radeon_device *rdev); | |
| 131 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 132 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 133 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
134 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 135 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 136 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
137 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 138 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 6f34be50 AD |
139 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 140 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 141 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 142 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 143 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| bae6b562 | 144 | |
| 44ca7478 PN |
145 | /* |
| 146 | * r200,rv250,rs300,rv280 | |
| 147 | */ | |
| 148 | extern int r200_copy_dma(struct radeon_device *rdev, | |
| 187f3da3 DV |
149 | uint64_t src_offset, |
| 150 | uint64_t dst_offset, | |
| 003cefe0 | 151 | unsigned num_gpu_pages, |
| 876dc9f3 | 152 | struct radeon_fence **fence); |
| 187f3da3 | 153 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
154 | |
| 155 | /* | |
| 156 | * r300,r350,rv350,rv380 | |
| 157 | */ | |
| 207bf9e9 JG |
158 | extern int r300_init(struct radeon_device *rdev); |
| 159 | extern void r300_fini(struct radeon_device *rdev); | |
| 160 | extern int r300_suspend(struct radeon_device *rdev); | |
| 161 | extern int r300_resume(struct radeon_device *rdev); | |
| a2d07b74 | 162 | extern int r300_asic_reset(struct radeon_device *rdev); |
| f712812e | 163 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 207bf9e9 JG |
164 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 165 | struct radeon_fence *fence); | |
| 166 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 167 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 168 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 207bf9e9 | 169 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 170 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
171 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 172 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 173 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 174 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 175 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 176 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 177 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 178 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 179 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 89e5181f | 180 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 44ca7478 | 181 | |
| 771fe6b9 JG |
182 | /* |
| 183 | * r420,r423,rv410 | |
| 184 | */ | |
| 9f022ddf JG |
185 | extern int r420_init(struct radeon_device *rdev); |
| 186 | extern void r420_fini(struct radeon_device *rdev); | |
| 187 | extern int r420_suspend(struct radeon_device *rdev); | |
| 188 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 189 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
190 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 191 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 192 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 193 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
194 | |
| 195 | /* | |
| 196 | * rs400,rs480 | |
| 197 | */ | |
| ca6ffc64 JG |
198 | extern int rs400_init(struct radeon_device *rdev); |
| 199 | extern void rs400_fini(struct radeon_device *rdev); | |
| 200 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 201 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 JG |
202 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 203 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 204 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 205 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
206 | int rs400_gart_init(struct radeon_device *rdev); |
| 207 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 208 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 209 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 210 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 89e5181f | 211 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
| 187f3da3 | 212 | |
| 771fe6b9 JG |
213 | /* |
| 214 | * rs600. | |
| 215 | */ | |
| 90aca4d2 | 216 | extern int rs600_asic_reset(struct radeon_device *rdev); |
| c010f800 JG |
217 | extern int rs600_init(struct radeon_device *rdev); |
| 218 | extern void rs600_fini(struct radeon_device *rdev); | |
| 219 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 220 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 221 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 222 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 223 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 224 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
225 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 226 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 227 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 228 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 229 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
230 | void rs600_hpd_init(struct radeon_device *rdev); |
| 231 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 232 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 233 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 234 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
235 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 236 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 237 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 6f34be50 AD |
238 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 239 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 240 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 187f3da3 | 241 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 3ae19b75 | 242 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 243 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| 429770b3 | 244 | |
| 771fe6b9 JG |
245 | /* |
| 246 | * rs690,rs740 | |
| 247 | */ | |
| 3bc68535 JG |
248 | int rs690_init(struct radeon_device *rdev); |
| 249 | void rs690_fini(struct radeon_device *rdev); | |
| 250 | int rs690_resume(struct radeon_device *rdev); | |
| 251 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
252 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 253 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 254 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
255 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 256 | struct drm_display_mode *mode1, | |
| 257 | struct drm_display_mode *mode2); | |
| 89e5181f | 258 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
259 | |
| 260 | /* | |
| 261 | * rv515 | |
| 262 | */ | |
| 187f3da3 | 263 | struct rv515_mc_save { |
| 187f3da3 DV |
264 | u32 vga_render_control; |
| 265 | u32 vga_hdp_control; | |
| 187f3da3 | 266 | }; |
| 81ee8fb6 | 267 | |
| 068a117c | 268 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 269 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
270 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 271 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| f712812e | 272 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| c93bb85b | 273 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
274 | int rv515_resume(struct radeon_device *rdev); |
| 275 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
276 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 277 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 278 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 279 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 280 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 281 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 282 | void rv515_debugfs(struct radeon_device *rdev); | |
| 89e5181f | 283 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
284 | |
| 285 | /* | |
| 286 | * r520,rv530,rv560,rv570,r580 | |
| 287 | */ | |
| d39c3b89 | 288 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 289 | int r520_resume(struct radeon_device *rdev); |
| 89e5181f | 290 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
291 | |
| 292 | /* | |
| 3ce0a23d | 293 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 294 | */ |
| 3ce0a23d JG |
295 | int r600_init(struct radeon_device *rdev); |
| 296 | void r600_fini(struct radeon_device *rdev); | |
| 297 | int r600_suspend(struct radeon_device *rdev); | |
| 298 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 299 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
300 | int r600_wb_init(struct radeon_device *rdev); |
| 301 | void r600_wb_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 302 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 771fe6b9 JG |
303 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 304 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d JG |
305 | int r600_cs_parse(struct radeon_cs_parser *p); |
| 306 | void r600_fence_ring_emit(struct radeon_device *rdev, | |
| 307 | struct radeon_fence *fence); | |
| 15d3332f | 308 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 309 | struct radeon_ring *cp, |
| 15d3332f | 310 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 311 | bool emit_wait); |
| 4d75658b AD |
312 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
| 313 | struct radeon_fence *fence); | |
| 314 | void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, | |
| 315 | struct radeon_ring *ring, | |
| 316 | struct radeon_semaphore *semaphore, | |
| 317 | bool emit_wait); | |
| 318 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 319 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| e32eb50d | 320 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 321 | int r600_asic_reset(struct radeon_device *rdev); |
| 3ce0a23d JG |
322 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 323 | uint32_t tiling_flags, uint32_t pitch, | |
| 324 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 325 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| f712812e | 326 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 4d75658b | 327 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d | 328 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 329 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 4d75658b | 330 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 3ce0a23d JG |
331 | int r600_copy_blit(struct radeon_device *rdev, |
| 332 | uint64_t src_offset, uint64_t dst_offset, | |
| 876dc9f3 | 333 | unsigned num_gpu_pages, struct radeon_fence **fence); |
| 4d75658b AD |
334 | int r600_copy_dma(struct radeon_device *rdev, |
| 335 | uint64_t src_offset, uint64_t dst_offset, | |
| 336 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
| 429770b3 AD |
337 | void r600_hpd_init(struct radeon_device *rdev); |
| 338 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 339 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 340 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 341 | enum radeon_hpd_id hpd); | |
| 062b389c | 342 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| def9ba9c | 343 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 344 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
345 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 346 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 347 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 3313e3d4 AD |
348 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 349 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
350 | bool r600_card_posted(struct radeon_device *rdev); |
| 351 | void r600_cp_stop(struct radeon_device *rdev); | |
| 352 | int r600_cp_start(struct radeon_device *rdev); | |
| e32eb50d | 353 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
| 3574dda4 DV |
354 | int r600_cp_resume(struct radeon_device *rdev); |
| 355 | void r600_cp_fini(struct radeon_device *rdev); | |
| 356 | int r600_count_pipe_bits(uint32_t val); | |
| 357 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 358 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 359 | void r600_scratch_init(struct radeon_device *rdev); | |
| 360 | int r600_blit_init(struct radeon_device *rdev); | |
| 361 | void r600_blit_fini(struct radeon_device *rdev); | |
| 362 | int r600_init_microcode(struct radeon_device *rdev); | |
| 363 | /* r600 irq */ | |
| 364 | int r600_irq_process(struct radeon_device *rdev); | |
| 365 | int r600_irq_init(struct radeon_device *rdev); | |
| 366 | void r600_irq_fini(struct radeon_device *rdev); | |
| 367 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 368 | int r600_irq_set(struct radeon_device *rdev); | |
| 369 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 370 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 371 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 372 | /* r600 audio */ | |
| 373 | int r600_audio_init(struct radeon_device *rdev); | |
| 3574dda4 | 374 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
| 3299de95 | 375 | struct r600_audio r600_audio_status(struct radeon_device *rdev); |
| 3574dda4 | 376 | void r600_audio_fini(struct radeon_device *rdev); |
| 3574dda4 DV |
377 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| 378 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| 4546b2c1 | 379 | /* r600 blit */ |
| f237750f | 380 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
| 220907d9 CK |
381 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
| 382 | struct radeon_semaphore **sem); | |
| 876dc9f3 | 383 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
| 220907d9 | 384 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
| 4546b2c1 DV |
385 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 386 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
| f237750f CK |
387 | unsigned num_gpu_pages, |
| 388 | struct radeon_sa_bo *vb); | |
| 89e5181f | 389 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 6759a0a7 | 390 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev); |
| 3ce0a23d | 391 | |
| 3ce0a23d JG |
392 | /* |
| 393 | * rv770,rv730,rv710,rv740 | |
| 394 | */ | |
| 395 | int rv770_init(struct radeon_device *rdev); | |
| 396 | void rv770_fini(struct radeon_device *rdev); | |
| 397 | int rv770_suspend(struct radeon_device *rdev); | |
| 398 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 DV |
399 | void rv770_pm_misc(struct radeon_device *rdev); |
| 400 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 401 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
| 402 | void r700_cp_stop(struct radeon_device *rdev); | |
| 403 | void r700_cp_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 404 | |
| bcc1c2a1 AD |
405 | /* |
| 406 | * evergreen | |
| 407 | */ | |
| 3574dda4 | 408 | struct evergreen_mc_save { |
| 3574dda4 DV |
409 | u32 vga_render_control; |
| 410 | u32 vga_hdp_control; | |
| 62444b74 | 411 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
| 3574dda4 | 412 | }; |
| 81ee8fb6 | 413 | |
| 0fcdb61e | 414 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
415 | int evergreen_init(struct radeon_device *rdev); |
| 416 | void evergreen_fini(struct radeon_device *rdev); | |
| 417 | int evergreen_suspend(struct radeon_device *rdev); | |
| 418 | int evergreen_resume(struct radeon_device *rdev); | |
| e32eb50d | 419 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 420 | int evergreen_asic_reset(struct radeon_device *rdev); |
| bcc1c2a1 | 421 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 422 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
423 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 424 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 425 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 426 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 427 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
428 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 429 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 430 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 431 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
432 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 433 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 434 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 435 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 27810fb2 | 436 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
| 6f34be50 AD |
437 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 438 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 439 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 440 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 3574dda4 DV |
441 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 442 | int evergreen_blit_init(struct radeon_device *rdev); | |
| 89e5181f | 443 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 4546b2c1 | 444 | |
| e3487629 AD |
445 | /* |
| 446 | * cayman | |
| 447 | */ | |
| b40e7e16 AD |
448 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 449 | struct radeon_fence *fence); | |
| e3487629 AD |
450 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 451 | int cayman_init(struct radeon_device *rdev); | |
| 452 | void cayman_fini(struct radeon_device *rdev); | |
| 453 | int cayman_suspend(struct radeon_device *rdev); | |
| 454 | int cayman_resume(struct radeon_device *rdev); | |
| e3487629 | 455 | int cayman_asic_reset(struct radeon_device *rdev); |
| 721604a1 JG |
456 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 457 | int cayman_vm_init(struct radeon_device *rdev); | |
| 458 | void cayman_vm_fini(struct radeon_device *rdev); | |
| 498522b4 | 459 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 089a786e | 460 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
| dce34bfd CK |
461 | void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
| 462 | uint64_t addr, unsigned count, | |
| 463 | uint32_t incr, uint32_t flags); | |
| 721604a1 | 464 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 45f9a39b | 465 | |
| 43b3cd99 AD |
466 | /* DCE6 - SI */ |
| 467 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
| 468 | ||
| 02779c08 AD |
469 | /* |
| 470 | * si | |
| 471 | */ | |
| 472 | void si_fence_ring_emit(struct radeon_device *rdev, | |
| 473 | struct radeon_fence *fence); | |
| 474 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 475 | int si_init(struct radeon_device *rdev); | |
| 476 | void si_fini(struct radeon_device *rdev); | |
| 477 | int si_suspend(struct radeon_device *rdev); | |
| 478 | int si_resume(struct radeon_device *rdev); | |
| 479 | bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 480 | int si_asic_reset(struct radeon_device *rdev); | |
| 481 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 482 | int si_irq_set(struct radeon_device *rdev); | |
| 483 | int si_irq_process(struct radeon_device *rdev); | |
| 484 | int si_vm_init(struct radeon_device *rdev); | |
| 485 | void si_vm_fini(struct radeon_device *rdev); | |
| 82ffd92b AD |
486 | void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
| 487 | uint64_t addr, unsigned count, | |
| 488 | uint32_t incr, uint32_t flags); | |
| 498522b4 | 489 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 02779c08 | 490 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 6759a0a7 | 491 | uint64_t si_get_gpu_clock(struct radeon_device *rdev); |
| 02779c08 | 492 | |
| 771fe6b9 | 493 | #endif |