projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 37e9b6a6 | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 49 | |
| 771fe6b9 | 50 | /* |
| 44ca7478 | 51 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 52 | */ |
| 2b497502 DV |
53 | struct r100_mc_save { |
| 54 | u32 GENMO_WT; | |
| 55 | u32 CRTC_EXT_CNTL; | |
| 56 | u32 CRTC_GEN_CNTL; | |
| 57 | u32 CRTC2_GEN_CNTL; | |
| 58 | u32 CUR_OFFSET; | |
| 59 | u32 CUR2_OFFSET; | |
| 60 | }; | |
| 61 | int r100_init(struct radeon_device *rdev); | |
| 62 | void r100_fini(struct radeon_device *rdev); | |
| 63 | int r100_suspend(struct radeon_device *rdev); | |
| 64 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 65 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| e32eb50d | 66 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 67 | int r100_asic_reset(struct radeon_device *rdev); |
| 7ed220d7 | 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 70 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| f712812e | 71 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 771fe6b9 JG |
72 | int r100_irq_set(struct radeon_device *rdev); |
| 73 | int r100_irq_process(struct radeon_device *rdev); | |
| 74 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 75 | struct radeon_fence *fence); | |
| 1654b817 | 76 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 77 | struct radeon_ring *cp, |
| 15d3332f | 78 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 79 | bool emit_wait); |
| 771fe6b9 JG |
80 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 81 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 82 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 83 | int r100_copy_blit(struct radeon_device *rdev, | |
| 84 | uint64_t src_offset, | |
| 85 | uint64_t dst_offset, | |
| 003cefe0 | 86 | unsigned num_gpu_pages, |
| 876dc9f3 | 87 | struct radeon_fence **fence); |
| e024e110 DA |
88 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 89 | uint32_t tiling_flags, uint32_t pitch, | |
| 90 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 91 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 92 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 93 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 94 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 429770b3 AD |
95 | void r100_hpd_init(struct radeon_device *rdev); |
| 96 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 97 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 98 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 99 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
100 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 101 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 102 | void r100_cp_disable(struct radeon_device *rdev); | |
| 103 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 104 | void r100_cp_fini(struct radeon_device *rdev); | |
| 105 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 106 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 107 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 108 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 109 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 110 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| f712812e | 111 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 2b497502 DV |
112 | void r100_irq_disable(struct radeon_device *rdev); |
| 113 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 114 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 115 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
116 | int r100_cp_reset(struct radeon_device *rdev); |
| 117 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 118 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
119 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 120 | struct radeon_cs_packet *pkt, | |
| 121 | struct radeon_bo *robj); | |
| 122 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 123 | struct radeon_cs_packet *pkt, | |
| 124 | const unsigned *auth, unsigned n, | |
| 125 | radeon_packet0_check_t check); | |
| 126 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 127 | struct radeon_cs_packet *pkt, | |
| 128 | unsigned idx); | |
| 129 | void r100_enable_bm(struct radeon_device *rdev); | |
| 130 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 131 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 132 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
133 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 134 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 135 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
136 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 137 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 6f34be50 | 138 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 3ae19b75 | 139 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 140 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| bae6b562 | 141 | |
| ea31bf69 AD |
142 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
| 143 | struct radeon_ring *ring); | |
| 144 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, | |
| 145 | struct radeon_ring *ring); | |
| 146 | void r100_gfx_set_wptr(struct radeon_device *rdev, | |
| 147 | struct radeon_ring *ring); | |
| 148 | ||
| 44ca7478 PN |
149 | /* |
| 150 | * r200,rv250,rs300,rv280 | |
| 151 | */ | |
| 152 | extern int r200_copy_dma(struct radeon_device *rdev, | |
| 187f3da3 DV |
153 | uint64_t src_offset, |
| 154 | uint64_t dst_offset, | |
| 003cefe0 | 155 | unsigned num_gpu_pages, |
| 876dc9f3 | 156 | struct radeon_fence **fence); |
| 187f3da3 | 157 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
158 | |
| 159 | /* | |
| 160 | * r300,r350,rv350,rv380 | |
| 161 | */ | |
| 207bf9e9 JG |
162 | extern int r300_init(struct radeon_device *rdev); |
| 163 | extern void r300_fini(struct radeon_device *rdev); | |
| 164 | extern int r300_suspend(struct radeon_device *rdev); | |
| 165 | extern int r300_resume(struct radeon_device *rdev); | |
| a2d07b74 | 166 | extern int r300_asic_reset(struct radeon_device *rdev); |
| f712812e | 167 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 207bf9e9 JG |
168 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 169 | struct radeon_fence *fence); | |
| 170 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 171 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 172 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 207bf9e9 | 173 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 174 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
175 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 176 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 177 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 178 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 179 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 180 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 181 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 182 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 183 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 89e5181f | 184 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 44ca7478 | 185 | |
| 771fe6b9 JG |
186 | /* |
| 187 | * r420,r423,rv410 | |
| 188 | */ | |
| 9f022ddf JG |
189 | extern int r420_init(struct radeon_device *rdev); |
| 190 | extern void r420_fini(struct radeon_device *rdev); | |
| 191 | extern int r420_suspend(struct radeon_device *rdev); | |
| 192 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 193 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
194 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 195 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 196 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 197 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
198 | |
| 199 | /* | |
| 200 | * rs400,rs480 | |
| 201 | */ | |
| ca6ffc64 JG |
202 | extern int rs400_init(struct radeon_device *rdev); |
| 203 | extern void rs400_fini(struct radeon_device *rdev); | |
| 204 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 205 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 JG |
206 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 207 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 208 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 209 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
210 | int rs400_gart_init(struct radeon_device *rdev); |
| 211 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 212 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 213 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 214 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 89e5181f | 215 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
| 187f3da3 | 216 | |
| 771fe6b9 JG |
217 | /* |
| 218 | * rs600. | |
| 219 | */ | |
| 90aca4d2 | 220 | extern int rs600_asic_reset(struct radeon_device *rdev); |
| c010f800 JG |
221 | extern int rs600_init(struct radeon_device *rdev); |
| 222 | extern void rs600_fini(struct radeon_device *rdev); | |
| 223 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 224 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 225 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 226 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 227 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 228 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
229 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 230 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 231 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 232 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 233 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
234 | void rs600_hpd_init(struct radeon_device *rdev); |
| 235 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 236 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 237 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 238 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
239 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 240 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 241 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 6f34be50 | 242 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 187f3da3 | 243 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 3ae19b75 | 244 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 245 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| 429770b3 | 246 | |
| 771fe6b9 JG |
247 | /* |
| 248 | * rs690,rs740 | |
| 249 | */ | |
| 3bc68535 JG |
250 | int rs690_init(struct radeon_device *rdev); |
| 251 | void rs690_fini(struct radeon_device *rdev); | |
| 252 | int rs690_resume(struct radeon_device *rdev); | |
| 253 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
254 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 255 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 256 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
257 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 258 | struct drm_display_mode *mode1, | |
| 259 | struct drm_display_mode *mode2); | |
| 89e5181f | 260 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
261 | |
| 262 | /* | |
| 263 | * rv515 | |
| 264 | */ | |
| 187f3da3 | 265 | struct rv515_mc_save { |
| 187f3da3 DV |
266 | u32 vga_render_control; |
| 267 | u32 vga_hdp_control; | |
| 6253e4c7 | 268 | bool crtc_enabled[2]; |
| 187f3da3 | 269 | }; |
| 81ee8fb6 | 270 | |
| 068a117c | 271 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 272 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
273 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 274 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| f712812e | 275 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| c93bb85b | 276 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
277 | int rv515_resume(struct radeon_device *rdev); |
| 278 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
279 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 280 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 281 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 282 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 283 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 284 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 285 | void rv515_debugfs(struct radeon_device *rdev); | |
| 89e5181f | 286 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
287 | |
| 288 | /* | |
| 289 | * r520,rv530,rv560,rv570,r580 | |
| 290 | */ | |
| d39c3b89 | 291 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 292 | int r520_resume(struct radeon_device *rdev); |
| 89e5181f | 293 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
294 | |
| 295 | /* | |
| 3ce0a23d | 296 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 297 | */ |
| 3ce0a23d JG |
298 | int r600_init(struct radeon_device *rdev); |
| 299 | void r600_fini(struct radeon_device *rdev); | |
| 300 | int r600_suspend(struct radeon_device *rdev); | |
| 301 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 302 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
303 | int r600_wb_init(struct radeon_device *rdev); |
| 304 | void r600_wb_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 305 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 771fe6b9 JG |
306 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 307 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d | 308 | int r600_cs_parse(struct radeon_cs_parser *p); |
| cf4ccd01 | 309 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
| 3ce0a23d JG |
310 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 311 | struct radeon_fence *fence); | |
| 1654b817 | 312 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 313 | struct radeon_ring *cp, |
| 15d3332f | 314 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 315 | bool emit_wait); |
| 4d75658b AD |
316 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
| 317 | struct radeon_fence *fence); | |
| 1654b817 | 318 | bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
| 4d75658b AD |
319 | struct radeon_ring *ring, |
| 320 | struct radeon_semaphore *semaphore, | |
| 321 | bool emit_wait); | |
| 322 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 323 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 123bc183 | 324 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 325 | int r600_asic_reset(struct radeon_device *rdev); |
| 3ce0a23d JG |
326 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 327 | uint32_t tiling_flags, uint32_t pitch, | |
| 328 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 329 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| f712812e | 330 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 4d75658b | 331 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d | 332 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 333 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 4d75658b | 334 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 072b5acc AD |
335 | int r600_copy_cpdma(struct radeon_device *rdev, |
| 336 | uint64_t src_offset, uint64_t dst_offset, | |
| 337 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
| 4d75658b AD |
338 | int r600_copy_dma(struct radeon_device *rdev, |
| 339 | uint64_t src_offset, uint64_t dst_offset, | |
| 340 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
| 429770b3 AD |
341 | void r600_hpd_init(struct radeon_device *rdev); |
| 342 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 343 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 344 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 345 | enum radeon_hpd_id hpd); | |
| 062b389c | 346 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| def9ba9c | 347 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 348 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
349 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 350 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 65337e60 SL |
351 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 352 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| ce8f5370 | 353 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
| 3313e3d4 AD |
354 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 355 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
356 | bool r600_card_posted(struct radeon_device *rdev); |
| 357 | void r600_cp_stop(struct radeon_device *rdev); | |
| 358 | int r600_cp_start(struct radeon_device *rdev); | |
| e32eb50d | 359 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
| 3574dda4 DV |
360 | int r600_cp_resume(struct radeon_device *rdev); |
| 361 | void r600_cp_fini(struct radeon_device *rdev); | |
| 362 | int r600_count_pipe_bits(uint32_t val); | |
| 363 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 364 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 365 | void r600_scratch_init(struct radeon_device *rdev); | |
| 3574dda4 | 366 | int r600_init_microcode(struct radeon_device *rdev); |
| ea31bf69 AD |
367 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
| 368 | struct radeon_ring *ring); | |
| 369 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, | |
| 370 | struct radeon_ring *ring); | |
| 371 | void r600_gfx_set_wptr(struct radeon_device *rdev, | |
| 372 | struct radeon_ring *ring); | |
| 3574dda4 DV |
373 | /* r600 irq */ |
| 374 | int r600_irq_process(struct radeon_device *rdev); | |
| 375 | int r600_irq_init(struct radeon_device *rdev); | |
| 376 | void r600_irq_fini(struct radeon_device *rdev); | |
| 377 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 378 | int r600_irq_set(struct radeon_device *rdev); | |
| 379 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 380 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 381 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 382 | /* r600 audio */ | |
| 383 | int r600_audio_init(struct radeon_device *rdev); | |
| b530602f | 384 | struct r600_audio_pin r600_audio_status(struct radeon_device *rdev); |
| 3574dda4 | 385 | void r600_audio_fini(struct radeon_device *rdev); |
| 8f33a156 RM |
386 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); |
| 387 | void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, | |
| 388 | size_t size); | |
| 389 | void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); | |
| 390 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder); | |
| 3574dda4 DV |
391 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| 392 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| a973bea1 AD |
393 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
| 394 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
| 89e5181f | 395 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 454d2e2a | 396 | u32 r600_get_xclk(struct radeon_device *rdev); |
| d0418894 | 397 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
| 6bd1c385 | 398 | int rv6xx_get_temp(struct radeon_device *rdev); |
| 1b9ba70a | 399 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 98243917 AD |
400 | int r600_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 401 | void r600_dpm_post_set_power_state(struct radeon_device *rdev); | |
| a4643ba3 | 402 | int r600_dpm_late_enable(struct radeon_device *rdev); |
| 2e1e6dad CK |
403 | /* r600 dma */ |
| 404 | uint32_t r600_dma_get_rptr(struct radeon_device *rdev, | |
| 405 | struct radeon_ring *ring); | |
| 406 | uint32_t r600_dma_get_wptr(struct radeon_device *rdev, | |
| 407 | struct radeon_ring *ring); | |
| 408 | void r600_dma_set_wptr(struct radeon_device *rdev, | |
| 409 | struct radeon_ring *ring); | |
| 4a6369e9 AD |
410 | /* rv6xx dpm */ |
| 411 | int rv6xx_dpm_init(struct radeon_device *rdev); | |
| 412 | int rv6xx_dpm_enable(struct radeon_device *rdev); | |
| 413 | void rv6xx_dpm_disable(struct radeon_device *rdev); | |
| 414 | int rv6xx_dpm_set_power_state(struct radeon_device *rdev); | |
| 415 | void rv6xx_setup_asic(struct radeon_device *rdev); | |
| 416 | void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 417 | void rv6xx_dpm_fini(struct radeon_device *rdev); | |
| 418 | u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 419 | u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 420 | void rv6xx_dpm_print_power_state(struct radeon_device *rdev, | |
| 421 | struct radeon_ps *ps); | |
| 242916a5 AD |
422 | void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 423 | struct seq_file *m); | |
| f4f85a8c AD |
424 | int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, |
| 425 | enum radeon_dpm_forced_level level); | |
| 9d67006e AD |
426 | /* rs780 dpm */ |
| 427 | int rs780_dpm_init(struct radeon_device *rdev); | |
| 428 | int rs780_dpm_enable(struct radeon_device *rdev); | |
| 429 | void rs780_dpm_disable(struct radeon_device *rdev); | |
| 430 | int rs780_dpm_set_power_state(struct radeon_device *rdev); | |
| 431 | void rs780_dpm_setup_asic(struct radeon_device *rdev); | |
| 432 | void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 433 | void rs780_dpm_fini(struct radeon_device *rdev); | |
| 434 | u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 435 | u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 436 | void rs780_dpm_print_power_state(struct radeon_device *rdev, | |
| 437 | struct radeon_ps *ps); | |
| 444bddc4 AD |
438 | void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 439 | struct seq_file *m); | |
| 63580c3e AB |
440 | int rs780_dpm_force_performance_level(struct radeon_device *rdev, |
| 441 | enum radeon_dpm_forced_level level); | |
| 3ce0a23d | 442 | |
| 3ce0a23d JG |
443 | /* |
| 444 | * rv770,rv730,rv710,rv740 | |
| 445 | */ | |
| 446 | int rv770_init(struct radeon_device *rdev); | |
| 447 | void rv770_fini(struct radeon_device *rdev); | |
| 448 | int rv770_suspend(struct radeon_device *rdev); | |
| 449 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 DV |
450 | void rv770_pm_misc(struct radeon_device *rdev); |
| 451 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 452 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
| 453 | void r700_cp_stop(struct radeon_device *rdev); | |
| 454 | void r700_cp_fini(struct radeon_device *rdev); | |
| 43fb7787 AD |
455 | int rv770_copy_dma(struct radeon_device *rdev, |
| 456 | uint64_t src_offset, uint64_t dst_offset, | |
| 457 | unsigned num_gpu_pages, | |
| 458 | struct radeon_fence **fence); | |
| 454d2e2a | 459 | u32 rv770_get_xclk(struct radeon_device *rdev); |
| ef0e6e65 | 460 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6bd1c385 | 461 | int rv770_get_temp(struct radeon_device *rdev); |
| 8f33a156 RM |
462 | /* hdmi */ |
| 463 | void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
| 66229b20 AD |
464 | /* rv7xx pm */ |
| 465 | int rv770_dpm_init(struct radeon_device *rdev); | |
| 466 | int rv770_dpm_enable(struct radeon_device *rdev); | |
| a3f11245 | 467 | int rv770_dpm_late_enable(struct radeon_device *rdev); |
| 66229b20 AD |
468 | void rv770_dpm_disable(struct radeon_device *rdev); |
| 469 | int rv770_dpm_set_power_state(struct radeon_device *rdev); | |
| 470 | void rv770_dpm_setup_asic(struct radeon_device *rdev); | |
| 471 | void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 472 | void rv770_dpm_fini(struct radeon_device *rdev); | |
| 473 | u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 474 | u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 475 | void rv770_dpm_print_power_state(struct radeon_device *rdev, | |
| 476 | struct radeon_ps *ps); | |
| bd210d11 AD |
477 | void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 478 | struct seq_file *m); | |
| 8b5e6b7f AD |
479 | int rv770_dpm_force_performance_level(struct radeon_device *rdev, |
| 480 | enum radeon_dpm_forced_level level); | |
| b06195d9 | 481 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); |
| 3ce0a23d | 482 | |
| bcc1c2a1 AD |
483 | /* |
| 484 | * evergreen | |
| 485 | */ | |
| 3574dda4 | 486 | struct evergreen_mc_save { |
| 3574dda4 DV |
487 | u32 vga_render_control; |
| 488 | u32 vga_hdp_control; | |
| 62444b74 | 489 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
| 3574dda4 | 490 | }; |
| 81ee8fb6 | 491 | |
| 0fcdb61e | 492 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
493 | int evergreen_init(struct radeon_device *rdev); |
| 494 | void evergreen_fini(struct radeon_device *rdev); | |
| 495 | int evergreen_suspend(struct radeon_device *rdev); | |
| 496 | int evergreen_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
497 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 498 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| a2d07b74 | 499 | int evergreen_asic_reset(struct radeon_device *rdev); |
| bcc1c2a1 | 500 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 501 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
502 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 503 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 504 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 505 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 506 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
507 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 508 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 509 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 510 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| d2ead3ea | 511 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
512 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 513 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 514 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 515 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 27810fb2 | 516 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
| 23d33ba3 | 517 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| a8b4925c | 518 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6f34be50 | 519 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 3ae19b75 | 520 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 3574dda4 | 521 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 89e5181f | 522 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 233d1ad5 AD |
523 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
| 524 | struct radeon_fence *fence); | |
| 525 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, | |
| 526 | struct radeon_ib *ib); | |
| 527 | int evergreen_copy_dma(struct radeon_device *rdev, | |
| 528 | uint64_t src_offset, uint64_t dst_offset, | |
| 529 | unsigned num_gpu_pages, | |
| 530 | struct radeon_fence **fence); | |
| a973bea1 AD |
531 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
| 532 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
| 6bd1c385 AD |
533 | int evergreen_get_temp(struct radeon_device *rdev); |
| 534 | int sumo_get_temp(struct radeon_device *rdev); | |
| 29a15221 | 535 | int tn_get_temp(struct radeon_device *rdev); |
| dc50ba7f AD |
536 | int cypress_dpm_init(struct radeon_device *rdev); |
| 537 | void cypress_dpm_setup_asic(struct radeon_device *rdev); | |
| 538 | int cypress_dpm_enable(struct radeon_device *rdev); | |
| 539 | void cypress_dpm_disable(struct radeon_device *rdev); | |
| 540 | int cypress_dpm_set_power_state(struct radeon_device *rdev); | |
| 541 | void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 542 | void cypress_dpm_fini(struct radeon_device *rdev); | |
| d0b54bdc | 543 | bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); |
| 6596afd4 AD |
544 | int btc_dpm_init(struct radeon_device *rdev); |
| 545 | void btc_dpm_setup_asic(struct radeon_device *rdev); | |
| 546 | int btc_dpm_enable(struct radeon_device *rdev); | |
| 547 | void btc_dpm_disable(struct radeon_device *rdev); | |
| e8a9539f | 548 | int btc_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 6596afd4 | 549 | int btc_dpm_set_power_state(struct radeon_device *rdev); |
| e8a9539f | 550 | void btc_dpm_post_set_power_state(struct radeon_device *rdev); |
| 6596afd4 | 551 | void btc_dpm_fini(struct radeon_device *rdev); |
| e8a9539f AD |
552 | u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); |
| 553 | u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| a84301c6 | 554 | bool btc_dpm_vblank_too_short(struct radeon_device *rdev); |
| 9f3f63f2 AD |
555 | void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 556 | struct seq_file *m); | |
| 80ea2c12 AD |
557 | int sumo_dpm_init(struct radeon_device *rdev); |
| 558 | int sumo_dpm_enable(struct radeon_device *rdev); | |
| 14ec9fab | 559 | int sumo_dpm_late_enable(struct radeon_device *rdev); |
| 80ea2c12 | 560 | void sumo_dpm_disable(struct radeon_device *rdev); |
| 422a56bc | 561 | int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 80ea2c12 | 562 | int sumo_dpm_set_power_state(struct radeon_device *rdev); |
| 422a56bc | 563 | void sumo_dpm_post_set_power_state(struct radeon_device *rdev); |
| 80ea2c12 AD |
564 | void sumo_dpm_setup_asic(struct radeon_device *rdev); |
| 565 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 566 | void sumo_dpm_fini(struct radeon_device *rdev); | |
| 567 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 568 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 569 | void sumo_dpm_print_power_state(struct radeon_device *rdev, | |
| 570 | struct radeon_ps *ps); | |
| fb70160c AD |
571 | void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 572 | struct seq_file *m); | |
| 5d5e5591 AD |
573 | int sumo_dpm_force_performance_level(struct radeon_device *rdev, |
| 574 | enum radeon_dpm_forced_level level); | |
| 4546b2c1 | 575 | |
| e3487629 AD |
576 | /* |
| 577 | * cayman | |
| 578 | */ | |
| b40e7e16 AD |
579 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 580 | struct radeon_fence *fence); | |
| e3487629 AD |
581 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 582 | int cayman_init(struct radeon_device *rdev); | |
| 583 | void cayman_fini(struct radeon_device *rdev); | |
| 584 | int cayman_suspend(struct radeon_device *rdev); | |
| 585 | int cayman_resume(struct radeon_device *rdev); | |
| e3487629 | 586 | int cayman_asic_reset(struct radeon_device *rdev); |
| 721604a1 JG |
587 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 588 | int cayman_vm_init(struct radeon_device *rdev); | |
| 589 | void cayman_vm_fini(struct radeon_device *rdev); | |
| 498522b4 | 590 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 089a786e | 591 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
| 721604a1 | 592 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| cd459e52 | 593 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| f60cbd11 AD |
594 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
| 595 | struct radeon_ib *ib); | |
| 123bc183 | 596 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| f60cbd11 | 597 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| 24c16439 CK |
598 | void cayman_dma_vm_set_page(struct radeon_device *rdev, |
| 599 | struct radeon_ib *ib, | |
| 600 | uint64_t pe, | |
| 601 | uint64_t addr, unsigned count, | |
| 602 | uint32_t incr, uint32_t flags); | |
| 603 | ||
| f60cbd11 | 604 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 45f9a39b | 605 | |
| ea31bf69 AD |
606 | u32 cayman_gfx_get_rptr(struct radeon_device *rdev, |
| 607 | struct radeon_ring *ring); | |
| 608 | u32 cayman_gfx_get_wptr(struct radeon_device *rdev, | |
| 609 | struct radeon_ring *ring); | |
| 610 | void cayman_gfx_set_wptr(struct radeon_device *rdev, | |
| 611 | struct radeon_ring *ring); | |
| 612 | uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, | |
| 613 | struct radeon_ring *ring); | |
| 614 | uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, | |
| 615 | struct radeon_ring *ring); | |
| 616 | void cayman_dma_set_wptr(struct radeon_device *rdev, | |
| 617 | struct radeon_ring *ring); | |
| 618 | ||
| 69e0b57a AD |
619 | int ni_dpm_init(struct radeon_device *rdev); |
| 620 | void ni_dpm_setup_asic(struct radeon_device *rdev); | |
| 621 | int ni_dpm_enable(struct radeon_device *rdev); | |
| 622 | void ni_dpm_disable(struct radeon_device *rdev); | |
| fee3d744 | 623 | int ni_dpm_pre_set_power_state(struct radeon_device *rdev); |
| 69e0b57a | 624 | int ni_dpm_set_power_state(struct radeon_device *rdev); |
| fee3d744 | 625 | void ni_dpm_post_set_power_state(struct radeon_device *rdev); |
| 69e0b57a AD |
626 | void ni_dpm_fini(struct radeon_device *rdev); |
| 627 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 628 | u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 629 | void ni_dpm_print_power_state(struct radeon_device *rdev, | |
| 630 | struct radeon_ps *ps); | |
| bdf0c4f0 AD |
631 | void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 632 | struct seq_file *m); | |
| 170a47f0 AD |
633 | int ni_dpm_force_performance_level(struct radeon_device *rdev, |
| 634 | enum radeon_dpm_forced_level level); | |
| 76ad73e5 | 635 | bool ni_dpm_vblank_too_short(struct radeon_device *rdev); |
| d70229f7 AD |
636 | int trinity_dpm_init(struct radeon_device *rdev); |
| 637 | int trinity_dpm_enable(struct radeon_device *rdev); | |
| bda44c1a | 638 | int trinity_dpm_late_enable(struct radeon_device *rdev); |
| d70229f7 | 639 | void trinity_dpm_disable(struct radeon_device *rdev); |
| a284c48a | 640 | int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); |
| d70229f7 | 641 | int trinity_dpm_set_power_state(struct radeon_device *rdev); |
| a284c48a | 642 | void trinity_dpm_post_set_power_state(struct radeon_device *rdev); |
| d70229f7 AD |
643 | void trinity_dpm_setup_asic(struct radeon_device *rdev); |
| 644 | void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 645 | void trinity_dpm_fini(struct radeon_device *rdev); | |
| 646 | u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 647 | u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 648 | void trinity_dpm_print_power_state(struct radeon_device *rdev, | |
| 649 | struct radeon_ps *ps); | |
| 490ab931 AD |
650 | void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 651 | struct seq_file *m); | |
| 9b5de596 AD |
652 | int trinity_dpm_force_performance_level(struct radeon_device *rdev, |
| 653 | enum radeon_dpm_forced_level level); | |
| 11877060 | 654 | void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
| d70229f7 | 655 | |
| 43b3cd99 AD |
656 | /* DCE6 - SI */ |
| 657 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
| b530602f AD |
658 | int dce6_audio_init(struct radeon_device *rdev); |
| 659 | void dce6_audio_fini(struct radeon_device *rdev); | |
| 43b3cd99 | 660 | |
| 02779c08 AD |
661 | /* |
| 662 | * si | |
| 663 | */ | |
| 664 | void si_fence_ring_emit(struct radeon_device *rdev, | |
| 665 | struct radeon_fence *fence); | |
| 666 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 667 | int si_init(struct radeon_device *rdev); | |
| 668 | void si_fini(struct radeon_device *rdev); | |
| 669 | int si_suspend(struct radeon_device *rdev); | |
| 670 | int si_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
671 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 672 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 02779c08 AD |
673 | int si_asic_reset(struct radeon_device *rdev); |
| 674 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 675 | int si_irq_set(struct radeon_device *rdev); | |
| 676 | int si_irq_process(struct radeon_device *rdev); | |
| 677 | int si_vm_init(struct radeon_device *rdev); | |
| 678 | void si_vm_fini(struct radeon_device *rdev); | |
| 498522b4 | 679 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 02779c08 | 680 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 8c5fd7ef AD |
681 | int si_copy_dma(struct radeon_device *rdev, |
| 682 | uint64_t src_offset, uint64_t dst_offset, | |
| 683 | unsigned num_gpu_pages, | |
| 684 | struct radeon_fence **fence); | |
| 24c16439 CK |
685 | void si_dma_vm_set_page(struct radeon_device *rdev, |
| 686 | struct radeon_ib *ib, | |
| 687 | uint64_t pe, | |
| 688 | uint64_t addr, unsigned count, | |
| 689 | uint32_t incr, uint32_t flags); | |
| 8c5fd7ef | 690 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 454d2e2a | 691 | u32 si_get_xclk(struct radeon_device *rdev); |
| d0418894 | 692 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
| 2539eb02 | 693 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6bd1c385 | 694 | int si_get_temp(struct radeon_device *rdev); |
| a9e61410 AD |
695 | int si_dpm_init(struct radeon_device *rdev); |
| 696 | void si_dpm_setup_asic(struct radeon_device *rdev); | |
| 697 | int si_dpm_enable(struct radeon_device *rdev); | |
| 963c115d | 698 | int si_dpm_late_enable(struct radeon_device *rdev); |
| a9e61410 AD |
699 | void si_dpm_disable(struct radeon_device *rdev); |
| 700 | int si_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 701 | int si_dpm_set_power_state(struct radeon_device *rdev); | |
| 702 | void si_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 703 | void si_dpm_fini(struct radeon_device *rdev); | |
| 704 | void si_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 7982128c AD |
705 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 706 | struct seq_file *m); | |
| a160a6a3 AD |
707 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
| 708 | enum radeon_dpm_forced_level level); | |
| 02779c08 | 709 | |
| 0672e27b AD |
710 | /* DCE8 - CIK */ |
| 711 | void dce8_bandwidth_update(struct radeon_device *rdev); | |
| 712 | ||
| 44fa346f AD |
713 | /* |
| 714 | * cik | |
| 715 | */ | |
| 716 | uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); | |
| 2c67912c | 717 | u32 cik_get_xclk(struct radeon_device *rdev); |
| 6e2c3c0a AD |
718 | uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 719 | void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 87167bb1 | 720 | int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 5ad6bf91 | 721 | int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
| 0672e27b AD |
722 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
| 723 | struct radeon_fence *fence); | |
| 1654b817 | 724 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
| 0672e27b AD |
725 | struct radeon_ring *ring, |
| 726 | struct radeon_semaphore *semaphore, | |
| 727 | bool emit_wait); | |
| 728 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 729 | int cik_copy_dma(struct radeon_device *rdev, | |
| 730 | uint64_t src_offset, uint64_t dst_offset, | |
| 731 | unsigned num_gpu_pages, | |
| 732 | struct radeon_fence **fence); | |
| c9dbd705 AD |
733 | int cik_copy_cpdma(struct radeon_device *rdev, |
| 734 | uint64_t src_offset, uint64_t dst_offset, | |
| 735 | unsigned num_gpu_pages, | |
| 736 | struct radeon_fence **fence); | |
| 0672e27b AD |
737 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 738 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 739 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 740 | void cik_fence_gfx_ring_emit(struct radeon_device *rdev, | |
| 741 | struct radeon_fence *fence); | |
| 742 | void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |
| 743 | struct radeon_fence *fence); | |
| 1654b817 | 744 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
| 0672e27b AD |
745 | struct radeon_ring *cp, |
| 746 | struct radeon_semaphore *semaphore, | |
| 747 | bool emit_wait); | |
| 748 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 749 | int cik_init(struct radeon_device *rdev); | |
| 750 | void cik_fini(struct radeon_device *rdev); | |
| 751 | int cik_suspend(struct radeon_device *rdev); | |
| 752 | int cik_resume(struct radeon_device *rdev); | |
| 753 | bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 754 | int cik_asic_reset(struct radeon_device *rdev); | |
| 755 | void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 756 | int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 757 | int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 758 | int cik_irq_set(struct radeon_device *rdev); | |
| 759 | int cik_irq_process(struct radeon_device *rdev); | |
| 760 | int cik_vm_init(struct radeon_device *rdev); | |
| 761 | void cik_vm_fini(struct radeon_device *rdev); | |
| 762 | void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
| 24c16439 CK |
763 | void cik_sdma_vm_set_page(struct radeon_device *rdev, |
| 764 | struct radeon_ib *ib, | |
| 765 | uint64_t pe, | |
| 766 | uint64_t addr, unsigned count, | |
| 767 | uint32_t incr, uint32_t flags); | |
| 0672e27b AD |
768 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 769 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
| ea31bf69 AD |
770 | u32 cik_gfx_get_rptr(struct radeon_device *rdev, |
| 771 | struct radeon_ring *ring); | |
| 772 | u32 cik_gfx_get_wptr(struct radeon_device *rdev, | |
| 773 | struct radeon_ring *ring); | |
| 774 | void cik_gfx_set_wptr(struct radeon_device *rdev, | |
| 775 | struct radeon_ring *ring); | |
| 776 | u32 cik_compute_get_rptr(struct radeon_device *rdev, | |
| 777 | struct radeon_ring *ring); | |
| 778 | u32 cik_compute_get_wptr(struct radeon_device *rdev, | |
| 779 | struct radeon_ring *ring); | |
| 780 | void cik_compute_set_wptr(struct radeon_device *rdev, | |
| 781 | struct radeon_ring *ring); | |
| 782 | u32 cik_sdma_get_rptr(struct radeon_device *rdev, | |
| 783 | struct radeon_ring *ring); | |
| 784 | u32 cik_sdma_get_wptr(struct radeon_device *rdev, | |
| 785 | struct radeon_ring *ring); | |
| 786 | void cik_sdma_set_wptr(struct radeon_device *rdev, | |
| 787 | struct radeon_ring *ring); | |
| 286d9cc6 AD |
788 | int ci_get_temp(struct radeon_device *rdev); |
| 789 | int kv_get_temp(struct radeon_device *rdev); | |
| 44fa346f | 790 | |
| cc8dbbb4 AD |
791 | int ci_dpm_init(struct radeon_device *rdev); |
| 792 | int ci_dpm_enable(struct radeon_device *rdev); | |
| 90208427 | 793 | int ci_dpm_late_enable(struct radeon_device *rdev); |
| cc8dbbb4 AD |
794 | void ci_dpm_disable(struct radeon_device *rdev); |
| 795 | int ci_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 796 | int ci_dpm_set_power_state(struct radeon_device *rdev); | |
| 797 | void ci_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 798 | void ci_dpm_setup_asic(struct radeon_device *rdev); | |
| 799 | void ci_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 800 | void ci_dpm_fini(struct radeon_device *rdev); | |
| 801 | u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 802 | u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 803 | void ci_dpm_print_power_state(struct radeon_device *rdev, | |
| 804 | struct radeon_ps *ps); | |
| 94b4adc5 AD |
805 | void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 806 | struct seq_file *m); | |
| 89536fd6 AD |
807 | int ci_dpm_force_performance_level(struct radeon_device *rdev, |
| 808 | enum radeon_dpm_forced_level level); | |
| 5496131e | 809 | bool ci_dpm_vblank_too_short(struct radeon_device *rdev); |
| 942bdf7f | 810 | void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
| cc8dbbb4 | 811 | |
| 41a524ab AD |
812 | int kv_dpm_init(struct radeon_device *rdev); |
| 813 | int kv_dpm_enable(struct radeon_device *rdev); | |
| d8852c34 | 814 | int kv_dpm_late_enable(struct radeon_device *rdev); |
| 41a524ab AD |
815 | void kv_dpm_disable(struct radeon_device *rdev); |
| 816 | int kv_dpm_pre_set_power_state(struct radeon_device *rdev); | |
| 817 | int kv_dpm_set_power_state(struct radeon_device *rdev); | |
| 818 | void kv_dpm_post_set_power_state(struct radeon_device *rdev); | |
| 819 | void kv_dpm_setup_asic(struct radeon_device *rdev); | |
| 820 | void kv_dpm_display_configuration_changed(struct radeon_device *rdev); | |
| 821 | void kv_dpm_fini(struct radeon_device *rdev); | |
| 822 | u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
| 823 | u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
| 824 | void kv_dpm_print_power_state(struct radeon_device *rdev, | |
| 825 | struct radeon_ps *ps); | |
| ae3e40e8 AD |
826 | void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 827 | struct seq_file *m); | |
| 2b4c8022 AD |
828 | int kv_dpm_force_performance_level(struct radeon_device *rdev, |
| 829 | enum radeon_dpm_forced_level level); | |
| 77df508a | 830 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
| b7a5ae97 | 831 | void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
| 41a524ab | 832 | |
| e409b128 CK |
833 | /* uvd v1.0 */ |
| 834 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, | |
| 835 | struct radeon_ring *ring); | |
| 836 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, | |
| 837 | struct radeon_ring *ring); | |
| 838 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, | |
| 839 | struct radeon_ring *ring); | |
| 840 | ||
| 841 | int uvd_v1_0_init(struct radeon_device *rdev); | |
| 842 | void uvd_v1_0_fini(struct radeon_device *rdev); | |
| 843 | int uvd_v1_0_start(struct radeon_device *rdev); | |
| 844 | void uvd_v1_0_stop(struct radeon_device *rdev); | |
| 845 | ||
| 846 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 847 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 1654b817 | 848 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
| e409b128 CK |
849 | struct radeon_ring *ring, |
| 850 | struct radeon_semaphore *semaphore, | |
| 851 | bool emit_wait); | |
| 852 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 853 | ||
| 854 | /* uvd v2.2 */ | |
| 855 | int uvd_v2_2_resume(struct radeon_device *rdev); | |
| 856 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, | |
| 857 | struct radeon_fence *fence); | |
| 858 | ||
| 859 | /* uvd v3.1 */ | |
| 1654b817 | 860 | bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, |
| e409b128 CK |
861 | struct radeon_ring *ring, |
| 862 | struct radeon_semaphore *semaphore, | |
| 863 | bool emit_wait); | |
| 864 | ||
| 865 | /* uvd v4.2 */ | |
| 866 | int uvd_v4_2_resume(struct radeon_device *rdev); | |
| 867 | ||
| d93f7937 CK |
868 | /* vce v1.0 */ |
| 869 | uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, | |
| 870 | struct radeon_ring *ring); | |
| 871 | uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, | |
| 872 | struct radeon_ring *ring); | |
| 873 | void vce_v1_0_set_wptr(struct radeon_device *rdev, | |
| 874 | struct radeon_ring *ring); | |
| 875 | int vce_v1_0_init(struct radeon_device *rdev); | |
| 876 | int vce_v1_0_start(struct radeon_device *rdev); | |
| 877 | ||
| 878 | /* vce v2.0 */ | |
| 879 | int vce_v2_0_resume(struct radeon_device *rdev); | |
| 880 | ||
| 771fe6b9 | 881 | #endif |