projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 45 | /* | |
| 44ca7478 | 46 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 47 | */ |
| 2b497502 DV |
48 | struct r100_mc_save { |
| 49 | u32 GENMO_WT; | |
| 50 | u32 CRTC_EXT_CNTL; | |
| 51 | u32 CRTC_GEN_CNTL; | |
| 52 | u32 CRTC2_GEN_CNTL; | |
| 53 | u32 CUR_OFFSET; | |
| 54 | u32 CUR2_OFFSET; | |
| 55 | }; | |
| 56 | int r100_init(struct radeon_device *rdev); | |
| 57 | void r100_fini(struct radeon_device *rdev); | |
| 58 | int r100_suspend(struct radeon_device *rdev); | |
| 59 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 60 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| 225758d8 | 61 | bool r100_gpu_is_lockup(struct radeon_device *rdev); |
| a2d07b74 | 62 | int r100_asic_reset(struct radeon_device *rdev); |
| 7ed220d7 | 63 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
64 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 65 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 3ce0a23d | 66 | void r100_cp_commit(struct radeon_device *rdev); |
| 771fe6b9 JG |
67 | void r100_ring_start(struct radeon_device *rdev); |
| 68 | int r100_irq_set(struct radeon_device *rdev); | |
| 69 | int r100_irq_process(struct radeon_device *rdev); | |
| 70 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 71 | struct radeon_fence *fence); | |
| 72 | int r100_cs_parse(struct radeon_cs_parser *p); | |
| 73 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 74 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 75 | int r100_copy_blit(struct radeon_device *rdev, | |
| 76 | uint64_t src_offset, | |
| 77 | uint64_t dst_offset, | |
| 003cefe0 | 78 | unsigned num_gpu_pages, |
| 771fe6b9 | 79 | struct radeon_fence *fence); |
| e024e110 DA |
80 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 81 | uint32_t tiling_flags, uint32_t pitch, | |
| 82 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 83 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 84 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 85 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 3ce0a23d | 86 | int r100_ring_test(struct radeon_device *rdev); |
| 429770b3 AD |
87 | void r100_hpd_init(struct radeon_device *rdev); |
| 88 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 89 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 90 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 91 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
92 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 93 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 94 | void r100_cp_disable(struct radeon_device *rdev); | |
| 95 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 96 | void r100_cp_fini(struct radeon_device *rdev); | |
| 97 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 98 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 99 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 100 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 101 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 102 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| 187f3da3 DV |
103 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, |
| 104 | struct radeon_cp *cp); | |
| 105 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, | |
| 106 | struct r100_gpu_lockup *lockup, | |
| 107 | struct radeon_cp *cp); | |
| 2b497502 DV |
108 | void r100_ib_fini(struct radeon_device *rdev); |
| 109 | int r100_ib_init(struct radeon_device *rdev); | |
| 110 | void r100_irq_disable(struct radeon_device *rdev); | |
| 111 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 112 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 113 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
114 | int r100_cp_reset(struct radeon_device *rdev); |
| 115 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 116 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
117 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 118 | struct radeon_cs_packet *pkt, | |
| 119 | struct radeon_bo *robj); | |
| 120 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 121 | struct radeon_cs_packet *pkt, | |
| 122 | const unsigned *auth, unsigned n, | |
| 123 | radeon_packet0_check_t check); | |
| 124 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 125 | struct radeon_cs_packet *pkt, | |
| 126 | unsigned idx); | |
| 127 | void r100_enable_bm(struct radeon_device *rdev); | |
| 128 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 129 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 130 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
131 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 132 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 133 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
134 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 135 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 6f34be50 AD |
136 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 137 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 138 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); | |
| bae6b562 | 139 | |
| 44ca7478 PN |
140 | /* |
| 141 | * r200,rv250,rs300,rv280 | |
| 142 | */ | |
| 143 | extern int r200_copy_dma(struct radeon_device *rdev, | |
| 187f3da3 DV |
144 | uint64_t src_offset, |
| 145 | uint64_t dst_offset, | |
| 003cefe0 | 146 | unsigned num_gpu_pages, |
| 225758d8 | 147 | struct radeon_fence *fence); |
| 187f3da3 | 148 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
149 | |
| 150 | /* | |
| 151 | * r300,r350,rv350,rv380 | |
| 152 | */ | |
| 207bf9e9 JG |
153 | extern int r300_init(struct radeon_device *rdev); |
| 154 | extern void r300_fini(struct radeon_device *rdev); | |
| 155 | extern int r300_suspend(struct radeon_device *rdev); | |
| 156 | extern int r300_resume(struct radeon_device *rdev); | |
| 225758d8 | 157 | extern bool r300_gpu_is_lockup(struct radeon_device *rdev); |
| a2d07b74 | 158 | extern int r300_asic_reset(struct radeon_device *rdev); |
| 207bf9e9 JG |
159 | extern void r300_ring_start(struct radeon_device *rdev); |
| 160 | extern void r300_fence_ring_emit(struct radeon_device *rdev, | |
| 161 | struct radeon_fence *fence); | |
| 162 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 163 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 164 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 207bf9e9 | 165 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 166 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
167 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 168 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 169 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 170 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 171 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 172 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 173 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 174 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 175 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 44ca7478 | 176 | |
| 771fe6b9 JG |
177 | /* |
| 178 | * r420,r423,rv410 | |
| 179 | */ | |
| 9f022ddf JG |
180 | extern int r420_init(struct radeon_device *rdev); |
| 181 | extern void r420_fini(struct radeon_device *rdev); | |
| 182 | extern int r420_suspend(struct radeon_device *rdev); | |
| 183 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 184 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
185 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 186 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 187 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 188 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
189 | |
| 190 | /* | |
| 191 | * rs400,rs480 | |
| 192 | */ | |
| ca6ffc64 JG |
193 | extern int rs400_init(struct radeon_device *rdev); |
| 194 | extern void rs400_fini(struct radeon_device *rdev); | |
| 195 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 196 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 JG |
197 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 198 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 199 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 200 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
201 | int rs400_gart_init(struct radeon_device *rdev); |
| 202 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 203 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 204 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 205 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 206 | ||
| 771fe6b9 JG |
207 | /* |
| 208 | * rs600. | |
| 209 | */ | |
| 90aca4d2 | 210 | extern int rs600_asic_reset(struct radeon_device *rdev); |
| c010f800 JG |
211 | extern int rs600_init(struct radeon_device *rdev); |
| 212 | extern void rs600_fini(struct radeon_device *rdev); | |
| 213 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 214 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 215 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 216 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 217 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 218 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
219 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 220 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 221 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 222 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 223 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
224 | void rs600_hpd_init(struct radeon_device *rdev); |
| 225 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 226 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 227 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 228 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
229 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 230 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 231 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 6f34be50 AD |
232 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 233 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 234 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 187f3da3 DV |
235 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 236 | ||
| 429770b3 | 237 | |
| 771fe6b9 JG |
238 | /* |
| 239 | * rs690,rs740 | |
| 240 | */ | |
| 3bc68535 JG |
241 | int rs690_init(struct radeon_device *rdev); |
| 242 | void rs690_fini(struct radeon_device *rdev); | |
| 243 | int rs690_resume(struct radeon_device *rdev); | |
| 244 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
245 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 246 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 247 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
248 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 249 | struct drm_display_mode *mode1, | |
| 250 | struct drm_display_mode *mode2); | |
| 771fe6b9 JG |
251 | |
| 252 | /* | |
| 253 | * rv515 | |
| 254 | */ | |
| 187f3da3 DV |
255 | struct rv515_mc_save { |
| 256 | u32 d1vga_control; | |
| 257 | u32 d2vga_control; | |
| 258 | u32 vga_render_control; | |
| 259 | u32 vga_hdp_control; | |
| 260 | u32 d1crtc_control; | |
| 261 | u32 d2crtc_control; | |
| 262 | }; | |
| 068a117c | 263 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 264 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
265 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 266 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 267 | void rv515_ring_start(struct radeon_device *rdev); | |
| c93bb85b | 268 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
269 | int rv515_resume(struct radeon_device *rdev); |
| 270 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
271 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 272 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 273 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 274 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 275 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 276 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 277 | void rv515_debugfs(struct radeon_device *rdev); | |
| 278 | ||
| 771fe6b9 JG |
279 | |
| 280 | /* | |
| 281 | * r520,rv530,rv560,rv570,r580 | |
| 282 | */ | |
| d39c3b89 | 283 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 284 | int r520_resume(struct radeon_device *rdev); |
| 771fe6b9 JG |
285 | |
| 286 | /* | |
| 3ce0a23d | 287 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 288 | */ |
| 3ce0a23d JG |
289 | int r600_init(struct radeon_device *rdev); |
| 290 | void r600_fini(struct radeon_device *rdev); | |
| 291 | int r600_suspend(struct radeon_device *rdev); | |
| 292 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 293 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
294 | int r600_wb_init(struct radeon_device *rdev); |
| 295 | void r600_wb_fini(struct radeon_device *rdev); | |
| 296 | void r600_cp_commit(struct radeon_device *rdev); | |
| 297 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 771fe6b9 JG |
298 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 299 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d JG |
300 | int r600_cs_parse(struct radeon_cs_parser *p); |
| 301 | void r600_fence_ring_emit(struct radeon_device *rdev, | |
| 302 | struct radeon_fence *fence); | |
| 225758d8 | 303 | bool r600_gpu_is_lockup(struct radeon_device *rdev); |
| a2d07b74 | 304 | int r600_asic_reset(struct radeon_device *rdev); |
| 3ce0a23d JG |
305 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 306 | uint32_t tiling_flags, uint32_t pitch, | |
| 307 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 308 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| 3574dda4 | 309 | int r600_ib_test(struct radeon_device *rdev); |
| 3ce0a23d | 310 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 3ce0a23d JG |
311 | int r600_ring_test(struct radeon_device *rdev); |
| 312 | int r600_copy_blit(struct radeon_device *rdev, | |
| 313 | uint64_t src_offset, uint64_t dst_offset, | |
| 003cefe0 | 314 | unsigned num_gpu_pages, struct radeon_fence *fence); |
| 429770b3 AD |
315 | void r600_hpd_init(struct radeon_device *rdev); |
| 316 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 317 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 318 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 319 | enum radeon_hpd_id hpd); | |
| 062b389c | 320 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| def9ba9c | 321 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 322 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
323 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 324 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 325 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 3313e3d4 AD |
326 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 327 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
328 | bool r600_card_posted(struct radeon_device *rdev); |
| 329 | void r600_cp_stop(struct radeon_device *rdev); | |
| 330 | int r600_cp_start(struct radeon_device *rdev); | |
| 331 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 332 | int r600_cp_resume(struct radeon_device *rdev); | |
| 333 | void r600_cp_fini(struct radeon_device *rdev); | |
| 334 | int r600_count_pipe_bits(uint32_t val); | |
| 335 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 336 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 337 | void r600_scratch_init(struct radeon_device *rdev); | |
| 338 | int r600_blit_init(struct radeon_device *rdev); | |
| 339 | void r600_blit_fini(struct radeon_device *rdev); | |
| 340 | int r600_init_microcode(struct radeon_device *rdev); | |
| 341 | /* r600 irq */ | |
| 342 | int r600_irq_process(struct radeon_device *rdev); | |
| 343 | int r600_irq_init(struct radeon_device *rdev); | |
| 344 | void r600_irq_fini(struct radeon_device *rdev); | |
| 345 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 346 | int r600_irq_set(struct radeon_device *rdev); | |
| 347 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 348 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 349 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 350 | /* r600 audio */ | |
| 351 | int r600_audio_init(struct radeon_device *rdev); | |
| 352 | int r600_audio_tmds_index(struct drm_encoder *encoder); | |
| 353 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
| 354 | int r600_audio_channels(struct radeon_device *rdev); | |
| 355 | int r600_audio_bits_per_sample(struct radeon_device *rdev); | |
| 356 | int r600_audio_rate(struct radeon_device *rdev); | |
| 357 | uint8_t r600_audio_status_bits(struct radeon_device *rdev); | |
| 358 | uint8_t r600_audio_category_code(struct radeon_device *rdev); | |
| 359 | void r600_audio_schedule_polling(struct radeon_device *rdev); | |
| 360 | void r600_audio_enable_polling(struct drm_encoder *encoder); | |
| 361 | void r600_audio_disable_polling(struct drm_encoder *encoder); | |
| 362 | void r600_audio_fini(struct radeon_device *rdev); | |
| 363 | void r600_hdmi_init(struct drm_encoder *encoder); | |
| 364 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
| 365 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| 4546b2c1 | 366 | /* r600 blit */ |
| b3530963 | 367 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages); |
| 4546b2c1 DV |
368 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
| 369 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
| 370 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
| b3530963 | 371 | unsigned num_gpu_pages); |
| 3ce0a23d | 372 | |
| 3ce0a23d JG |
373 | /* |
| 374 | * rv770,rv730,rv710,rv740 | |
| 375 | */ | |
| 376 | int rv770_init(struct radeon_device *rdev); | |
| 377 | void rv770_fini(struct radeon_device *rdev); | |
| 378 | int rv770_suspend(struct radeon_device *rdev); | |
| 379 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 DV |
380 | void rv770_pm_misc(struct radeon_device *rdev); |
| 381 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 382 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
| 383 | void r700_cp_stop(struct radeon_device *rdev); | |
| 384 | void r700_cp_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 385 | |
| bcc1c2a1 AD |
386 | /* |
| 387 | * evergreen | |
| 388 | */ | |
| 3574dda4 DV |
389 | struct evergreen_mc_save { |
| 390 | u32 vga_control[6]; | |
| 391 | u32 vga_render_control; | |
| 392 | u32 vga_hdp_control; | |
| 393 | u32 crtc_control[6]; | |
| 394 | }; | |
| 0fcdb61e | 395 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
396 | int evergreen_init(struct radeon_device *rdev); |
| 397 | void evergreen_fini(struct radeon_device *rdev); | |
| 398 | int evergreen_suspend(struct radeon_device *rdev); | |
| 399 | int evergreen_resume(struct radeon_device *rdev); | |
| 225758d8 | 400 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev); |
| a2d07b74 | 401 | int evergreen_asic_reset(struct radeon_device *rdev); |
| bcc1c2a1 | 402 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 403 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
404 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 405 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 406 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 407 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 408 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
409 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 410 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 411 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 412 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
413 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 414 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 415 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 416 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 6f34be50 AD |
417 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 418 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 419 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3574dda4 DV |
420 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 421 | int evergreen_blit_init(struct radeon_device *rdev); | |
| 4546b2c1 | 422 | |
| e3487629 AD |
423 | /* |
| 424 | * cayman | |
| 425 | */ | |
| 426 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 427 | int cayman_init(struct radeon_device *rdev); | |
| 428 | void cayman_fini(struct radeon_device *rdev); | |
| 429 | int cayman_suspend(struct radeon_device *rdev); | |
| 430 | int cayman_resume(struct radeon_device *rdev); | |
| 431 | bool cayman_gpu_is_lockup(struct radeon_device *rdev); | |
| 432 | int cayman_asic_reset(struct radeon_device *rdev); | |
| 45f9a39b | 433 | |
| 771fe6b9 | 434 | #endif |