[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_ASIC_H__
#define __RADEON_ASIC_H__

/*
 * common functions
 */
uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);

uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);

/*
 * r100,rv100,rs100,rv200,rs200
 */
struct r100_mc_save {
	u32	GENMO_WT;
	u32	CRTC_EXT_CNTL;
	u32	CRTC_GEN_CNTL;
	u32	CRTC2_GEN_CNTL;
	u32	CUR_OFFSET;
	u32	CUR2_OFFSET;
};
int r100_init(struct radeon_device *rdev);
void r100_fini(struct radeon_device *rdev);
int r100_suspend(struct radeon_device *rdev);
int r100_resume(struct radeon_device *rdev);
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void r100_vga_set_state(struct radeon_device *rdev, bool state);
bool r100_gpu_is_lockup(struct radeon_device *rdev);
int r100_asic_reset(struct radeon_device *rdev);
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
void r100_cp_commit(struct radeon_device *rdev);
void r100_ring_start(struct radeon_device *rdev);
int r100_irq_set(struct radeon_device *rdev);
int r100_irq_process(struct radeon_device *rdev);
void r100_fence_ring_emit(struct radeon_device *rdev,
			  struct radeon_fence *fence);
int r100_cs_parse(struct radeon_cs_parser *p);
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
int r100_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset,
		   uint64_t dst_offset,
		   unsigned num_pages,
		   struct radeon_fence *fence);
int r100_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size);
void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
void r100_bandwidth_update(struct radeon_device *rdev);
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
int r100_ring_test(struct radeon_device *rdev);
void r100_hpd_init(struct radeon_device *rdev);
void r100_hpd_fini(struct radeon_device *rdev);
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r100_hpd_set_polarity(struct radeon_device *rdev,
			   enum radeon_hpd_id hpd);
int r100_debugfs_rbbm_init(struct radeon_device *rdev);
int r100_debugfs_cp_init(struct radeon_device *rdev);
void r100_cp_disable(struct radeon_device *rdev);
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
void r100_cp_fini(struct radeon_device *rdev);
int r100_pci_gart_init(struct radeon_device *rdev);
void r100_pci_gart_fini(struct radeon_device *rdev);
int r100_pci_gart_enable(struct radeon_device *rdev);
void r100_pci_gart_disable(struct radeon_device *rdev);
int r100_debugfs_mc_info_init(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
void r100_ib_fini(struct radeon_device *rdev);
int r100_ib_init(struct radeon_device *rdev);
void r100_irq_disable(struct radeon_device *rdev);
void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
void r100_vram_init_sizes(struct radeon_device *rdev);
void r100_wb_disable(struct radeon_device *rdev);
void r100_wb_fini(struct radeon_device *rdev);
int r100_wb_init(struct radeon_device *rdev);
int r100_cp_reset(struct radeon_device *rdev);
void r100_vga_render_disable(struct radeon_device *rdev);
int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
					 struct radeon_cs_packet *pkt,
					 struct radeon_bo *robj);
int r100_cs_parse_packet0(struct radeon_cs_parser *p,
			  struct radeon_cs_packet *pkt,
			  const unsigned *auth, unsigned n,
			  radeon_packet0_check_t check);
int r100_cs_packet_parse(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt,
			 unsigned idx);
void r100_enable_bm(struct radeon_device *rdev);
void r100_set_common_regs(struct radeon_device *rdev);
void r100_bm_disable(struct radeon_device *rdev);
/*
 * r200,rv250,rs300,rv280
 */
extern int r200_copy_dma(struct radeon_device *rdev,
			uint64_t src_offset,
			uint64_t dst_offset,
			unsigned num_pages,
			 struct radeon_fence *fence);

/*
 * r300,r350,rv350,rv380
 */
extern int r300_init(struct radeon_device *rdev);
extern void r300_fini(struct radeon_device *rdev);
extern int r300_suspend(struct radeon_device *rdev);
extern int r300_resume(struct radeon_device *rdev);
extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
extern int r300_asic_reset(struct radeon_device *rdev);
extern void r300_ring_start(struct radeon_device *rdev);
extern void r300_fence_ring_emit(struct radeon_device *rdev,
				struct radeon_fence *fence);
extern int r300_cs_parse(struct radeon_cs_parser *p);
extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
extern int rv370_get_pcie_lanes(struct radeon_device *rdev);

/*
 * r420,r423,rv410
 */
extern int r420_init(struct radeon_device *rdev);
extern void r420_fini(struct radeon_device *rdev);
extern int r420_suspend(struct radeon_device *rdev);
extern int r420_resume(struct radeon_device *rdev);

/*
 * rs400,rs480
 */
extern int rs400_init(struct radeon_device *rdev);
extern void rs400_fini(struct radeon_device *rdev);
extern int rs400_suspend(struct radeon_device *rdev);
extern int rs400_resume(struct radeon_device *rdev);
void rs400_gart_tlb_flush(struct radeon_device *rdev);
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

/*
 * rs600.
 */
extern int rs600_asic_reset(struct radeon_device *rdev);
extern int rs600_init(struct radeon_device *rdev);
extern void rs600_fini(struct radeon_device *rdev);
extern int rs600_suspend(struct radeon_device *rdev);
extern int rs600_resume(struct radeon_device *rdev);
int rs600_irq_set(struct radeon_device *rdev);
int rs600_irq_process(struct radeon_device *rdev);
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
void rs600_gart_tlb_flush(struct radeon_device *rdev);
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rs600_bandwidth_update(struct radeon_device *rdev);
void rs600_hpd_init(struct radeon_device *rdev);
void rs600_hpd_fini(struct radeon_device *rdev);
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void rs600_hpd_set_polarity(struct radeon_device *rdev,
			    enum radeon_hpd_id hpd);

/*
 * rs690,rs740
 */
int rs690_init(struct radeon_device *rdev);
void rs690_fini(struct radeon_device *rdev);
int rs690_resume(struct radeon_device *rdev);
int rs690_suspend(struct radeon_device *rdev);
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rs690_bandwidth_update(struct radeon_device *rdev);

/*
 * rv515
 */
int rv515_init(struct radeon_device *rdev);
void rv515_fini(struct radeon_device *rdev);
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rv515_ring_start(struct radeon_device *rdev);
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rv515_bandwidth_update(struct radeon_device *rdev);
int rv515_resume(struct radeon_device *rdev);
int rv515_suspend(struct radeon_device *rdev);

/*
 * r520,rv530,rv560,rv570,r580
 */
int r520_init(struct radeon_device *rdev);
int r520_resume(struct radeon_device *rdev);

/*
 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 */
int r600_init(struct radeon_device *rdev);
void r600_fini(struct radeon_device *rdev);
int r600_suspend(struct radeon_device *rdev);
int r600_resume(struct radeon_device *rdev);
void r600_vga_set_state(struct radeon_device *rdev, bool state);
int r600_wb_init(struct radeon_device *rdev);
void r600_wb_fini(struct radeon_device *rdev);
void r600_cp_commit(struct radeon_device *rdev);
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
int r600_cs_parse(struct radeon_cs_parser *p);
void r600_fence_ring_emit(struct radeon_device *rdev,
			  struct radeon_fence *fence);
int r600_copy_dma(struct radeon_device *rdev,
		  uint64_t src_offset,
		  uint64_t dst_offset,
		  unsigned num_pages,
		  struct radeon_fence *fence);
int r600_irq_process(struct radeon_device *rdev);
int r600_irq_set(struct radeon_device *rdev);
bool r600_gpu_is_lockup(struct radeon_device *rdev);
int r600_asic_reset(struct radeon_device *rdev);
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size);
void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
int r600_ring_test(struct radeon_device *rdev);
int r600_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset, uint64_t dst_offset,
		   unsigned num_pages, struct radeon_fence *fence);
void r600_hpd_init(struct radeon_device *rdev);
void r600_hpd_fini(struct radeon_device *rdev);
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r600_hpd_set_polarity(struct radeon_device *rdev,
			   enum radeon_hpd_id hpd);
extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);

/*
 * rv770,rv730,rv710,rv740
 */
int rv770_init(struct radeon_device *rdev);
void rv770_fini(struct radeon_device *rdev);
int rv770_suspend(struct radeon_device *rdev);
int rv770_resume(struct radeon_device *rdev);

/*
 * evergreen
 */
int evergreen_init(struct radeon_device *rdev);
void evergreen_fini(struct radeon_device *rdev);
int evergreen_suspend(struct radeon_device *rdev);
int evergreen_resume(struct radeon_device *rdev);
bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
int evergreen_asic_reset(struct radeon_device *rdev);
void evergreen_bandwidth_update(struct radeon_device *rdev);
void evergreen_hpd_init(struct radeon_device *rdev);
void evergreen_hpd_fini(struct radeon_device *rdev);
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void evergreen_hpd_set_polarity(struct radeon_device *rdev,
				enum radeon_hpd_id hpd);
#endif
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#ifndef __RADEON_ASIC_H__
	29	#define __RADEON_ASIC_H__
	30
	31	/*
	32	* common functions
	33	*/
7433874e	34	uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
771fe6b9	35	void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
5ea597f3	36	uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
771fe6b9 JG	37	void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
771fe6b9 JG	38
7433874e	39	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
771fe6b9	40	void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
7433874e	41	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
771fe6b9 JG	42	void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
	43	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
	44
	45	/*
44ca7478	46	* r100,rv100,rs100,rv200,rs200
771fe6b9	47	*/
2b497502 DV	48	struct r100_mc_save {
	49	u32 GENMO_WT;
	50	u32 CRTC_EXT_CNTL;
	51	u32 CRTC_GEN_CNTL;
	52	u32 CRTC2_GEN_CNTL;
	53	u32 CUR_OFFSET;
	54	u32 CUR2_OFFSET;
	55	};
	56	int r100_init(struct radeon_device *rdev);
	57	void r100_fini(struct radeon_device *rdev);
	58	int r100_suspend(struct radeon_device *rdev);
	59	int r100_resume(struct radeon_device *rdev);
771fe6b9 JG	60	uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	61	void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
28d52043	62	void r100_vga_set_state(struct radeon_device *rdev, bool state);
225758d8	63	bool r100_gpu_is_lockup(struct radeon_device *rdev);
a2d07b74	64	int r100_asic_reset(struct radeon_device *rdev);
7ed220d7	65	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9 JG	66	void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9 JG	67	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
3ce0a23d	68	void r100_cp_commit(struct radeon_device *rdev);
771fe6b9 JG	69	void r100_ring_start(struct radeon_device *rdev);
	70	int r100_irq_set(struct radeon_device *rdev);
	71	int r100_irq_process(struct radeon_device *rdev);
	72	void r100_fence_ring_emit(struct radeon_device *rdev,
	73	struct radeon_fence *fence);
	74	int r100_cs_parse(struct radeon_cs_parser *p);
	75	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	76	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
	77	int r100_copy_blit(struct radeon_device *rdev,
	78	uint64_t src_offset,
	79	uint64_t dst_offset,
	80	unsigned num_pages,
	81	struct radeon_fence *fence);
e024e110 DA	82	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
	83	uint32_t tiling_flags, uint32_t pitch,
	84	uint32_t offset, uint32_t obj_size);
9479c54f	85	void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
c93bb85b	86	void r100_bandwidth_update(struct radeon_device *rdev);
3ce0a23d	87	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
3ce0a23d	88	int r100_ring_test(struct radeon_device *rdev);
429770b3 AD	89	void r100_hpd_init(struct radeon_device *rdev);
	90	void r100_hpd_fini(struct radeon_device *rdev);
	91	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	92	void r100_hpd_set_polarity(struct radeon_device *rdev,
	93	enum radeon_hpd_id hpd);
2b497502 DV	94	int r100_debugfs_rbbm_init(struct radeon_device *rdev);
	95	int r100_debugfs_cp_init(struct radeon_device *rdev);
	96	void r100_cp_disable(struct radeon_device *rdev);
	97	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
	98	void r100_cp_fini(struct radeon_device *rdev);
	99	int r100_pci_gart_init(struct radeon_device *rdev);
	100	void r100_pci_gart_fini(struct radeon_device *rdev);
	101	int r100_pci_gart_enable(struct radeon_device *rdev);
	102	void r100_pci_gart_disable(struct radeon_device *rdev);
	103	int r100_debugfs_mc_info_init(struct radeon_device *rdev);
	104	int r100_gui_wait_for_idle(struct radeon_device *rdev);
	105	void r100_ib_fini(struct radeon_device *rdev);
	106	int r100_ib_init(struct radeon_device *rdev);
	107	void r100_irq_disable(struct radeon_device *rdev);
	108	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save);
	109	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save);
	110	void r100_vram_init_sizes(struct radeon_device *rdev);
	111	void r100_wb_disable(struct radeon_device *rdev);
	112	void r100_wb_fini(struct radeon_device *rdev);
	113	int r100_wb_init(struct radeon_device *rdev);
2b497502 DV	114	int r100_cp_reset(struct radeon_device *rdev);
	115	void r100_vga_render_disable(struct radeon_device *rdev);
	116	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
	117	struct radeon_cs_packet *pkt,
	118	struct radeon_bo *robj);
	119	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
	120	struct radeon_cs_packet *pkt,
	121	const unsigned *auth, unsigned n,
	122	radeon_packet0_check_t check);
	123	int r100_cs_packet_parse(struct radeon_cs_parser *p,
	124	struct radeon_cs_packet *pkt,
	125	unsigned idx);
	126	void r100_enable_bm(struct radeon_device *rdev);
	127	void r100_set_common_regs(struct radeon_device *rdev);
90aca4d2	128	void r100_bm_disable(struct radeon_device *rdev);
44ca7478 PN	129	/*
	130	* r200,rv250,rs300,rv280
	131	*/
	132	extern int r200_copy_dma(struct radeon_device *rdev,
	133	uint64_t src_offset,
	134	uint64_t dst_offset,
	135	unsigned num_pages,
225758d8	136	struct radeon_fence *fence);
771fe6b9 JG	137
	138	/*
	139	* r300,r350,rv350,rv380
	140	*/
207bf9e9 JG	141	extern int r300_init(struct radeon_device *rdev);
	142	extern void r300_fini(struct radeon_device *rdev);
	143	extern int r300_suspend(struct radeon_device *rdev);
	144	extern int r300_resume(struct radeon_device *rdev);
225758d8	145	extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
a2d07b74	146	extern int r300_asic_reset(struct radeon_device *rdev);
207bf9e9 JG	147	extern void r300_ring_start(struct radeon_device *rdev);
	148	extern void r300_fence_ring_emit(struct radeon_device *rdev,
	149	struct radeon_fence *fence);
	150	extern int r300_cs_parse(struct radeon_cs_parser *p);
	151	extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
	152	extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	153	extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
	154	extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	155	extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
c836a412	156	extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
44ca7478	157
771fe6b9 JG	158	/*
	159	* r420,r423,rv410
	160	*/
9f022ddf JG	161	extern int r420_init(struct radeon_device *rdev);
	162	extern void r420_fini(struct radeon_device *rdev);
	163	extern int r420_suspend(struct radeon_device *rdev);
	164	extern int r420_resume(struct radeon_device *rdev);
771fe6b9 JG	165
	166	/*
	167	* rs400,rs480
	168	*/
ca6ffc64 JG	169	extern int rs400_init(struct radeon_device *rdev);
	170	extern void rs400_fini(struct radeon_device *rdev);
	171	extern int rs400_suspend(struct radeon_device *rdev);
	172	extern int rs400_resume(struct radeon_device *rdev);
771fe6b9 JG	173	void rs400_gart_tlb_flush(struct radeon_device *rdev);
	174	int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	175	uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	176	void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
771fe6b9 JG	177
	178	/*
	179	* rs600.
	180	*/
90aca4d2	181	extern int rs600_asic_reset(struct radeon_device *rdev);
c010f800 JG	182	extern int rs600_init(struct radeon_device *rdev);
	183	extern void rs600_fini(struct radeon_device *rdev);
	184	extern int rs600_suspend(struct radeon_device *rdev);
	185	extern int rs600_resume(struct radeon_device *rdev);
771fe6b9	186	int rs600_irq_set(struct radeon_device *rdev);
7ed220d7 MD	187	int rs600_irq_process(struct radeon_device *rdev);
7ed220d7 MD	188	u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9 JG	189	void rs600_gart_tlb_flush(struct radeon_device *rdev);
	190	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	191	uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	192	void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	193	void rs600_bandwidth_update(struct radeon_device *rdev);
429770b3 AD	194	void rs600_hpd_init(struct radeon_device *rdev);
	195	void rs600_hpd_fini(struct radeon_device *rdev);
	196	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	197	void rs600_hpd_set_polarity(struct radeon_device *rdev,
	198	enum radeon_hpd_id hpd);
	199
771fe6b9 JG	200	/*
	201	* rs690,rs740
	202	*/
3bc68535 JG	203	int rs690_init(struct radeon_device *rdev);
	204	void rs690_fini(struct radeon_device *rdev);
	205	int rs690_resume(struct radeon_device *rdev);
	206	int rs690_suspend(struct radeon_device *rdev);
771fe6b9 JG	207	uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	208	void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	209	void rs690_bandwidth_update(struct radeon_device *rdev);
771fe6b9 JG	210
	211	/*
	212	* rv515
	213	*/
068a117c	214	int rv515_init(struct radeon_device *rdev);
d39c3b89	215	void rv515_fini(struct radeon_device *rdev);
771fe6b9 JG	216	uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	217	void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	218	void rv515_ring_start(struct radeon_device *rdev);
	219	uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
	220	void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	221	void rv515_bandwidth_update(struct radeon_device *rdev);
d39c3b89 JG	222	int rv515_resume(struct radeon_device *rdev);
d39c3b89 JG	223	int rv515_suspend(struct radeon_device *rdev);
771fe6b9 JG	224
	225	/*
	226	* r520,rv530,rv560,rv570,r580
	227	*/
d39c3b89	228	int r520_init(struct radeon_device *rdev);
f0ed1f65	229	int r520_resume(struct radeon_device *rdev);
771fe6b9 JG	230
771fe6b9 JG	231	/*
3ce0a23d	232	* r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
771fe6b9	233	*/
3ce0a23d JG	234	int r600_init(struct radeon_device *rdev);
	235	void r600_fini(struct radeon_device *rdev);
	236	int r600_suspend(struct radeon_device *rdev);
	237	int r600_resume(struct radeon_device *rdev);
28d52043	238	void r600_vga_set_state(struct radeon_device *rdev, bool state);
3ce0a23d JG	239	int r600_wb_init(struct radeon_device *rdev);
	240	void r600_wb_fini(struct radeon_device *rdev);
	241	void r600_cp_commit(struct radeon_device *rdev);
	242	void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9 JG	243	uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	244	void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
3ce0a23d JG	245	int r600_cs_parse(struct radeon_cs_parser *p);
	246	void r600_fence_ring_emit(struct radeon_device *rdev,
	247	struct radeon_fence *fence);
	248	int r600_copy_dma(struct radeon_device *rdev,
	249	uint64_t src_offset,
	250	uint64_t dst_offset,
	251	unsigned num_pages,
	252	struct radeon_fence *fence);
	253	int r600_irq_process(struct radeon_device *rdev);
	254	int r600_irq_set(struct radeon_device *rdev);
225758d8	255	bool r600_gpu_is_lockup(struct radeon_device *rdev);
a2d07b74	256	int r600_asic_reset(struct radeon_device *rdev);
3ce0a23d JG	257	int r600_set_surface_reg(struct radeon_device *rdev, int reg,
	258	uint32_t tiling_flags, uint32_t pitch,
	259	uint32_t offset, uint32_t obj_size);
9479c54f	260	void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
3ce0a23d	261	void r600_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
3ce0a23d JG	262	int r600_ring_test(struct radeon_device *rdev);
	263	int r600_copy_blit(struct radeon_device *rdev,
	264	uint64_t src_offset, uint64_t dst_offset,
	265	unsigned num_pages, struct radeon_fence *fence);
429770b3 AD	266	void r600_hpd_init(struct radeon_device *rdev);
	267	void r600_hpd_fini(struct radeon_device *rdev);
	268	bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	269	void r600_hpd_set_polarity(struct radeon_device *rdev,
	270	enum radeon_hpd_id hpd);
062b389c	271	extern void r600_ioctl_wait_idle(struct radeon_device rdev, struct radeon_bo bo);
3ce0a23d	272
3ce0a23d JG	273	/*
	274	* rv770,rv730,rv710,rv740
	275	*/
	276	int rv770_init(struct radeon_device *rdev);
	277	void rv770_fini(struct radeon_device *rdev);
	278	int rv770_suspend(struct radeon_device *rdev);
	279	int rv770_resume(struct radeon_device *rdev);
3ce0a23d	280
bcc1c2a1 AD	281	/*
	282	* evergreen
	283	*/
	284	int evergreen_init(struct radeon_device *rdev);
	285	void evergreen_fini(struct radeon_device *rdev);
	286	int evergreen_suspend(struct radeon_device *rdev);
	287	int evergreen_resume(struct radeon_device *rdev);
225758d8	288	bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
a2d07b74	289	int evergreen_asic_reset(struct radeon_device *rdev);
bcc1c2a1 AD	290	void evergreen_bandwidth_update(struct radeon_device *rdev);
	291	void evergreen_hpd_init(struct radeon_device *rdev);
	292	void evergreen_hpd_fini(struct radeon_device *rdev);
	293	bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	294	void evergreen_hpd_set_polarity(struct radeon_device *rdev,
	295	enum radeon_hpd_id hpd);
771fe6b9	296	#endif