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drm/radeon/kms: r600 CS parser fixes
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30
AD		 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
771fe6b9
JG		 52
53/* from radeon_legacy_encoder.c */
54extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62};
63
eed45b30
AD		 64static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
771fe6b9 66{
771fe6b9 67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 72 uint16_t data_offset, size;
73 int i, num_indices;
771fe6b9
JG		 74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
95beb690 78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
95beb690
AD		 81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
83
84 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 85 gpio = &i2c_info->asGPIO_Info[i];
86
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
107 else
108 i2c.hw_capable = false;
109
110 if (gpio->sucI2cId.ucAccess == 0xa0)
111 i2c.mm_i2c = true;
112 else
113 i2c.mm_i2c = false;
114
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116
117 i2c.valid = true;
118 break;
119 }
d3f420d1
AD		 120 }
121 }
771fe6b9
JG		 122
123 return i2c;
124}
125
eed45b30
AD		 126static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 u8 id)
128{
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 struct radeon_gpio_rec gpio;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
132 struct _ATOM_GPIO_PIN_LUT *gpio_info;
133 ATOM_GPIO_PIN_ASSIGNMENT *pin;
134 u16 data_offset, size;
135 int i, num_indices;
136
137 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
138 gpio.valid = false;
139
a084e6ee
AD		 140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 142
a084e6ee
AD		 143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 145
a084e6ee
AD		 146 for (i = 0; i < num_indices; i++) {
147 pin = &gpio_info->asGPIO_Pin[i];
148 if (id == pin->ucGPIO_ID) {
149 gpio.id = pin->ucGPIO_ID;
150 gpio.reg = pin->usGpioPin_AIndex * 4;
151 gpio.mask = (1 << pin->ucGpioPinBitShift);
152 gpio.valid = true;
153 break;
154 }
eed45b30
AD		 155 }
156 }
157
158 return gpio;
159}
160
161static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
162 struct radeon_gpio_rec *gpio)
163{
164 struct radeon_hpd hpd;
bcc1c2a1
AD		 165 u32 reg;
166
167 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A;
169 else
170 reg = AVIVO_DC_GPIO_HPD_A;
171
eed45b30 172 hpd.gpio = *gpio;
bcc1c2a1 173 if (gpio->reg == reg) {
eed45b30
AD		 174 switch(gpio->mask) {
175 case (1 << 0):
176 hpd.hpd = RADEON_HPD_1;
177 break;
178 case (1 << 8):
179 hpd.hpd = RADEON_HPD_2;
180 break;
181 case (1 << 16):
182 hpd.hpd = RADEON_HPD_3;
183 break;
184 case (1 << 24):
185 hpd.hpd = RADEON_HPD_4;
186 break;
187 case (1 << 26):
188 hpd.hpd = RADEON_HPD_5;
189 break;
190 case (1 << 28):
191 hpd.hpd = RADEON_HPD_6;
192 break;
193 default:
194 hpd.hpd = RADEON_HPD_NONE;
195 break;
196 }
197 } else
198 hpd.hpd = RADEON_HPD_NONE;
199 return hpd;
200}
201
771fe6b9
JG		 202static bool radeon_atom_apply_quirks(struct drm_device *dev,
203 uint32_t supported_device,
204 int *connector_type,
848577ee 205 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 206 uint16_t *line_mux,
207 struct radeon_hpd *hpd)
771fe6b9
JG		 208{
209
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) &&
212 (dev->pdev->subsystem_vendor == 0x1043) &&
213 (dev->pdev->subsystem_device == 0x826d)) {
214 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
215 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
216 *connector_type = DRM_MODE_CONNECTOR_DVID;
217 }
218
c86a9038
AD		 219 /* Asrock RS600 board lists the DVI port as HDMI */
220 if ((dev->pdev->device == 0x7941) &&
221 (dev->pdev->subsystem_vendor == 0x1849) &&
222 (dev->pdev->subsystem_device == 0x7941)) {
223 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
224 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
225 *connector_type = DRM_MODE_CONNECTOR_DVID;
226 }
227
771fe6b9
JG		 228 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
229 if ((dev->pdev->device == 0x7941) &&
230 (dev->pdev->subsystem_vendor == 0x147b) &&
231 (dev->pdev->subsystem_device == 0x2412)) {
232 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
233 return false;
234 }
235
236 /* Falcon NW laptop lists vga ddc line for LVDS */
237 if ((dev->pdev->device == 0x5653) &&
238 (dev->pdev->subsystem_vendor == 0x1462) &&
239 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 240 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 241 i2c_bus->valid = false;
848577ee
AD		 242 *line_mux = 53;
243 }
771fe6b9
JG		 244 }
245
4e3f9b78
AD		 246 /* HIS X1300 is DVI+VGA, not DVI+DVI */
247 if ((dev->pdev->device == 0x7146) &&
248 (dev->pdev->subsystem_vendor == 0x17af) &&
249 (dev->pdev->subsystem_device == 0x2058)) {
250 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
251 return false;
252 }
253
aa1a750e
DA		 254 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
255 if ((dev->pdev->device == 0x7142) &&
256 (dev->pdev->subsystem_vendor == 0x1458) &&
257 (dev->pdev->subsystem_device == 0x2134)) {
258 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
259 return false;
260 }
261
262
771fe6b9
JG		 263 /* Funky macbooks */
264 if ((dev->pdev->device == 0x71C5) &&
265 (dev->pdev->subsystem_vendor == 0x106b) &&
266 (dev->pdev->subsystem_device == 0x0080)) {
267 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
268 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
269 return false;
e1e8a5dd
AD		 270 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
271 *line_mux = 0x90;
771fe6b9
JG		 272 }
273
771fe6b9
JG		 274 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
275 if ((dev->pdev->device == 0x9598) &&
276 (dev->pdev->subsystem_vendor == 0x1043) &&
277 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 278 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 279 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 280 }
281 }
282
e153b70b
AD		 283 /* ASUS HD 3600 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x9598) &&
285 (dev->pdev->subsystem_vendor == 0x1043) &&
286 (dev->pdev->subsystem_device == 0x01e4)) {
287 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
288 *connector_type = DRM_MODE_CONNECTOR_DVII;
289 }
290 }
291
705af9c7
AD		 292 /* ASUS HD 3450 board lists the DVI port as HDMI */
293 if ((dev->pdev->device == 0x95C5) &&
294 (dev->pdev->subsystem_vendor == 0x1043) &&
295 (dev->pdev->subsystem_device == 0x01e2)) {
296 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 297 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 298 }
299 }
300
705af9c7
AD		 301 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
302 * HDMI + VGA reporting as HDMI
303 */
304 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
305 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
306 *connector_type = DRM_MODE_CONNECTOR_VGA;
307 *line_mux = 0;
308 }
309 }
310
3e5f8ff3
AD		 311 /* Acer laptop reports DVI-D as DVI-I */
312 if ((dev->pdev->device == 0x95c4) &&
313 (dev->pdev->subsystem_vendor == 0x1025) &&
314 (dev->pdev->subsystem_device == 0x013c)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
316 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 }
319
efa8450f
DA		 320 /* XFX Pine Group device rv730 reports no VGA DDC lines
321 * even though they are wired up to record 0x93
322 */
323 if ((dev->pdev->device == 0x9498) &&
324 (dev->pdev->subsystem_vendor == 0x1682) &&
325 (dev->pdev->subsystem_device == 0x2452)) {
326 struct radeon_device *rdev = dev->dev_private;
327 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
328 }
771fe6b9
JG		 329 return true;
330}
331
332const int supported_devices_connector_convert[] = {
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_VGA,
335 DRM_MODE_CONNECTOR_DVII,
336 DRM_MODE_CONNECTOR_DVID,
337 DRM_MODE_CONNECTOR_DVIA,
338 DRM_MODE_CONNECTOR_SVIDEO,
339 DRM_MODE_CONNECTOR_Composite,
340 DRM_MODE_CONNECTOR_LVDS,
341 DRM_MODE_CONNECTOR_Unknown,
342 DRM_MODE_CONNECTOR_Unknown,
343 DRM_MODE_CONNECTOR_HDMIA,
344 DRM_MODE_CONNECTOR_HDMIB,
345 DRM_MODE_CONNECTOR_Unknown,
346 DRM_MODE_CONNECTOR_Unknown,
347 DRM_MODE_CONNECTOR_9PinDIN,
348 DRM_MODE_CONNECTOR_DisplayPort
349};
350
b75fad06
AD		 351const uint16_t supported_devices_connector_object_id_convert[] = {
352 CONNECTOR_OBJECT_ID_NONE,
353 CONNECTOR_OBJECT_ID_VGA,
354 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
355 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
356 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
357 CONNECTOR_OBJECT_ID_COMPOSITE,
358 CONNECTOR_OBJECT_ID_SVIDEO,
359 CONNECTOR_OBJECT_ID_LVDS,
360 CONNECTOR_OBJECT_ID_9PIN_DIN,
361 CONNECTOR_OBJECT_ID_9PIN_DIN,
362 CONNECTOR_OBJECT_ID_DISPLAYPORT,
363 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
364 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
365 CONNECTOR_OBJECT_ID_SVIDEO
366};
367
771fe6b9
JG		 368const int object_connector_convert[] = {
369 DRM_MODE_CONNECTOR_Unknown,
370 DRM_MODE_CONNECTOR_DVII,
371 DRM_MODE_CONNECTOR_DVII,
372 DRM_MODE_CONNECTOR_DVID,
373 DRM_MODE_CONNECTOR_DVID,
374 DRM_MODE_CONNECTOR_VGA,
375 DRM_MODE_CONNECTOR_Composite,
376 DRM_MODE_CONNECTOR_SVIDEO,
377 DRM_MODE_CONNECTOR_Unknown,
705af9c7 378 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 379 DRM_MODE_CONNECTOR_9PinDIN,
380 DRM_MODE_CONNECTOR_Unknown,
381 DRM_MODE_CONNECTOR_HDMIA,
382 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 383 DRM_MODE_CONNECTOR_LVDS,
384 DRM_MODE_CONNECTOR_9PinDIN,
385 DRM_MODE_CONNECTOR_Unknown,
386 DRM_MODE_CONNECTOR_Unknown,
387 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 388 DRM_MODE_CONNECTOR_DisplayPort,
389 DRM_MODE_CONNECTOR_eDP,
390 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 391};
392
393bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
394{
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_mode_info *mode_info = &rdev->mode_info;
397 struct atom_context *ctx = mode_info->atom_context;
398 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 399 u16 size, data_offset;
400 u8 frev, crev;
771fe6b9
JG		 401 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
402 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
403 ATOM_OBJECT_HEADER *obj_header;
404 int i, j, path_size, device_support;
405 int connector_type;
eed45b30 406 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 407 bool linkb;
408 struct radeon_i2c_bus_rec ddc_bus;
eed45b30
AD		 409 struct radeon_gpio_rec gpio;
410 struct radeon_hpd hpd;
411
a084e6ee 412 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 413 return false;
414
415 if (crev < 2)
416 return false;
417
418 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
419 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
420 (ctx->bios + data_offset +
421 le16_to_cpu(obj_header->usDisplayPathTableOffset));
422 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
423 (ctx->bios + data_offset +
424 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
425 device_support = le16_to_cpu(obj_header->usDeviceSupport);
426
427 path_size = 0;
428 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
429 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
430 ATOM_DISPLAY_OBJECT_PATH *path;
431 addr += path_size;
432 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
433 path_size += le16_to_cpu(path->usSize);
434 linkb = false;
771fe6b9
JG		 435 if (device_support & le16_to_cpu(path->usDeviceTag)) {
436 uint8_t con_obj_id, con_obj_num, con_obj_type;
437
438 con_obj_id =
439 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
440 >> OBJECT_ID_SHIFT;
441 con_obj_num =
442 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
443 >> ENUM_ID_SHIFT;
444 con_obj_type =
445 (le16_to_cpu(path->usConnObjectId) &
446 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
447
4bbd4973
DA		 448 /* TODO CV support */
449 if (le16_to_cpu(path->usDeviceTag) ==
450 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 451 continue;
452
ee59f2b4
AD		 453 /* IGP chips */
454 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 455 (con_obj_id ==
456 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
457 uint16_t igp_offset = 0;
458 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
459
460 index =
461 GetIndexIntoMasterTable(DATA,
462 IntegratedSystemInfo);
463
a084e6ee
AD		 464 if (atom_parse_data_header(ctx, index, &size, &frev,
465 &crev, &igp_offset)) {
466
467 if (crev >= 2) {
468 igp_obj =
469 (ATOM_INTEGRATED_SYSTEM_INFO_V2
470 *) (ctx->bios + igp_offset);
471
472 if (igp_obj) {
473 uint32_t slot_config, ct;
474
475 if (con_obj_num == 1)
476 slot_config =
477 igp_obj->
478 ulDDISlot1Config;
479 else
480 slot_config =
481 igp_obj->
482 ulDDISlot2Config;
483
484 ct = (slot_config >> 16) & 0xff;
485 connector_type =
486 object_connector_convert
487 [ct];
488 connector_object_id = ct;
489 igp_lane_info =
490 slot_config & 0xffff;
491 } else
492 continue;
771fe6b9
JG		 493 } else
494 continue;
a084e6ee
AD		 495 } else {
496 igp_lane_info = 0;
497 connector_type =
498 object_connector_convert[con_obj_id];
499 connector_object_id = con_obj_id;
500 }
771fe6b9
JG		 501 } else {
502 igp_lane_info = 0;
503 connector_type =
504 object_connector_convert[con_obj_id];
b75fad06 505 connector_object_id = con_obj_id;
771fe6b9
JG		 506 }
507
508 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
509 continue;
510
511 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
512 j++) {
513 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
514
515 enc_obj_id =
516 (le16_to_cpu(path->usGraphicObjIds[j]) &
517 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
518 enc_obj_num =
519 (le16_to_cpu(path->usGraphicObjIds[j]) &
520 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
521 enc_obj_type =
522 (le16_to_cpu(path->usGraphicObjIds[j]) &
523 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
524
525 /* FIXME: add support for router objects */
526 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
527 if (enc_obj_num == 2)
528 linkb = true;
529 else
530 linkb = false;
531
532 radeon_add_atom_encoder(dev,
533 enc_obj_id,
534 le16_to_cpu
535 (path->
536 usDeviceTag));
537
538 }
539 }
540
eed45b30 541 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 542 ddc_bus.valid = false;
543 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 544 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 545 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 546 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
547 if (le16_to_cpu(path->usConnObjectId) ==
548 le16_to_cpu(con_obj->asObjects[j].
549 usObjectID)) {
550 ATOM_COMMON_RECORD_HEADER
551 *record =
552 (ATOM_COMMON_RECORD_HEADER
553 *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(con_obj->
556 asObjects[j].
557 usRecordOffset));
558 ATOM_I2C_RECORD *i2c_record;
eed45b30 559 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 560 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 561
771fe6b9
JG		 562 while (record->ucRecordType > 0
563 && record->
564 ucRecordType <=
565 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 566 switch (record->ucRecordType) {
771fe6b9
JG		 567 case ATOM_I2C_RECORD_TYPE:
568 i2c_record =
eed45b30
AD		 569 (ATOM_I2C_RECORD *)
570 record;
d3f420d1
AD		 571 i2c_config =
572 (ATOM_I2C_ID_CONFIG_ACCESS *)
573 &i2c_record->sucI2cId;
eed45b30 574 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 575 i2c_config->
576 ucAccess);
eed45b30
AD		 577 break;
578 case ATOM_HPD_INT_RECORD_TYPE:
579 hpd_record =
580 (ATOM_HPD_INT_RECORD *)
581 record;
582 gpio = radeon_lookup_gpio(rdev,
583 hpd_record->ucHPDIntGPIOID);
584 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
585 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 586 break;
587 }
588 record =
589 (ATOM_COMMON_RECORD_HEADER
590 *) ((char *)record
591 +
592 record->
593 ucRecordSize);
594 }
595 break;
596 }
597 }
eed45b30 598 }
771fe6b9 599
bcc1c2a1 600 /* needed for aux chan transactions */
8e36ed00 601 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 602
705af9c7
AD		 603 conn_id = le16_to_cpu(path->usConnObjectId);
604
605 if (!radeon_atom_apply_quirks
606 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 607 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 608 continue;
609
771fe6b9 610 radeon_add_atom_connector(dev,
705af9c7 611 conn_id,
771fe6b9
JG		 612 le16_to_cpu(path->
613 usDeviceTag),
614 connector_type, &ddc_bus,
b75fad06 615 linkb, igp_lane_info,
eed45b30
AD		 616 connector_object_id,
617 &hpd);
771fe6b9
JG		 618
619 }
620 }
621
622 radeon_link_encoder_connector(dev);
623
624 return true;
625}
626
b75fad06
AD		 627static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
628 int connector_type,
629 uint16_t devices)
630{
631 struct radeon_device *rdev = dev->dev_private;
632
633 if (rdev->flags & RADEON_IS_IGP) {
634 return supported_devices_connector_object_id_convert
635 [connector_type];
636 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
637 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
638 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
639 struct radeon_mode_info *mode_info = &rdev->mode_info;
640 struct atom_context *ctx = mode_info->atom_context;
641 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
642 uint16_t size, data_offset;
643 uint8_t frev, crev;
644 ATOM_XTMDS_INFO *xtmds;
645
a084e6ee
AD		 646 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
647 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 648
a084e6ee
AD		 649 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
650 if (connector_type == DRM_MODE_CONNECTOR_DVII)
651 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
652 else
653 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
654 } else {
655 if (connector_type == DRM_MODE_CONNECTOR_DVII)
656 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
657 else
658 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
659 }
660 } else
661 return supported_devices_connector_object_id_convert
662 [connector_type];
b75fad06
AD		 663 } else {
664 return supported_devices_connector_object_id_convert
665 [connector_type];
666 }
667}
668
771fe6b9
JG		 669struct bios_connector {
670 bool valid;
705af9c7 671 uint16_t line_mux;
771fe6b9
JG		 672 uint16_t devices;
673 int connector_type;
674 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 675 struct radeon_hpd hpd;
771fe6b9
JG		 676};
677
678bool radeon_get_atom_connector_info_from_supported_devices_table(struct
679 drm_device
680 *dev)
681{
682 struct radeon_device *rdev = dev->dev_private;
683 struct radeon_mode_info *mode_info = &rdev->mode_info;
684 struct atom_context *ctx = mode_info->atom_context;
685 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
686 uint16_t size, data_offset;
687 uint8_t frev, crev;
688 uint16_t device_support;
689 uint8_t dac;
690 union atom_supported_devices *supported_devices;
eed45b30 691 int i, j, max_device;
f49d273d
PB		 692 struct bios_connector *bios_connectors;
693 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
771fe6b9 694
f49d273d
PB		 695 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
696 if (!bios_connectors)
697 return false;
698
699 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
700 &data_offset)) {
701 kfree(bios_connectors);
a084e6ee 702 return false;
f49d273d 703 }
771fe6b9
JG		 704
705 supported_devices =
706 (union atom_supported_devices *)(ctx->bios + data_offset);
707
708 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
709
eed45b30
AD		 710 if (frev > 1)
711 max_device = ATOM_MAX_SUPPORTED_DEVICE;
712 else
713 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
714
715 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 716 ATOM_CONNECTOR_INFO_I2C ci =
717 supported_devices->info.asConnInfo[i];
718
719 bios_connectors[i].valid = false;
720
721 if (!(device_support & (1 << i))) {
722 continue;
723 }
724
725 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 726 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 727 continue;
728 }
729
771fe6b9
JG		 730 bios_connectors[i].connector_type =
731 supported_devices_connector_convert[ci.sucConnectorInfo.
732 sbfAccess.
733 bfConnectorType];
734
735 if (bios_connectors[i].connector_type ==
736 DRM_MODE_CONNECTOR_Unknown)
737 continue;
738
739 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
740
d3f420d1
AD		 741 bios_connectors[i].line_mux =
742 ci.sucI2cId.ucAccess;
771fe6b9
JG		 743
744 /* give tv unique connector ids */
745 if (i == ATOM_DEVICE_TV1_INDEX) {
746 bios_connectors[i].ddc_bus.valid = false;
747 bios_connectors[i].line_mux = 50;
748 } else if (i == ATOM_DEVICE_TV2_INDEX) {
749 bios_connectors[i].ddc_bus.valid = false;
750 bios_connectors[i].line_mux = 51;
751 } else if (i == ATOM_DEVICE_CV_INDEX) {
752 bios_connectors[i].ddc_bus.valid = false;
753 bios_connectors[i].line_mux = 52;
754 } else
755 bios_connectors[i].ddc_bus =
eed45b30
AD		 756 radeon_lookup_i2c_gpio(rdev,
757 bios_connectors[i].line_mux);
758
759 if ((crev > 1) && (frev > 1)) {
760 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
761 switch (isb) {
762 case 0x4:
763 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
764 break;
765 case 0xa:
766 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
767 break;
768 default:
769 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
770 break;
771 }
772 } else {
773 if (i == ATOM_DEVICE_DFP1_INDEX)
774 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
775 else if (i == ATOM_DEVICE_DFP2_INDEX)
776 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
777 else
778 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
779 }
771fe6b9
JG		 780
781 /* Always set the connector type to VGA for CRT1/CRT2. if they are
782 * shared with a DVI port, we'll pick up the DVI connector when we
783 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
784 */
785 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
786 bios_connectors[i].connector_type =
787 DRM_MODE_CONNECTOR_VGA;
788
789 if (!radeon_atom_apply_quirks
790 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 791 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
792 &bios_connectors[i].hpd))
771fe6b9
JG		 793 continue;
794
795 bios_connectors[i].valid = true;
796 bios_connectors[i].devices = (1 << i);
797
798 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
799 radeon_add_atom_encoder(dev,
800 radeon_get_encoder_id(dev,
801 (1 << i),
802 dac),
803 (1 << i));
804 else
805 radeon_add_legacy_encoder(dev,
806 radeon_get_encoder_id(dev,
f56cd64f 807 (1 << i),
771fe6b9
JG		 808 dac),
809 (1 << i));
810 }
811
812 /* combine shared connectors */
eed45b30 813 for (i = 0; i < max_device; i++) {
771fe6b9 814 if (bios_connectors[i].valid) {
eed45b30 815 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 816 if (bios_connectors[j].valid && (i != j)) {
817 if (bios_connectors[i].line_mux ==
818 bios_connectors[j].line_mux) {
f56cd64f
AD		 819 /* make sure not to combine LVDS */
820 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
821 bios_connectors[i].line_mux = 53;
822 bios_connectors[i].ddc_bus.valid = false;
823 continue;
824 }
825 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
826 bios_connectors[j].line_mux = 53;
827 bios_connectors[j].ddc_bus.valid = false;
828 continue;
829 }
830 /* combine analog and digital for DVI-I */
831 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
832 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
833 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
834 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
835 bios_connectors[i].devices |=
836 bios_connectors[j].devices;
837 bios_connectors[i].connector_type =
838 DRM_MODE_CONNECTOR_DVII;
839 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 840 bios_connectors[i].hpd =
841 bios_connectors[j].hpd;
f56cd64f 842 bios_connectors[j].valid = false;
771fe6b9
JG		 843 }
844 }
845 }
846 }
847 }
848 }
849
850 /* add the connectors */
eed45b30 851 for (i = 0; i < max_device; i++) {
b75fad06
AD		 852 if (bios_connectors[i].valid) {
853 uint16_t connector_object_id =
854 atombios_get_connector_object_id(dev,
855 bios_connectors[i].connector_type,
856 bios_connectors[i].devices);
771fe6b9
JG		 857 radeon_add_atom_connector(dev,
858 bios_connectors[i].line_mux,
859 bios_connectors[i].devices,
860 bios_connectors[i].
861 connector_type,
862 &bios_connectors[i].ddc_bus,
b75fad06 863 false, 0,
eed45b30
AD		 864 connector_object_id,
865 &bios_connectors[i].hpd);
b75fad06 866 }
771fe6b9
JG		 867 }
868
869 radeon_link_encoder_connector(dev);
870
f49d273d 871 kfree(bios_connectors);
771fe6b9
JG		 872 return true;
873}
874
875union firmware_info {
876 ATOM_FIRMWARE_INFO info;
877 ATOM_FIRMWARE_INFO_V1_2 info_12;
878 ATOM_FIRMWARE_INFO_V1_3 info_13;
879 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 880 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 881};
882
883bool radeon_atom_get_clock_info(struct drm_device *dev)
884{
885 struct radeon_device *rdev = dev->dev_private;
886 struct radeon_mode_info *mode_info = &rdev->mode_info;
887 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
888 union firmware_info *firmware_info;
889 uint8_t frev, crev;
890 struct radeon_pll *p1pll = &rdev->clock.p1pll;
891 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 892 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 893 struct radeon_pll *spll = &rdev->clock.spll;
894 struct radeon_pll *mpll = &rdev->clock.mpll;
895 uint16_t data_offset;
896
a084e6ee
AD		 897 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
898 &frev, &crev, &data_offset)) {
899 firmware_info =
900 (union firmware_info *)(mode_info->atom_context->bios +
901 data_offset);
771fe6b9
JG		 902 /* pixel clocks */
903 p1pll->reference_freq =
904 le16_to_cpu(firmware_info->info.usReferenceClock);
905 p1pll->reference_div = 0;
906
bc293e58
MF		 907 if (crev < 2)
908 p1pll->pll_out_min =
909 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
910 else
911 p1pll->pll_out_min =
912 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 913 p1pll->pll_out_max =
914 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
915
86cb2bbf
AD		 916 if (crev >= 4) {
917 p1pll->lcd_pll_out_min =
918 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
919 if (p1pll->lcd_pll_out_min == 0)
920 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
921 p1pll->lcd_pll_out_max =
922 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
923 if (p1pll->lcd_pll_out_max == 0)
924 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
925 } else {
926 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
927 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
928 }
929
771fe6b9
JG		 930 if (p1pll->pll_out_min == 0) {
931 if (ASIC_IS_AVIVO(rdev))
932 p1pll->pll_out_min = 64800;
933 else
934 p1pll->pll_out_min = 20000;
8f552a66
AD		 935 } else if (p1pll->pll_out_min > 64800) {
936 /* Limiting the pll output range is a good thing generally as
937 * it limits the number of possible pll combinations for a given
938 * frequency presumably to the ones that work best on each card.
939 * However, certain duallink DVI monitors seem to like
940 * pll combinations that would be limited by this at least on
941 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
942 * family.
943 */
b27b6375
AD		 944 if (!radeon_new_pll)
945 p1pll->pll_out_min = 64800;
771fe6b9
JG		 946 }
947
948 p1pll->pll_in_min =
949 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
950 p1pll->pll_in_max =
951 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
952
953 *p2pll = *p1pll;
954
955 /* system clock */
956 spll->reference_freq =
957 le16_to_cpu(firmware_info->info.usReferenceClock);
958 spll->reference_div = 0;
959
960 spll->pll_out_min =
961 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
962 spll->pll_out_max =
963 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
964
965 /* ??? */
966 if (spll->pll_out_min == 0) {
967 if (ASIC_IS_AVIVO(rdev))
968 spll->pll_out_min = 64800;
969 else
970 spll->pll_out_min = 20000;
971 }
972
973 spll->pll_in_min =
974 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
975 spll->pll_in_max =
976 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
977
978 /* memory clock */
979 mpll->reference_freq =
980 le16_to_cpu(firmware_info->info.usReferenceClock);
981 mpll->reference_div = 0;
982
983 mpll->pll_out_min =
984 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
985 mpll->pll_out_max =
986 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
987
988 /* ??? */
989 if (mpll->pll_out_min == 0) {
990 if (ASIC_IS_AVIVO(rdev))
991 mpll->pll_out_min = 64800;
992 else
993 mpll->pll_out_min = 20000;
994 }
995
996 mpll->pll_in_min =
997 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
998 mpll->pll_in_max =
999 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1000
1001 rdev->clock.default_sclk =
1002 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1003 rdev->clock.default_mclk =
1004 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1005
bcc1c2a1
AD		 1006 if (ASIC_IS_DCE4(rdev)) {
1007 rdev->clock.default_dispclk =
1008 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1009 if (rdev->clock.default_dispclk == 0)
1010 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1011 rdev->clock.dp_extclk =
1012 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1013 }
1014 *dcpll = *p1pll;
1015
771fe6b9
JG		 1016 return true;
1017 }
bcc1c2a1 1018
771fe6b9
JG		 1019 return false;
1020}
1021
06b6476d
AD		 1022union igp_info {
1023 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1024 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1025};
1026
1027bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1028{
1029 struct radeon_mode_info *mode_info = &rdev->mode_info;
1030 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1031 union igp_info *igp_info;
1032 u8 frev, crev;
1033 u16 data_offset;
1034
4c70b2ea
AD		 1035 /* sideport is AMD only */
1036 if (rdev->family == CHIP_RS600)
1037 return false;
1038
a084e6ee
AD		 1039 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1040 &frev, &crev, &data_offset)) {
1041 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1042 data_offset);
06b6476d
AD		 1043 switch (crev) {
1044 case 1:
4c70b2ea
AD		 1045 if (igp_info->info.ulBootUpMemoryClock)
1046 return true;
06b6476d
AD		 1047 break;
1048 case 2:
1049 if (igp_info->info_2.ucMemoryType & 0x0f)
1050 return true;
1051 break;
1052 default:
1053 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1054 break;
1055 }
1056 }
1057 return false;
1058}
1059
445282db
DA		 1060bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1061 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1062{
1063 struct drm_device *dev = encoder->base.dev;
1064 struct radeon_device *rdev = dev->dev_private;
1065 struct radeon_mode_info *mode_info = &rdev->mode_info;
1066 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1067 uint16_t data_offset;
1068 struct _ATOM_TMDS_INFO *tmds_info;
1069 uint8_t frev, crev;
1070 uint16_t maxfreq;
1071 int i;
771fe6b9 1072
a084e6ee
AD		 1073 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1074 &frev, &crev, &data_offset)) {
1075 tmds_info =
1076 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1077 data_offset);
771fe6b9 1078
771fe6b9
JG		 1079 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1080 for (i = 0; i < 4; i++) {
1081 tmds->tmds_pll[i].freq =
1082 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1083 tmds->tmds_pll[i].value =
1084 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1085 tmds->tmds_pll[i].value |=
1086 (tmds_info->asMiscInfo[i].
1087 ucPLL_VCO_Gain & 0x3f) << 6;
1088 tmds->tmds_pll[i].value |=
1089 (tmds_info->asMiscInfo[i].
1090 ucPLL_DutyCycle & 0xf) << 12;
1091 tmds->tmds_pll[i].value |=
1092 (tmds_info->asMiscInfo[i].
1093 ucPLL_VoltageSwing & 0xf) << 16;
1094
d9fdaafb 1095 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1096 tmds->tmds_pll[i].freq,
1097 tmds->tmds_pll[i].value);
1098
1099 if (maxfreq == tmds->tmds_pll[i].freq) {
1100 tmds->tmds_pll[i].freq = 0xffffffff;
1101 break;
1102 }
1103 }
445282db 1104 return true;
771fe6b9 1105 }
445282db 1106 return false;
771fe6b9
JG		 1107}
1108
ebbe1cb9
AD		 1109static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1110 radeon_encoder
1111 *encoder,
1112 int id)
1113{
1114 struct drm_device *dev = encoder->base.dev;
1115 struct radeon_device *rdev = dev->dev_private;
1116 struct radeon_mode_info *mode_info = &rdev->mode_info;
1117 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1118 uint16_t data_offset;
1119 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1120 uint8_t frev, crev;
1121 struct radeon_atom_ss *ss = NULL;
279b215e 1122 int i;
ebbe1cb9
AD		 1123
1124 if (id > ATOM_MAX_SS_ENTRY)
1125 return NULL;
1126
a084e6ee
AD		 1127 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1128 &frev, &crev, &data_offset)) {
1129 ss_info =
1130 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1131
ebbe1cb9
AD		 1132 ss =
1133 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1134
1135 if (!ss)
1136 return NULL;
1137
279b215e
AD		 1138 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1139 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1140 ss->percentage =
1141 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1142 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1143 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1144 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1145 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1146 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1147 break;
279b215e
AD		 1148 }
1149 }
ebbe1cb9
AD		 1150 }
1151 return ss;
1152}
1153
771fe6b9
JG		 1154union lvds_info {
1155 struct _ATOM_LVDS_INFO info;
1156 struct _ATOM_LVDS_INFO_V12 info_12;
1157};
1158
1159struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1160 radeon_encoder
1161 *encoder)
1162{
1163 struct drm_device *dev = encoder->base.dev;
1164 struct radeon_device *rdev = dev->dev_private;
1165 struct radeon_mode_info *mode_info = &rdev->mode_info;
1166 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1167 uint16_t data_offset, misc;
771fe6b9
JG		 1168 union lvds_info *lvds_info;
1169 uint8_t frev, crev;
1170 struct radeon_encoder_atom_dig *lvds = NULL;
1171
a084e6ee
AD		 1172 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1173 &frev, &crev, &data_offset)) {
1174 lvds_info =
1175 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1176 lvds =
1177 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1178
1179 if (!lvds)
1180 return NULL;
1181
de2103e4 1182 lvds->native_mode.clock =
771fe6b9 1183 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1184 lvds->native_mode.hdisplay =
771fe6b9 1185 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1186 lvds->native_mode.vdisplay =
771fe6b9 1187 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1188 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1189 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1190 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1191 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1192 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1193 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1194 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1195 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1196 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1197 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1198 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1199 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1200 lvds->panel_pwr_delay =
1201 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1202 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1203
1204 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1205 if (misc & ATOM_VSYNC_POLARITY)
1206 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1207 if (misc & ATOM_HSYNC_POLARITY)
1208 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1209 if (misc & ATOM_COMPOSITESYNC)
1210 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1211 if (misc & ATOM_INTERLACE)
1212 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1213 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1214 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1215
de2103e4
AD		 1216 /* set crtc values */
1217 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1218
ebbe1cb9
AD		 1219 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1220
7c27f87d 1221 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1222 if (radeon_new_pll == 0)
1223 lvds->pll_algo = PLL_ALGO_LEGACY;
1224 else
1225 lvds->pll_algo = PLL_ALGO_NEW;
1226 } else {
1227 if (radeon_new_pll == 1)
1228 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1229 else
1230 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1231 }
7c27f87d 1232
771fe6b9
JG		 1233 encoder->native_mode = lvds->native_mode;
1234 }
1235 return lvds;
1236}
1237
6fe7ac3f
AD		 1238struct radeon_encoder_primary_dac *
1239radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1240{
1241 struct drm_device *dev = encoder->base.dev;
1242 struct radeon_device *rdev = dev->dev_private;
1243 struct radeon_mode_info *mode_info = &rdev->mode_info;
1244 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1245 uint16_t data_offset;
1246 struct _COMPASSIONATE_DATA *dac_info;
1247 uint8_t frev, crev;
1248 uint8_t bg, dac;
6fe7ac3f
AD		 1249 struct radeon_encoder_primary_dac *p_dac = NULL;
1250
a084e6ee
AD		 1251 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1252 &frev, &crev, &data_offset)) {
1253 dac_info = (struct _COMPASSIONATE_DATA *)
1254 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1255
6fe7ac3f
AD		 1256 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1257
1258 if (!p_dac)
1259 return NULL;
1260
1261 bg = dac_info->ucDAC1_BG_Adjustment;
1262 dac = dac_info->ucDAC1_DAC_Adjustment;
1263 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1264
1265 }
1266 return p_dac;
1267}
1268
4ce001ab 1269bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1270 struct drm_display_mode *mode)
4ce001ab
DA		 1271{
1272 struct radeon_mode_info *mode_info = &rdev->mode_info;
1273 ATOM_ANALOG_TV_INFO *tv_info;
1274 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1275 ATOM_DTD_FORMAT *dtd_timings;
1276 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1277 u8 frev, crev;
5a9bcacc 1278 u16 data_offset, misc;
4ce001ab 1279
a084e6ee
AD		 1280 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1281 &frev, &crev, &data_offset))
1282 return false;
4ce001ab
DA		 1283
1284 switch (crev) {
1285 case 1:
1286 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1287 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1288 return false;
1289
5a9bcacc
AD		 1290 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1291 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1292 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1293 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1294 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1295
1296 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1297 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1298 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1299 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1300 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1301
1302 mode->flags = 0;
1303 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1304 if (misc & ATOM_VSYNC_POLARITY)
1305 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1306 if (misc & ATOM_HSYNC_POLARITY)
1307 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1308 if (misc & ATOM_COMPOSITESYNC)
1309 mode->flags |= DRM_MODE_FLAG_CSYNC;
1310 if (misc & ATOM_INTERLACE)
1311 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1312 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1313 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1314
1315 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1316
1317 if (index == 1) {
1318 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1319 mode->crtc_htotal -= 1;
1320 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1321 }
1322 break;
1323 case 2:
1324 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1325 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1326 return false;
1327
1328 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1329 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1330 le16_to_cpu(dtd_timings->usHBlanking_Time);
1331 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1332 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1333 le16_to_cpu(dtd_timings->usHSyncOffset);
1334 mode->crtc_hsync_end = mode->crtc_hsync_start +
1335 le16_to_cpu(dtd_timings->usHSyncWidth);
1336
1337 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1338 le16_to_cpu(dtd_timings->usVBlanking_Time);
1339 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1340 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1341 le16_to_cpu(dtd_timings->usVSyncOffset);
1342 mode->crtc_vsync_end = mode->crtc_vsync_start +
1343 le16_to_cpu(dtd_timings->usVSyncWidth);
1344
1345 mode->flags = 0;
1346 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1347 if (misc & ATOM_VSYNC_POLARITY)
1348 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1349 if (misc & ATOM_HSYNC_POLARITY)
1350 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1351 if (misc & ATOM_COMPOSITESYNC)
1352 mode->flags |= DRM_MODE_FLAG_CSYNC;
1353 if (misc & ATOM_INTERLACE)
1354 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1355 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1356 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1357
1358 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1359 break;
1360 }
1361 return true;
1362}
1363
d79766fa
AD		 1364enum radeon_tv_std
1365radeon_atombios_get_tv_info(struct radeon_device *rdev)
1366{
1367 struct radeon_mode_info *mode_info = &rdev->mode_info;
1368 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1369 uint16_t data_offset;
1370 uint8_t frev, crev;
1371 struct _ATOM_ANALOG_TV_INFO *tv_info;
1372 enum radeon_tv_std tv_std = TV_STD_NTSC;
1373
a084e6ee
AD		 1374 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1375 &frev, &crev, &data_offset)) {
d79766fa 1376
a084e6ee
AD		 1377 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1378 (mode_info->atom_context->bios + data_offset);
d79766fa 1379
a084e6ee
AD		 1380 switch (tv_info->ucTV_BootUpDefaultStandard) {
1381 case ATOM_TV_NTSC:
1382 tv_std = TV_STD_NTSC;
1383 DRM_INFO("Default TV standard: NTSC\n");
1384 break;
1385 case ATOM_TV_NTSCJ:
1386 tv_std = TV_STD_NTSC_J;
1387 DRM_INFO("Default TV standard: NTSC-J\n");
1388 break;
1389 case ATOM_TV_PAL:
1390 tv_std = TV_STD_PAL;
1391 DRM_INFO("Default TV standard: PAL\n");
1392 break;
1393 case ATOM_TV_PALM:
1394 tv_std = TV_STD_PAL_M;
1395 DRM_INFO("Default TV standard: PAL-M\n");
1396 break;
1397 case ATOM_TV_PALN:
1398 tv_std = TV_STD_PAL_N;
1399 DRM_INFO("Default TV standard: PAL-N\n");
1400 break;
1401 case ATOM_TV_PALCN:
1402 tv_std = TV_STD_PAL_CN;
1403 DRM_INFO("Default TV standard: PAL-CN\n");
1404 break;
1405 case ATOM_TV_PAL60:
1406 tv_std = TV_STD_PAL_60;
1407 DRM_INFO("Default TV standard: PAL-60\n");
1408 break;
1409 case ATOM_TV_SECAM:
1410 tv_std = TV_STD_SECAM;
1411 DRM_INFO("Default TV standard: SECAM\n");
1412 break;
1413 default:
1414 tv_std = TV_STD_NTSC;
1415 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1416 break;
1417 }
d79766fa
AD		 1418 }
1419 return tv_std;
1420}
1421
6fe7ac3f
AD		 1422struct radeon_encoder_tv_dac *
1423radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1424{
1425 struct drm_device *dev = encoder->base.dev;
1426 struct radeon_device *rdev = dev->dev_private;
1427 struct radeon_mode_info *mode_info = &rdev->mode_info;
1428 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1429 uint16_t data_offset;
1430 struct _COMPASSIONATE_DATA *dac_info;
1431 uint8_t frev, crev;
1432 uint8_t bg, dac;
6fe7ac3f
AD		 1433 struct radeon_encoder_tv_dac *tv_dac = NULL;
1434
a084e6ee
AD		 1435 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1436 &frev, &crev, &data_offset)) {
6fe7ac3f 1437
a084e6ee
AD		 1438 dac_info = (struct _COMPASSIONATE_DATA *)
1439 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1440
6fe7ac3f
AD		 1441 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1442
1443 if (!tv_dac)
1444 return NULL;
1445
1446 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1447 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1448 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1449
1450 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1451 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1452 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1453
1454 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1455 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1456 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1457
d79766fa 1458 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1459 }
1460 return tv_dac;
1461}
1462
29fb52ca
AD		 1463static const char *thermal_controller_names[] = {
1464 "NONE",
678e7dfa
AD		 1465 "lm63",
1466 "adm1032",
1467 "adm1030",
1468 "max6649",
1469 "lm64",
1470 "f75375",
1471 "asc7xxx",
29fb52ca
AD		 1472};
1473
1474static const char *pp_lib_thermal_controller_names[] = {
1475 "NONE",
678e7dfa
AD		 1476 "lm63",
1477 "adm1032",
1478 "adm1030",
1479 "max6649",
1480 "lm64",
1481 "f75375",
29fb52ca
AD		 1482 "RV6xx",
1483 "RV770",
678e7dfa 1484 "adt7473",
49f65982
AD		 1485 "External GPIO",
1486 "Evergreen",
678e7dfa 1487 "adt7473 with internal",
49f65982 1488
29fb52ca
AD		 1489};
1490
56278a8e
AD		 1491union power_info {
1492 struct _ATOM_POWERPLAY_INFO info;
1493 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1494 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1495 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1496};
1497
1498void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1499{
56278a8e
AD		 1500 struct radeon_mode_info *mode_info = &rdev->mode_info;
1501 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1502 u16 data_offset;
1503 u8 frev, crev;
1504 u32 misc, misc2 = 0, sclk, mclk;
1505 union power_info *power_info;
1506 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1507 struct _ATOM_PPLIB_STATE *power_state;
1508 int num_modes = 0, i, j;
1509 int state_index = 0, mode_index = 0;
29fb52ca 1510 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1511
a48b9b4e 1512 rdev->pm.default_power_state_index = -1;
56278a8e 1513
a084e6ee
AD		 1514 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1515 &frev, &crev, &data_offset)) {
1516 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1517 if (frev < 4) {
29fb52ca
AD		 1518 /* add the i2c bus for thermal/fan chip */
1519 if (power_info->info.ucOverdriveThermalController > 0) {
1520 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1521 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1522 power_info->info.ucOverdriveControllerAddress >> 1);
1523 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1524 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
678e7dfa
AD		 1525 if (rdev->pm.i2c_bus) {
1526 struct i2c_board_info info = { };
1527 const char *name = thermal_controller_names[power_info->info.
1528 ucOverdriveThermalController];
1529 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1530 strlcpy(info.type, name, sizeof(info.type));
1531 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1532 }
29fb52ca 1533 }
56278a8e
AD		 1534 num_modes = power_info->info.ucNumOfPowerModeEntries;
1535 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1536 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1537 /* last mode is usually default, array is low to high */
56278a8e
AD		 1538 for (i = 0; i < num_modes; i++) {
1539 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1540 switch (frev) {
1541 case 1:
1542 rdev->pm.power_state[state_index].num_clock_modes = 1;
1543 rdev->pm.power_state[state_index].clock_info[0].mclk =
1544 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1545 rdev->pm.power_state[state_index].clock_info[0].sclk =
1546 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1547 /* skip invalid modes */
1548 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1549 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1550 continue;
79daedc9 1551 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1552 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1553 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1554 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1555 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1556 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1557 VOLTAGE_GPIO;
1558 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1559 radeon_lookup_gpio(rdev,
1560 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1561 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1562 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1563 true;
1564 else
1565 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1566 false;
1567 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1568 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1569 VOLTAGE_VDDC;
1570 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1571 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1572 }
d7311171 1573 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1574 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1575 /* order matters! */
1576 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1577 rdev->pm.power_state[state_index].type =
1578 POWER_STATE_TYPE_POWERSAVE;
1579 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1580 rdev->pm.power_state[state_index].type =
1581 POWER_STATE_TYPE_BATTERY;
1582 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1583 rdev->pm.power_state[state_index].type =
1584 POWER_STATE_TYPE_BATTERY;
1585 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1586 rdev->pm.power_state[state_index].type =
1587 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1588 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1589 rdev->pm.power_state[state_index].type =
1590 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1591 rdev->pm.power_state[state_index].flags &=
d7311171 1592 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1593 }
56278a8e 1594 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1595 rdev->pm.power_state[state_index].type =
1596 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1597 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1598 rdev->pm.power_state[state_index].default_clock_mode =
1599 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1600 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1601 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1602 } else if (state_index == 0) {
1603 rdev->pm.power_state[state_index].clock_info[0].flags |=
1604 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1605 }
1606 state_index++;
1607 break;
1608 case 2:
1609 rdev->pm.power_state[state_index].num_clock_modes = 1;
1610 rdev->pm.power_state[state_index].clock_info[0].mclk =
1611 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1612 rdev->pm.power_state[state_index].clock_info[0].sclk =
1613 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1614 /* skip invalid modes */
1615 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1616 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1617 continue;
79daedc9 1618 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1619 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1620 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1621 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1622 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1623 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1624 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1625 VOLTAGE_GPIO;
1626 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1627 radeon_lookup_gpio(rdev,
1628 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1629 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1630 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1631 true;
1632 else
1633 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1634 false;
1635 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1636 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1637 VOLTAGE_VDDC;
1638 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1639 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1640 }
d7311171 1641 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1642 rdev->pm.power_state[state_index].misc = misc;
1643 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1644 /* order matters! */
1645 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1646 rdev->pm.power_state[state_index].type =
1647 POWER_STATE_TYPE_POWERSAVE;
1648 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1649 rdev->pm.power_state[state_index].type =
1650 POWER_STATE_TYPE_BATTERY;
1651 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1652 rdev->pm.power_state[state_index].type =
1653 POWER_STATE_TYPE_BATTERY;
1654 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1655 rdev->pm.power_state[state_index].type =
1656 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1657 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1658 rdev->pm.power_state[state_index].type =
1659 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1660 rdev->pm.power_state[state_index].flags &=
d7311171 1661 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1662 }
0ec0e74f
AD		 1663 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1664 rdev->pm.power_state[state_index].type =
1665 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1666 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1667 rdev->pm.power_state[state_index].flags &=
d7311171 1668 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1669 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1670 rdev->pm.power_state[state_index].type =
1671 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1672 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1673 rdev->pm.power_state[state_index].default_clock_mode =
1674 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1675 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1676 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1677 } else if (state_index == 0) {
1678 rdev->pm.power_state[state_index].clock_info[0].flags |=
1679 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1680 }
1681 state_index++;
1682 break;
1683 case 3:
1684 rdev->pm.power_state[state_index].num_clock_modes = 1;
1685 rdev->pm.power_state[state_index].clock_info[0].mclk =
1686 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1687 rdev->pm.power_state[state_index].clock_info[0].sclk =
1688 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1689 /* skip invalid modes */
1690 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1691 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1692 continue;
79daedc9 1693 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1694 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1695 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1696 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1697 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1698 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1699 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1700 VOLTAGE_GPIO;
1701 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1702 radeon_lookup_gpio(rdev,
1703 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1704 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1705 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1706 true;
1707 else
1708 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1709 false;
1710 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1711 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1712 VOLTAGE_VDDC;
1713 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1714 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1715 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1716 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1717 true;
1718 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1719 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1720 }
1721 }
d7311171 1722 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1723 rdev->pm.power_state[state_index].misc = misc;
1724 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1725 /* order matters! */
1726 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1727 rdev->pm.power_state[state_index].type =
1728 POWER_STATE_TYPE_POWERSAVE;
1729 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1730 rdev->pm.power_state[state_index].type =
1731 POWER_STATE_TYPE_BATTERY;
1732 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1733 rdev->pm.power_state[state_index].type =
1734 POWER_STATE_TYPE_BATTERY;
1735 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1736 rdev->pm.power_state[state_index].type =
1737 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1738 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1739 rdev->pm.power_state[state_index].type =
1740 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1741 rdev->pm.power_state[state_index].flags &=
d7311171 1742 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1743 }
0ec0e74f
AD		 1744 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1745 rdev->pm.power_state[state_index].type =
1746 POWER_STATE_TYPE_BALANCED;
56278a8e 1747 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1748 rdev->pm.power_state[state_index].type =
1749 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1750 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1751 rdev->pm.power_state[state_index].default_clock_mode =
1752 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1753 } else if (state_index == 0) {
1754 rdev->pm.power_state[state_index].clock_info[0].flags |=
1755 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1756 }
1757 state_index++;
1758 break;
1759 }
1760 }
02b17cc0 1761 /* last mode is usually default */
a48b9b4e 1762 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1763 rdev->pm.power_state[state_index - 1].type =
1764 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1765 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1766 rdev->pm.power_state[state_index - 1].default_clock_mode =
1767 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1768 rdev->pm.power_state[state_index].flags &=
d7311171 1769 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1770 rdev->pm.power_state[state_index].misc = 0;
1771 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1772 }
49f65982 1773 } else {
c5e8ce61
AD		 1774 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1775 uint8_t fw_frev, fw_crev;
1776 uint16_t fw_data_offset, vddc = 0;
1777 union firmware_info *firmware_info;
1778 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1779
1780 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1781 &fw_frev, &fw_crev, &fw_data_offset)) {
1782 firmware_info =
1783 (union firmware_info *)(mode_info->atom_context->bios +
1784 fw_data_offset);
1785 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1786 }
1787
29fb52ca 1788 /* add the i2c bus for thermal/fan chip */
678e7dfa 1789 if (controller->ucType > 0) {
21a8122a 1790 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 1791 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1792 (controller->ucFanParameters &
29fb52ca 1793 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 1794 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1795 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1796 DRM_INFO("Internal thermal controller %s fan control\n",
1797 (controller->ucFanParameters &
1798 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1799 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1800 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1801 DRM_INFO("Internal thermal controller %s fan control\n",
1802 (controller->ucFanParameters &
1803 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1804 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 1805 } else if ((controller->ucType ==
49f65982 1806 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1807 (controller->ucType ==
49f65982
AD		 1808 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1809 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1810 } else {
1811 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1812 pp_lib_thermal_controller_names[controller->ucType],
1813 controller->ucI2cAddress >> 1,
1814 (controller->ucFanParameters &
29fb52ca 1815 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1816 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
29fb52ca 1817 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
678e7dfa
AD		 1818 if (rdev->pm.i2c_bus) {
1819 struct i2c_board_info info = { };
1820 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1821 info.addr = controller->ucI2cAddress >> 1;
1822 strlcpy(info.type, name, sizeof(info.type));
1823 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1824 }
1825
29fb52ca
AD		 1826 }
1827 }
02b17cc0 1828 /* first mode is usually default, followed by low to high */
56278a8e
AD		 1829 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1830 mode_index = 0;
1831 power_state = (struct _ATOM_PPLIB_STATE *)
1832 (mode_info->atom_context->bios +
1833 data_offset +
1834 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1835 i * power_info->info_4.ucStateEntrySize);
1836 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1837 (mode_info->atom_context->bios +
1838 data_offset +
1839 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1840 (power_state->ucNonClockStateIndex *
1841 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1842 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1843 if (rdev->flags & RADEON_IS_IGP) {
1844 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1845 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1846 (mode_info->atom_context->bios +
1847 data_offset +
1848 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1849 (power_state->ucClockStateIndices[j] *
1850 power_info->info_4.ucClockInfoSize));
1851 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1852 sclk |= clock_info->ucLowEngineClockHigh << 16;
1853 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1854 /* skip invalid modes */
1855 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1856 continue;
aa1df0f2 1857 /* voltage works differently on IGPs */
56278a8e 1858 mode_index++;
49f65982
AD		 1859 } else if (ASIC_IS_DCE4(rdev)) {
1860 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1861 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1862 (mode_info->atom_context->bios +
1863 data_offset +
1864 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1865 (power_state->ucClockStateIndices[j] *
1866 power_info->info_4.ucClockInfoSize));
1867 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1868 sclk |= clock_info->ucEngineClockHigh << 16;
1869 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1870 mclk |= clock_info->ucMemoryClockHigh << 16;
1871 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1872 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1873 /* skip invalid modes */
1874 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1875 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1876 continue;
49f65982
AD		 1877 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1878 VOLTAGE_SW;
1879 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1880 clock_info->usVDDC;
1881 /* XXX usVDDCI */
1882 mode_index++;
56278a8e
AD		 1883 } else {
1884 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1885 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1886 (mode_info->atom_context->bios +
1887 data_offset +
1888 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1889 (power_state->ucClockStateIndices[j] *
1890 power_info->info_4.ucClockInfoSize));
1891 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1892 sclk |= clock_info->ucEngineClockHigh << 16;
1893 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1894 mclk |= clock_info->ucMemoryClockHigh << 16;
1895 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1896 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1897 /* skip invalid modes */
1898 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1899 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1900 continue;
56278a8e
AD		 1901 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1902 VOLTAGE_SW;
1903 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1904 clock_info->usVDDC;
1905 mode_index++;
1906 }
1907 }
1908 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1909 if (mode_index) {
845db70d 1910 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 1911 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 1912 rdev->pm.power_state[state_index].misc = misc;
1913 rdev->pm.power_state[state_index].misc2 = misc2;
1914 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 1915 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1916 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 1917 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1918 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1919 rdev->pm.power_state[state_index].type =
1920 POWER_STATE_TYPE_BATTERY;
1921 break;
1922 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1923 rdev->pm.power_state[state_index].type =
1924 POWER_STATE_TYPE_BALANCED;
1925 break;
1926 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1927 rdev->pm.power_state[state_index].type =
1928 POWER_STATE_TYPE_PERFORMANCE;
1929 break;
1930 }
a48b9b4e
AD		 1931 rdev->pm.power_state[state_index].flags = 0;
1932 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1933 rdev->pm.power_state[state_index].flags |=
d7311171 1934 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1935 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 1936 rdev->pm.power_state[state_index].type =
1937 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1938 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1939 rdev->pm.power_state[state_index].default_clock_mode =
1940 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 1941 /* patch the table values with the default slck/mclk from firmware info */
1942 for (j = 0; j < mode_index; j++) {
1943 rdev->pm.power_state[state_index].clock_info[j].mclk =
1944 rdev->clock.default_mclk;
1945 rdev->pm.power_state[state_index].clock_info[j].sclk =
1946 rdev->clock.default_sclk;
1947 if (vddc)
1948 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
1949 vddc;
1950 }
56278a8e
AD		 1951 }
1952 state_index++;
1953 }
1954 }
d7311171
AD		 1955 /* if multiple clock modes, mark the lowest as no display */
1956 for (i = 0; i < state_index; i++) {
1957 if (rdev->pm.power_state[i].num_clock_modes > 1)
1958 rdev->pm.power_state[i].clock_info[0].flags |=
1959 RADEON_PM_MODE_NO_DISPLAY;
1960 }
02b17cc0 1961 /* first mode is usually default */
a48b9b4e 1962 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1963 rdev->pm.power_state[0].type =
1964 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1965 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 1966 rdev->pm.power_state[0].default_clock_mode =
1967 &rdev->pm.power_state[0].clock_info[0];
1968 }
56278a8e
AD		 1969 }
1970 } else {
56278a8e 1971 /* add the default mode */
0ec0e74f
AD		 1972 rdev->pm.power_state[state_index].type =
1973 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1974 rdev->pm.power_state[state_index].num_clock_modes = 1;
1975 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1976 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1977 rdev->pm.power_state[state_index].default_clock_mode =
1978 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 1979 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 1980 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 1981 rdev->pm.default_power_state_index = state_index;
1982 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 1983 state_index++;
1984 }
02b17cc0 1985
56278a8e 1986 rdev->pm.num_power_states = state_index;
9038dfdf 1987
a48b9b4e
AD		 1988 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1989 rdev->pm.current_clock_mode_index = 0;
4d60173f 1990 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 1991}
1992
771fe6b9 1993void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 1994{
771fe6b9
JG		 1995 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1996 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 1997
1998 args.ucEnable = enable;
1999
2000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2001}
2002
7433874e
RM		 2003uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2004{
2005 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2006 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2007
2008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2009 return args.ulReturnEngineClock;
2010}
2011
2012uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2013{
2014 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2015 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2016
2017 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2018 return args.ulReturnMemoryClock;
2019}
2020
771fe6b9
JG		 2021void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2022 uint32_t eng_clock)
2023{
2024 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2025 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2026
2027 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2028
2029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2030}
2031
2032void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2033 uint32_t mem_clock)
2034{
2035 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2036 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2037
2038 if (rdev->flags & RADEON_IS_IGP)
2039 return;
2040
2041 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2042
2043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2044}
2045
7ac9aa5a
AD		 2046union set_voltage {
2047 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2048 struct _SET_VOLTAGE_PARAMETERS v1;
2049 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2050};
2051
2052void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2053{
2054 union set_voltage args;
2055 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2056 u8 frev, crev, volt_index = level;
2057
2058 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2059 return;
2060
2061 switch (crev) {
2062 case 1:
2063 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2064 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2065 args.v1.ucVoltageIndex = volt_index;
2066 break;
2067 case 2:
2068 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2069 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2070 args.v2.usVoltageLevel = cpu_to_le16(level);
2071 break;
2072 default:
2073 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2074 return;
2075 }
2076
2077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2078}
2079
2080
2081
771fe6b9
JG		 2082void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2083{
2084 struct radeon_device *rdev = dev->dev_private;
2085 uint32_t bios_2_scratch, bios_6_scratch;
2086
2087 if (rdev->family >= CHIP_R600) {
4ce001ab 2088 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2089 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2090 } else {
4ce001ab 2091 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2092 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2093 }
2094
2095 /* let the bios control the backlight */
2096 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2097
2098 /* tell the bios not to handle mode switching */
2099 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2100
2101 if (rdev->family >= CHIP_R600) {
2102 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2103 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2104 } else {
2105 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2106 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2107 }
2108
2109}
2110
f657c2a7
YZ		 2111void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2112{
2113 uint32_t scratch_reg;
2114 int i;
2115
2116 if (rdev->family >= CHIP_R600)
2117 scratch_reg = R600_BIOS_0_SCRATCH;
2118 else
2119 scratch_reg = RADEON_BIOS_0_SCRATCH;
2120
2121 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2122 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2123}
2124
2125void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2126{
2127 uint32_t scratch_reg;
2128 int i;
2129
2130 if (rdev->family >= CHIP_R600)
2131 scratch_reg = R600_BIOS_0_SCRATCH;
2132 else
2133 scratch_reg = RADEON_BIOS_0_SCRATCH;
2134
2135 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2136 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2137}
2138
771fe6b9
JG		 2139void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2140{
2141 struct drm_device *dev = encoder->dev;
2142 struct radeon_device *rdev = dev->dev_private;
2143 uint32_t bios_6_scratch;
2144
2145 if (rdev->family >= CHIP_R600)
2146 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2147 else
2148 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2149
2150 if (lock)
2151 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2152 else
2153 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2154
2155 if (rdev->family >= CHIP_R600)
2156 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2157 else
2158 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2159}
2160
2161/* at some point we may want to break this out into individual functions */
2162void
2163radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2164 struct drm_encoder *encoder,
2165 bool connected)
2166{
2167 struct drm_device *dev = connector->dev;
2168 struct radeon_device *rdev = dev->dev_private;
2169 struct radeon_connector *radeon_connector =
2170 to_radeon_connector(connector);
2171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2172 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2173
2174 if (rdev->family >= CHIP_R600) {
2175 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2176 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2177 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2178 } else {
2179 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2180 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2181 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2182 }
2183
2184 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2185 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2186 if (connected) {
d9fdaafb 2187 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2188 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2189 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2190 } else {
d9fdaafb 2191 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2192 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2193 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2194 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2195 }
2196 }
2197 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2198 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2199 if (connected) {
d9fdaafb 2200 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2201 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2202 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2203 } else {
d9fdaafb 2204 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2205 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2206 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2207 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2208 }
2209 }
2210 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2211 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2212 if (connected) {
d9fdaafb 2213 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2214 bios_0_scratch |= ATOM_S0_LCD1;
2215 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2216 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2217 } else {
d9fdaafb 2218 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2219 bios_0_scratch &= ~ATOM_S0_LCD1;
2220 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2221 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2222 }
2223 }
2224 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2225 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2226 if (connected) {
d9fdaafb 2227 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2228 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2229 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2230 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2231 } else {
d9fdaafb 2232 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2233 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2234 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2235 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2236 }
2237 }
2238 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2239 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2240 if (connected) {
d9fdaafb 2241 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2242 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2243 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2244 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2245 } else {
d9fdaafb 2246 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2247 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2248 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2249 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2250 }
2251 }
2252 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2253 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2254 if (connected) {
d9fdaafb 2255 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2256 bios_0_scratch |= ATOM_S0_DFP1;
2257 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2258 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2259 } else {
d9fdaafb 2260 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2261 bios_0_scratch &= ~ATOM_S0_DFP1;
2262 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2263 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2264 }
2265 }
2266 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2267 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2268 if (connected) {
d9fdaafb 2269 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2270 bios_0_scratch |= ATOM_S0_DFP2;
2271 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2272 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2273 } else {
d9fdaafb 2274 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2275 bios_0_scratch &= ~ATOM_S0_DFP2;
2276 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2277 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2278 }
2279 }
2280 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2281 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2282 if (connected) {
d9fdaafb 2283 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2284 bios_0_scratch |= ATOM_S0_DFP3;
2285 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2286 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2287 } else {
d9fdaafb 2288 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2289 bios_0_scratch &= ~ATOM_S0_DFP3;
2290 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2291 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2292 }
2293 }
2294 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2295 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2296 if (connected) {
d9fdaafb 2297 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2298 bios_0_scratch |= ATOM_S0_DFP4;
2299 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2300 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2301 } else {
d9fdaafb 2302 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2303 bios_0_scratch &= ~ATOM_S0_DFP4;
2304 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2305 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2306 }
2307 }
2308 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2309 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2310 if (connected) {
d9fdaafb 2311 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2312 bios_0_scratch |= ATOM_S0_DFP5;
2313 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2314 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2315 } else {
d9fdaafb 2316 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2317 bios_0_scratch &= ~ATOM_S0_DFP5;
2318 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2319 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2320 }
2321 }
2322
2323 if (rdev->family >= CHIP_R600) {
2324 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2325 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2326 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2327 } else {
2328 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2329 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2330 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2331 }
2332}
2333
2334void
2335radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2336{
2337 struct drm_device *dev = encoder->dev;
2338 struct radeon_device *rdev = dev->dev_private;
2339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2340 uint32_t bios_3_scratch;
2341
2342 if (rdev->family >= CHIP_R600)
2343 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2344 else
2345 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2346
2347 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2348 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2349 bios_3_scratch |= (crtc << 18);
2350 }
2351 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2352 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2353 bios_3_scratch |= (crtc << 24);
2354 }
2355 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2356 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2357 bios_3_scratch |= (crtc << 16);
2358 }
2359 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2360 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2361 bios_3_scratch |= (crtc << 20);
2362 }
2363 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2364 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2365 bios_3_scratch |= (crtc << 17);
2366 }
2367 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2368 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2369 bios_3_scratch |= (crtc << 19);
2370 }
2371 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2372 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2373 bios_3_scratch |= (crtc << 23);
2374 }
2375 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2376 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2377 bios_3_scratch |= (crtc << 25);
2378 }
2379
2380 if (rdev->family >= CHIP_R600)
2381 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2382 else
2383 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2384}
2385
2386void
2387radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2388{
2389 struct drm_device *dev = encoder->dev;
2390 struct radeon_device *rdev = dev->dev_private;
2391 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2392 uint32_t bios_2_scratch;
2393
2394 if (rdev->family >= CHIP_R600)
2395 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2396 else
2397 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2398
2399 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2400 if (on)
2401 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2402 else
2403 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2404 }
2405 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2406 if (on)
2407 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2408 else
2409 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2410 }
2411 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2412 if (on)
2413 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2414 else
2415 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2416 }
2417 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2418 if (on)
2419 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2420 else
2421 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2422 }
2423 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2424 if (on)
2425 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2426 else
2427 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2428 }
2429 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2430 if (on)
2431 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2432 else
2433 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2434 }
2435 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2436 if (on)
2437 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2438 else
2439 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2440 }
2441 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2442 if (on)
2443 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2444 else
2445 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2446 }
2447 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2448 if (on)
2449 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2450 else
2451 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2452 }
2453 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2454 if (on)
2455 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2456 else
2457 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2458 }
2459
2460 if (rdev->family >= CHIP_R600)
2461 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2462 else
2463 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2464}
Linux kernel - Deliverables
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