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drm/radeon/kms: make sure ss id matches
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30
AD		 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
771fe6b9
JG		 52
53/* from radeon_legacy_encoder.c */
54extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62};
63
eed45b30
AD		 64static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
771fe6b9 66{
771fe6b9 67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73
74 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
75 i2c.valid = false;
76
77 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
6a93cb25
AD		 81 gpio = &i2c_info->asGPIO_Info[id];
82
83 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
84 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
85 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
86 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
87 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
88 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
89 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
90 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
91 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
92 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
93 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
94 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
95 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
96 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
97 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
98 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
99
100 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
101 i2c.hw_capable = true;
102 else
103 i2c.hw_capable = false;
104
105 if (gpio->sucI2cId.ucAccess == 0xa0)
106 i2c.mm_i2c = true;
107 else
108 i2c.mm_i2c = false;
109
110 i2c.i2c_id = gpio->sucI2cId.ucAccess;
111
771fe6b9
JG		 112 i2c.valid = true;
113
114 return i2c;
115}
116
eed45b30
AD		 117static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
118 u8 id)
119{
120 struct atom_context *ctx = rdev->mode_info.atom_context;
121 struct radeon_gpio_rec gpio;
122 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
123 struct _ATOM_GPIO_PIN_LUT *gpio_info;
124 ATOM_GPIO_PIN_ASSIGNMENT *pin;
125 u16 data_offset, size;
126 int i, num_indices;
127
128 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
129 gpio.valid = false;
130
131 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
132
133 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
134
135 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
136
137 for (i = 0; i < num_indices; i++) {
138 pin = &gpio_info->asGPIO_Pin[i];
139 if (id == pin->ucGPIO_ID) {
140 gpio.id = pin->ucGPIO_ID;
141 gpio.reg = pin->usGpioPin_AIndex * 4;
142 gpio.mask = (1 << pin->ucGpioPinBitShift);
143 gpio.valid = true;
144 break;
145 }
146 }
147
148 return gpio;
149}
150
151static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
152 struct radeon_gpio_rec *gpio)
153{
154 struct radeon_hpd hpd;
155 hpd.gpio = *gpio;
156 if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
157 switch(gpio->mask) {
158 case (1 << 0):
159 hpd.hpd = RADEON_HPD_1;
160 break;
161 case (1 << 8):
162 hpd.hpd = RADEON_HPD_2;
163 break;
164 case (1 << 16):
165 hpd.hpd = RADEON_HPD_3;
166 break;
167 case (1 << 24):
168 hpd.hpd = RADEON_HPD_4;
169 break;
170 case (1 << 26):
171 hpd.hpd = RADEON_HPD_5;
172 break;
173 case (1 << 28):
174 hpd.hpd = RADEON_HPD_6;
175 break;
176 default:
177 hpd.hpd = RADEON_HPD_NONE;
178 break;
179 }
180 } else
181 hpd.hpd = RADEON_HPD_NONE;
182 return hpd;
183}
184
771fe6b9
JG		 185static bool radeon_atom_apply_quirks(struct drm_device *dev,
186 uint32_t supported_device,
187 int *connector_type,
848577ee 188 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 189 uint16_t *line_mux,
190 struct radeon_hpd *hpd)
771fe6b9
JG		 191{
192
193 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
194 if ((dev->pdev->device == 0x791e) &&
195 (dev->pdev->subsystem_vendor == 0x1043) &&
196 (dev->pdev->subsystem_device == 0x826d)) {
197 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
198 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
199 *connector_type = DRM_MODE_CONNECTOR_DVID;
200 }
201
202 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
203 if ((dev->pdev->device == 0x7941) &&
204 (dev->pdev->subsystem_vendor == 0x147b) &&
205 (dev->pdev->subsystem_device == 0x2412)) {
206 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
207 return false;
208 }
209
210 /* Falcon NW laptop lists vga ddc line for LVDS */
211 if ((dev->pdev->device == 0x5653) &&
212 (dev->pdev->subsystem_vendor == 0x1462) &&
213 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 214 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 215 i2c_bus->valid = false;
848577ee
AD		 216 *line_mux = 53;
217 }
771fe6b9
JG		 218 }
219
4e3f9b78
AD		 220 /* HIS X1300 is DVI+VGA, not DVI+DVI */
221 if ((dev->pdev->device == 0x7146) &&
222 (dev->pdev->subsystem_vendor == 0x17af) &&
223 (dev->pdev->subsystem_device == 0x2058)) {
224 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
225 return false;
226 }
227
aa1a750e
DA		 228 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
229 if ((dev->pdev->device == 0x7142) &&
230 (dev->pdev->subsystem_vendor == 0x1458) &&
231 (dev->pdev->subsystem_device == 0x2134)) {
232 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
233 return false;
234 }
235
236
771fe6b9
JG		 237 /* Funky macbooks */
238 if ((dev->pdev->device == 0x71C5) &&
239 (dev->pdev->subsystem_vendor == 0x106b) &&
240 (dev->pdev->subsystem_device == 0x0080)) {
241 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
242 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
243 return false;
244 }
245
771fe6b9
JG		 246 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
247 if ((dev->pdev->device == 0x9598) &&
248 (dev->pdev->subsystem_vendor == 0x1043) &&
249 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 250 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 251 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 252 }
253 }
254
255 /* ASUS HD 3450 board lists the DVI port as HDMI */
256 if ((dev->pdev->device == 0x95C5) &&
257 (dev->pdev->subsystem_vendor == 0x1043) &&
258 (dev->pdev->subsystem_device == 0x01e2)) {
259 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 260 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 261 }
262 }
263
705af9c7
AD		 264 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
265 * HDMI + VGA reporting as HDMI
266 */
267 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
268 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
269 *connector_type = DRM_MODE_CONNECTOR_VGA;
270 *line_mux = 0;
271 }
272 }
273
3e5f8ff3
AD		 274 /* Acer laptop reports DVI-D as DVI-I */
275 if ((dev->pdev->device == 0x95c4) &&
276 (dev->pdev->subsystem_vendor == 0x1025) &&
277 (dev->pdev->subsystem_device == 0x013c)) {
278 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
279 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
280 *connector_type = DRM_MODE_CONNECTOR_DVID;
281 }
282
771fe6b9
JG		 283 return true;
284}
285
286const int supported_devices_connector_convert[] = {
287 DRM_MODE_CONNECTOR_Unknown,
288 DRM_MODE_CONNECTOR_VGA,
289 DRM_MODE_CONNECTOR_DVII,
290 DRM_MODE_CONNECTOR_DVID,
291 DRM_MODE_CONNECTOR_DVIA,
292 DRM_MODE_CONNECTOR_SVIDEO,
293 DRM_MODE_CONNECTOR_Composite,
294 DRM_MODE_CONNECTOR_LVDS,
295 DRM_MODE_CONNECTOR_Unknown,
296 DRM_MODE_CONNECTOR_Unknown,
297 DRM_MODE_CONNECTOR_HDMIA,
298 DRM_MODE_CONNECTOR_HDMIB,
299 DRM_MODE_CONNECTOR_Unknown,
300 DRM_MODE_CONNECTOR_Unknown,
301 DRM_MODE_CONNECTOR_9PinDIN,
302 DRM_MODE_CONNECTOR_DisplayPort
303};
304
b75fad06
AD		 305const uint16_t supported_devices_connector_object_id_convert[] = {
306 CONNECTOR_OBJECT_ID_NONE,
307 CONNECTOR_OBJECT_ID_VGA,
308 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
309 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
310 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
311 CONNECTOR_OBJECT_ID_COMPOSITE,
312 CONNECTOR_OBJECT_ID_SVIDEO,
313 CONNECTOR_OBJECT_ID_LVDS,
314 CONNECTOR_OBJECT_ID_9PIN_DIN,
315 CONNECTOR_OBJECT_ID_9PIN_DIN,
316 CONNECTOR_OBJECT_ID_DISPLAYPORT,
317 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
318 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
319 CONNECTOR_OBJECT_ID_SVIDEO
320};
321
771fe6b9
JG		 322const int object_connector_convert[] = {
323 DRM_MODE_CONNECTOR_Unknown,
324 DRM_MODE_CONNECTOR_DVII,
325 DRM_MODE_CONNECTOR_DVII,
326 DRM_MODE_CONNECTOR_DVID,
327 DRM_MODE_CONNECTOR_DVID,
328 DRM_MODE_CONNECTOR_VGA,
329 DRM_MODE_CONNECTOR_Composite,
330 DRM_MODE_CONNECTOR_SVIDEO,
331 DRM_MODE_CONNECTOR_Unknown,
705af9c7 332 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 333 DRM_MODE_CONNECTOR_9PinDIN,
334 DRM_MODE_CONNECTOR_Unknown,
335 DRM_MODE_CONNECTOR_HDMIA,
336 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 337 DRM_MODE_CONNECTOR_LVDS,
338 DRM_MODE_CONNECTOR_9PinDIN,
339 DRM_MODE_CONNECTOR_Unknown,
340 DRM_MODE_CONNECTOR_Unknown,
341 DRM_MODE_CONNECTOR_Unknown,
342 DRM_MODE_CONNECTOR_DisplayPort
343};
344
345bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
346{
347 struct radeon_device *rdev = dev->dev_private;
348 struct radeon_mode_info *mode_info = &rdev->mode_info;
349 struct atom_context *ctx = mode_info->atom_context;
350 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 351 u16 size, data_offset;
352 u8 frev, crev;
771fe6b9
JG		 353 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
354 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
355 ATOM_OBJECT_HEADER *obj_header;
356 int i, j, path_size, device_support;
357 int connector_type;
eed45b30 358 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 359 bool linkb;
360 struct radeon_i2c_bus_rec ddc_bus;
eed45b30
AD		 361 struct radeon_gpio_rec gpio;
362 struct radeon_hpd hpd;
363
771fe6b9
JG		 364 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
365
366 if (data_offset == 0)
367 return false;
368
369 if (crev < 2)
370 return false;
371
372 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
373 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
374 (ctx->bios + data_offset +
375 le16_to_cpu(obj_header->usDisplayPathTableOffset));
376 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
377 (ctx->bios + data_offset +
378 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
379 device_support = le16_to_cpu(obj_header->usDeviceSupport);
380
381 path_size = 0;
382 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
383 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
384 ATOM_DISPLAY_OBJECT_PATH *path;
385 addr += path_size;
386 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
387 path_size += le16_to_cpu(path->usSize);
388 linkb = false;
771fe6b9
JG		 389 if (device_support & le16_to_cpu(path->usDeviceTag)) {
390 uint8_t con_obj_id, con_obj_num, con_obj_type;
391
392 con_obj_id =
393 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
394 >> OBJECT_ID_SHIFT;
395 con_obj_num =
396 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
397 >> ENUM_ID_SHIFT;
398 con_obj_type =
399 (le16_to_cpu(path->usConnObjectId) &
400 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
401
4bbd4973
DA		 402 /* TODO CV support */
403 if (le16_to_cpu(path->usDeviceTag) ==
404 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 405 continue;
406
ee59f2b4
AD		 407 /* IGP chips */
408 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 409 (con_obj_id ==
410 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
411 uint16_t igp_offset = 0;
412 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
413
414 index =
415 GetIndexIntoMasterTable(DATA,
416 IntegratedSystemInfo);
417
418 atom_parse_data_header(ctx, index, &size, &frev,
419 &crev, &igp_offset);
420
421 if (crev >= 2) {
422 igp_obj =
423 (ATOM_INTEGRATED_SYSTEM_INFO_V2
424 *) (ctx->bios + igp_offset);
425
426 if (igp_obj) {
427 uint32_t slot_config, ct;
428
429 if (con_obj_num == 1)
430 slot_config =
431 igp_obj->
432 ulDDISlot1Config;
433 else
434 slot_config =
435 igp_obj->
436 ulDDISlot2Config;
437
438 ct = (slot_config >> 16) & 0xff;
439 connector_type =
440 object_connector_convert
441 [ct];
b75fad06 442 connector_object_id = ct;
771fe6b9
JG		 443 igp_lane_info =
444 slot_config & 0xffff;
445 } else
446 continue;
447 } else
448 continue;
449 } else {
450 igp_lane_info = 0;
451 connector_type =
452 object_connector_convert[con_obj_id];
b75fad06 453 connector_object_id = con_obj_id;
771fe6b9
JG		 454 }
455
456 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
457 continue;
458
459 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
460 j++) {
461 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
462
463 enc_obj_id =
464 (le16_to_cpu(path->usGraphicObjIds[j]) &
465 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
466 enc_obj_num =
467 (le16_to_cpu(path->usGraphicObjIds[j]) &
468 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
469 enc_obj_type =
470 (le16_to_cpu(path->usGraphicObjIds[j]) &
471 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
472
473 /* FIXME: add support for router objects */
474 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
475 if (enc_obj_num == 2)
476 linkb = true;
477 else
478 linkb = false;
479
480 radeon_add_atom_encoder(dev,
481 enc_obj_id,
482 le16_to_cpu
483 (path->
484 usDeviceTag));
485
486 }
487 }
488
eed45b30 489 /* look up gpio for ddc, hpd */
771fe6b9 490 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 491 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 492 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
493 if (le16_to_cpu(path->usConnObjectId) ==
494 le16_to_cpu(con_obj->asObjects[j].
495 usObjectID)) {
496 ATOM_COMMON_RECORD_HEADER
497 *record =
498 (ATOM_COMMON_RECORD_HEADER
499 *)
500 (ctx->bios + data_offset +
501 le16_to_cpu(con_obj->
502 asObjects[j].
503 usRecordOffset));
504 ATOM_I2C_RECORD *i2c_record;
eed45b30
AD		 505 ATOM_HPD_INT_RECORD *hpd_record;
506 hpd.hpd = RADEON_HPD_NONE;
6a93cb25 507
771fe6b9
JG		 508 while (record->ucRecordType > 0
509 && record->
510 ucRecordType <=
511 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 512 switch (record->ucRecordType) {
771fe6b9
JG		 513 case ATOM_I2C_RECORD_TYPE:
514 i2c_record =
eed45b30
AD		 515 (ATOM_I2C_RECORD *)
516 record;
517 ddc_bus = radeon_lookup_i2c_gpio(rdev,
518 i2c_record->
519 sucI2cId.
520 bfI2C_LineMux);
521 break;
522 case ATOM_HPD_INT_RECORD_TYPE:
523 hpd_record =
524 (ATOM_HPD_INT_RECORD *)
525 record;
526 gpio = radeon_lookup_gpio(rdev,
527 hpd_record->ucHPDIntGPIOID);
528 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
529 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 530 break;
531 }
532 record =
533 (ATOM_COMMON_RECORD_HEADER
534 *) ((char *)record
535 +
536 record->
537 ucRecordSize);
538 }
539 break;
540 }
541 }
eed45b30
AD		 542 } else {
543 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 544 ddc_bus.valid = false;
eed45b30 545 }
771fe6b9 546
705af9c7
AD		 547 conn_id = le16_to_cpu(path->usConnObjectId);
548
549 if (!radeon_atom_apply_quirks
550 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 551 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 552 continue;
553
771fe6b9 554 radeon_add_atom_connector(dev,
705af9c7 555 conn_id,
771fe6b9
JG		 556 le16_to_cpu(path->
557 usDeviceTag),
558 connector_type, &ddc_bus,
b75fad06 559 linkb, igp_lane_info,
eed45b30
AD		 560 connector_object_id,
561 &hpd);
771fe6b9
JG		 562
563 }
564 }
565
566 radeon_link_encoder_connector(dev);
567
568 return true;
569}
570
b75fad06
AD		 571static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
572 int connector_type,
573 uint16_t devices)
574{
575 struct radeon_device *rdev = dev->dev_private;
576
577 if (rdev->flags & RADEON_IS_IGP) {
578 return supported_devices_connector_object_id_convert
579 [connector_type];
580 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
581 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
582 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
583 struct radeon_mode_info *mode_info = &rdev->mode_info;
584 struct atom_context *ctx = mode_info->atom_context;
585 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
586 uint16_t size, data_offset;
587 uint8_t frev, crev;
588 ATOM_XTMDS_INFO *xtmds;
589
590 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
591 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
592
593 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
594 if (connector_type == DRM_MODE_CONNECTOR_DVII)
595 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
596 else
597 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
598 } else {
599 if (connector_type == DRM_MODE_CONNECTOR_DVII)
600 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
601 else
602 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
603 }
604 } else {
605 return supported_devices_connector_object_id_convert
606 [connector_type];
607 }
608}
609
771fe6b9
JG		 610struct bios_connector {
611 bool valid;
705af9c7 612 uint16_t line_mux;
771fe6b9
JG		 613 uint16_t devices;
614 int connector_type;
615 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 616 struct radeon_hpd hpd;
771fe6b9
JG		 617};
618
619bool radeon_get_atom_connector_info_from_supported_devices_table(struct
620 drm_device
621 *dev)
622{
623 struct radeon_device *rdev = dev->dev_private;
624 struct radeon_mode_info *mode_info = &rdev->mode_info;
625 struct atom_context *ctx = mode_info->atom_context;
626 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
627 uint16_t size, data_offset;
628 uint8_t frev, crev;
629 uint16_t device_support;
630 uint8_t dac;
631 union atom_supported_devices *supported_devices;
eed45b30 632 int i, j, max_device;
771fe6b9
JG		 633 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
634
635 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
636
637 supported_devices =
638 (union atom_supported_devices *)(ctx->bios + data_offset);
639
640 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
641
eed45b30
AD		 642 if (frev > 1)
643 max_device = ATOM_MAX_SUPPORTED_DEVICE;
644 else
645 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
646
647 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 648 ATOM_CONNECTOR_INFO_I2C ci =
649 supported_devices->info.asConnInfo[i];
650
651 bios_connectors[i].valid = false;
652
653 if (!(device_support & (1 << i))) {
654 continue;
655 }
656
657 if (i == ATOM_DEVICE_CV_INDEX) {
658 DRM_DEBUG("Skipping Component Video\n");
659 continue;
660 }
661
771fe6b9
JG		 662 bios_connectors[i].connector_type =
663 supported_devices_connector_convert[ci.sucConnectorInfo.
664 sbfAccess.
665 bfConnectorType];
666
667 if (bios_connectors[i].connector_type ==
668 DRM_MODE_CONNECTOR_Unknown)
669 continue;
670
671 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
672
673 if ((rdev->family == CHIP_RS690) ||
674 (rdev->family == CHIP_RS740)) {
675 if ((i == ATOM_DEVICE_DFP2_INDEX)
676 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
677 bios_connectors[i].line_mux =
678 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
679 else if ((i == ATOM_DEVICE_DFP3_INDEX)
680 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
681 bios_connectors[i].line_mux =
682 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
683 else
684 bios_connectors[i].line_mux =
685 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
686 } else
687 bios_connectors[i].line_mux =
688 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
689
690 /* give tv unique connector ids */
691 if (i == ATOM_DEVICE_TV1_INDEX) {
692 bios_connectors[i].ddc_bus.valid = false;
693 bios_connectors[i].line_mux = 50;
694 } else if (i == ATOM_DEVICE_TV2_INDEX) {
695 bios_connectors[i].ddc_bus.valid = false;
696 bios_connectors[i].line_mux = 51;
697 } else if (i == ATOM_DEVICE_CV_INDEX) {
698 bios_connectors[i].ddc_bus.valid = false;
699 bios_connectors[i].line_mux = 52;
700 } else
701 bios_connectors[i].ddc_bus =
eed45b30
AD		 702 radeon_lookup_i2c_gpio(rdev,
703 bios_connectors[i].line_mux);
704
705 if ((crev > 1) && (frev > 1)) {
706 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
707 switch (isb) {
708 case 0x4:
709 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
710 break;
711 case 0xa:
712 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
713 break;
714 default:
715 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
716 break;
717 }
718 } else {
719 if (i == ATOM_DEVICE_DFP1_INDEX)
720 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
721 else if (i == ATOM_DEVICE_DFP2_INDEX)
722 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
723 else
724 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
725 }
771fe6b9
JG		 726
727 /* Always set the connector type to VGA for CRT1/CRT2. if they are
728 * shared with a DVI port, we'll pick up the DVI connector when we
729 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
730 */
731 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
732 bios_connectors[i].connector_type =
733 DRM_MODE_CONNECTOR_VGA;
734
735 if (!radeon_atom_apply_quirks
736 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 737 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
738 &bios_connectors[i].hpd))
771fe6b9
JG		 739 continue;
740
741 bios_connectors[i].valid = true;
742 bios_connectors[i].devices = (1 << i);
743
744 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
745 radeon_add_atom_encoder(dev,
746 radeon_get_encoder_id(dev,
747 (1 << i),
748 dac),
749 (1 << i));
750 else
751 radeon_add_legacy_encoder(dev,
752 radeon_get_encoder_id(dev,
753 (1 <<
754 i),
755 dac),
756 (1 << i));
757 }
758
759 /* combine shared connectors */
eed45b30 760 for (i = 0; i < max_device; i++) {
771fe6b9 761 if (bios_connectors[i].valid) {
eed45b30 762 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 763 if (bios_connectors[j].valid && (i != j)) {
764 if (bios_connectors[i].line_mux ==
765 bios_connectors[j].line_mux) {
766 if (((bios_connectors[i].
767 devices &
768 (ATOM_DEVICE_DFP_SUPPORT))
769 && (bios_connectors[j].
770 devices &
771 (ATOM_DEVICE_CRT_SUPPORT)))
772 ||
773 ((bios_connectors[j].
774 devices &
775 (ATOM_DEVICE_DFP_SUPPORT))
776 && (bios_connectors[i].
777 devices &
778 (ATOM_DEVICE_CRT_SUPPORT)))) {
779 bios_connectors[i].
780 devices |=
781 bios_connectors[j].
782 devices;
783 bios_connectors[i].
784 connector_type =
785 DRM_MODE_CONNECTOR_DVII;
eed45b30
AD		 786 if (bios_connectors[j].devices &
787 (ATOM_DEVICE_DFP_SUPPORT))
788 bios_connectors[i].hpd =
789 bios_connectors[j].hpd;
771fe6b9
JG		 790 bios_connectors[j].
791 valid = false;
792 }
793 }
794 }
795 }
796 }
797 }
798
799 /* add the connectors */
eed45b30 800 for (i = 0; i < max_device; i++) {
b75fad06
AD		 801 if (bios_connectors[i].valid) {
802 uint16_t connector_object_id =
803 atombios_get_connector_object_id(dev,
804 bios_connectors[i].connector_type,
805 bios_connectors[i].devices);
771fe6b9
JG		 806 radeon_add_atom_connector(dev,
807 bios_connectors[i].line_mux,
808 bios_connectors[i].devices,
809 bios_connectors[i].
810 connector_type,
811 &bios_connectors[i].ddc_bus,
b75fad06 812 false, 0,
eed45b30
AD		 813 connector_object_id,
814 &bios_connectors[i].hpd);
b75fad06 815 }
771fe6b9
JG		 816 }
817
818 radeon_link_encoder_connector(dev);
819
820 return true;
821}
822
823union firmware_info {
824 ATOM_FIRMWARE_INFO info;
825 ATOM_FIRMWARE_INFO_V1_2 info_12;
826 ATOM_FIRMWARE_INFO_V1_3 info_13;
827 ATOM_FIRMWARE_INFO_V1_4 info_14;
828};
829
830bool radeon_atom_get_clock_info(struct drm_device *dev)
831{
832 struct radeon_device *rdev = dev->dev_private;
833 struct radeon_mode_info *mode_info = &rdev->mode_info;
834 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
835 union firmware_info *firmware_info;
836 uint8_t frev, crev;
837 struct radeon_pll *p1pll = &rdev->clock.p1pll;
838 struct radeon_pll *p2pll = &rdev->clock.p2pll;
839 struct radeon_pll *spll = &rdev->clock.spll;
840 struct radeon_pll *mpll = &rdev->clock.mpll;
841 uint16_t data_offset;
842
843 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
844 &crev, &data_offset);
845
846 firmware_info =
847 (union firmware_info *)(mode_info->atom_context->bios +
848 data_offset);
849
850 if (firmware_info) {
851 /* pixel clocks */
852 p1pll->reference_freq =
853 le16_to_cpu(firmware_info->info.usReferenceClock);
854 p1pll->reference_div = 0;
855
bc293e58
MF		 856 if (crev < 2)
857 p1pll->pll_out_min =
858 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
859 else
860 p1pll->pll_out_min =
861 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 862 p1pll->pll_out_max =
863 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
864
865 if (p1pll->pll_out_min == 0) {
866 if (ASIC_IS_AVIVO(rdev))
867 p1pll->pll_out_min = 64800;
868 else
869 p1pll->pll_out_min = 20000;
8f552a66
AD		 870 } else if (p1pll->pll_out_min > 64800) {
871 /* Limiting the pll output range is a good thing generally as
872 * it limits the number of possible pll combinations for a given
873 * frequency presumably to the ones that work best on each card.
874 * However, certain duallink DVI monitors seem to like
875 * pll combinations that would be limited by this at least on
876 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
877 * family.
878 */
879 p1pll->pll_out_min = 64800;
771fe6b9
JG		 880 }
881
882 p1pll->pll_in_min =
883 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
884 p1pll->pll_in_max =
885 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
886
887 *p2pll = *p1pll;
888
889 /* system clock */
890 spll->reference_freq =
891 le16_to_cpu(firmware_info->info.usReferenceClock);
892 spll->reference_div = 0;
893
894 spll->pll_out_min =
895 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
896 spll->pll_out_max =
897 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
898
899 /* ??? */
900 if (spll->pll_out_min == 0) {
901 if (ASIC_IS_AVIVO(rdev))
902 spll->pll_out_min = 64800;
903 else
904 spll->pll_out_min = 20000;
905 }
906
907 spll->pll_in_min =
908 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
909 spll->pll_in_max =
910 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
911
912 /* memory clock */
913 mpll->reference_freq =
914 le16_to_cpu(firmware_info->info.usReferenceClock);
915 mpll->reference_div = 0;
916
917 mpll->pll_out_min =
918 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
919 mpll->pll_out_max =
920 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
921
922 /* ??? */
923 if (mpll->pll_out_min == 0) {
924 if (ASIC_IS_AVIVO(rdev))
925 mpll->pll_out_min = 64800;
926 else
927 mpll->pll_out_min = 20000;
928 }
929
930 mpll->pll_in_min =
931 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
932 mpll->pll_in_max =
933 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
934
935 rdev->clock.default_sclk =
936 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
937 rdev->clock.default_mclk =
938 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
939
940 return true;
941 }
942 return false;
943}
944
445282db
DA		 945bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
946 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 947{
948 struct drm_device *dev = encoder->base.dev;
949 struct radeon_device *rdev = dev->dev_private;
950 struct radeon_mode_info *mode_info = &rdev->mode_info;
951 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
952 uint16_t data_offset;
953 struct _ATOM_TMDS_INFO *tmds_info;
954 uint8_t frev, crev;
955 uint16_t maxfreq;
956 int i;
771fe6b9
JG		 957
958 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
959 &crev, &data_offset);
960
961 tmds_info =
962 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
963 data_offset);
964
965 if (tmds_info) {
771fe6b9
JG		 966 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
967 for (i = 0; i < 4; i++) {
968 tmds->tmds_pll[i].freq =
969 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
970 tmds->tmds_pll[i].value =
971 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
972 tmds->tmds_pll[i].value |=
973 (tmds_info->asMiscInfo[i].
974 ucPLL_VCO_Gain & 0x3f) << 6;
975 tmds->tmds_pll[i].value |=
976 (tmds_info->asMiscInfo[i].
977 ucPLL_DutyCycle & 0xf) << 12;
978 tmds->tmds_pll[i].value |=
979 (tmds_info->asMiscInfo[i].
980 ucPLL_VoltageSwing & 0xf) << 16;
981
982 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
983 tmds->tmds_pll[i].freq,
984 tmds->tmds_pll[i].value);
985
986 if (maxfreq == tmds->tmds_pll[i].freq) {
987 tmds->tmds_pll[i].freq = 0xffffffff;
988 break;
989 }
990 }
445282db 991 return true;
771fe6b9 992 }
445282db 993 return false;
771fe6b9
JG		 994}
995
ebbe1cb9
AD		 996static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
997 radeon_encoder
998 *encoder,
999 int id)
1000{
1001 struct drm_device *dev = encoder->base.dev;
1002 struct radeon_device *rdev = dev->dev_private;
1003 struct radeon_mode_info *mode_info = &rdev->mode_info;
1004 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1005 uint16_t data_offset;
1006 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1007 uint8_t frev, crev;
1008 struct radeon_atom_ss *ss = NULL;
279b215e 1009 int i;
ebbe1cb9
AD		 1010
1011 if (id > ATOM_MAX_SS_ENTRY)
1012 return NULL;
1013
1014 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1015 &crev, &data_offset);
1016
1017 ss_info =
1018 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1019
1020 if (ss_info) {
1021 ss =
1022 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1023
1024 if (!ss)
1025 return NULL;
1026
279b215e
AD		 1027 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1028 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1029 ss->percentage =
1030 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1031 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1032 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1033 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1034 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1035 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1036 }
1037 }
ebbe1cb9
AD		 1038 }
1039 return ss;
1040}
1041
771fe6b9
JG		 1042union lvds_info {
1043 struct _ATOM_LVDS_INFO info;
1044 struct _ATOM_LVDS_INFO_V12 info_12;
1045};
1046
1047struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1048 radeon_encoder
1049 *encoder)
1050{
1051 struct drm_device *dev = encoder->base.dev;
1052 struct radeon_device *rdev = dev->dev_private;
1053 struct radeon_mode_info *mode_info = &rdev->mode_info;
1054 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1055 uint16_t data_offset, misc;
771fe6b9
JG		 1056 union lvds_info *lvds_info;
1057 uint8_t frev, crev;
1058 struct radeon_encoder_atom_dig *lvds = NULL;
1059
1060 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1061 &crev, &data_offset);
1062
1063 lvds_info =
1064 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1065
1066 if (lvds_info) {
1067 lvds =
1068 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1069
1070 if (!lvds)
1071 return NULL;
1072
de2103e4 1073 lvds->native_mode.clock =
771fe6b9 1074 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1075 lvds->native_mode.hdisplay =
771fe6b9 1076 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1077 lvds->native_mode.vdisplay =
771fe6b9 1078 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1079 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1080 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1081 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1082 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1083 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1084 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1085 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1086 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1087 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1088 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1089 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1090 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1091 lvds->panel_pwr_delay =
1092 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1093 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1094
1095 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1096 if (misc & ATOM_VSYNC_POLARITY)
1097 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1098 if (misc & ATOM_HSYNC_POLARITY)
1099 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1100 if (misc & ATOM_COMPOSITESYNC)
1101 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1102 if (misc & ATOM_INTERLACE)
1103 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1104 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1105 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1106
de2103e4
AD		 1107 /* set crtc values */
1108 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1109
ebbe1cb9
AD		 1110 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1111
771fe6b9
JG		 1112 encoder->native_mode = lvds->native_mode;
1113 }
1114 return lvds;
1115}
1116
6fe7ac3f
AD		 1117struct radeon_encoder_primary_dac *
1118radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1119{
1120 struct drm_device *dev = encoder->base.dev;
1121 struct radeon_device *rdev = dev->dev_private;
1122 struct radeon_mode_info *mode_info = &rdev->mode_info;
1123 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1124 uint16_t data_offset;
1125 struct _COMPASSIONATE_DATA *dac_info;
1126 uint8_t frev, crev;
1127 uint8_t bg, dac;
6fe7ac3f
AD		 1128 struct radeon_encoder_primary_dac *p_dac = NULL;
1129
1130 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1131
1132 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1133
1134 if (dac_info) {
1135 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1136
1137 if (!p_dac)
1138 return NULL;
1139
1140 bg = dac_info->ucDAC1_BG_Adjustment;
1141 dac = dac_info->ucDAC1_DAC_Adjustment;
1142 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1143
1144 }
1145 return p_dac;
1146}
1147
4ce001ab 1148bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1149 struct drm_display_mode *mode)
4ce001ab
DA		 1150{
1151 struct radeon_mode_info *mode_info = &rdev->mode_info;
1152 ATOM_ANALOG_TV_INFO *tv_info;
1153 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1154 ATOM_DTD_FORMAT *dtd_timings;
1155 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1156 u8 frev, crev;
5a9bcacc 1157 u16 data_offset, misc;
4ce001ab
DA		 1158
1159 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1160
1161 switch (crev) {
1162 case 1:
1163 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1164 if (index > MAX_SUPPORTED_TV_TIMING)
1165 return false;
1166
5a9bcacc
AD		 1167 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1168 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1169 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1170 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1171 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1172
1173 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1174 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1175 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1176 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1177 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1178
1179 mode->flags = 0;
1180 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1181 if (misc & ATOM_VSYNC_POLARITY)
1182 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1183 if (misc & ATOM_HSYNC_POLARITY)
1184 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1185 if (misc & ATOM_COMPOSITESYNC)
1186 mode->flags |= DRM_MODE_FLAG_CSYNC;
1187 if (misc & ATOM_INTERLACE)
1188 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1189 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1190 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1191
1192 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1193
1194 if (index == 1) {
1195 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1196 mode->crtc_htotal -= 1;
1197 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1198 }
1199 break;
1200 case 2:
1201 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1202 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1203 return false;
1204
1205 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1206 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1207 le16_to_cpu(dtd_timings->usHBlanking_Time);
1208 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1209 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1210 le16_to_cpu(dtd_timings->usHSyncOffset);
1211 mode->crtc_hsync_end = mode->crtc_hsync_start +
1212 le16_to_cpu(dtd_timings->usHSyncWidth);
1213
1214 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1215 le16_to_cpu(dtd_timings->usVBlanking_Time);
1216 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1217 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1218 le16_to_cpu(dtd_timings->usVSyncOffset);
1219 mode->crtc_vsync_end = mode->crtc_vsync_start +
1220 le16_to_cpu(dtd_timings->usVSyncWidth);
1221
1222 mode->flags = 0;
1223 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1224 if (misc & ATOM_VSYNC_POLARITY)
1225 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1226 if (misc & ATOM_HSYNC_POLARITY)
1227 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1228 if (misc & ATOM_COMPOSITESYNC)
1229 mode->flags |= DRM_MODE_FLAG_CSYNC;
1230 if (misc & ATOM_INTERLACE)
1231 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1232 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1233 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1234
1235 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1236 break;
1237 }
1238 return true;
1239}
1240
6fe7ac3f
AD		 1241struct radeon_encoder_tv_dac *
1242radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1243{
1244 struct drm_device *dev = encoder->base.dev;
1245 struct radeon_device *rdev = dev->dev_private;
1246 struct radeon_mode_info *mode_info = &rdev->mode_info;
1247 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1248 uint16_t data_offset;
1249 struct _COMPASSIONATE_DATA *dac_info;
1250 uint8_t frev, crev;
1251 uint8_t bg, dac;
6fe7ac3f
AD		 1252 struct radeon_encoder_tv_dac *tv_dac = NULL;
1253
1254 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1255
1256 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1257
1258 if (dac_info) {
1259 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1260
1261 if (!tv_dac)
1262 return NULL;
1263
1264 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1265 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1266 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1267
1268 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1269 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1270 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1271
1272 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1273 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1274 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1275
1276 }
1277 return tv_dac;
1278}
1279
771fe6b9
JG		 1280void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1281{
1282 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1283 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1284
1285 args.ucEnable = enable;
1286
1287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1288}
1289
1290void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1291{
1292 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1293 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1294
1295 args.ucEnable = enable;
1296
1297 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1298}
1299
7433874e
RM		 1300uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1301{
1302 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1303 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1304
1305 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1306 return args.ulReturnEngineClock;
1307}
1308
1309uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1310{
1311 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1312 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1313
1314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1315 return args.ulReturnMemoryClock;
1316}
1317
771fe6b9
JG		 1318void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1319 uint32_t eng_clock)
1320{
1321 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1322 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1323
1324 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1325
1326 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1327}
1328
1329void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1330 uint32_t mem_clock)
1331{
1332 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1333 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1334
1335 if (rdev->flags & RADEON_IS_IGP)
1336 return;
1337
1338 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1339
1340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1341}
1342
1343void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1344{
1345 struct radeon_device *rdev = dev->dev_private;
1346 uint32_t bios_2_scratch, bios_6_scratch;
1347
1348 if (rdev->family >= CHIP_R600) {
4ce001ab 1349 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1350 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1351 } else {
4ce001ab 1352 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1353 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1354 }
1355
1356 /* let the bios control the backlight */
1357 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1358
1359 /* tell the bios not to handle mode switching */
1360 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1361
1362 if (rdev->family >= CHIP_R600) {
1363 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1364 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1365 } else {
1366 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1367 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1368 }
1369
1370}
1371
f657c2a7
YZ		 1372void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1373{
1374 uint32_t scratch_reg;
1375 int i;
1376
1377 if (rdev->family >= CHIP_R600)
1378 scratch_reg = R600_BIOS_0_SCRATCH;
1379 else
1380 scratch_reg = RADEON_BIOS_0_SCRATCH;
1381
1382 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1383 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1384}
1385
1386void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1387{
1388 uint32_t scratch_reg;
1389 int i;
1390
1391 if (rdev->family >= CHIP_R600)
1392 scratch_reg = R600_BIOS_0_SCRATCH;
1393 else
1394 scratch_reg = RADEON_BIOS_0_SCRATCH;
1395
1396 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1397 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1398}
1399
771fe6b9
JG		 1400void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1401{
1402 struct drm_device *dev = encoder->dev;
1403 struct radeon_device *rdev = dev->dev_private;
1404 uint32_t bios_6_scratch;
1405
1406 if (rdev->family >= CHIP_R600)
1407 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1408 else
1409 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1410
1411 if (lock)
1412 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1413 else
1414 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1415
1416 if (rdev->family >= CHIP_R600)
1417 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1418 else
1419 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1420}
1421
1422/* at some point we may want to break this out into individual functions */
1423void
1424radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1425 struct drm_encoder *encoder,
1426 bool connected)
1427{
1428 struct drm_device *dev = connector->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_connector *radeon_connector =
1431 to_radeon_connector(connector);
1432 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1433 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1434
1435 if (rdev->family >= CHIP_R600) {
1436 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1437 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1438 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1439 } else {
1440 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1441 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1442 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1443 }
1444
1445 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1446 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1447 if (connected) {
1448 DRM_DEBUG("TV1 connected\n");
1449 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1450 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1451 } else {
1452 DRM_DEBUG("TV1 disconnected\n");
1453 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1454 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1455 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1456 }
1457 }
1458 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1459 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1460 if (connected) {
1461 DRM_DEBUG("CV connected\n");
1462 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1463 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1464 } else {
1465 DRM_DEBUG("CV disconnected\n");
1466 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1467 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1468 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1469 }
1470 }
1471 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1472 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1473 if (connected) {
1474 DRM_DEBUG("LCD1 connected\n");
1475 bios_0_scratch |= ATOM_S0_LCD1;
1476 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1477 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1478 } else {
1479 DRM_DEBUG("LCD1 disconnected\n");
1480 bios_0_scratch &= ~ATOM_S0_LCD1;
1481 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1482 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1483 }
1484 }
1485 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1486 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1487 if (connected) {
1488 DRM_DEBUG("CRT1 connected\n");
1489 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1490 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1491 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1492 } else {
1493 DRM_DEBUG("CRT1 disconnected\n");
1494 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1495 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1496 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1497 }
1498 }
1499 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1500 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1501 if (connected) {
1502 DRM_DEBUG("CRT2 connected\n");
1503 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1504 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1505 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1506 } else {
1507 DRM_DEBUG("CRT2 disconnected\n");
1508 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1509 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1510 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1511 }
1512 }
1513 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1514 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1515 if (connected) {
1516 DRM_DEBUG("DFP1 connected\n");
1517 bios_0_scratch |= ATOM_S0_DFP1;
1518 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1519 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1520 } else {
1521 DRM_DEBUG("DFP1 disconnected\n");
1522 bios_0_scratch &= ~ATOM_S0_DFP1;
1523 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1524 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1525 }
1526 }
1527 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1528 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1529 if (connected) {
1530 DRM_DEBUG("DFP2 connected\n");
1531 bios_0_scratch |= ATOM_S0_DFP2;
1532 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1533 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1534 } else {
1535 DRM_DEBUG("DFP2 disconnected\n");
1536 bios_0_scratch &= ~ATOM_S0_DFP2;
1537 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1538 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1539 }
1540 }
1541 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1542 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1543 if (connected) {
1544 DRM_DEBUG("DFP3 connected\n");
1545 bios_0_scratch |= ATOM_S0_DFP3;
1546 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1547 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1548 } else {
1549 DRM_DEBUG("DFP3 disconnected\n");
1550 bios_0_scratch &= ~ATOM_S0_DFP3;
1551 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1552 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1553 }
1554 }
1555 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1556 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1557 if (connected) {
1558 DRM_DEBUG("DFP4 connected\n");
1559 bios_0_scratch |= ATOM_S0_DFP4;
1560 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1561 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1562 } else {
1563 DRM_DEBUG("DFP4 disconnected\n");
1564 bios_0_scratch &= ~ATOM_S0_DFP4;
1565 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1566 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1567 }
1568 }
1569 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1570 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1571 if (connected) {
1572 DRM_DEBUG("DFP5 connected\n");
1573 bios_0_scratch |= ATOM_S0_DFP5;
1574 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1575 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1576 } else {
1577 DRM_DEBUG("DFP5 disconnected\n");
1578 bios_0_scratch &= ~ATOM_S0_DFP5;
1579 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1580 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1581 }
1582 }
1583
1584 if (rdev->family >= CHIP_R600) {
1585 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1586 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1587 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1588 } else {
1589 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1590 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1591 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1592 }
1593}
1594
1595void
1596radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1597{
1598 struct drm_device *dev = encoder->dev;
1599 struct radeon_device *rdev = dev->dev_private;
1600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1601 uint32_t bios_3_scratch;
1602
1603 if (rdev->family >= CHIP_R600)
1604 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1605 else
1606 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1607
1608 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1609 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1610 bios_3_scratch |= (crtc << 18);
1611 }
1612 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1613 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1614 bios_3_scratch |= (crtc << 24);
1615 }
1616 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1617 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1618 bios_3_scratch |= (crtc << 16);
1619 }
1620 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1621 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1622 bios_3_scratch |= (crtc << 20);
1623 }
1624 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1625 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1626 bios_3_scratch |= (crtc << 17);
1627 }
1628 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1629 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1630 bios_3_scratch |= (crtc << 19);
1631 }
1632 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1633 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1634 bios_3_scratch |= (crtc << 23);
1635 }
1636 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1637 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1638 bios_3_scratch |= (crtc << 25);
1639 }
1640
1641 if (rdev->family >= CHIP_R600)
1642 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1643 else
1644 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1645}
1646
1647void
1648radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1649{
1650 struct drm_device *dev = encoder->dev;
1651 struct radeon_device *rdev = dev->dev_private;
1652 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1653 uint32_t bios_2_scratch;
1654
1655 if (rdev->family >= CHIP_R600)
1656 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1657 else
1658 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1659
1660 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1661 if (on)
1662 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1663 else
1664 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1665 }
1666 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1667 if (on)
1668 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1669 else
1670 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1671 }
1672 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1673 if (on)
1674 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1675 else
1676 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1677 }
1678 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1679 if (on)
1680 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1681 else
1682 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1683 }
1684 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1685 if (on)
1686 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1687 else
1688 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1689 }
1690 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1691 if (on)
1692 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1693 else
1694 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1695 }
1696 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1697 if (on)
1698 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1699 else
1700 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1701 }
1702 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1703 if (on)
1704 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1705 else
1706 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1707 }
1708 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1709 if (on)
1710 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1711 else
1712 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1713 }
1714 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1715 if (on)
1716 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1717 else
1718 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1719 }
1720
1721 if (rdev->family >= CHIP_R600)
1722 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1723 else
1724 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1725}
Linux kernel - Deliverables
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