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drm/radeon/kms: fix GTT/VRAM overlapping test
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
88 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
91 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
92 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
93 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
94 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
95 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
96 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
97 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
98 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
99 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
100 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
101 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
102 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
103 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
104 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
105
106 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
107 i2c.hw_capable = true;
108 else
109 i2c.hw_capable = false;
110
111 if (gpio->sucI2cId.ucAccess == 0xa0)
112 i2c.mm_i2c = true;
113 else
114 i2c.mm_i2c = false;
115
116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
117
f376b94f
AD		 118 if (i2c.mask_clk_reg)
119 i2c.valid = true;
a084e6ee
AD		 120 break;
121 }
d3f420d1
AD		 122 }
123 }
771fe6b9
JG		 124
125 return i2c;
126}
127
f376b94f
AD		 128void radeon_atombios_i2c_init(struct radeon_device *rdev)
129{
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137 char stmp[32];
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false;
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
166
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
169 else
170 i2c.hw_capable = false;
171
172 if (gpio->sucI2cId.ucAccess == 0xa0)
173 i2c.mm_i2c = true;
174 else
175 i2c.mm_i2c = false;
176
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
178
179 if (i2c.mask_clk_reg) {
180 i2c.valid = true;
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
183 }
184 }
185 }
186}
187
eed45b30
AD		 188static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
189 u8 id)
190{
191 struct atom_context *ctx = rdev->mode_info.atom_context;
192 struct radeon_gpio_rec gpio;
193 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
194 struct _ATOM_GPIO_PIN_LUT *gpio_info;
195 ATOM_GPIO_PIN_ASSIGNMENT *pin;
196 u16 data_offset, size;
197 int i, num_indices;
198
199 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
200 gpio.valid = false;
201
a084e6ee
AD		 202 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
203 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 204
a084e6ee
AD		 205 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
206 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 207
a084e6ee
AD		 208 for (i = 0; i < num_indices; i++) {
209 pin = &gpio_info->asGPIO_Pin[i];
210 if (id == pin->ucGPIO_ID) {
211 gpio.id = pin->ucGPIO_ID;
212 gpio.reg = pin->usGpioPin_AIndex * 4;
213 gpio.mask = (1 << pin->ucGpioPinBitShift);
214 gpio.valid = true;
215 break;
216 }
eed45b30
AD		 217 }
218 }
219
220 return gpio;
221}
222
223static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
224 struct radeon_gpio_rec *gpio)
225{
226 struct radeon_hpd hpd;
bcc1c2a1
AD		 227 u32 reg;
228
229 if (ASIC_IS_DCE4(rdev))
230 reg = EVERGREEN_DC_GPIO_HPD_A;
231 else
232 reg = AVIVO_DC_GPIO_HPD_A;
233
eed45b30 234 hpd.gpio = *gpio;
bcc1c2a1 235 if (gpio->reg == reg) {
eed45b30
AD		 236 switch(gpio->mask) {
237 case (1 << 0):
238 hpd.hpd = RADEON_HPD_1;
239 break;
240 case (1 << 8):
241 hpd.hpd = RADEON_HPD_2;
242 break;
243 case (1 << 16):
244 hpd.hpd = RADEON_HPD_3;
245 break;
246 case (1 << 24):
247 hpd.hpd = RADEON_HPD_4;
248 break;
249 case (1 << 26):
250 hpd.hpd = RADEON_HPD_5;
251 break;
252 case (1 << 28):
253 hpd.hpd = RADEON_HPD_6;
254 break;
255 default:
256 hpd.hpd = RADEON_HPD_NONE;
257 break;
258 }
259 } else
260 hpd.hpd = RADEON_HPD_NONE;
261 return hpd;
262}
263
771fe6b9
JG		 264static bool radeon_atom_apply_quirks(struct drm_device *dev,
265 uint32_t supported_device,
266 int *connector_type,
848577ee 267 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 268 uint16_t *line_mux,
269 struct radeon_hpd *hpd)
771fe6b9 270{
9ea2c4be 271 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 272
273 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
274 if ((dev->pdev->device == 0x791e) &&
275 (dev->pdev->subsystem_vendor == 0x1043) &&
276 (dev->pdev->subsystem_device == 0x826d)) {
277 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
278 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
279 *connector_type = DRM_MODE_CONNECTOR_DVID;
280 }
281
c86a9038
AD		 282 /* Asrock RS600 board lists the DVI port as HDMI */
283 if ((dev->pdev->device == 0x7941) &&
284 (dev->pdev->subsystem_vendor == 0x1849) &&
285 (dev->pdev->subsystem_device == 0x7941)) {
286 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
287 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
288 *connector_type = DRM_MODE_CONNECTOR_DVID;
289 }
290
771fe6b9
JG		 291 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
292 if ((dev->pdev->device == 0x7941) &&
293 (dev->pdev->subsystem_vendor == 0x147b) &&
294 (dev->pdev->subsystem_device == 0x2412)) {
295 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
296 return false;
297 }
298
299 /* Falcon NW laptop lists vga ddc line for LVDS */
300 if ((dev->pdev->device == 0x5653) &&
301 (dev->pdev->subsystem_vendor == 0x1462) &&
302 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 303 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 304 i2c_bus->valid = false;
848577ee
AD		 305 *line_mux = 53;
306 }
771fe6b9
JG		 307 }
308
4e3f9b78
AD		 309 /* HIS X1300 is DVI+VGA, not DVI+DVI */
310 if ((dev->pdev->device == 0x7146) &&
311 (dev->pdev->subsystem_vendor == 0x17af) &&
312 (dev->pdev->subsystem_device == 0x2058)) {
313 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
314 return false;
315 }
316
aa1a750e
DA		 317 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
318 if ((dev->pdev->device == 0x7142) &&
319 (dev->pdev->subsystem_vendor == 0x1458) &&
320 (dev->pdev->subsystem_device == 0x2134)) {
321 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
322 return false;
323 }
324
325
771fe6b9
JG		 326 /* Funky macbooks */
327 if ((dev->pdev->device == 0x71C5) &&
328 (dev->pdev->subsystem_vendor == 0x106b) &&
329 (dev->pdev->subsystem_device == 0x0080)) {
330 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
331 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
332 return false;
e1e8a5dd
AD		 333 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
334 *line_mux = 0x90;
771fe6b9
JG		 335 }
336
771fe6b9
JG		 337 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
338 if ((dev->pdev->device == 0x9598) &&
339 (dev->pdev->subsystem_vendor == 0x1043) &&
340 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 341 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 342 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 343 }
344 }
345
e153b70b
AD		 346 /* ASUS HD 3600 board lists the DVI port as HDMI */
347 if ((dev->pdev->device == 0x9598) &&
348 (dev->pdev->subsystem_vendor == 0x1043) &&
349 (dev->pdev->subsystem_device == 0x01e4)) {
350 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
351 *connector_type = DRM_MODE_CONNECTOR_DVII;
352 }
353 }
354
705af9c7
AD		 355 /* ASUS HD 3450 board lists the DVI port as HDMI */
356 if ((dev->pdev->device == 0x95C5) &&
357 (dev->pdev->subsystem_vendor == 0x1043) &&
358 (dev->pdev->subsystem_device == 0x01e2)) {
359 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 360 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 361 }
362 }
363
705af9c7
AD		 364 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
365 * HDMI + VGA reporting as HDMI
366 */
367 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
368 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
369 *connector_type = DRM_MODE_CONNECTOR_VGA;
370 *line_mux = 0;
371 }
372 }
373
9ea2c4be 374 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 375 if ((dev->pdev->device == 0x95c4) &&
376 (dev->pdev->subsystem_vendor == 0x1025) &&
377 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 378 struct radeon_gpio_rec gpio;
379
3e5f8ff3 380 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 381 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
382 gpio = radeon_lookup_gpio(rdev, 6);
383 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 384 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 385 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
386 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
387 gpio = radeon_lookup_gpio(rdev, 7);
388 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
389 }
3e5f8ff3
AD		 390 }
391
efa8450f
DA		 392 /* XFX Pine Group device rv730 reports no VGA DDC lines
393 * even though they are wired up to record 0x93
394 */
395 if ((dev->pdev->device == 0x9498) &&
396 (dev->pdev->subsystem_vendor == 0x1682) &&
397 (dev->pdev->subsystem_device == 0x2452)) {
398 struct radeon_device *rdev = dev->dev_private;
399 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
400 }
771fe6b9
JG		 401 return true;
402}
403
404const int supported_devices_connector_convert[] = {
405 DRM_MODE_CONNECTOR_Unknown,
406 DRM_MODE_CONNECTOR_VGA,
407 DRM_MODE_CONNECTOR_DVII,
408 DRM_MODE_CONNECTOR_DVID,
409 DRM_MODE_CONNECTOR_DVIA,
410 DRM_MODE_CONNECTOR_SVIDEO,
411 DRM_MODE_CONNECTOR_Composite,
412 DRM_MODE_CONNECTOR_LVDS,
413 DRM_MODE_CONNECTOR_Unknown,
414 DRM_MODE_CONNECTOR_Unknown,
415 DRM_MODE_CONNECTOR_HDMIA,
416 DRM_MODE_CONNECTOR_HDMIB,
417 DRM_MODE_CONNECTOR_Unknown,
418 DRM_MODE_CONNECTOR_Unknown,
419 DRM_MODE_CONNECTOR_9PinDIN,
420 DRM_MODE_CONNECTOR_DisplayPort
421};
422
b75fad06
AD		 423const uint16_t supported_devices_connector_object_id_convert[] = {
424 CONNECTOR_OBJECT_ID_NONE,
425 CONNECTOR_OBJECT_ID_VGA,
426 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
427 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
428 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
429 CONNECTOR_OBJECT_ID_COMPOSITE,
430 CONNECTOR_OBJECT_ID_SVIDEO,
431 CONNECTOR_OBJECT_ID_LVDS,
432 CONNECTOR_OBJECT_ID_9PIN_DIN,
433 CONNECTOR_OBJECT_ID_9PIN_DIN,
434 CONNECTOR_OBJECT_ID_DISPLAYPORT,
435 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
436 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
437 CONNECTOR_OBJECT_ID_SVIDEO
438};
439
771fe6b9
JG		 440const int object_connector_convert[] = {
441 DRM_MODE_CONNECTOR_Unknown,
442 DRM_MODE_CONNECTOR_DVII,
443 DRM_MODE_CONNECTOR_DVII,
444 DRM_MODE_CONNECTOR_DVID,
445 DRM_MODE_CONNECTOR_DVID,
446 DRM_MODE_CONNECTOR_VGA,
447 DRM_MODE_CONNECTOR_Composite,
448 DRM_MODE_CONNECTOR_SVIDEO,
449 DRM_MODE_CONNECTOR_Unknown,
705af9c7 450 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 451 DRM_MODE_CONNECTOR_9PinDIN,
452 DRM_MODE_CONNECTOR_Unknown,
453 DRM_MODE_CONNECTOR_HDMIA,
454 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 455 DRM_MODE_CONNECTOR_LVDS,
456 DRM_MODE_CONNECTOR_9PinDIN,
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 460 DRM_MODE_CONNECTOR_DisplayPort,
461 DRM_MODE_CONNECTOR_eDP,
462 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 463};
464
465bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
466{
467 struct radeon_device *rdev = dev->dev_private;
468 struct radeon_mode_info *mode_info = &rdev->mode_info;
469 struct atom_context *ctx = mode_info->atom_context;
470 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 471 u16 size, data_offset;
472 u8 frev, crev;
771fe6b9 473 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 474 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 475 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
476 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 477 int i, j, k, path_size, device_support;
771fe6b9 478 int connector_type;
eed45b30 479 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 480 bool linkb;
481 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 482 struct radeon_router router;
eed45b30
AD		 483 struct radeon_gpio_rec gpio;
484 struct radeon_hpd hpd;
485
a084e6ee 486 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 487 return false;
488
489 if (crev < 2)
490 return false;
491
26b5bc98
AD		 492 router.valid = false;
493
771fe6b9
JG		 494 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
495 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
496 (ctx->bios + data_offset +
497 le16_to_cpu(obj_header->usDisplayPathTableOffset));
498 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
499 (ctx->bios + data_offset +
500 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 501 router_obj = (ATOM_OBJECT_TABLE *)
502 (ctx->bios + data_offset +
503 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 504 device_support = le16_to_cpu(obj_header->usDeviceSupport);
505
506 path_size = 0;
507 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
508 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
509 ATOM_DISPLAY_OBJECT_PATH *path;
510 addr += path_size;
511 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
512 path_size += le16_to_cpu(path->usSize);
513 linkb = false;
771fe6b9
JG		 514 if (device_support & le16_to_cpu(path->usDeviceTag)) {
515 uint8_t con_obj_id, con_obj_num, con_obj_type;
516
517 con_obj_id =
518 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
519 >> OBJECT_ID_SHIFT;
520 con_obj_num =
521 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
522 >> ENUM_ID_SHIFT;
523 con_obj_type =
524 (le16_to_cpu(path->usConnObjectId) &
525 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
526
4bbd4973
DA		 527 /* TODO CV support */
528 if (le16_to_cpu(path->usDeviceTag) ==
529 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 530 continue;
531
ee59f2b4
AD		 532 /* IGP chips */
533 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 534 (con_obj_id ==
535 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
536 uint16_t igp_offset = 0;
537 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
538
539 index =
540 GetIndexIntoMasterTable(DATA,
541 IntegratedSystemInfo);
542
a084e6ee
AD		 543 if (atom_parse_data_header(ctx, index, &size, &frev,
544 &crev, &igp_offset)) {
545
546 if (crev >= 2) {
547 igp_obj =
548 (ATOM_INTEGRATED_SYSTEM_INFO_V2
549 *) (ctx->bios + igp_offset);
550
551 if (igp_obj) {
552 uint32_t slot_config, ct;
553
554 if (con_obj_num == 1)
555 slot_config =
556 igp_obj->
557 ulDDISlot1Config;
558 else
559 slot_config =
560 igp_obj->
561 ulDDISlot2Config;
562
563 ct = (slot_config >> 16) & 0xff;
564 connector_type =
565 object_connector_convert
566 [ct];
567 connector_object_id = ct;
568 igp_lane_info =
569 slot_config & 0xffff;
570 } else
571 continue;
771fe6b9
JG		 572 } else
573 continue;
a084e6ee
AD		 574 } else {
575 igp_lane_info = 0;
576 connector_type =
577 object_connector_convert[con_obj_id];
578 connector_object_id = con_obj_id;
579 }
771fe6b9
JG		 580 } else {
581 igp_lane_info = 0;
582 connector_type =
583 object_connector_convert[con_obj_id];
b75fad06 584 connector_object_id = con_obj_id;
771fe6b9
JG		 585 }
586
587 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
588 continue;
589
26b5bc98
AD		 590 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
591 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 592
26b5bc98 593 grph_obj_id =
771fe6b9
JG		 594 (le16_to_cpu(path->usGraphicObjIds[j]) &
595 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 596 grph_obj_num =
771fe6b9
JG		 597 (le16_to_cpu(path->usGraphicObjIds[j]) &
598 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 599 grph_obj_type =
771fe6b9
JG		 600 (le16_to_cpu(path->usGraphicObjIds[j]) &
601 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
602
26b5bc98
AD		 603 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
604 if (grph_obj_num == 2)
771fe6b9
JG		 605 linkb = true;
606 else
607 linkb = false;
608
609 radeon_add_atom_encoder(dev,
26b5bc98 610 grph_obj_id,
771fe6b9
JG		 611 le16_to_cpu
612 (path->
613 usDeviceTag));
614
26b5bc98
AD		 615 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
616 router.valid = false;
617 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
618 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
619 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
620 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
621 (ctx->bios + data_offset +
622 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
623 ATOM_I2C_RECORD *i2c_record;
624 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
625 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
626 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
627 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
628 (ctx->bios + data_offset +
629 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
630 int enum_id;
631
632 router.router_id = router_obj_id;
633 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
634 enum_id++) {
635 if (le16_to_cpu(path->usConnObjectId) ==
636 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
637 break;
638 }
639
640 while (record->ucRecordType > 0 &&
641 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
642 switch (record->ucRecordType) {
643 case ATOM_I2C_RECORD_TYPE:
644 i2c_record =
645 (ATOM_I2C_RECORD *)
646 record;
647 i2c_config =
648 (ATOM_I2C_ID_CONFIG_ACCESS *)
649 &i2c_record->sucI2cId;
650 router.i2c_info =
651 radeon_lookup_i2c_gpio(rdev,
652 i2c_config->
653 ucAccess);
654 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
655 break;
656 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
657 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
658 record;
659 router.valid = true;
660 router.mux_type = ddc_path->ucMuxType;
661 router.mux_control_pin = ddc_path->ucMuxControlPin;
662 router.mux_state = ddc_path->ucMuxState[enum_id];
663 break;
664 }
665 record = (ATOM_COMMON_RECORD_HEADER *)
666 ((char *)record + record->ucRecordSize);
667 }
668 }
669 }
771fe6b9
JG		 670 }
671 }
672
eed45b30 673 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 674 ddc_bus.valid = false;
675 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 676 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 677 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 678 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
679 if (le16_to_cpu(path->usConnObjectId) ==
680 le16_to_cpu(con_obj->asObjects[j].
681 usObjectID)) {
682 ATOM_COMMON_RECORD_HEADER
683 *record =
684 (ATOM_COMMON_RECORD_HEADER
685 *)
686 (ctx->bios + data_offset +
687 le16_to_cpu(con_obj->
688 asObjects[j].
689 usRecordOffset));
690 ATOM_I2C_RECORD *i2c_record;
eed45b30 691 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 692 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 693
771fe6b9
JG		 694 while (record->ucRecordType > 0
695 && record->
696 ucRecordType <=
697 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 698 switch (record->ucRecordType) {
771fe6b9
JG		 699 case ATOM_I2C_RECORD_TYPE:
700 i2c_record =
eed45b30
AD		 701 (ATOM_I2C_RECORD *)
702 record;
d3f420d1
AD		 703 i2c_config =
704 (ATOM_I2C_ID_CONFIG_ACCESS *)
705 &i2c_record->sucI2cId;
eed45b30 706 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 707 i2c_config->
708 ucAccess);
eed45b30
AD		 709 break;
710 case ATOM_HPD_INT_RECORD_TYPE:
711 hpd_record =
712 (ATOM_HPD_INT_RECORD *)
713 record;
714 gpio = radeon_lookup_gpio(rdev,
715 hpd_record->ucHPDIntGPIOID);
716 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
717 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 718 break;
719 }
720 record =
721 (ATOM_COMMON_RECORD_HEADER
722 *) ((char *)record
723 +
724 record->
725 ucRecordSize);
726 }
727 break;
728 }
729 }
eed45b30 730 }
771fe6b9 731
bcc1c2a1 732 /* needed for aux chan transactions */
8e36ed00 733 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 734
705af9c7
AD		 735 conn_id = le16_to_cpu(path->usConnObjectId);
736
737 if (!radeon_atom_apply_quirks
738 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 739 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 740 continue;
741
771fe6b9 742 radeon_add_atom_connector(dev,
705af9c7 743 conn_id,
771fe6b9
JG		 744 le16_to_cpu(path->
745 usDeviceTag),
746 connector_type, &ddc_bus,
b75fad06 747 linkb, igp_lane_info,
eed45b30 748 connector_object_id,
26b5bc98
AD		 749 &hpd,
750 &router);
771fe6b9
JG		 751
752 }
753 }
754
755 radeon_link_encoder_connector(dev);
756
757 return true;
758}
759
b75fad06
AD		 760static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
761 int connector_type,
762 uint16_t devices)
763{
764 struct radeon_device *rdev = dev->dev_private;
765
766 if (rdev->flags & RADEON_IS_IGP) {
767 return supported_devices_connector_object_id_convert
768 [connector_type];
769 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
770 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
771 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
772 struct radeon_mode_info *mode_info = &rdev->mode_info;
773 struct atom_context *ctx = mode_info->atom_context;
774 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
775 uint16_t size, data_offset;
776 uint8_t frev, crev;
777 ATOM_XTMDS_INFO *xtmds;
778
a084e6ee
AD		 779 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
780 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 781
a084e6ee
AD		 782 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
783 if (connector_type == DRM_MODE_CONNECTOR_DVII)
784 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
785 else
786 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
787 } else {
788 if (connector_type == DRM_MODE_CONNECTOR_DVII)
789 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
790 else
791 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
792 }
793 } else
794 return supported_devices_connector_object_id_convert
795 [connector_type];
b75fad06
AD		 796 } else {
797 return supported_devices_connector_object_id_convert
798 [connector_type];
799 }
800}
801
771fe6b9
JG		 802struct bios_connector {
803 bool valid;
705af9c7 804 uint16_t line_mux;
771fe6b9
JG		 805 uint16_t devices;
806 int connector_type;
807 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 808 struct radeon_hpd hpd;
771fe6b9
JG		 809};
810
811bool radeon_get_atom_connector_info_from_supported_devices_table(struct
812 drm_device
813 *dev)
814{
815 struct radeon_device *rdev = dev->dev_private;
816 struct radeon_mode_info *mode_info = &rdev->mode_info;
817 struct atom_context *ctx = mode_info->atom_context;
818 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
819 uint16_t size, data_offset;
820 uint8_t frev, crev;
821 uint16_t device_support;
822 uint8_t dac;
823 union atom_supported_devices *supported_devices;
eed45b30 824 int i, j, max_device;
f49d273d
PB		 825 struct bios_connector *bios_connectors;
826 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 827 struct radeon_router router;
828
829 router.valid = false;
771fe6b9 830
f49d273d
PB		 831 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
832 if (!bios_connectors)
833 return false;
834
835 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
836 &data_offset)) {
837 kfree(bios_connectors);
a084e6ee 838 return false;
f49d273d 839 }
771fe6b9
JG		 840
841 supported_devices =
842 (union atom_supported_devices *)(ctx->bios + data_offset);
843
844 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
845
eed45b30
AD		 846 if (frev > 1)
847 max_device = ATOM_MAX_SUPPORTED_DEVICE;
848 else
849 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
850
851 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 852 ATOM_CONNECTOR_INFO_I2C ci =
853 supported_devices->info.asConnInfo[i];
854
855 bios_connectors[i].valid = false;
856
857 if (!(device_support & (1 << i))) {
858 continue;
859 }
860
861 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 862 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 863 continue;
864 }
865
771fe6b9
JG		 866 bios_connectors[i].connector_type =
867 supported_devices_connector_convert[ci.sucConnectorInfo.
868 sbfAccess.
869 bfConnectorType];
870
871 if (bios_connectors[i].connector_type ==
872 DRM_MODE_CONNECTOR_Unknown)
873 continue;
874
875 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
876
d3f420d1
AD		 877 bios_connectors[i].line_mux =
878 ci.sucI2cId.ucAccess;
771fe6b9
JG		 879
880 /* give tv unique connector ids */
881 if (i == ATOM_DEVICE_TV1_INDEX) {
882 bios_connectors[i].ddc_bus.valid = false;
883 bios_connectors[i].line_mux = 50;
884 } else if (i == ATOM_DEVICE_TV2_INDEX) {
885 bios_connectors[i].ddc_bus.valid = false;
886 bios_connectors[i].line_mux = 51;
887 } else if (i == ATOM_DEVICE_CV_INDEX) {
888 bios_connectors[i].ddc_bus.valid = false;
889 bios_connectors[i].line_mux = 52;
890 } else
891 bios_connectors[i].ddc_bus =
eed45b30
AD		 892 radeon_lookup_i2c_gpio(rdev,
893 bios_connectors[i].line_mux);
894
895 if ((crev > 1) && (frev > 1)) {
896 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
897 switch (isb) {
898 case 0x4:
899 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
900 break;
901 case 0xa:
902 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
903 break;
904 default:
905 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
906 break;
907 }
908 } else {
909 if (i == ATOM_DEVICE_DFP1_INDEX)
910 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
911 else if (i == ATOM_DEVICE_DFP2_INDEX)
912 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
913 else
914 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
915 }
771fe6b9
JG		 916
917 /* Always set the connector type to VGA for CRT1/CRT2. if they are
918 * shared with a DVI port, we'll pick up the DVI connector when we
919 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
920 */
921 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
922 bios_connectors[i].connector_type =
923 DRM_MODE_CONNECTOR_VGA;
924
925 if (!radeon_atom_apply_quirks
926 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 927 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
928 &bios_connectors[i].hpd))
771fe6b9
JG		 929 continue;
930
931 bios_connectors[i].valid = true;
932 bios_connectors[i].devices = (1 << i);
933
934 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
935 radeon_add_atom_encoder(dev,
936 radeon_get_encoder_id(dev,
937 (1 << i),
938 dac),
939 (1 << i));
940 else
941 radeon_add_legacy_encoder(dev,
942 radeon_get_encoder_id(dev,
f56cd64f 943 (1 << i),
771fe6b9
JG		 944 dac),
945 (1 << i));
946 }
947
948 /* combine shared connectors */
eed45b30 949 for (i = 0; i < max_device; i++) {
771fe6b9 950 if (bios_connectors[i].valid) {
eed45b30 951 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 952 if (bios_connectors[j].valid && (i != j)) {
953 if (bios_connectors[i].line_mux ==
954 bios_connectors[j].line_mux) {
f56cd64f
AD		 955 /* make sure not to combine LVDS */
956 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
957 bios_connectors[i].line_mux = 53;
958 bios_connectors[i].ddc_bus.valid = false;
959 continue;
960 }
961 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
962 bios_connectors[j].line_mux = 53;
963 bios_connectors[j].ddc_bus.valid = false;
964 continue;
965 }
966 /* combine analog and digital for DVI-I */
967 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
968 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
969 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
970 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
971 bios_connectors[i].devices |=
972 bios_connectors[j].devices;
973 bios_connectors[i].connector_type =
974 DRM_MODE_CONNECTOR_DVII;
975 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 976 bios_connectors[i].hpd =
977 bios_connectors[j].hpd;
f56cd64f 978 bios_connectors[j].valid = false;
771fe6b9
JG		 979 }
980 }
981 }
982 }
983 }
984 }
985
986 /* add the connectors */
eed45b30 987 for (i = 0; i < max_device; i++) {
b75fad06
AD		 988 if (bios_connectors[i].valid) {
989 uint16_t connector_object_id =
990 atombios_get_connector_object_id(dev,
991 bios_connectors[i].connector_type,
992 bios_connectors[i].devices);
771fe6b9
JG		 993 radeon_add_atom_connector(dev,
994 bios_connectors[i].line_mux,
995 bios_connectors[i].devices,
996 bios_connectors[i].
997 connector_type,
998 &bios_connectors[i].ddc_bus,
b75fad06 999 false, 0,
eed45b30 1000 connector_object_id,
26b5bc98
AD		 1001 &bios_connectors[i].hpd,
1002 &router);
b75fad06 1003 }
771fe6b9
JG		 1004 }
1005
1006 radeon_link_encoder_connector(dev);
1007
f49d273d 1008 kfree(bios_connectors);
771fe6b9
JG		 1009 return true;
1010}
1011
1012union firmware_info {
1013 ATOM_FIRMWARE_INFO info;
1014 ATOM_FIRMWARE_INFO_V1_2 info_12;
1015 ATOM_FIRMWARE_INFO_V1_3 info_13;
1016 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1017 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1018};
1019
1020bool radeon_atom_get_clock_info(struct drm_device *dev)
1021{
1022 struct radeon_device *rdev = dev->dev_private;
1023 struct radeon_mode_info *mode_info = &rdev->mode_info;
1024 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1025 union firmware_info *firmware_info;
1026 uint8_t frev, crev;
1027 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1028 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1029 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1030 struct radeon_pll *spll = &rdev->clock.spll;
1031 struct radeon_pll *mpll = &rdev->clock.mpll;
1032 uint16_t data_offset;
1033
a084e6ee
AD		 1034 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1035 &frev, &crev, &data_offset)) {
1036 firmware_info =
1037 (union firmware_info *)(mode_info->atom_context->bios +
1038 data_offset);
771fe6b9
JG		 1039 /* pixel clocks */
1040 p1pll->reference_freq =
1041 le16_to_cpu(firmware_info->info.usReferenceClock);
1042 p1pll->reference_div = 0;
1043
bc293e58
MF		 1044 if (crev < 2)
1045 p1pll->pll_out_min =
1046 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1047 else
1048 p1pll->pll_out_min =
1049 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1050 p1pll->pll_out_max =
1051 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1052
86cb2bbf
AD		 1053 if (crev >= 4) {
1054 p1pll->lcd_pll_out_min =
1055 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1056 if (p1pll->lcd_pll_out_min == 0)
1057 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1058 p1pll->lcd_pll_out_max =
1059 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1060 if (p1pll->lcd_pll_out_max == 0)
1061 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1062 } else {
1063 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1064 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1065 }
1066
771fe6b9
JG		 1067 if (p1pll->pll_out_min == 0) {
1068 if (ASIC_IS_AVIVO(rdev))
1069 p1pll->pll_out_min = 64800;
1070 else
1071 p1pll->pll_out_min = 20000;
8f552a66
AD		 1072 } else if (p1pll->pll_out_min > 64800) {
1073 /* Limiting the pll output range is a good thing generally as
1074 * it limits the number of possible pll combinations for a given
1075 * frequency presumably to the ones that work best on each card.
1076 * However, certain duallink DVI monitors seem to like
1077 * pll combinations that would be limited by this at least on
1078 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1079 * family.
1080 */
b27b6375
AD		 1081 if (!radeon_new_pll)
1082 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1083 }
1084
1085 p1pll->pll_in_min =
1086 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1087 p1pll->pll_in_max =
1088 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1089
1090 *p2pll = *p1pll;
1091
1092 /* system clock */
1093 spll->reference_freq =
1094 le16_to_cpu(firmware_info->info.usReferenceClock);
1095 spll->reference_div = 0;
1096
1097 spll->pll_out_min =
1098 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1099 spll->pll_out_max =
1100 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1101
1102 /* ??? */
1103 if (spll->pll_out_min == 0) {
1104 if (ASIC_IS_AVIVO(rdev))
1105 spll->pll_out_min = 64800;
1106 else
1107 spll->pll_out_min = 20000;
1108 }
1109
1110 spll->pll_in_min =
1111 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1112 spll->pll_in_max =
1113 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1114
1115 /* memory clock */
1116 mpll->reference_freq =
1117 le16_to_cpu(firmware_info->info.usReferenceClock);
1118 mpll->reference_div = 0;
1119
1120 mpll->pll_out_min =
1121 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1122 mpll->pll_out_max =
1123 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1124
1125 /* ??? */
1126 if (mpll->pll_out_min == 0) {
1127 if (ASIC_IS_AVIVO(rdev))
1128 mpll->pll_out_min = 64800;
1129 else
1130 mpll->pll_out_min = 20000;
1131 }
1132
1133 mpll->pll_in_min =
1134 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1135 mpll->pll_in_max =
1136 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1137
1138 rdev->clock.default_sclk =
1139 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1140 rdev->clock.default_mclk =
1141 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1142
bcc1c2a1
AD		 1143 if (ASIC_IS_DCE4(rdev)) {
1144 rdev->clock.default_dispclk =
1145 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1146 if (rdev->clock.default_dispclk == 0)
1147 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1148 rdev->clock.dp_extclk =
1149 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1150 }
1151 *dcpll = *p1pll;
1152
771fe6b9
JG		 1153 return true;
1154 }
bcc1c2a1 1155
771fe6b9
JG		 1156 return false;
1157}
1158
06b6476d
AD		 1159union igp_info {
1160 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1161 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1162};
1163
1164bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1165{
1166 struct radeon_mode_info *mode_info = &rdev->mode_info;
1167 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1168 union igp_info *igp_info;
1169 u8 frev, crev;
1170 u16 data_offset;
1171
4c70b2ea
AD		 1172 /* sideport is AMD only */
1173 if (rdev->family == CHIP_RS600)
1174 return false;
1175
a084e6ee
AD		 1176 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1177 &frev, &crev, &data_offset)) {
1178 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1179 data_offset);
06b6476d
AD		 1180 switch (crev) {
1181 case 1:
4c70b2ea
AD		 1182 if (igp_info->info.ulBootUpMemoryClock)
1183 return true;
06b6476d
AD		 1184 break;
1185 case 2:
1186 if (igp_info->info_2.ucMemoryType & 0x0f)
1187 return true;
1188 break;
1189 default:
1190 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1191 break;
1192 }
1193 }
1194 return false;
1195}
1196
445282db
DA		 1197bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1198 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1199{
1200 struct drm_device *dev = encoder->base.dev;
1201 struct radeon_device *rdev = dev->dev_private;
1202 struct radeon_mode_info *mode_info = &rdev->mode_info;
1203 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1204 uint16_t data_offset;
1205 struct _ATOM_TMDS_INFO *tmds_info;
1206 uint8_t frev, crev;
1207 uint16_t maxfreq;
1208 int i;
771fe6b9 1209
a084e6ee
AD		 1210 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1211 &frev, &crev, &data_offset)) {
1212 tmds_info =
1213 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1214 data_offset);
771fe6b9 1215
771fe6b9
JG		 1216 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1217 for (i = 0; i < 4; i++) {
1218 tmds->tmds_pll[i].freq =
1219 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1220 tmds->tmds_pll[i].value =
1221 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1222 tmds->tmds_pll[i].value |=
1223 (tmds_info->asMiscInfo[i].
1224 ucPLL_VCO_Gain & 0x3f) << 6;
1225 tmds->tmds_pll[i].value |=
1226 (tmds_info->asMiscInfo[i].
1227 ucPLL_DutyCycle & 0xf) << 12;
1228 tmds->tmds_pll[i].value |=
1229 (tmds_info->asMiscInfo[i].
1230 ucPLL_VoltageSwing & 0xf) << 16;
1231
d9fdaafb 1232 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1233 tmds->tmds_pll[i].freq,
1234 tmds->tmds_pll[i].value);
1235
1236 if (maxfreq == tmds->tmds_pll[i].freq) {
1237 tmds->tmds_pll[i].freq = 0xffffffff;
1238 break;
1239 }
1240 }
445282db 1241 return true;
771fe6b9 1242 }
445282db 1243 return false;
771fe6b9
JG		 1244}
1245
ebbe1cb9
AD		 1246static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1247 radeon_encoder
1248 *encoder,
1249 int id)
1250{
1251 struct drm_device *dev = encoder->base.dev;
1252 struct radeon_device *rdev = dev->dev_private;
1253 struct radeon_mode_info *mode_info = &rdev->mode_info;
1254 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1255 uint16_t data_offset;
1256 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1257 uint8_t frev, crev;
1258 struct radeon_atom_ss *ss = NULL;
279b215e 1259 int i;
ebbe1cb9
AD		 1260
1261 if (id > ATOM_MAX_SS_ENTRY)
1262 return NULL;
1263
a084e6ee
AD		 1264 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1265 &frev, &crev, &data_offset)) {
1266 ss_info =
1267 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1268
ebbe1cb9
AD		 1269 ss =
1270 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1271
1272 if (!ss)
1273 return NULL;
1274
279b215e
AD		 1275 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1276 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1277 ss->percentage =
1278 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1279 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1280 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1281 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1282 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1283 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1284 break;
279b215e
AD		 1285 }
1286 }
ebbe1cb9
AD		 1287 }
1288 return ss;
1289}
1290
771fe6b9
JG		 1291union lvds_info {
1292 struct _ATOM_LVDS_INFO info;
1293 struct _ATOM_LVDS_INFO_V12 info_12;
1294};
1295
1296struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1297 radeon_encoder
1298 *encoder)
1299{
1300 struct drm_device *dev = encoder->base.dev;
1301 struct radeon_device *rdev = dev->dev_private;
1302 struct radeon_mode_info *mode_info = &rdev->mode_info;
1303 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1304 uint16_t data_offset, misc;
771fe6b9
JG		 1305 union lvds_info *lvds_info;
1306 uint8_t frev, crev;
1307 struct radeon_encoder_atom_dig *lvds = NULL;
1308
a084e6ee
AD		 1309 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1310 &frev, &crev, &data_offset)) {
1311 lvds_info =
1312 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1313 lvds =
1314 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1315
1316 if (!lvds)
1317 return NULL;
1318
de2103e4 1319 lvds->native_mode.clock =
771fe6b9 1320 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1321 lvds->native_mode.hdisplay =
771fe6b9 1322 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1323 lvds->native_mode.vdisplay =
771fe6b9 1324 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1325 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1326 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1327 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1328 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1329 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1330 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1331 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1332 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1333 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1334 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1335 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1336 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1337 lvds->panel_pwr_delay =
1338 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1339 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1340
1341 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1342 if (misc & ATOM_VSYNC_POLARITY)
1343 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1344 if (misc & ATOM_HSYNC_POLARITY)
1345 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1346 if (misc & ATOM_COMPOSITESYNC)
1347 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1348 if (misc & ATOM_INTERLACE)
1349 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1350 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1351 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1352
de2103e4
AD		 1353 /* set crtc values */
1354 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1355
ebbe1cb9
AD		 1356 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1357
7c27f87d 1358 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1359 if (radeon_new_pll == 0)
1360 lvds->pll_algo = PLL_ALGO_LEGACY;
1361 else
1362 lvds->pll_algo = PLL_ALGO_NEW;
1363 } else {
1364 if (radeon_new_pll == 1)
1365 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1366 else
1367 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1368 }
7c27f87d 1369
771fe6b9
JG		 1370 encoder->native_mode = lvds->native_mode;
1371 }
1372 return lvds;
1373}
1374
6fe7ac3f
AD		 1375struct radeon_encoder_primary_dac *
1376radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1377{
1378 struct drm_device *dev = encoder->base.dev;
1379 struct radeon_device *rdev = dev->dev_private;
1380 struct radeon_mode_info *mode_info = &rdev->mode_info;
1381 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1382 uint16_t data_offset;
1383 struct _COMPASSIONATE_DATA *dac_info;
1384 uint8_t frev, crev;
1385 uint8_t bg, dac;
6fe7ac3f
AD		 1386 struct radeon_encoder_primary_dac *p_dac = NULL;
1387
a084e6ee
AD		 1388 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1389 &frev, &crev, &data_offset)) {
1390 dac_info = (struct _COMPASSIONATE_DATA *)
1391 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1392
6fe7ac3f
AD		 1393 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1394
1395 if (!p_dac)
1396 return NULL;
1397
1398 bg = dac_info->ucDAC1_BG_Adjustment;
1399 dac = dac_info->ucDAC1_DAC_Adjustment;
1400 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1401
1402 }
1403 return p_dac;
1404}
1405
4ce001ab 1406bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1407 struct drm_display_mode *mode)
4ce001ab
DA		 1408{
1409 struct radeon_mode_info *mode_info = &rdev->mode_info;
1410 ATOM_ANALOG_TV_INFO *tv_info;
1411 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1412 ATOM_DTD_FORMAT *dtd_timings;
1413 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1414 u8 frev, crev;
5a9bcacc 1415 u16 data_offset, misc;
4ce001ab 1416
a084e6ee
AD		 1417 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1418 &frev, &crev, &data_offset))
1419 return false;
4ce001ab
DA		 1420
1421 switch (crev) {
1422 case 1:
1423 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1424 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1425 return false;
1426
5a9bcacc
AD		 1427 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1428 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1429 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1430 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1431 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1432
1433 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1434 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1435 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1436 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1437 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1438
1439 mode->flags = 0;
1440 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1441 if (misc & ATOM_VSYNC_POLARITY)
1442 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1443 if (misc & ATOM_HSYNC_POLARITY)
1444 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1445 if (misc & ATOM_COMPOSITESYNC)
1446 mode->flags |= DRM_MODE_FLAG_CSYNC;
1447 if (misc & ATOM_INTERLACE)
1448 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1449 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1450 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1451
1452 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1453
1454 if (index == 1) {
1455 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1456 mode->crtc_htotal -= 1;
1457 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1458 }
1459 break;
1460 case 2:
1461 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1462 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1463 return false;
1464
1465 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1466 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1467 le16_to_cpu(dtd_timings->usHBlanking_Time);
1468 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1469 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1470 le16_to_cpu(dtd_timings->usHSyncOffset);
1471 mode->crtc_hsync_end = mode->crtc_hsync_start +
1472 le16_to_cpu(dtd_timings->usHSyncWidth);
1473
1474 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1475 le16_to_cpu(dtd_timings->usVBlanking_Time);
1476 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1477 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1478 le16_to_cpu(dtd_timings->usVSyncOffset);
1479 mode->crtc_vsync_end = mode->crtc_vsync_start +
1480 le16_to_cpu(dtd_timings->usVSyncWidth);
1481
1482 mode->flags = 0;
1483 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1484 if (misc & ATOM_VSYNC_POLARITY)
1485 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1486 if (misc & ATOM_HSYNC_POLARITY)
1487 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1488 if (misc & ATOM_COMPOSITESYNC)
1489 mode->flags |= DRM_MODE_FLAG_CSYNC;
1490 if (misc & ATOM_INTERLACE)
1491 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1492 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1493 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1494
1495 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1496 break;
1497 }
1498 return true;
1499}
1500
d79766fa
AD		 1501enum radeon_tv_std
1502radeon_atombios_get_tv_info(struct radeon_device *rdev)
1503{
1504 struct radeon_mode_info *mode_info = &rdev->mode_info;
1505 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1506 uint16_t data_offset;
1507 uint8_t frev, crev;
1508 struct _ATOM_ANALOG_TV_INFO *tv_info;
1509 enum radeon_tv_std tv_std = TV_STD_NTSC;
1510
a084e6ee
AD		 1511 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1512 &frev, &crev, &data_offset)) {
d79766fa 1513
a084e6ee
AD		 1514 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1515 (mode_info->atom_context->bios + data_offset);
d79766fa 1516
a084e6ee
AD		 1517 switch (tv_info->ucTV_BootUpDefaultStandard) {
1518 case ATOM_TV_NTSC:
1519 tv_std = TV_STD_NTSC;
1520 DRM_INFO("Default TV standard: NTSC\n");
1521 break;
1522 case ATOM_TV_NTSCJ:
1523 tv_std = TV_STD_NTSC_J;
1524 DRM_INFO("Default TV standard: NTSC-J\n");
1525 break;
1526 case ATOM_TV_PAL:
1527 tv_std = TV_STD_PAL;
1528 DRM_INFO("Default TV standard: PAL\n");
1529 break;
1530 case ATOM_TV_PALM:
1531 tv_std = TV_STD_PAL_M;
1532 DRM_INFO("Default TV standard: PAL-M\n");
1533 break;
1534 case ATOM_TV_PALN:
1535 tv_std = TV_STD_PAL_N;
1536 DRM_INFO("Default TV standard: PAL-N\n");
1537 break;
1538 case ATOM_TV_PALCN:
1539 tv_std = TV_STD_PAL_CN;
1540 DRM_INFO("Default TV standard: PAL-CN\n");
1541 break;
1542 case ATOM_TV_PAL60:
1543 tv_std = TV_STD_PAL_60;
1544 DRM_INFO("Default TV standard: PAL-60\n");
1545 break;
1546 case ATOM_TV_SECAM:
1547 tv_std = TV_STD_SECAM;
1548 DRM_INFO("Default TV standard: SECAM\n");
1549 break;
1550 default:
1551 tv_std = TV_STD_NTSC;
1552 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1553 break;
1554 }
d79766fa
AD		 1555 }
1556 return tv_std;
1557}
1558
6fe7ac3f
AD		 1559struct radeon_encoder_tv_dac *
1560radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1561{
1562 struct drm_device *dev = encoder->base.dev;
1563 struct radeon_device *rdev = dev->dev_private;
1564 struct radeon_mode_info *mode_info = &rdev->mode_info;
1565 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1566 uint16_t data_offset;
1567 struct _COMPASSIONATE_DATA *dac_info;
1568 uint8_t frev, crev;
1569 uint8_t bg, dac;
6fe7ac3f
AD		 1570 struct radeon_encoder_tv_dac *tv_dac = NULL;
1571
a084e6ee
AD		 1572 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1573 &frev, &crev, &data_offset)) {
6fe7ac3f 1574
a084e6ee
AD		 1575 dac_info = (struct _COMPASSIONATE_DATA *)
1576 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1577
6fe7ac3f
AD		 1578 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1579
1580 if (!tv_dac)
1581 return NULL;
1582
1583 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1584 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1585 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1586
1587 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1588 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1589 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1590
1591 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1592 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1593 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1594
d79766fa 1595 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1596 }
1597 return tv_dac;
1598}
1599
29fb52ca
AD		 1600static const char *thermal_controller_names[] = {
1601 "NONE",
678e7dfa
AD		 1602 "lm63",
1603 "adm1032",
1604 "adm1030",
1605 "max6649",
1606 "lm64",
1607 "f75375",
1608 "asc7xxx",
29fb52ca
AD		 1609};
1610
1611static const char *pp_lib_thermal_controller_names[] = {
1612 "NONE",
678e7dfa
AD		 1613 "lm63",
1614 "adm1032",
1615 "adm1030",
1616 "max6649",
1617 "lm64",
1618 "f75375",
29fb52ca
AD		 1619 "RV6xx",
1620 "RV770",
678e7dfa 1621 "adt7473",
49f65982
AD		 1622 "External GPIO",
1623 "Evergreen",
678e7dfa 1624 "adt7473 with internal",
49f65982 1625
29fb52ca
AD		 1626};
1627
56278a8e
AD		 1628union power_info {
1629 struct _ATOM_POWERPLAY_INFO info;
1630 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1631 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1632 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1633};
1634
1635void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1636{
56278a8e
AD		 1637 struct radeon_mode_info *mode_info = &rdev->mode_info;
1638 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1639 u16 data_offset;
1640 u8 frev, crev;
1641 u32 misc, misc2 = 0, sclk, mclk;
1642 union power_info *power_info;
1643 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1644 struct _ATOM_PPLIB_STATE *power_state;
1645 int num_modes = 0, i, j;
1646 int state_index = 0, mode_index = 0;
29fb52ca 1647 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1648
a48b9b4e 1649 rdev->pm.default_power_state_index = -1;
56278a8e 1650
a084e6ee
AD		 1651 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1652 &frev, &crev, &data_offset)) {
1653 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1654 if (frev < 4) {
29fb52ca
AD		 1655 /* add the i2c bus for thermal/fan chip */
1656 if (power_info->info.ucOverdriveThermalController > 0) {
1657 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1658 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1659 power_info->info.ucOverdriveControllerAddress >> 1);
1660 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
f376b94f 1661 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1662 if (rdev->pm.i2c_bus) {
1663 struct i2c_board_info info = { };
1664 const char *name = thermal_controller_names[power_info->info.
1665 ucOverdriveThermalController];
1666 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1667 strlcpy(info.type, name, sizeof(info.type));
1668 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1669 }
29fb52ca 1670 }
56278a8e
AD		 1671 num_modes = power_info->info.ucNumOfPowerModeEntries;
1672 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1673 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1674 /* last mode is usually default, array is low to high */
56278a8e
AD		 1675 for (i = 0; i < num_modes; i++) {
1676 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1677 switch (frev) {
1678 case 1:
1679 rdev->pm.power_state[state_index].num_clock_modes = 1;
1680 rdev->pm.power_state[state_index].clock_info[0].mclk =
1681 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1682 rdev->pm.power_state[state_index].clock_info[0].sclk =
1683 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1684 /* skip invalid modes */
1685 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1686 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1687 continue;
79daedc9 1688 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1689 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1690 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1691 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1692 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1693 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1694 VOLTAGE_GPIO;
1695 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1696 radeon_lookup_gpio(rdev,
1697 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1698 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1699 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1700 true;
1701 else
1702 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1703 false;
1704 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1705 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1706 VOLTAGE_VDDC;
1707 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1708 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1709 }
d7311171 1710 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1711 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1712 /* order matters! */
1713 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1714 rdev->pm.power_state[state_index].type =
1715 POWER_STATE_TYPE_POWERSAVE;
1716 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1717 rdev->pm.power_state[state_index].type =
1718 POWER_STATE_TYPE_BATTERY;
1719 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1720 rdev->pm.power_state[state_index].type =
1721 POWER_STATE_TYPE_BATTERY;
1722 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1723 rdev->pm.power_state[state_index].type =
1724 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1725 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1726 rdev->pm.power_state[state_index].type =
1727 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1728 rdev->pm.power_state[state_index].flags &=
d7311171 1729 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1730 }
56278a8e 1731 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1732 rdev->pm.power_state[state_index].type =
1733 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1734 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1735 rdev->pm.power_state[state_index].default_clock_mode =
1736 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1737 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1738 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1739 } else if (state_index == 0) {
1740 rdev->pm.power_state[state_index].clock_info[0].flags |=
1741 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1742 }
1743 state_index++;
1744 break;
1745 case 2:
1746 rdev->pm.power_state[state_index].num_clock_modes = 1;
1747 rdev->pm.power_state[state_index].clock_info[0].mclk =
1748 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1749 rdev->pm.power_state[state_index].clock_info[0].sclk =
1750 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1751 /* skip invalid modes */
1752 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1753 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1754 continue;
79daedc9 1755 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1756 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1757 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1758 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1759 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1760 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1761 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1762 VOLTAGE_GPIO;
1763 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1764 radeon_lookup_gpio(rdev,
1765 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1766 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1767 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1768 true;
1769 else
1770 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1771 false;
1772 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1773 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1774 VOLTAGE_VDDC;
1775 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1776 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1777 }
d7311171 1778 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1779 rdev->pm.power_state[state_index].misc = misc;
1780 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1781 /* order matters! */
1782 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1783 rdev->pm.power_state[state_index].type =
1784 POWER_STATE_TYPE_POWERSAVE;
1785 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1786 rdev->pm.power_state[state_index].type =
1787 POWER_STATE_TYPE_BATTERY;
1788 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1789 rdev->pm.power_state[state_index].type =
1790 POWER_STATE_TYPE_BATTERY;
1791 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1792 rdev->pm.power_state[state_index].type =
1793 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1794 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1795 rdev->pm.power_state[state_index].type =
1796 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1797 rdev->pm.power_state[state_index].flags &=
d7311171 1798 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1799 }
0ec0e74f
AD		 1800 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1801 rdev->pm.power_state[state_index].type =
1802 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1803 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1804 rdev->pm.power_state[state_index].flags &=
d7311171 1805 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1806 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1807 rdev->pm.power_state[state_index].type =
1808 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1809 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1810 rdev->pm.power_state[state_index].default_clock_mode =
1811 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1812 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1813 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1814 } else if (state_index == 0) {
1815 rdev->pm.power_state[state_index].clock_info[0].flags |=
1816 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1817 }
1818 state_index++;
1819 break;
1820 case 3:
1821 rdev->pm.power_state[state_index].num_clock_modes = 1;
1822 rdev->pm.power_state[state_index].clock_info[0].mclk =
1823 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1824 rdev->pm.power_state[state_index].clock_info[0].sclk =
1825 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1826 /* skip invalid modes */
1827 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1828 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1829 continue;
79daedc9 1830 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1831 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1832 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1833 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1834 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1835 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1836 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1837 VOLTAGE_GPIO;
1838 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1839 radeon_lookup_gpio(rdev,
1840 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1841 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1842 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1843 true;
1844 else
1845 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1846 false;
1847 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1848 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1849 VOLTAGE_VDDC;
1850 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1851 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1852 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1853 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1854 true;
1855 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1856 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1857 }
1858 }
d7311171 1859 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1860 rdev->pm.power_state[state_index].misc = misc;
1861 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1862 /* order matters! */
1863 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1864 rdev->pm.power_state[state_index].type =
1865 POWER_STATE_TYPE_POWERSAVE;
1866 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1867 rdev->pm.power_state[state_index].type =
1868 POWER_STATE_TYPE_BATTERY;
1869 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1870 rdev->pm.power_state[state_index].type =
1871 POWER_STATE_TYPE_BATTERY;
1872 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1873 rdev->pm.power_state[state_index].type =
1874 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1875 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1876 rdev->pm.power_state[state_index].type =
1877 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1878 rdev->pm.power_state[state_index].flags &=
d7311171 1879 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1880 }
0ec0e74f
AD		 1881 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1882 rdev->pm.power_state[state_index].type =
1883 POWER_STATE_TYPE_BALANCED;
56278a8e 1884 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1885 rdev->pm.power_state[state_index].type =
1886 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1887 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1888 rdev->pm.power_state[state_index].default_clock_mode =
1889 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1890 } else if (state_index == 0) {
1891 rdev->pm.power_state[state_index].clock_info[0].flags |=
1892 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1893 }
1894 state_index++;
1895 break;
1896 }
1897 }
02b17cc0 1898 /* last mode is usually default */
a48b9b4e 1899 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1900 rdev->pm.power_state[state_index - 1].type =
1901 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1902 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1903 rdev->pm.power_state[state_index - 1].default_clock_mode =
1904 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1905 rdev->pm.power_state[state_index].flags &=
d7311171 1906 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1907 rdev->pm.power_state[state_index].misc = 0;
1908 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1909 }
49f65982 1910 } else {
c5e8ce61
AD		 1911 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1912 uint8_t fw_frev, fw_crev;
1913 uint16_t fw_data_offset, vddc = 0;
1914 union firmware_info *firmware_info;
1915 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1916
1917 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1918 &fw_frev, &fw_crev, &fw_data_offset)) {
1919 firmware_info =
1920 (union firmware_info *)(mode_info->atom_context->bios +
1921 fw_data_offset);
1922 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1923 }
1924
29fb52ca 1925 /* add the i2c bus for thermal/fan chip */
678e7dfa 1926 if (controller->ucType > 0) {
21a8122a 1927 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 1928 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1929 (controller->ucFanParameters &
29fb52ca 1930 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 1931 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1932 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1933 DRM_INFO("Internal thermal controller %s fan control\n",
1934 (controller->ucFanParameters &
1935 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1936 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1937 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1938 DRM_INFO("Internal thermal controller %s fan control\n",
1939 (controller->ucFanParameters &
1940 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1941 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 1942 } else if ((controller->ucType ==
49f65982 1943 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1944 (controller->ucType ==
49f65982
AD		 1945 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1946 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1947 } else {
1948 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1949 pp_lib_thermal_controller_names[controller->ucType],
1950 controller->ucI2cAddress >> 1,
1951 (controller->ucFanParameters &
29fb52ca 1952 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1953 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
f376b94f 1954 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1955 if (rdev->pm.i2c_bus) {
1956 struct i2c_board_info info = { };
1957 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1958 info.addr = controller->ucI2cAddress >> 1;
1959 strlcpy(info.type, name, sizeof(info.type));
1960 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1961 }
1962
29fb52ca
AD		 1963 }
1964 }
02b17cc0 1965 /* first mode is usually default, followed by low to high */
56278a8e
AD		 1966 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1967 mode_index = 0;
1968 power_state = (struct _ATOM_PPLIB_STATE *)
1969 (mode_info->atom_context->bios +
1970 data_offset +
1971 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1972 i * power_info->info_4.ucStateEntrySize);
1973 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1974 (mode_info->atom_context->bios +
1975 data_offset +
1976 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1977 (power_state->ucNonClockStateIndex *
1978 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1979 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1980 if (rdev->flags & RADEON_IS_IGP) {
1981 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1982 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1983 (mode_info->atom_context->bios +
1984 data_offset +
1985 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1986 (power_state->ucClockStateIndices[j] *
1987 power_info->info_4.ucClockInfoSize));
1988 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1989 sclk |= clock_info->ucLowEngineClockHigh << 16;
1990 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1991 /* skip invalid modes */
1992 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1993 continue;
aa1df0f2 1994 /* voltage works differently on IGPs */
56278a8e 1995 mode_index++;
49f65982
AD		 1996 } else if (ASIC_IS_DCE4(rdev)) {
1997 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1998 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1999 (mode_info->atom_context->bios +
2000 data_offset +
2001 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2002 (power_state->ucClockStateIndices[j] *
2003 power_info->info_4.ucClockInfoSize));
2004 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2005 sclk |= clock_info->ucEngineClockHigh << 16;
2006 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2007 mclk |= clock_info->ucMemoryClockHigh << 16;
2008 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2009 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2010 /* skip invalid modes */
2011 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2012 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2013 continue;
49f65982
AD		 2014 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2015 VOLTAGE_SW;
2016 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2017 clock_info->usVDDC;
2018 /* XXX usVDDCI */
2019 mode_index++;
56278a8e
AD		 2020 } else {
2021 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2022 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2023 (mode_info->atom_context->bios +
2024 data_offset +
2025 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2026 (power_state->ucClockStateIndices[j] *
2027 power_info->info_4.ucClockInfoSize));
2028 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2029 sclk |= clock_info->ucEngineClockHigh << 16;
2030 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2031 mclk |= clock_info->ucMemoryClockHigh << 16;
2032 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2033 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2034 /* skip invalid modes */
2035 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2036 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2037 continue;
56278a8e
AD		 2038 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2039 VOLTAGE_SW;
2040 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2041 clock_info->usVDDC;
2042 mode_index++;
2043 }
2044 }
2045 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2046 if (mode_index) {
845db70d 2047 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 2048 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 2049 rdev->pm.power_state[state_index].misc = misc;
2050 rdev->pm.power_state[state_index].misc2 = misc2;
2051 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 2052 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2053 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 2054 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2055 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2056 rdev->pm.power_state[state_index].type =
2057 POWER_STATE_TYPE_BATTERY;
2058 break;
2059 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2060 rdev->pm.power_state[state_index].type =
2061 POWER_STATE_TYPE_BALANCED;
2062 break;
2063 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_PERFORMANCE;
2066 break;
a44d2f37
AD		 2067 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2068 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2069 rdev->pm.power_state[state_index].type =
2070 POWER_STATE_TYPE_PERFORMANCE;
2071 break;
0ec0e74f 2072 }
a48b9b4e
AD		 2073 rdev->pm.power_state[state_index].flags = 0;
2074 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2075 rdev->pm.power_state[state_index].flags |=
d7311171 2076 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 2077 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 2078 rdev->pm.power_state[state_index].type =
2079 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2080 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 2081 rdev->pm.power_state[state_index].default_clock_mode =
2082 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 2083 /* patch the table values with the default slck/mclk from firmware info */
2084 for (j = 0; j < mode_index; j++) {
2085 rdev->pm.power_state[state_index].clock_info[j].mclk =
2086 rdev->clock.default_mclk;
2087 rdev->pm.power_state[state_index].clock_info[j].sclk =
2088 rdev->clock.default_sclk;
2089 if (vddc)
2090 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2091 vddc;
2092 }
56278a8e
AD		 2093 }
2094 state_index++;
2095 }
2096 }
d7311171
AD		 2097 /* if multiple clock modes, mark the lowest as no display */
2098 for (i = 0; i < state_index; i++) {
2099 if (rdev->pm.power_state[i].num_clock_modes > 1)
2100 rdev->pm.power_state[i].clock_info[0].flags |=
2101 RADEON_PM_MODE_NO_DISPLAY;
2102 }
02b17cc0 2103 /* first mode is usually default */
a48b9b4e 2104 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2105 rdev->pm.power_state[0].type =
2106 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2107 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 2108 rdev->pm.power_state[0].default_clock_mode =
2109 &rdev->pm.power_state[0].clock_info[0];
2110 }
56278a8e
AD		 2111 }
2112 } else {
56278a8e 2113 /* add the default mode */
0ec0e74f
AD		 2114 rdev->pm.power_state[state_index].type =
2115 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2116 rdev->pm.power_state[state_index].num_clock_modes = 1;
2117 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2118 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2119 rdev->pm.power_state[state_index].default_clock_mode =
2120 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2121 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2122 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2123 rdev->pm.default_power_state_index = state_index;
2124 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2125 state_index++;
2126 }
02b17cc0 2127
56278a8e 2128 rdev->pm.num_power_states = state_index;
9038dfdf 2129
a48b9b4e
AD		 2130 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2131 rdev->pm.current_clock_mode_index = 0;
4d60173f 2132 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2133}
2134
771fe6b9 2135void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2136{
771fe6b9
JG		 2137 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2138 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2139
2140 args.ucEnable = enable;
2141
2142 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2143}
2144
7433874e
RM		 2145uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2146{
2147 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2148 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2149
2150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2151 return args.ulReturnEngineClock;
2152}
2153
2154uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2155{
2156 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2157 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2158
2159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2160 return args.ulReturnMemoryClock;
2161}
2162
771fe6b9
JG		 2163void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2164 uint32_t eng_clock)
2165{
2166 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2167 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2168
2169 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2170
2171 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2172}
2173
2174void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2175 uint32_t mem_clock)
2176{
2177 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2178 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2179
2180 if (rdev->flags & RADEON_IS_IGP)
2181 return;
2182
2183 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2184
2185 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2186}
2187
7ac9aa5a
AD		 2188union set_voltage {
2189 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2190 struct _SET_VOLTAGE_PARAMETERS v1;
2191 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2192};
2193
2194void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2195{
2196 union set_voltage args;
2197 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2198 u8 frev, crev, volt_index = level;
2199
2200 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2201 return;
2202
2203 switch (crev) {
2204 case 1:
2205 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2206 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2207 args.v1.ucVoltageIndex = volt_index;
2208 break;
2209 case 2:
2210 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2211 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2212 args.v2.usVoltageLevel = cpu_to_le16(level);
2213 break;
2214 default:
2215 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2216 return;
2217 }
2218
2219 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2220}
2221
2222
2223
771fe6b9
JG		 2224void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2225{
2226 struct radeon_device *rdev = dev->dev_private;
2227 uint32_t bios_2_scratch, bios_6_scratch;
2228
2229 if (rdev->family >= CHIP_R600) {
4ce001ab 2230 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2231 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2232 } else {
4ce001ab 2233 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2234 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2235 }
2236
2237 /* let the bios control the backlight */
2238 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2239
2240 /* tell the bios not to handle mode switching */
2241 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2242
2243 if (rdev->family >= CHIP_R600) {
2244 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2245 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2246 } else {
2247 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2248 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2249 }
2250
2251}
2252
f657c2a7
YZ		 2253void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2254{
2255 uint32_t scratch_reg;
2256 int i;
2257
2258 if (rdev->family >= CHIP_R600)
2259 scratch_reg = R600_BIOS_0_SCRATCH;
2260 else
2261 scratch_reg = RADEON_BIOS_0_SCRATCH;
2262
2263 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2264 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2265}
2266
2267void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2268{
2269 uint32_t scratch_reg;
2270 int i;
2271
2272 if (rdev->family >= CHIP_R600)
2273 scratch_reg = R600_BIOS_0_SCRATCH;
2274 else
2275 scratch_reg = RADEON_BIOS_0_SCRATCH;
2276
2277 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2278 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2279}
2280
771fe6b9
JG		 2281void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2282{
2283 struct drm_device *dev = encoder->dev;
2284 struct radeon_device *rdev = dev->dev_private;
2285 uint32_t bios_6_scratch;
2286
2287 if (rdev->family >= CHIP_R600)
2288 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2289 else
2290 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2291
2292 if (lock)
2293 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2294 else
2295 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2296
2297 if (rdev->family >= CHIP_R600)
2298 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2299 else
2300 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2301}
2302
2303/* at some point we may want to break this out into individual functions */
2304void
2305radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2306 struct drm_encoder *encoder,
2307 bool connected)
2308{
2309 struct drm_device *dev = connector->dev;
2310 struct radeon_device *rdev = dev->dev_private;
2311 struct radeon_connector *radeon_connector =
2312 to_radeon_connector(connector);
2313 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2314 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2315
2316 if (rdev->family >= CHIP_R600) {
2317 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2318 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2319 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2320 } else {
2321 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2322 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2323 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2324 }
2325
2326 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2327 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2328 if (connected) {
d9fdaafb 2329 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2330 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2331 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2332 } else {
d9fdaafb 2333 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2334 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2335 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2336 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2337 }
2338 }
2339 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2340 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2341 if (connected) {
d9fdaafb 2342 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2343 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2344 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2345 } else {
d9fdaafb 2346 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2347 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2348 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2349 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2350 }
2351 }
2352 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2353 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2354 if (connected) {
d9fdaafb 2355 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2356 bios_0_scratch |= ATOM_S0_LCD1;
2357 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2358 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2359 } else {
d9fdaafb 2360 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2361 bios_0_scratch &= ~ATOM_S0_LCD1;
2362 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2363 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2364 }
2365 }
2366 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2367 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2368 if (connected) {
d9fdaafb 2369 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2370 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2371 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2372 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2373 } else {
d9fdaafb 2374 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2375 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2376 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2377 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2378 }
2379 }
2380 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2381 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2382 if (connected) {
d9fdaafb 2383 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2384 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2385 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2386 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2387 } else {
d9fdaafb 2388 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2389 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2390 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2391 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2392 }
2393 }
2394 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2395 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2396 if (connected) {
d9fdaafb 2397 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2398 bios_0_scratch |= ATOM_S0_DFP1;
2399 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2400 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2401 } else {
d9fdaafb 2402 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2403 bios_0_scratch &= ~ATOM_S0_DFP1;
2404 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2405 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2406 }
2407 }
2408 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2409 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2410 if (connected) {
d9fdaafb 2411 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2412 bios_0_scratch |= ATOM_S0_DFP2;
2413 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2414 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2415 } else {
d9fdaafb 2416 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2417 bios_0_scratch &= ~ATOM_S0_DFP2;
2418 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2419 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2420 }
2421 }
2422 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2423 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2424 if (connected) {
d9fdaafb 2425 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2426 bios_0_scratch |= ATOM_S0_DFP3;
2427 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2428 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2429 } else {
d9fdaafb 2430 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2431 bios_0_scratch &= ~ATOM_S0_DFP3;
2432 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2433 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2434 }
2435 }
2436 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2437 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2438 if (connected) {
d9fdaafb 2439 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2440 bios_0_scratch |= ATOM_S0_DFP4;
2441 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2442 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2443 } else {
d9fdaafb 2444 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2445 bios_0_scratch &= ~ATOM_S0_DFP4;
2446 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2447 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2448 }
2449 }
2450 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2451 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2452 if (connected) {
d9fdaafb 2453 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2454 bios_0_scratch |= ATOM_S0_DFP5;
2455 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2456 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2457 } else {
d9fdaafb 2458 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2459 bios_0_scratch &= ~ATOM_S0_DFP5;
2460 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2461 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2462 }
2463 }
2464
2465 if (rdev->family >= CHIP_R600) {
2466 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2467 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2468 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2469 } else {
2470 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2471 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2472 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2473 }
2474}
2475
2476void
2477radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2478{
2479 struct drm_device *dev = encoder->dev;
2480 struct radeon_device *rdev = dev->dev_private;
2481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2482 uint32_t bios_3_scratch;
2483
2484 if (rdev->family >= CHIP_R600)
2485 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2486 else
2487 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2488
2489 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2490 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2491 bios_3_scratch |= (crtc << 18);
2492 }
2493 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2494 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2495 bios_3_scratch |= (crtc << 24);
2496 }
2497 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2498 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2499 bios_3_scratch |= (crtc << 16);
2500 }
2501 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2502 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2503 bios_3_scratch |= (crtc << 20);
2504 }
2505 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2506 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2507 bios_3_scratch |= (crtc << 17);
2508 }
2509 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2510 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2511 bios_3_scratch |= (crtc << 19);
2512 }
2513 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2514 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2515 bios_3_scratch |= (crtc << 23);
2516 }
2517 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2518 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2519 bios_3_scratch |= (crtc << 25);
2520 }
2521
2522 if (rdev->family >= CHIP_R600)
2523 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2524 else
2525 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2526}
2527
2528void
2529radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2530{
2531 struct drm_device *dev = encoder->dev;
2532 struct radeon_device *rdev = dev->dev_private;
2533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2534 uint32_t bios_2_scratch;
2535
2536 if (rdev->family >= CHIP_R600)
2537 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2538 else
2539 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2540
2541 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2542 if (on)
2543 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2544 else
2545 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2546 }
2547 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2548 if (on)
2549 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2550 else
2551 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2552 }
2553 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2554 if (on)
2555 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2556 else
2557 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2558 }
2559 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2560 if (on)
2561 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2562 else
2563 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2564 }
2565 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2566 if (on)
2567 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2568 else
2569 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2570 }
2571 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2572 if (on)
2573 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2574 else
2575 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2576 }
2577 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2578 if (on)
2579 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2580 else
2581 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2582 }
2583 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2584 if (on)
2585 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2586 else
2587 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2588 }
2589 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2590 if (on)
2591 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2592 else
2593 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2594 }
2595 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2596 if (on)
2597 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2598 else
2599 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2600 }
2601
2602 if (rdev->family >= CHIP_R600)
2603 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2604 else
2605 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2606}
Linux kernel - Deliverables
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