projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/atom: fix voltage table parsing
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36868bda 40 uint32_t supported_device, u16 caps);
771fe6b9
JG		 41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
21240f9b
AD		 65static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
66 ATOM_GPIO_I2C_ASSIGMENT *gpio,
67 u8 index)
68{
69 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
70 if ((rdev->family == CHIP_R420) ||
71 (rdev->family == CHIP_R423) ||
72 (rdev->family == CHIP_RV410)) {
73 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
74 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
76 gpio->ucClkMaskShift = 0x19;
77 gpio->ucDataMaskShift = 0x18;
78 }
79 }
80
81 /* some evergreen boards have bad data for this entry */
82 if (ASIC_IS_DCE4(rdev)) {
83 if ((index == 7) &&
84 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
85 (gpio->sucI2cId.ucAccess == 0)) {
86 gpio->sucI2cId.ucAccess = 0x97;
87 gpio->ucDataMaskShift = 8;
88 gpio->ucDataEnShift = 8;
89 gpio->ucDataY_Shift = 8;
90 gpio->ucDataA_Shift = 8;
91 }
92 }
93
94 /* some DCE3 boards have bad data for this entry */
95 if (ASIC_IS_DCE3(rdev)) {
96 if ((index == 4) &&
97 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
98 (gpio->sucI2cId.ucAccess == 0x94))
99 gpio->sucI2cId.ucAccess = 0x14;
100 }
101}
102
103static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
104{
105 struct radeon_i2c_bus_rec i2c;
106
107 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
108
109 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
110 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
111 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
112 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
113 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
114 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
115 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
116 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
117 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
118 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
119 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
120 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
121 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
122 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
123 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
124 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
125
126 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
127 i2c.hw_capable = true;
128 else
129 i2c.hw_capable = false;
130
131 if (gpio->sucI2cId.ucAccess == 0xa0)
132 i2c.mm_i2c = true;
133 else
134 i2c.mm_i2c = false;
135
136 i2c.i2c_id = gpio->sucI2cId.ucAccess;
137
138 if (i2c.mask_clk_reg)
139 i2c.valid = true;
140 else
141 i2c.valid = false;
142
143 return i2c;
144}
145
ce580fab 146static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
eed45b30 147 uint8_t id)
771fe6b9 148{
771fe6b9 149 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 151 struct radeon_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 154 uint16_t data_offset, size;
155 int i, num_indices;
771fe6b9
JG		 156
157 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
158 i2c.valid = false;
159
95beb690 160 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 161 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
162
95beb690
AD		 163 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
164 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
165
166 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 167 gpio = &i2c_info->asGPIO_Info[i];
168
21240f9b 169 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
3074adc8 170
a084e6ee 171 if (gpio->sucI2cId.ucAccess == id) {
21240f9b 172 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
a084e6ee
AD		 173 break;
174 }
d3f420d1
AD		 175 }
176 }
771fe6b9
JG		 177
178 return i2c;
179}
180
f376b94f
AD		 181void radeon_atombios_i2c_init(struct radeon_device *rdev)
182{
183 struct atom_context *ctx = rdev->mode_info.atom_context;
184 ATOM_GPIO_I2C_ASSIGMENT *gpio;
185 struct radeon_i2c_bus_rec i2c;
186 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
187 struct _ATOM_GPIO_I2C_INFO *i2c_info;
188 uint16_t data_offset, size;
189 int i, num_indices;
190 char stmp[32];
191
f376b94f
AD		 192 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
193 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
194
195 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
196 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
197
198 for (i = 0; i < num_indices; i++) {
199 gpio = &i2c_info->asGPIO_Info[i];
d724502a 200
21240f9b 201 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
ea39302b 202
21240f9b 203 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
3074adc8 204
21240f9b 205 if (i2c.valid) {
f376b94f
AD		 206 sprintf(stmp, "0x%x", i2c.i2c_id);
207 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
208 }
209 }
210 }
211}
212
ce580fab 213static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
eed45b30
AD		 214 u8 id)
215{
216 struct atom_context *ctx = rdev->mode_info.atom_context;
217 struct radeon_gpio_rec gpio;
218 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
219 struct _ATOM_GPIO_PIN_LUT *gpio_info;
220 ATOM_GPIO_PIN_ASSIGNMENT *pin;
221 u16 data_offset, size;
222 int i, num_indices;
223
224 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
225 gpio.valid = false;
226
a084e6ee
AD		 227 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
228 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 229
a084e6ee
AD		 230 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
231 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 232
a084e6ee
AD		 233 for (i = 0; i < num_indices; i++) {
234 pin = &gpio_info->asGPIO_Pin[i];
235 if (id == pin->ucGPIO_ID) {
236 gpio.id = pin->ucGPIO_ID;
4589433c 237 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
a084e6ee
AD		 238 gpio.mask = (1 << pin->ucGpioPinBitShift);
239 gpio.valid = true;
240 break;
241 }
eed45b30
AD		 242 }
243 }
244
245 return gpio;
246}
247
248static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
249 struct radeon_gpio_rec *gpio)
250{
251 struct radeon_hpd hpd;
bcc1c2a1
AD		 252 u32 reg;
253
1d978dac
JD		 254 memset(&hpd, 0, sizeof(struct radeon_hpd));
255
82d118ef
AD		 256 if (ASIC_IS_DCE6(rdev))
257 reg = SI_DC_GPIO_HPD_A;
258 else if (ASIC_IS_DCE4(rdev))
bcc1c2a1
AD		 259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
eed45b30 263 hpd.gpio = *gpio;
bcc1c2a1 264 if (gpio->reg == reg) {
eed45b30
AD		 265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291}
292
771fe6b9
JG		 293static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
848577ee 296 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
771fe6b9
JG		 299{
300
301 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
302 if ((dev->pdev->device == 0x791e) &&
303 (dev->pdev->subsystem_vendor == 0x1043) &&
304 (dev->pdev->subsystem_device == 0x826d)) {
305 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
306 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
307 *connector_type = DRM_MODE_CONNECTOR_DVID;
308 }
309
c86a9038
AD		 310 /* Asrock RS600 board lists the DVI port as HDMI */
311 if ((dev->pdev->device == 0x7941) &&
312 (dev->pdev->subsystem_vendor == 0x1849) &&
313 (dev->pdev->subsystem_device == 0x7941)) {
314 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
315 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
316 *connector_type = DRM_MODE_CONNECTOR_DVID;
317 }
318
f36fce0f
AD		 319 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
320 if ((dev->pdev->device == 0x796e) &&
321 (dev->pdev->subsystem_vendor == 0x1462) &&
322 (dev->pdev->subsystem_device == 0x7302)) {
323 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
324 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
325 return false;
326 }
327
771fe6b9
JG		 328 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
329 if ((dev->pdev->device == 0x7941) &&
330 (dev->pdev->subsystem_vendor == 0x147b) &&
331 (dev->pdev->subsystem_device == 0x2412)) {
332 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
333 return false;
334 }
335
336 /* Falcon NW laptop lists vga ddc line for LVDS */
337 if ((dev->pdev->device == 0x5653) &&
338 (dev->pdev->subsystem_vendor == 0x1462) &&
339 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 340 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 341 i2c_bus->valid = false;
848577ee
AD		 342 *line_mux = 53;
343 }
771fe6b9
JG		 344 }
345
4e3f9b78
AD		 346 /* HIS X1300 is DVI+VGA, not DVI+DVI */
347 if ((dev->pdev->device == 0x7146) &&
348 (dev->pdev->subsystem_vendor == 0x17af) &&
349 (dev->pdev->subsystem_device == 0x2058)) {
350 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
351 return false;
352 }
353
aa1a750e
DA		 354 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
355 if ((dev->pdev->device == 0x7142) &&
356 (dev->pdev->subsystem_vendor == 0x1458) &&
357 (dev->pdev->subsystem_device == 0x2134)) {
358 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
359 return false;
360 }
361
362
771fe6b9
JG		 363 /* Funky macbooks */
364 if ((dev->pdev->device == 0x71C5) &&
365 (dev->pdev->subsystem_vendor == 0x106b) &&
366 (dev->pdev->subsystem_device == 0x0080)) {
367 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
368 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
369 return false;
e1e8a5dd
AD		 370 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
371 *line_mux = 0x90;
771fe6b9
JG		 372 }
373
be23da8a
AD		 374 /* mac rv630, rv730, others */
375 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
376 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
377 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
378 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
f598aa75
AD		 379 }
380
771fe6b9
JG		 381 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
382 if ((dev->pdev->device == 0x9598) &&
383 (dev->pdev->subsystem_vendor == 0x1043) &&
384 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 385 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 386 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 387 }
388 }
389
e153b70b
AD		 390 /* ASUS HD 3600 board lists the DVI port as HDMI */
391 if ((dev->pdev->device == 0x9598) &&
392 (dev->pdev->subsystem_vendor == 0x1043) &&
393 (dev->pdev->subsystem_device == 0x01e4)) {
394 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
395 *connector_type = DRM_MODE_CONNECTOR_DVII;
396 }
397 }
398
705af9c7
AD		 399 /* ASUS HD 3450 board lists the DVI port as HDMI */
400 if ((dev->pdev->device == 0x95C5) &&
401 (dev->pdev->subsystem_vendor == 0x1043) &&
402 (dev->pdev->subsystem_device == 0x01e2)) {
403 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 404 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 405 }
406 }
407
705af9c7
AD		 408 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
409 * HDMI + VGA reporting as HDMI
410 */
411 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
412 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
413 *connector_type = DRM_MODE_CONNECTOR_VGA;
414 *line_mux = 0;
415 }
416 }
417
4f87af46 418 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
2f299d5d
AD		 419 * on the laptop and a DVI port on the docking station and
420 * both share the same encoder, hpd pin, and ddc line.
421 * So while the bios table is technically correct,
422 * we drop the DVI port here since xrandr has no concept of
423 * encoders and will try and drive both connectors
424 * with different crtcs which isn't possible on the hardware
425 * side and leaves no crtcs for LVDS or VGA.
426 */
4f87af46 427 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
3e5f8ff3
AD		 428 (dev->pdev->subsystem_vendor == 0x1025) &&
429 (dev->pdev->subsystem_device == 0x013c)) {
430 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be 431 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
2f299d5d 432 /* actually it's a DVI-D port not DVI-I */
3e5f8ff3 433 *connector_type = DRM_MODE_CONNECTOR_DVID;
2f299d5d 434 return false;
9ea2c4be 435 }
3e5f8ff3
AD		 436 }
437
efa8450f
DA		 438 /* XFX Pine Group device rv730 reports no VGA DDC lines
439 * even though they are wired up to record 0x93
440 */
441 if ((dev->pdev->device == 0x9498) &&
442 (dev->pdev->subsystem_vendor == 0x1682) &&
1ebf169a
AD		 443 (dev->pdev->subsystem_device == 0x2452) &&
444 (i2c_bus->valid == false) &&
445 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
efa8450f
DA		 446 struct radeon_device *rdev = dev->dev_private;
447 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
448 }
4c1b2d2d
AD		 449
450 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
52e9b39d 451 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
4c1b2d2d
AD		 452 (dev->pdev->subsystem_vendor == 0x1734) &&
453 (dev->pdev->subsystem_device == 0x11bd)) {
454 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
455 *connector_type = DRM_MODE_CONNECTOR_DVII;
456 *line_mux = 0x3103;
457 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
458 *connector_type = DRM_MODE_CONNECTOR_DVII;
459 }
460 }
461
462
771fe6b9
JG		 463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
b75fad06
AD		 485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
771fe6b9
JG		 502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
705af9c7 512 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 533 u16 size, data_offset;
534 u8 frev, crev;
771fe6b9 535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
36868bda 536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
26b5bc98 537 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 540 int i, j, k, path_size, device_support;
771fe6b9 541 int connector_type;
eed45b30 542 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 543 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 544 struct radeon_router router;
eed45b30
AD		 545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
a084e6ee 548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
36868bda
AD		 561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
26b5bc98
AD		 564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
5137ee94 576
771fe6b9
JG		 577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
4bbd4973
DA		 590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 593 continue;
594
ee59f2b4
AD		 595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
a084e6ee
AD		 606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
771fe6b9
JG		 635 } else
636 continue;
a084e6ee
AD		 637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
771fe6b9
JG		 643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
b75fad06 647 connector_object_id = con_obj_id;
771fe6b9
JG		 648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
bdd91b2b
TW		 653 router.ddc_valid = false;
654 router.cd_valid = false;
26b5bc98
AD		 655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 657
26b5bc98 658 grph_obj_id =
771fe6b9
JG		 659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 661 grph_obj_num =
771fe6b9
JG		 662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 664 grph_obj_type =
771fe6b9
JG		 665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
26b5bc98 668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
36868bda
AD		 669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
771fe6b9 677
97ea530f
JL		 678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
36868bda
AD		 680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
26b5bc98 699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
97ea530f
JL		 724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
26b5bc98
AD		 726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
fb939dfc
AD		 744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
771fe6b9
JG		 763 }
764 }
765
eed45b30 766 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 769 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
eed45b30 784 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 786
97ea530f
JL		 787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 790 switch (record->ucRecordType) {
771fe6b9
JG		 791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
eed45b30
AD		 793 (ATOM_I2C_RECORD *)
794 record;
d3f420d1
AD		 795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
eed45b30 798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 799 i2c_config->
800 ucAccess);
eed45b30
AD		 801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
eed45b30 822 }
771fe6b9 823
bcc1c2a1 824 /* needed for aux chan transactions */
8e36ed00 825 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 826
705af9c7
AD		 827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 831 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 832 continue;
833
771fe6b9 834 radeon_add_atom_connector(dev,
705af9c7 835 conn_id,
771fe6b9
JG		 836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
5137ee94 839 igp_lane_info,
eed45b30 840 connector_object_id,
26b5bc98
AD		 841 &hpd,
842 &router);
771fe6b9
JG		 843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850}
851
b75fad06
AD		 852static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855{
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
a084e6ee
AD		 871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 873
a084e6ee
AD		 874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
b75fad06
AD		 888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892}
893
771fe6b9
JG		 894struct bios_connector {
895 bool valid;
705af9c7 896 uint16_t line_mux;
771fe6b9
JG		 897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 900 struct radeon_hpd hpd;
771fe6b9
JG		 901};
902
903bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906{
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
eed45b30 916 int i, j, max_device;
f49d273d
PB		 917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 919 struct radeon_router router;
920
fb939dfc
AD		 921 router.ddc_valid = false;
922 router.cd_valid = false;
771fe6b9 923
f49d273d
PB		 924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
a084e6ee 931 return false;
f49d273d 932 }
771fe6b9
JG		 933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
eed45b30
AD		 939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 955 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 956 continue;
957 }
958
771fe6b9
JG		 959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
d3f420d1
AD		 970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
771fe6b9
JG		 972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
eed45b30
AD		 985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
771fe6b9
JG		 1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
771fe6b9
JG		 1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
5137ee94 1029 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1030 (1 << i),
1031 dac),
36868bda
AD		 1032 (1 << i),
1033 0);
771fe6b9
JG		 1034 else
1035 radeon_add_legacy_encoder(dev,
5137ee94 1036 radeon_get_encoder_enum(dev,
f56cd64f 1037 (1 << i),
771fe6b9
JG		 1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
eed45b30 1043 for (i = 0; i < max_device; i++) {
771fe6b9 1044 if (bios_connectors[i].valid) {
eed45b30 1045 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
f56cd64f
AD		 1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
f56cd64f 1072 bios_connectors[j].valid = false;
771fe6b9
JG		 1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
eed45b30 1081 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
771fe6b9
JG		 1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
5137ee94 1093 0,
eed45b30 1094 connector_object_id,
26b5bc98
AD		 1095 &bios_connectors[i].hpd,
1096 &router);
b75fad06 1097 }
771fe6b9
JG		 1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
f49d273d 1102 kfree(bios_connectors);
771fe6b9
JG		 1103 return true;
1104}
1105
1106union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
f82b3ddc 1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
771fe6b9
JG		 1113};
1114
1115bool radeon_atom_get_clock_info(struct drm_device *dev)
1116{
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
a084e6ee
AD		 1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
771fe6b9
JG		 1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
bc293e58
MF		 1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
86cb2bbf
AD		 1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
771fe6b9
JG		 1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
f82b3ddc
AD		 1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
f82b3ddc
AD		 1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
bcc1c2a1
AD		 1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
f82b3ddc
AD		 1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
bcc1c2a1
AD		 1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
4489cd62 1246 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
bcc1c2a1
AD		 1247 }
1248 *dcpll = *p1pll;
1249
b20f9bef
AD		 1250 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1251 if (rdev->clock.max_pixel_clock == 0)
1252 rdev->clock.max_pixel_clock = 40000;
1253
af7912e5
AD		 1254 /* not technically a clock, but... */
1255 rdev->mode_info.firmware_flags =
1256 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1257
771fe6b9
JG		 1258 return true;
1259 }
bcc1c2a1 1260
771fe6b9
JG		 1261 return false;
1262}
1263
06b6476d
AD		 1264union igp_info {
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
3838f46e
AD		 1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
c2037ad1 1269 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
06b6476d
AD		 1270};
1271
1272bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1273{
1274 struct radeon_mode_info *mode_info = &rdev->mode_info;
1275 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1276 union igp_info *igp_info;
1277 u8 frev, crev;
1278 u16 data_offset;
1279
4c70b2ea
AD		 1280 /* sideport is AMD only */
1281 if (rdev->family == CHIP_RS600)
1282 return false;
1283
a084e6ee
AD		 1284 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1285 &frev, &crev, &data_offset)) {
1286 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1287 data_offset);
06b6476d
AD		 1288 switch (crev) {
1289 case 1:
4589433c 1290 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
4c70b2ea 1291 return true;
06b6476d
AD		 1292 break;
1293 case 2:
4589433c 1294 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
06b6476d
AD		 1295 return true;
1296 break;
1297 default:
1298 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1299 break;
1300 }
1301 }
1302 return false;
1303}
1304
445282db
DA		 1305bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1306 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1307{
1308 struct drm_device *dev = encoder->base.dev;
1309 struct radeon_device *rdev = dev->dev_private;
1310 struct radeon_mode_info *mode_info = &rdev->mode_info;
1311 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1312 uint16_t data_offset;
1313 struct _ATOM_TMDS_INFO *tmds_info;
1314 uint8_t frev, crev;
1315 uint16_t maxfreq;
1316 int i;
771fe6b9 1317
a084e6ee
AD		 1318 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1319 &frev, &crev, &data_offset)) {
1320 tmds_info =
1321 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1322 data_offset);
771fe6b9 1323
771fe6b9
JG		 1324 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1325 for (i = 0; i < 4; i++) {
1326 tmds->tmds_pll[i].freq =
1327 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1328 tmds->tmds_pll[i].value =
1329 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1330 tmds->tmds_pll[i].value |=
1331 (tmds_info->asMiscInfo[i].
1332 ucPLL_VCO_Gain & 0x3f) << 6;
1333 tmds->tmds_pll[i].value |=
1334 (tmds_info->asMiscInfo[i].
1335 ucPLL_DutyCycle & 0xf) << 12;
1336 tmds->tmds_pll[i].value |=
1337 (tmds_info->asMiscInfo[i].
1338 ucPLL_VoltageSwing & 0xf) << 16;
1339
d9fdaafb 1340 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1341 tmds->tmds_pll[i].freq,
1342 tmds->tmds_pll[i].value);
1343
1344 if (maxfreq == tmds->tmds_pll[i].freq) {
1345 tmds->tmds_pll[i].freq = 0xffffffff;
1346 break;
1347 }
1348 }
445282db 1349 return true;
771fe6b9 1350 }
445282db 1351 return false;
771fe6b9
JG		 1352}
1353
ba032a58
AD		 1354bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1355 struct radeon_atom_ss *ss,
1356 int id)
ebbe1cb9 1357{
ebbe1cb9
AD		 1358 struct radeon_mode_info *mode_info = &rdev->mode_info;
1359 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1360 uint16_t data_offset, size;
ebbe1cb9
AD		 1361 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1362 uint8_t frev, crev;
ba032a58 1363 int i, num_indices;
ebbe1cb9 1364
ba032a58
AD		 1365 memset(ss, 0, sizeof(struct radeon_atom_ss));
1366 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1367 &frev, &crev, &data_offset)) {
1368 ss_info =
1369 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1370
ba032a58
AD		 1371 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1372 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1373
ba032a58 1374 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1375 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1376 ss->percentage =
1377 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1378 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1379 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1380 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1381 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1382 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1383 return true;
1384 }
1385 }
1386 }
1387 return false;
1388}
1389
4339c442
AD		 1390static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1391 struct radeon_atom_ss *ss,
1392 int id)
1393{
1394 struct radeon_mode_info *mode_info = &rdev->mode_info;
1395 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1396 u16 data_offset, size;
3838f46e 1397 union igp_info *igp_info;
4339c442
AD		 1398 u8 frev, crev;
1399 u16 percentage = 0, rate = 0;
1400
1401 /* get any igp specific overrides */
1402 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1403 &frev, &crev, &data_offset)) {
3838f46e 1404 igp_info = (union igp_info *)
4339c442 1405 (mode_info->atom_context->bios + data_offset);
3838f46e
AD		 1406 switch (crev) {
1407 case 6:
1408 switch (id) {
1409 case ASIC_INTERNAL_SS_ON_TMDS:
1410 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1411 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1412 break;
1413 case ASIC_INTERNAL_SS_ON_HDMI:
1414 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1415 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1416 break;
1417 case ASIC_INTERNAL_SS_ON_LVDS:
1418 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1419 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1420 break;
1421 }
4339c442 1422 break;
3838f46e
AD		 1423 case 7:
1424 switch (id) {
1425 case ASIC_INTERNAL_SS_ON_TMDS:
1426 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1427 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1428 break;
1429 case ASIC_INTERNAL_SS_ON_HDMI:
1430 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1431 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1432 break;
1433 case ASIC_INTERNAL_SS_ON_LVDS:
1434 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1435 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1436 break;
1437 }
4339c442 1438 break;
c2037ad1
AD		 1439 case 8:
1440 switch (id) {
1441 case ASIC_INTERNAL_SS_ON_TMDS:
1442 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1443 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1444 break;
1445 case ASIC_INTERNAL_SS_ON_HDMI:
1446 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1447 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1448 break;
1449 case ASIC_INTERNAL_SS_ON_LVDS:
1450 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1451 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1452 break;
1453 }
1454 break;
3838f46e
AD		 1455 default:
1456 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
4339c442
AD		 1457 break;
1458 }
1459 if (percentage)
1460 ss->percentage = percentage;
1461 if (rate)
1462 ss->rate = rate;
1463 }
1464}
1465
ba032a58
AD		 1466union asic_ss_info {
1467 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1468 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1469 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1470};
1471
1472bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1473 struct radeon_atom_ss *ss,
1474 int id, u32 clock)
1475{
1476 struct radeon_mode_info *mode_info = &rdev->mode_info;
1477 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1478 uint16_t data_offset, size;
1479 union asic_ss_info *ss_info;
1480 uint8_t frev, crev;
1481 int i, num_indices;
1482
1483 memset(ss, 0, sizeof(struct radeon_atom_ss));
1484 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1485 &frev, &crev, &data_offset)) {
1486
1487 ss_info =
1488 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1489
1490 switch (frev) {
1491 case 1:
1492 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1493 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1494
1495 for (i = 0; i < num_indices; i++) {
1496 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1497 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1498 ss->percentage =
1499 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1500 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1501 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1502 return true;
1503 }
279b215e 1504 }
ba032a58
AD		 1505 break;
1506 case 2:
1507 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1508 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1509 for (i = 0; i < num_indices; i++) {
1510 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1511 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1512 ss->percentage =
1513 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1514 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1515 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
ae5b0abb
AD		 1516 if ((crev == 2) &&
1517 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1518 (id == ASIC_INTERNAL_MEMORY_SS)))
1519 ss->rate /= 100;
ba032a58
AD		 1520 return true;
1521 }
1522 }
1523 break;
1524 case 3:
1525 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1526 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1527 for (i = 0; i < num_indices; i++) {
1528 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1529 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1530 ss->percentage =
1531 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1532 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1533 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
ae5b0abb
AD		 1534 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1535 (id == ASIC_INTERNAL_MEMORY_SS))
1536 ss->rate /= 100;
4339c442
AD		 1537 if (rdev->flags & RADEON_IS_IGP)
1538 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
ba032a58
AD		 1539 return true;
1540 }
1541 }
1542 break;
1543 default:
1544 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1545 break;
279b215e 1546 }
ba032a58 1547
ebbe1cb9 1548 }
ba032a58 1549 return false;
ebbe1cb9
AD		 1550}
1551
771fe6b9
JG		 1552union lvds_info {
1553 struct _ATOM_LVDS_INFO info;
1554 struct _ATOM_LVDS_INFO_V12 info_12;
1555};
1556
1557struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1558 radeon_encoder
1559 *encoder)
1560{
1561 struct drm_device *dev = encoder->base.dev;
1562 struct radeon_device *rdev = dev->dev_private;
1563 struct radeon_mode_info *mode_info = &rdev->mode_info;
1564 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1565 uint16_t data_offset, misc;
771fe6b9
JG		 1566 union lvds_info *lvds_info;
1567 uint8_t frev, crev;
1568 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1569 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1570
a084e6ee
AD		 1571 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1572 &frev, &crev, &data_offset)) {
1573 lvds_info =
1574 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1575 lvds =
1576 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1577
1578 if (!lvds)
1579 return NULL;
1580
de2103e4 1581 lvds->native_mode.clock =
771fe6b9 1582 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1583 lvds->native_mode.hdisplay =
771fe6b9 1584 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1585 lvds->native_mode.vdisplay =
771fe6b9 1586 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1587 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1588 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1589 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1590 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1591 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1592 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1593 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1594 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1595 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1596 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1597 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1598 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1599 lvds->panel_pwr_delay =
1600 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1601 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1602
1603 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1604 if (misc & ATOM_VSYNC_POLARITY)
1605 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1606 if (misc & ATOM_HSYNC_POLARITY)
1607 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1608 if (misc & ATOM_COMPOSITESYNC)
1609 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1610 if (misc & ATOM_INTERLACE)
1611 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1612 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1613 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1614
4589433c
CC		 1615 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1616 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
7a868e18 1617
de2103e4
AD		 1618 /* set crtc values */
1619 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1620
ba032a58 1621 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1622
771fe6b9 1623 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1624
1625 if (encoder_enum == 2)
1626 lvds->linkb = true;
1627 else
1628 lvds->linkb = false;
1629
c324acd5 1630 /* parse the lcd record table */
4589433c 1631 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
c324acd5
AD		 1632 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1633 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1634 bool bad_record = false;
05fa7ea7
AD		 1635 u8 *record;
1636
1637 if ((frev == 1) && (crev < 2))
1638 /* absolute */
1639 record = (u8 *)(mode_info->atom_context->bios +
1640 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1641 else
1642 /* relative */
1643 record = (u8 *)(mode_info->atom_context->bios +
1644 data_offset +
1645 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
c324acd5
AD		 1646 while (*record != ATOM_RECORD_END_TYPE) {
1647 switch (*record) {
1648 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1649 record += sizeof(ATOM_PATCH_RECORD_MODE);
1650 break;
1651 case LCD_RTS_RECORD_TYPE:
1652 record += sizeof(ATOM_LCD_RTS_RECORD);
1653 break;
1654 case LCD_CAP_RECORD_TYPE:
1655 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1656 break;
1657 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1658 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1659 if (fake_edid_record->ucFakeEDIDLength) {
1660 struct edid *edid;
1661 int edid_size =
1662 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1663 edid = kmalloc(edid_size, GFP_KERNEL);
1664 if (edid) {
1665 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1666 fake_edid_record->ucFakeEDIDLength);
1667
eaa4f5e1 1668 if (drm_edid_is_valid(edid)) {
c324acd5 1669 rdev->mode_info.bios_hardcoded_edid = edid;
eaa4f5e1
DA		 1670 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1671 } else
c324acd5
AD		 1672 kfree(edid);
1673 }
1674 }
1675 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1676 break;
1677 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1678 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1679 lvds->native_mode.width_mm = panel_res_record->usHSize;
1680 lvds->native_mode.height_mm = panel_res_record->usVSize;
1681 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1682 break;
1683 default:
1684 DRM_ERROR("Bad LCD record %d\n", *record);
1685 bad_record = true;
1686 break;
1687 }
1688 if (bad_record)
1689 break;
1690 }
1691 }
771fe6b9
JG		 1692 }
1693 return lvds;
1694}
1695
6fe7ac3f
AD		 1696struct radeon_encoder_primary_dac *
1697radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1698{
1699 struct drm_device *dev = encoder->base.dev;
1700 struct radeon_device *rdev = dev->dev_private;
1701 struct radeon_mode_info *mode_info = &rdev->mode_info;
1702 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1703 uint16_t data_offset;
1704 struct _COMPASSIONATE_DATA *dac_info;
1705 uint8_t frev, crev;
1706 uint8_t bg, dac;
6fe7ac3f
AD		 1707 struct radeon_encoder_primary_dac *p_dac = NULL;
1708
a084e6ee
AD		 1709 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1710 &frev, &crev, &data_offset)) {
1711 dac_info = (struct _COMPASSIONATE_DATA *)
1712 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1713
6fe7ac3f
AD		 1714 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1715
1716 if (!p_dac)
1717 return NULL;
1718
1719 bg = dac_info->ucDAC1_BG_Adjustment;
1720 dac = dac_info->ucDAC1_DAC_Adjustment;
1721 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1722
1723 }
1724 return p_dac;
1725}
1726
4ce001ab 1727bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1728 struct drm_display_mode *mode)
4ce001ab
DA		 1729{
1730 struct radeon_mode_info *mode_info = &rdev->mode_info;
1731 ATOM_ANALOG_TV_INFO *tv_info;
1732 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1733 ATOM_DTD_FORMAT *dtd_timings;
1734 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1735 u8 frev, crev;
5a9bcacc 1736 u16 data_offset, misc;
4ce001ab 1737
a084e6ee
AD		 1738 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1739 &frev, &crev, &data_offset))
1740 return false;
4ce001ab
DA		 1741
1742 switch (crev) {
1743 case 1:
1744 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1745 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1746 return false;
1747
5a9bcacc
AD		 1748 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1749 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1750 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1751 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1752 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1753
1754 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1755 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1756 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1757 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1758 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1759
1760 mode->flags = 0;
1761 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1762 if (misc & ATOM_VSYNC_POLARITY)
1763 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1764 if (misc & ATOM_HSYNC_POLARITY)
1765 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1766 if (misc & ATOM_COMPOSITESYNC)
1767 mode->flags |= DRM_MODE_FLAG_CSYNC;
1768 if (misc & ATOM_INTERLACE)
1769 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1770 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1771 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1772
1773 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1774
1775 if (index == 1) {
1776 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1777 mode->crtc_htotal -= 1;
1778 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1779 }
1780 break;
1781 case 2:
1782 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1783 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1784 return false;
1785
1786 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1787 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1788 le16_to_cpu(dtd_timings->usHBlanking_Time);
1789 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1790 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1791 le16_to_cpu(dtd_timings->usHSyncOffset);
1792 mode->crtc_hsync_end = mode->crtc_hsync_start +
1793 le16_to_cpu(dtd_timings->usHSyncWidth);
1794
1795 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1796 le16_to_cpu(dtd_timings->usVBlanking_Time);
1797 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1798 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1799 le16_to_cpu(dtd_timings->usVSyncOffset);
1800 mode->crtc_vsync_end = mode->crtc_vsync_start +
1801 le16_to_cpu(dtd_timings->usVSyncWidth);
1802
1803 mode->flags = 0;
1804 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1805 if (misc & ATOM_VSYNC_POLARITY)
1806 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1807 if (misc & ATOM_HSYNC_POLARITY)
1808 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1809 if (misc & ATOM_COMPOSITESYNC)
1810 mode->flags |= DRM_MODE_FLAG_CSYNC;
1811 if (misc & ATOM_INTERLACE)
1812 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1813 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1814 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1815
1816 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1817 break;
1818 }
1819 return true;
1820}
1821
d79766fa
AD		 1822enum radeon_tv_std
1823radeon_atombios_get_tv_info(struct radeon_device *rdev)
1824{
1825 struct radeon_mode_info *mode_info = &rdev->mode_info;
1826 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1827 uint16_t data_offset;
1828 uint8_t frev, crev;
1829 struct _ATOM_ANALOG_TV_INFO *tv_info;
1830 enum radeon_tv_std tv_std = TV_STD_NTSC;
1831
a084e6ee
AD		 1832 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1833 &frev, &crev, &data_offset)) {
d79766fa 1834
a084e6ee
AD		 1835 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1836 (mode_info->atom_context->bios + data_offset);
d79766fa 1837
a084e6ee
AD		 1838 switch (tv_info->ucTV_BootUpDefaultStandard) {
1839 case ATOM_TV_NTSC:
1840 tv_std = TV_STD_NTSC;
40f76d81 1841 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1842 break;
1843 case ATOM_TV_NTSCJ:
1844 tv_std = TV_STD_NTSC_J;
40f76d81 1845 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1846 break;
1847 case ATOM_TV_PAL:
1848 tv_std = TV_STD_PAL;
40f76d81 1849 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1850 break;
1851 case ATOM_TV_PALM:
1852 tv_std = TV_STD_PAL_M;
40f76d81 1853 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1854 break;
1855 case ATOM_TV_PALN:
1856 tv_std = TV_STD_PAL_N;
40f76d81 1857 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1858 break;
1859 case ATOM_TV_PALCN:
1860 tv_std = TV_STD_PAL_CN;
40f76d81 1861 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1862 break;
1863 case ATOM_TV_PAL60:
1864 tv_std = TV_STD_PAL_60;
40f76d81 1865 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1866 break;
1867 case ATOM_TV_SECAM:
1868 tv_std = TV_STD_SECAM;
40f76d81 1869 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1870 break;
1871 default:
1872 tv_std = TV_STD_NTSC;
40f76d81 1873 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1874 break;
1875 }
d79766fa
AD		 1876 }
1877 return tv_std;
1878}
1879
6fe7ac3f
AD		 1880struct radeon_encoder_tv_dac *
1881radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1882{
1883 struct drm_device *dev = encoder->base.dev;
1884 struct radeon_device *rdev = dev->dev_private;
1885 struct radeon_mode_info *mode_info = &rdev->mode_info;
1886 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1887 uint16_t data_offset;
1888 struct _COMPASSIONATE_DATA *dac_info;
1889 uint8_t frev, crev;
1890 uint8_t bg, dac;
6fe7ac3f
AD		 1891 struct radeon_encoder_tv_dac *tv_dac = NULL;
1892
a084e6ee
AD		 1893 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1894 &frev, &crev, &data_offset)) {
6fe7ac3f 1895
a084e6ee
AD		 1896 dac_info = (struct _COMPASSIONATE_DATA *)
1897 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1898
6fe7ac3f
AD		 1899 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1900
1901 if (!tv_dac)
1902 return NULL;
1903
1904 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1905 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1906 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1907
1908 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1909 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1910 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1911
1912 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1913 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1915
d79766fa 1916 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1917 }
1918 return tv_dac;
1919}
1920
29fb52ca
AD		 1921static const char *thermal_controller_names[] = {
1922 "NONE",
678e7dfa
AD		 1923 "lm63",
1924 "adm1032",
1925 "adm1030",
1926 "max6649",
1927 "lm64",
1928 "f75375",
1929 "asc7xxx",
29fb52ca
AD		 1930};
1931
1932static const char *pp_lib_thermal_controller_names[] = {
1933 "NONE",
678e7dfa
AD		 1934 "lm63",
1935 "adm1032",
1936 "adm1030",
1937 "max6649",
1938 "lm64",
1939 "f75375",
29fb52ca
AD		 1940 "RV6xx",
1941 "RV770",
678e7dfa 1942 "adt7473",
560154e9 1943 "NONE",
49f65982
AD		 1944 "External GPIO",
1945 "Evergreen",
b0e66414
AD		 1946 "emc2103",
1947 "Sumo",
4fddba1f 1948 "Northern Islands",
14607d08
AD		 1949 "Southern Islands",
1950 "lm96163",
51150207 1951 "Sea Islands",
29fb52ca
AD		 1952};
1953
56278a8e
AD		 1954union power_info {
1955 struct _ATOM_POWERPLAY_INFO info;
1956 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1957 struct _ATOM_POWERPLAY_INFO_V3 info_3;
560154e9 1958 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
b0e66414
AD		 1959 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1960 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
56278a8e
AD		 1961};
1962
560154e9
AD		 1963union pplib_clock_info {
1964 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1965 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1966 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
b0e66414 1967 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
14607d08 1968 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
bc19f597 1969 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
560154e9
AD		 1970};
1971
1972union pplib_power_state {
1973 struct _ATOM_PPLIB_STATE v1;
1974 struct _ATOM_PPLIB_STATE_V2 v2;
1975};
1976
1977static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1978 int state_index,
1979 u32 misc, u32 misc2)
1980{
1981 rdev->pm.power_state[state_index].misc = misc;
1982 rdev->pm.power_state[state_index].misc2 = misc2;
1983 /* order matters! */
1984 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1985 rdev->pm.power_state[state_index].type =
1986 POWER_STATE_TYPE_POWERSAVE;
1987 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1988 rdev->pm.power_state[state_index].type =
1989 POWER_STATE_TYPE_BATTERY;
1990 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1991 rdev->pm.power_state[state_index].type =
1992 POWER_STATE_TYPE_BATTERY;
1993 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1994 rdev->pm.power_state[state_index].type =
1995 POWER_STATE_TYPE_BALANCED;
1996 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1997 rdev->pm.power_state[state_index].type =
1998 POWER_STATE_TYPE_PERFORMANCE;
1999 rdev->pm.power_state[state_index].flags &=
2000 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2001 }
2002 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2003 rdev->pm.power_state[state_index].type =
2004 POWER_STATE_TYPE_BALANCED;
2005 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2006 rdev->pm.power_state[state_index].type =
2007 POWER_STATE_TYPE_DEFAULT;
2008 rdev->pm.default_power_state_index = state_index;
2009 rdev->pm.power_state[state_index].default_clock_mode =
2010 &rdev->pm.power_state[state_index].clock_info[0];
2011 } else if (state_index == 0) {
2012 rdev->pm.power_state[state_index].clock_info[0].flags |=
2013 RADEON_PM_MODE_NO_DISPLAY;
2014 }
2015}
2016
2017static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
771fe6b9 2018{
56278a8e 2019 struct radeon_mode_info *mode_info = &rdev->mode_info;
560154e9
AD		 2020 u32 misc, misc2 = 0;
2021 int num_modes = 0, i;
2022 int state_index = 0;
2023 struct radeon_i2c_bus_rec i2c_bus;
2024 union power_info *power_info;
56278a8e 2025 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
560154e9 2026 u16 data_offset;
56278a8e 2027 u8 frev, crev;
771fe6b9 2028
560154e9
AD		 2029 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2030 &frev, &crev, &data_offset))
2031 return state_index;
2032 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2033
2034 /* add the i2c bus for thermal/fan chip */
4755fab5
AD		 2035 if ((power_info->info.ucOverdriveThermalController > 0) &&
2036 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
560154e9
AD		 2037 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2038 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2039 power_info->info.ucOverdriveControllerAddress >> 1);
2040 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2041 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2042 if (rdev->pm.i2c_bus) {
2043 struct i2c_board_info info = { };
2044 const char *name = thermal_controller_names[power_info->info.
2045 ucOverdriveThermalController];
2046 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2047 strlcpy(info.type, name, sizeof(info.type));
2048 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2049 }
2050 }
2051 num_modes = power_info->info.ucNumOfPowerModeEntries;
2052 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2053 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
f8e6bfc2
AD		 2054 if (num_modes == 0)
2055 return state_index;
0975b162
AD		 2056 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2057 if (!rdev->pm.power_state)
2058 return state_index;
560154e9
AD		 2059 /* last mode is usually default, array is low to high */
2060 for (i = 0; i < num_modes; i++) {
6991b8f2
AD		 2061 rdev->pm.power_state[state_index].clock_info =
2062 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2063 if (!rdev->pm.power_state[state_index].clock_info)
2064 return state_index;
2065 rdev->pm.power_state[state_index].num_clock_modes = 1;
560154e9
AD		 2066 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2067 switch (frev) {
2068 case 1:
560154e9
AD		 2069 rdev->pm.power_state[state_index].clock_info[0].mclk =
2070 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2071 rdev->pm.power_state[state_index].clock_info[0].sclk =
2072 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2073 /* skip invalid modes */
2074 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2075 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2076 continue;
2077 rdev->pm.power_state[state_index].pcie_lanes =
2078 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2079 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2080 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2081 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2082 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2083 VOLTAGE_GPIO;
2084 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2085 radeon_lookup_gpio(rdev,
2086 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2087 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2088 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2089 true;
2090 else
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2092 false;
2093 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2094 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2095 VOLTAGE_VDDC;
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2097 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
29fb52ca 2098 }
560154e9
AD		 2099 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2100 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2101 state_index++;
2102 break;
2103 case 2:
560154e9
AD		 2104 rdev->pm.power_state[state_index].clock_info[0].mclk =
2105 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2106 rdev->pm.power_state[state_index].clock_info[0].sclk =
2107 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2108 /* skip invalid modes */
2109 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2110 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2111 continue;
2112 rdev->pm.power_state[state_index].pcie_lanes =
2113 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2114 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2115 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2116 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2117 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2119 VOLTAGE_GPIO;
2120 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2121 radeon_lookup_gpio(rdev,
2122 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2123 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2124 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2125 true;
2126 else
2127 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2128 false;
2129 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2131 VOLTAGE_VDDC;
2132 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2133 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
56278a8e 2134 }
560154e9
AD		 2135 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2136 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2137 state_index++;
2138 break;
2139 case 3:
560154e9
AD		 2140 rdev->pm.power_state[state_index].clock_info[0].mclk =
2141 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2142 rdev->pm.power_state[state_index].clock_info[0].sclk =
2143 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2144 /* skip invalid modes */
2145 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2146 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2147 continue;
2148 rdev->pm.power_state[state_index].pcie_lanes =
2149 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2150 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2151 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2152 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2153 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2155 VOLTAGE_GPIO;
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2157 radeon_lookup_gpio(rdev,
2158 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2159 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2161 true;
2162 else
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2164 false;
2165 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2167 VOLTAGE_VDDC;
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2169 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2170 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2171 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2172 true;
2173 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2174 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2175 }
02b17cc0 2176 }
560154e9
AD		 2177 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2178 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2179 state_index++;
2180 break;
2181 }
2182 }
2183 /* last mode is usually default */
2184 if (rdev->pm.default_power_state_index == -1) {
2185 rdev->pm.power_state[state_index - 1].type =
2186 POWER_STATE_TYPE_DEFAULT;
2187 rdev->pm.default_power_state_index = state_index - 1;
2188 rdev->pm.power_state[state_index - 1].default_clock_mode =
2189 &rdev->pm.power_state[state_index - 1].clock_info[0];
2190 rdev->pm.power_state[state_index].flags &=
2191 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2192 rdev->pm.power_state[state_index].misc = 0;
2193 rdev->pm.power_state[state_index].misc2 = 0;
2194 }
2195 return state_index;
2196}
2197
2198static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2199 ATOM_PPLIB_THERMALCONTROLLER *controller)
2200{
2201 struct radeon_i2c_bus_rec i2c_bus;
2202
2203 /* add the i2c bus for thermal/fan chip */
2204 if (controller->ucType > 0) {
2205 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2206 DRM_INFO("Internal thermal controller %s fan control\n",
2207 (controller->ucFanParameters &
2208 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2209 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2210 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2211 DRM_INFO("Internal thermal controller %s fan control\n",
2212 (controller->ucFanParameters &
2213 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2214 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2215 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2216 DRM_INFO("Internal thermal controller %s fan control\n",
2217 (controller->ucFanParameters &
2218 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2219 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
b0e66414
AD		 2220 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2221 DRM_INFO("Internal thermal controller %s fan control\n",
2222 (controller->ucFanParameters &
2223 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2224 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
4fddba1f
AD		 2225 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2226 DRM_INFO("Internal thermal controller %s fan control\n",
2227 (controller->ucFanParameters &
2228 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2229 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
14607d08
AD		 2230 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2231 DRM_INFO("Internal thermal controller %s fan control\n",
2232 (controller->ucFanParameters &
2233 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2234 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
51150207
AD		 2235 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2236 DRM_INFO("Internal thermal controller %s fan control\n",
2237 (controller->ucFanParameters &
2238 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2239 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
560154e9
AD		 2240 } else if ((controller->ucType ==
2241 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2242 (controller->ucType ==
b0e66414
AD		 2243 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2244 (controller->ucType ==
2245 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
560154e9 2246 DRM_INFO("Special thermal controller config\n");
4755fab5 2247 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
560154e9
AD		 2248 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2249 pp_lib_thermal_controller_names[controller->ucType],
2250 controller->ucI2cAddress >> 1,
2251 (controller->ucFanParameters &
2252 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2253 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2254 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2255 if (rdev->pm.i2c_bus) {
2256 struct i2c_board_info info = { };
2257 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2258 info.addr = controller->ucI2cAddress >> 1;
2259 strlcpy(info.type, name, sizeof(info.type));
2260 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
c5e8ce61 2261 }
4755fab5
AD		 2262 } else {
2263 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2264 controller->ucType,
2265 controller->ucI2cAddress >> 1,
2266 (controller->ucFanParameters &
2267 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
560154e9
AD		 2268 }
2269 }
2270}
c5e8ce61 2271
4a6369e9 2272void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2abba66e 2273 u16 *vddc, u16 *vddci, u16 *mvdd)
560154e9
AD		 2274{
2275 struct radeon_mode_info *mode_info = &rdev->mode_info;
2276 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2277 u8 frev, crev;
2278 u16 data_offset;
2279 union firmware_info *firmware_info;
2feea49a
AD		 2280
2281 *vddc = 0;
2282 *vddci = 0;
2abba66e 2283 *mvdd = 0;
678e7dfa 2284
560154e9
AD		 2285 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2286 &frev, &crev, &data_offset)) {
2287 firmware_info =
2288 (union firmware_info *)(mode_info->atom_context->bios +
2289 data_offset);
2feea49a 2290 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2abba66e 2291 if ((frev == 2) && (crev >= 2)) {
2feea49a 2292 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2abba66e
AD		 2293 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2294 }
560154e9 2295 }
560154e9
AD		 2296}
2297
2298static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2299 int state_index, int mode_index,
2300 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2301{
2302 int j;
2303 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2304 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2abba66e 2305 u16 vddc, vddci, mvdd;
2feea49a 2306
2abba66e 2307 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
560154e9
AD		 2308
2309 rdev->pm.power_state[state_index].misc = misc;
2310 rdev->pm.power_state[state_index].misc2 = misc2;
2311 rdev->pm.power_state[state_index].pcie_lanes =
2312 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2313 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2314 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2315 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2316 rdev->pm.power_state[state_index].type =
2317 POWER_STATE_TYPE_BATTERY;
2318 break;
2319 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2320 rdev->pm.power_state[state_index].type =
2321 POWER_STATE_TYPE_BALANCED;
2322 break;
2323 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2324 rdev->pm.power_state[state_index].type =
2325 POWER_STATE_TYPE_PERFORMANCE;
2326 break;
2327 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2328 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2329 rdev->pm.power_state[state_index].type =
2330 POWER_STATE_TYPE_PERFORMANCE;
2331 break;
2332 }
2333 rdev->pm.power_state[state_index].flags = 0;
2334 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2335 rdev->pm.power_state[state_index].flags |=
2336 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2337 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2338 rdev->pm.power_state[state_index].type =
2339 POWER_STATE_TYPE_DEFAULT;
2340 rdev->pm.default_power_state_index = state_index;
2341 rdev->pm.power_state[state_index].default_clock_mode =
2342 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
982cb329 2343 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
9ace9f7b
AD		 2344 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2345 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2346 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2347 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2feea49a 2348 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
9ace9f7b 2349 } else {
ae5b0abb
AD		 2350 u16 max_vddci = 0;
2351
2352 if (ASIC_IS_DCE4(rdev))
2353 radeon_atom_get_max_voltage(rdev,
2354 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2355 &max_vddci);
2356 /* patch the table values with the default sclk/mclk from firmware info */
9ace9f7b
AD		 2357 for (j = 0; j < mode_index; j++) {
2358 rdev->pm.power_state[state_index].clock_info[j].mclk =
2359 rdev->clock.default_mclk;
2360 rdev->pm.power_state[state_index].clock_info[j].sclk =
2361 rdev->clock.default_sclk;
2362 if (vddc)
2363 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2364 vddc;
ae5b0abb
AD		 2365 if (max_vddci)
2366 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2367 max_vddci;
9ace9f7b 2368 }
560154e9
AD		 2369 }
2370 }
2371}
2372
2373static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2374 int state_index, int mode_index,
2375 union pplib_clock_info *clock_info)
2376{
2377 u32 sclk, mclk;
e83753bb 2378 u16 vddc;
560154e9
AD		 2379
2380 if (rdev->flags & RADEON_IS_IGP) {
b0e66414
AD		 2381 if (rdev->family >= CHIP_PALM) {
2382 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2383 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2384 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2385 } else {
2386 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2387 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2388 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2389 }
bc19f597
AD		 2390 } else if (rdev->family >= CHIP_BONAIRE) {
2391 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2392 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2393 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2394 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2395 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2396 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2397 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2398 VOLTAGE_NONE;
982cb329 2399 } else if (rdev->family >= CHIP_TAHITI) {
14607d08
AD		 2400 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2401 sclk |= clock_info->si.ucEngineClockHigh << 16;
2402 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2403 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2404 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2405 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2406 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2407 VOLTAGE_SW;
2408 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2409 le16_to_cpu(clock_info->si.usVDDC);
2410 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2411 le16_to_cpu(clock_info->si.usVDDCI);
982cb329 2412 } else if (rdev->family >= CHIP_CEDAR) {
560154e9
AD		 2413 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2414 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2415 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2416 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2417 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2418 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2419 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2420 VOLTAGE_SW;
2421 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2422 le16_to_cpu(clock_info->evergreen.usVDDC);
2feea49a
AD		 2423 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2424 le16_to_cpu(clock_info->evergreen.usVDDCI);
560154e9
AD		 2425 } else {
2426 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2427 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2428 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2429 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2430 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2431 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2432 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2433 VOLTAGE_SW;
2434 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2435 le16_to_cpu(clock_info->r600.usVDDC);
560154e9
AD		 2436 }
2437
ee4017f4 2438 /* patch up vddc if necessary */
e83753bb
AD		 2439 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2440 case ATOM_VIRTUAL_VOLTAGE_ID0:
2441 case ATOM_VIRTUAL_VOLTAGE_ID1:
2442 case ATOM_VIRTUAL_VOLTAGE_ID2:
2443 case ATOM_VIRTUAL_VOLTAGE_ID3:
2444 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2445 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2446 &vddc) == 0)
ee4017f4 2447 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
e83753bb
AD		 2448 break;
2449 default:
2450 break;
ee4017f4
AD		 2451 }
2452
560154e9
AD		 2453 if (rdev->flags & RADEON_IS_IGP) {
2454 /* skip invalid modes */
2455 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2456 return false;
2457 } else {
2458 /* skip invalid modes */
2459 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2460 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2461 return false;
2462 }
2463 return true;
2464}
2465
2466static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2467{
2468 struct radeon_mode_info *mode_info = &rdev->mode_info;
2469 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2470 union pplib_power_state *power_state;
2471 int i, j;
2472 int state_index = 0, mode_index = 0;
2473 union pplib_clock_info *clock_info;
2474 bool valid;
2475 union power_info *power_info;
2476 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2477 u16 data_offset;
2478 u8 frev, crev;
2479
2480 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2481 &frev, &crev, &data_offset))
2482 return state_index;
2483 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2484
2485 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
f8e6bfc2
AD		 2486 if (power_info->pplib.ucNumStates == 0)
2487 return state_index;
0975b162
AD		 2488 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2489 power_info->pplib.ucNumStates, GFP_KERNEL);
2490 if (!rdev->pm.power_state)
2491 return state_index;
560154e9
AD		 2492 /* first mode is usually default, followed by low to high */
2493 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2494 mode_index = 0;
2495 power_state = (union pplib_power_state *)
2496 (mode_info->atom_context->bios + data_offset +
2497 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2498 i * power_info->pplib.ucStateEntrySize);
2499 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2500 (mode_info->atom_context->bios + data_offset +
2501 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2502 (power_state->v1.ucNonClockStateIndex *
2503 power_info->pplib.ucNonClockSize));
8f3f1c9a
AD		 2504 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2505 ((power_info->pplib.ucStateEntrySize - 1) ?
2506 (power_info->pplib.ucStateEntrySize - 1) : 1),
2507 GFP_KERNEL);
2508 if (!rdev->pm.power_state[i].clock_info)
2509 return state_index;
2510 if (power_info->pplib.ucStateEntrySize - 1) {
2511 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2512 clock_info = (union pplib_clock_info *)
2513 (mode_info->atom_context->bios + data_offset +
2514 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2515 (power_state->v1.ucClockStateIndices[j] *
2516 power_info->pplib.ucClockInfoSize));
2517 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2518 state_index, mode_index,
2519 clock_info);
2520 if (valid)
2521 mode_index++;
2522 }
2523 } else {
2524 rdev->pm.power_state[state_index].clock_info[0].mclk =
2525 rdev->clock.default_mclk;
2526 rdev->pm.power_state[state_index].clock_info[0].sclk =
2527 rdev->clock.default_sclk;
2528 mode_index++;
560154e9
AD		 2529 }
2530 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2531 if (mode_index) {
2532 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2533 non_clock_info);
2534 state_index++;
2535 }
2536 }
2537 /* if multiple clock modes, mark the lowest as no display */
2538 for (i = 0; i < state_index; i++) {
2539 if (rdev->pm.power_state[i].num_clock_modes > 1)
2540 rdev->pm.power_state[i].clock_info[0].flags |=
2541 RADEON_PM_MODE_NO_DISPLAY;
2542 }
2543 /* first mode is usually default */
2544 if (rdev->pm.default_power_state_index == -1) {
2545 rdev->pm.power_state[0].type =
2546 POWER_STATE_TYPE_DEFAULT;
2547 rdev->pm.default_power_state_index = 0;
2548 rdev->pm.power_state[0].default_clock_mode =
2549 &rdev->pm.power_state[0].clock_info[0];
2550 }
2551 return state_index;
2552}
2553
b0e66414
AD		 2554static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2555{
2556 struct radeon_mode_info *mode_info = &rdev->mode_info;
2557 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2558 union pplib_power_state *power_state;
2559 int i, j, non_clock_array_index, clock_array_index;
2560 int state_index = 0, mode_index = 0;
2561 union pplib_clock_info *clock_info;
f7346881
AD		 2562 struct _StateArray *state_array;
2563 struct _ClockInfoArray *clock_info_array;
2564 struct _NonClockInfoArray *non_clock_info_array;
b0e66414
AD		 2565 bool valid;
2566 union power_info *power_info;
2567 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2568 u16 data_offset;
2569 u8 frev, crev;
441e76ca 2570 u8 *power_state_offset;
b0e66414
AD		 2571
2572 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2573 &frev, &crev, &data_offset))
2574 return state_index;
2575 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2576
2577 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
f7346881 2578 state_array = (struct _StateArray *)
b0e66414 2579 (mode_info->atom_context->bios + data_offset +
4589433c 2580 le16_to_cpu(power_info->pplib.usStateArrayOffset));
f7346881 2581 clock_info_array = (struct _ClockInfoArray *)
b0e66414 2582 (mode_info->atom_context->bios + data_offset +
4589433c 2583 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
f7346881 2584 non_clock_info_array = (struct _NonClockInfoArray *)
b0e66414 2585 (mode_info->atom_context->bios + data_offset +
4589433c 2586 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
f8e6bfc2
AD		 2587 if (state_array->ucNumEntries == 0)
2588 return state_index;
0975b162
AD		 2589 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2590 state_array->ucNumEntries, GFP_KERNEL);
2591 if (!rdev->pm.power_state)
2592 return state_index;
441e76ca 2593 power_state_offset = (u8 *)state_array->states;
b0e66414
AD		 2594 for (i = 0; i < state_array->ucNumEntries; i++) {
2595 mode_index = 0;
441e76ca
AD		 2596 power_state = (union pplib_power_state *)power_state_offset;
2597 non_clock_array_index = power_state->v2.nonClockInfoIndex;
b0e66414
AD		 2598 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2599 &non_clock_info_array->nonClockInfo[non_clock_array_index];
8f3f1c9a
AD		 2600 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2601 (power_state->v2.ucNumDPMLevels ?
2602 power_state->v2.ucNumDPMLevels : 1),
2603 GFP_KERNEL);
2604 if (!rdev->pm.power_state[i].clock_info)
2605 return state_index;
2606 if (power_state->v2.ucNumDPMLevels) {
2607 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2608 clock_array_index = power_state->v2.clockInfoIndex[j];
8f3f1c9a 2609 clock_info = (union pplib_clock_info *)
f7346881 2610 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
8f3f1c9a
AD		 2611 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2612 state_index, mode_index,
2613 clock_info);
2614 if (valid)
2615 mode_index++;
2616 }
2617 } else {
2618 rdev->pm.power_state[state_index].clock_info[0].mclk =
2619 rdev->clock.default_mclk;
2620 rdev->pm.power_state[state_index].clock_info[0].sclk =
2621 rdev->clock.default_sclk;
2622 mode_index++;
b0e66414
AD		 2623 }
2624 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2625 if (mode_index) {
2626 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2627 non_clock_info);
2628 state_index++;
2629 }
441e76ca 2630 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
b0e66414
AD		 2631 }
2632 /* if multiple clock modes, mark the lowest as no display */
2633 for (i = 0; i < state_index; i++) {
2634 if (rdev->pm.power_state[i].num_clock_modes > 1)
2635 rdev->pm.power_state[i].clock_info[0].flags |=
2636 RADEON_PM_MODE_NO_DISPLAY;
2637 }
2638 /* first mode is usually default */
2639 if (rdev->pm.default_power_state_index == -1) {
2640 rdev->pm.power_state[0].type =
2641 POWER_STATE_TYPE_DEFAULT;
2642 rdev->pm.default_power_state_index = 0;
2643 rdev->pm.power_state[0].default_clock_mode =
2644 &rdev->pm.power_state[0].clock_info[0];
2645 }
2646 return state_index;
2647}
2648
560154e9
AD		 2649void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2650{
2651 struct radeon_mode_info *mode_info = &rdev->mode_info;
2652 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2653 u16 data_offset;
2654 u8 frev, crev;
2655 int state_index = 0;
2656
2657 rdev->pm.default_power_state_index = -1;
2658
2659 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2660 &frev, &crev, &data_offset)) {
2661 switch (frev) {
2662 case 1:
2663 case 2:
2664 case 3:
2665 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2666 break;
2667 case 4:
2668 case 5:
2669 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2670 break;
b0e66414
AD		 2671 case 6:
2672 state_index = radeon_atombios_parse_power_table_6(rdev);
2673 break;
560154e9
AD		 2674 default:
2675 break;
56278a8e 2676 }
f8e6bfc2
AD		 2677 }
2678
2679 if (state_index == 0) {
0975b162
AD		 2680 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2681 if (rdev->pm.power_state) {
8f3f1c9a
AD		 2682 rdev->pm.power_state[0].clock_info =
2683 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2684 if (rdev->pm.power_state[0].clock_info) {
2685 /* add the default mode */
2686 rdev->pm.power_state[state_index].type =
2687 POWER_STATE_TYPE_DEFAULT;
2688 rdev->pm.power_state[state_index].num_clock_modes = 1;
2689 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2690 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2691 rdev->pm.power_state[state_index].default_clock_mode =
2692 &rdev->pm.power_state[state_index].clock_info[0];
2693 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2694 rdev->pm.power_state[state_index].pcie_lanes = 16;
2695 rdev->pm.default_power_state_index = state_index;
2696 rdev->pm.power_state[state_index].flags = 0;
2697 state_index++;
2698 }
0975b162 2699 }
56278a8e 2700 }
02b17cc0 2701
56278a8e 2702 rdev->pm.num_power_states = state_index;
9038dfdf 2703
a48b9b4e
AD		 2704 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2705 rdev->pm.current_clock_mode_index = 0;
4376eee9
AM		 2706 if (rdev->pm.default_power_state_index >= 0)
2707 rdev->pm.current_vddc =
2708 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2709 else
2710 rdev->pm.current_vddc = 0;
771fe6b9
JG		 2711}
2712
7062ab67
CK		 2713union get_clock_dividers {
2714 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2715 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2716 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2717 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2718 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
9219ed65
AD		 2719 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2720 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
7062ab67
CK		 2721};
2722
2723int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2724 u8 clock_type,
2725 u32 clock,
2726 bool strobe_mode,
2727 struct atom_clock_dividers *dividers)
2728{
2729 union get_clock_dividers args;
2730 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2731 u8 frev, crev;
2732
2733 memset(&args, 0, sizeof(args));
2734 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2735
2736 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2737 return -EINVAL;
2738
2739 switch (crev) {
2740 case 1:
2741 /* r4xx, r5xx */
2742 args.v1.ucAction = clock_type;
2743 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2744
2745 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2746
2747 dividers->post_div = args.v1.ucPostDiv;
2748 dividers->fb_div = args.v1.ucFbDiv;
2749 dividers->enable_post_div = true;
2750 break;
2751 case 2:
2752 case 3:
360b1f5e
AD		 2753 case 5:
2754 /* r6xx, r7xx, evergreen, ni, si */
7062ab67
CK		 2755 if (rdev->family <= CHIP_RV770) {
2756 args.v2.ucAction = clock_type;
2757 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2758
2759 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2760
2761 dividers->post_div = args.v2.ucPostDiv;
2762 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2763 dividers->ref_div = args.v2.ucAction;
2764 if (rdev->family == CHIP_RV770) {
2765 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2766 true : false;
2767 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2768 } else
2769 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2770 } else {
2771 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
f4a2596c 2772 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
7062ab67
CK		 2773
2774 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2775
2776 dividers->post_div = args.v3.ucPostDiv;
2777 dividers->enable_post_div = (args.v3.ucCntlFlag &
2778 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2779 dividers->enable_dithen = (args.v3.ucCntlFlag &
2780 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2781 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2782 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2783 dividers->ref_div = args.v3.ucRefDiv;
2784 dividers->vco_mode = (args.v3.ucCntlFlag &
2785 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2786 } else {
360b1f5e
AD		 2787 /* for SI we use ComputeMemoryClockParam for memory plls */
2788 if (rdev->family >= CHIP_TAHITI)
2789 return -EINVAL;
f4a2596c 2790 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
7062ab67
CK		 2791 if (strobe_mode)
2792 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2793
2794 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2795
2796 dividers->post_div = args.v5.ucPostDiv;
2797 dividers->enable_post_div = (args.v5.ucCntlFlag &
2798 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2799 dividers->enable_dithen = (args.v5.ucCntlFlag &
2800 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2801 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2802 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2803 dividers->ref_div = args.v5.ucRefDiv;
2804 dividers->vco_mode = (args.v5.ucCntlFlag &
2805 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2806 }
2807 }
2808 break;
2809 case 4:
2810 /* fusion */
2811 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2812
2813 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2814
9219ed65 2815 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
7062ab67
CK		 2816 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2817 break;
9219ed65
AD		 2818 case 6:
2819 /* CI */
2820 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2821 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2822 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2823
2824 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2825
2826 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2827 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2828 dividers->ref_div = args.v6_out.ucPllRefDiv;
2829 dividers->post_div = args.v6_out.ucPllPostDiv;
2830 dividers->flags = args.v6_out.ucPllCntlFlag;
2831 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2832 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2833 break;
7062ab67
CK		 2834 default:
2835 return -EINVAL;
2836 }
2837 return 0;
2838}
2839
eaa778af
AD		 2840int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2841 u32 clock,
2842 bool strobe_mode,
2843 struct atom_mpll_param *mpll_param)
2844{
2845 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2846 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2847 u8 frev, crev;
2848
2849 memset(&args, 0, sizeof(args));
2850 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2851
2852 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2853 return -EINVAL;
2854
2855 switch (frev) {
2856 case 2:
2857 switch (crev) {
2858 case 1:
2859 /* SI */
2860 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2861 args.ucInputFlag = 0;
2862 if (strobe_mode)
2863 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2864
2865 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2866
2867 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2868 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2869 mpll_param->post_div = args.ucPostDiv;
2870 mpll_param->dll_speed = args.ucDllSpeed;
2871 mpll_param->bwcntl = args.ucBWCntl;
2872 mpll_param->vco_mode =
2873 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0;
2874 mpll_param->yclk_sel =
2875 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2876 mpll_param->qdr =
2877 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2878 mpll_param->half_rate =
2879 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2880 break;
2881 default:
2882 return -EINVAL;
2883 }
2884 break;
2885 default:
2886 return -EINVAL;
2887 }
2888 return 0;
2889}
2890
771fe6b9 2891void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2892{
771fe6b9
JG		 2893 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2894 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2895
2896 args.ucEnable = enable;
2897
2898 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2899}
2900
7433874e
RM		 2901uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2902{
2903 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2904 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2905
2906 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2907 return le32_to_cpu(args.ulReturnEngineClock);
7433874e
RM		 2908}
2909
2910uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2911{
2912 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2913 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2914
2915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2916 return le32_to_cpu(args.ulReturnMemoryClock);
7433874e
RM		 2917}
2918
771fe6b9
JG		 2919void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2920 uint32_t eng_clock)
2921{
2922 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2923 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2924
4589433c 2925 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
771fe6b9
JG		 2926
2927 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2928}
2929
2930void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2931 uint32_t mem_clock)
2932{
2933 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2934 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2935
2936 if (rdev->flags & RADEON_IS_IGP)
2937 return;
2938
4589433c 2939 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
771fe6b9
JG		 2940
2941 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2942}
2943
ae5b0abb
AD		 2944void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
2945 u32 eng_clock, u32 mem_clock)
2946{
2947 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2948 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2949 u32 tmp;
2950
2951 memset(&args, 0, sizeof(args));
2952
2953 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
2954 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
2955
2956 args.ulTargetEngineClock = cpu_to_le32(tmp);
2957 if (mem_clock)
2958 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
2959
2960 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2961}
2962
2963void radeon_atom_update_memory_dll(struct radeon_device *rdev,
2964 u32 mem_clock)
2965{
2966 u32 args;
2967 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2968
2969 args = cpu_to_le32(mem_clock); /* 10 khz */
2970
2971 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2972}
2973
2974void radeon_atom_set_ac_timing(struct radeon_device *rdev,
2975 u32 mem_clock)
2976{
2977 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2978 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2979 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
2980
2981 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
2982
2983 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2984}
2985
7ac9aa5a
AD		 2986union set_voltage {
2987 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2988 struct _SET_VOLTAGE_PARAMETERS v1;
2989 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
e83753bb 2990 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
7ac9aa5a
AD		 2991};
2992
8a83ec5e 2993void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
7ac9aa5a
AD		 2994{
2995 union set_voltage args;
2996 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
8a83ec5e 2997 u8 frev, crev, volt_index = voltage_level;
7ac9aa5a
AD		 2998
2999 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3000 return;
3001
a377e187
AD		 3002 /* 0xff01 is a flag rather then an actual voltage */
3003 if (voltage_level == 0xff01)
3004 return;
3005
7ac9aa5a
AD		 3006 switch (crev) {
3007 case 1:
8a83ec5e 3008 args.v1.ucVoltageType = voltage_type;
7ac9aa5a
AD		 3009 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3010 args.v1.ucVoltageIndex = volt_index;
3011 break;
3012 case 2:
8a83ec5e 3013 args.v2.ucVoltageType = voltage_type;
7ac9aa5a 3014 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
8a83ec5e 3015 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
7ac9aa5a 3016 break;
e83753bb
AD		 3017 case 3:
3018 args.v3.ucVoltageType = voltage_type;
3019 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3020 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3021 break;
7ac9aa5a
AD		 3022 default:
3023 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3024 return;
3025 }
3026
3027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3028}
3029
ae5b0abb
AD		 3030int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3031 u16 voltage_id, u16 *voltage)
ee4017f4
AD		 3032{
3033 union set_voltage args;
3034 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3035 u8 frev, crev;
3036
3037 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3038 return -EINVAL;
3039
3040 switch (crev) {
3041 case 1:
3042 return -EINVAL;
3043 case 2:
3044 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3045 args.v2.ucVoltageMode = 0;
3046 args.v2.usVoltageLevel = 0;
3047
3048 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3049
3050 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3051 break;
e83753bb
AD		 3052 case 3:
3053 args.v3.ucVoltageType = voltage_type;
3054 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3055 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3056
3057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3058
3059 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3060 break;
ee4017f4
AD		 3061 default:
3062 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3063 return -EINVAL;
3064 }
7ac9aa5a 3065
ee4017f4
AD		 3066 return 0;
3067}
7ac9aa5a 3068
beb79f40
AD		 3069int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3070 u16 *voltage,
3071 u16 leakage_idx)
3072{
3073 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3074}
3075
ae5b0abb
AD		 3076int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3077 u16 voltage_level, u8 voltage_type,
3078 u32 *gpio_value, u32 *gpio_mask)
3079{
3080 union set_voltage args;
3081 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3082 u8 frev, crev;
3083
3084 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3085 return -EINVAL;
3086
3087 switch (crev) {
3088 case 1:
3089 return -EINVAL;
3090 case 2:
3091 args.v2.ucVoltageType = voltage_type;
3092 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3093 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3094
3095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3096
3097 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3098
3099 args.v2.ucVoltageType = voltage_type;
3100 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3101 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3102
3103 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3104
3105 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3106 break;
3107 default:
3108 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3109 return -EINVAL;
3110 }
3111
3112 return 0;
3113}
3114
3115union voltage_object_info {
58653abd
AD		 3116 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3117 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3118 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
ae5b0abb
AD		 3119};
3120
779187f2
AD		 3121union voltage_object {
3122 struct _ATOM_VOLTAGE_OBJECT v1;
3123 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3124 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3125};
3126
3127static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3128 u8 voltage_type)
3129{
3130 u32 size = v1->sHeader.usStructureSize;
3131 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3132 u8 *start = (u8 *)v1;
3133
3134 while (offset < size) {
3135 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3136 if (vo->ucVoltageType == voltage_type)
3137 return vo;
3138 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3139 vo->asFormula.ucNumOfVoltageEntries;
3140 }
3141 return NULL;
3142}
3143
3144static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3145 u8 voltage_type)
3146{
3147 u32 size = v2->sHeader.usStructureSize;
3148 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3149 u8 *start = (u8*)v2;
3150
3151 while (offset < size) {
3152 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3153 if (vo->ucVoltageType == voltage_type)
3154 return vo;
3155 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3156 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3157 }
3158 return NULL;
3159}
3160
3161static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3162 u8 voltage_type, u8 voltage_mode)
3163{
3164 u32 size = v3->sHeader.usStructureSize;
3165 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3166 u8 *start = (u8*)v3;
3167
3168 while (offset < size) {
3169 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3170 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3171 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3172 return vo;
3173 offset += vo->asGpioVoltageObj.sHeader.usSize;
3174 }
3175 return NULL;
3176}
3177
ae5b0abb 3178bool
58653abd
AD		 3179radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3180 u8 voltage_type, u8 voltage_mode)
ae5b0abb
AD		 3181{
3182 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3183 u8 frev, crev;
3184 u16 data_offset, size;
ae5b0abb 3185 union voltage_object_info *voltage_info;
779187f2 3186 union voltage_object *voltage_object = NULL;
ae5b0abb
AD		 3187
3188 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3189 &frev, &crev, &data_offset)) {
3190 voltage_info = (union voltage_object_info *)
3191 (rdev->mode_info.atom_context->bios + data_offset);
3192
58653abd 3193 switch (frev) {
ae5b0abb 3194 case 1:
58653abd
AD		 3195 case 2:
3196 switch (crev) {
3197 case 1:
779187f2
AD		 3198 voltage_object = (union voltage_object *)
3199 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3200 if (voltage_object &&
3201 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3202 return true;
58653abd
AD		 3203 break;
3204 case 2:
779187f2
AD		 3205 voltage_object = (union voltage_object *)
3206 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3207 if (voltage_object &&
3208 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3209 return true;
58653abd
AD		 3210 break;
3211 default:
3212 DRM_ERROR("unknown voltage object table\n");
3213 return false;
ae5b0abb
AD		 3214 }
3215 break;
58653abd
AD		 3216 case 3:
3217 switch (crev) {
3218 case 1:
779187f2
AD		 3219 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3220 voltage_type, voltage_mode))
3221 return true;
58653abd
AD		 3222 break;
3223 default:
3224 DRM_ERROR("unknown voltage object table\n");
3225 return false;
ae5b0abb
AD		 3226 }
3227 break;
3228 default:
3229 DRM_ERROR("unknown voltage object table\n");
3230 return false;
3231 }
3232
3233 }
3234 return false;
3235}
3236
3237int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3238 u8 voltage_type, u16 *max_voltage)
3239{
3240 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3241 u8 frev, crev;
3242 u16 data_offset, size;
ae5b0abb 3243 union voltage_object_info *voltage_info;
779187f2 3244 union voltage_object *voltage_object = NULL;
ae5b0abb
AD		 3245
3246 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3247 &frev, &crev, &data_offset)) {
3248 voltage_info = (union voltage_object_info *)
3249 (rdev->mode_info.atom_context->bios + data_offset);
3250
3251 switch (crev) {
3252 case 1:
779187f2
AD		 3253 voltage_object = (union voltage_object *)
3254 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3255 if (voltage_object) {
3256 ATOM_VOLTAGE_FORMULA *formula =
3257 &voltage_object->v1.asFormula;
3258 if (formula->ucFlag & 1)
3259 *max_voltage =
3260 le16_to_cpu(formula->usVoltageBaseLevel) +
3261 formula->ucNumOfVoltageEntries / 2 *
3262 le16_to_cpu(formula->usVoltageStep);
3263 else
3264 *max_voltage =
3265 le16_to_cpu(formula->usVoltageBaseLevel) +
3266 (formula->ucNumOfVoltageEntries - 1) *
3267 le16_to_cpu(formula->usVoltageStep);
3268 return 0;
ae5b0abb
AD		 3269 }
3270 break;
3271 case 2:
779187f2
AD		 3272 voltage_object = (union voltage_object *)
3273 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3274 if (voltage_object) {
3275 ATOM_VOLTAGE_FORMULA_V2 *formula =
3276 &voltage_object->v2.asFormula;
3277 if (formula->ucNumOfVoltageEntries) {
3278 *max_voltage =
3279 le16_to_cpu(formula->asVIDAdjustEntries[
3280 formula->ucNumOfVoltageEntries - 1
3281 ].usVoltageValue);
3282 return 0;
ae5b0abb
AD		 3283 }
3284 }
3285 break;
3286 default:
3287 DRM_ERROR("unknown voltage object table\n");
3288 return -EINVAL;
3289 }
3290
3291 }
3292 return -EINVAL;
3293}
3294
3295int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3296 u8 voltage_type, u16 *min_voltage)
3297{
3298 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3299 u8 frev, crev;
3300 u16 data_offset, size;
ae5b0abb 3301 union voltage_object_info *voltage_info;
779187f2 3302 union voltage_object *voltage_object = NULL;
ae5b0abb
AD		 3303
3304 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3305 &frev, &crev, &data_offset)) {
3306 voltage_info = (union voltage_object_info *)
3307 (rdev->mode_info.atom_context->bios + data_offset);
3308
3309 switch (crev) {
3310 case 1:
779187f2
AD		 3311 voltage_object = (union voltage_object *)
3312 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3313 if (voltage_object) {
3314 ATOM_VOLTAGE_FORMULA *formula =
3315 &voltage_object->v1.asFormula;
3316 *min_voltage =
3317 le16_to_cpu(formula->usVoltageBaseLevel);
3318 return 0;
ae5b0abb
AD		 3319 }
3320 break;
3321 case 2:
779187f2
AD		 3322 voltage_object = (union voltage_object *)
3323 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3324 if (voltage_object) {
3325 ATOM_VOLTAGE_FORMULA_V2 *formula =
3326 &voltage_object->v2.asFormula;
3327 if (formula->ucNumOfVoltageEntries) {
3328 *min_voltage =
3329 le16_to_cpu(formula->asVIDAdjustEntries[
3330 0
3331 ].usVoltageValue);
3332 return 0;
ae5b0abb
AD		 3333 }
3334 }
3335 break;
3336 default:
3337 DRM_ERROR("unknown voltage object table\n");
3338 return -EINVAL;
3339 }
3340
3341 }
3342 return -EINVAL;
3343}
3344
3345int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3346 u8 voltage_type, u16 *voltage_step)
3347{
3348 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3349 u8 frev, crev;
3350 u16 data_offset, size;
ae5b0abb 3351 union voltage_object_info *voltage_info;
779187f2 3352 union voltage_object *voltage_object = NULL;
ae5b0abb
AD		 3353
3354 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3355 &frev, &crev, &data_offset)) {
3356 voltage_info = (union voltage_object_info *)
3357 (rdev->mode_info.atom_context->bios + data_offset);
3358
3359 switch (crev) {
3360 case 1:
779187f2
AD		 3361 voltage_object = (union voltage_object *)
3362 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3363 if (voltage_object) {
3364 ATOM_VOLTAGE_FORMULA *formula =
3365 &voltage_object->v1.asFormula;
3366 if (formula->ucFlag & 1)
3367 *voltage_step =
3368 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3369 else
3370 *voltage_step =
3371 le16_to_cpu(formula->usVoltageStep);
3372 return 0;
ae5b0abb
AD		 3373 }
3374 break;
3375 case 2:
3376 return -EINVAL;
3377 default:
3378 DRM_ERROR("unknown voltage object table\n");
3379 return -EINVAL;
3380 }
3381
3382 }
3383 return -EINVAL;
3384}
3385
3386int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3387 u8 voltage_type,
3388 u16 nominal_voltage,
3389 u16 *true_voltage)
3390{
3391 u16 min_voltage, max_voltage, voltage_step;
3392
3393 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3394 return -EINVAL;
3395 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3396 return -EINVAL;
3397 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3398 return -EINVAL;
3399
3400 if (nominal_voltage <= min_voltage)
3401 *true_voltage = min_voltage;
3402 else if (nominal_voltage >= max_voltage)
3403 *true_voltage = max_voltage;
3404 else
3405 *true_voltage = min_voltage +
3406 ((nominal_voltage - min_voltage) / voltage_step) *
3407 voltage_step;
3408
3409 return 0;
3410}
3411
3412int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 3413 u8 voltage_type, u8 voltage_mode,
ae5b0abb
AD		 3414 struct atom_voltage_table *voltage_table)
3415{
3416 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3417 u8 frev, crev;
3418 u16 data_offset, size;
779187f2 3419 int i, ret;
ae5b0abb 3420 union voltage_object_info *voltage_info;
779187f2 3421 union voltage_object *voltage_object = NULL;
ae5b0abb
AD		 3422
3423 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3424 &frev, &crev, &data_offset)) {
3425 voltage_info = (union voltage_object_info *)
3426 (rdev->mode_info.atom_context->bios + data_offset);
3427
65171944 3428 switch (frev) {
ae5b0abb 3429 case 1:
ae5b0abb 3430 case 2:
65171944
AD		 3431 switch (crev) {
3432 case 1:
3433 DRM_ERROR("old table version %d, %d\n", frev, crev);
3434 return -EINVAL;
3435 case 2:
779187f2
AD		 3436 voltage_object = (union voltage_object *)
3437 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3438 if (voltage_object) {
3439 ATOM_VOLTAGE_FORMULA_V2 *formula =
3440 &voltage_object->v2.asFormula;
3441 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3442 return -EINVAL;
3443 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3444 voltage_table->entries[i].value =
3445 le16_to_cpu(formula->asVIDAdjustEntries[i].usVoltageValue);
3446 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3447 voltage_table->entries[i].value,
3448 voltage_type,
3449 &voltage_table->entries[i].smio_low,
3450 &voltage_table->mask_low);
3451 if (ret)
3452 return ret;
ae5b0abb 3453 }
779187f2
AD		 3454 voltage_table->count = formula->ucNumOfVoltageEntries;
3455 return 0;
ae5b0abb 3456 }
65171944
AD		 3457 break;
3458 default:
3459 DRM_ERROR("unknown voltage object table\n");
3460 return -EINVAL;
3461 }
3462 break;
3463 case 3:
3464 switch (crev) {
3465 case 1:
779187f2
AD		 3466 voltage_object = (union voltage_object *)
3467 atom_lookup_voltage_object_v3(&voltage_info->v3,
3468 voltage_type, voltage_mode);
3469 if (voltage_object) {
3470 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3471 &voltage_object->v3.asGpioVoltageObj;
3472 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3473 return -EINVAL;
3474 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3475 voltage_table->entries[i].value =
3476 le16_to_cpu(gpio->asVolGpioLut[i].usVoltageValue);
3477 voltage_table->entries[i].smio_low =
3478 le32_to_cpu(gpio->asVolGpioLut[i].ulVoltageId);
65171944 3479 }
779187f2
AD		 3480 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3481 voltage_table->count = gpio->ucGpioEntryNum;
3482 voltage_table->phase_delay = gpio->ucPhaseDelay;
3483 return 0;
65171944
AD		 3484 }
3485 break;
3486 default:
3487 DRM_ERROR("unknown voltage object table\n");
3488 return -EINVAL;
ae5b0abb
AD		 3489 }
3490 break;
3491 default:
3492 DRM_ERROR("unknown voltage object table\n");
3493 return -EINVAL;
3494 }
ae5b0abb
AD		 3495 }
3496 return -EINVAL;
3497}
3498
3499union vram_info {
3500 struct _ATOM_VRAM_INFO_V3 v1_3;
3501 struct _ATOM_VRAM_INFO_V4 v1_4;
3502 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3503};
3504
3505int radeon_atom_get_memory_info(struct radeon_device *rdev,
3506 u8 module_index, struct atom_memory_info *mem_info)
3507{
3508 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3509 u8 frev, crev, i;
3510 u16 data_offset, size;
3511 union vram_info *vram_info;
3512 u8 *p;
3513
3514 memset(mem_info, 0, sizeof(struct atom_memory_info));
3515
3516 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3517 &frev, &crev, &data_offset)) {
3518 vram_info = (union vram_info *)
3519 (rdev->mode_info.atom_context->bios + data_offset);
3520 switch (frev) {
3521 case 1:
3522 switch (crev) {
3523 case 3:
3524 /* r6xx */
3525 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3526 ATOM_VRAM_MODULE_V3 *vram_module =
3527 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3528 p = (u8 *)vram_info->v1_3.aVramInfo;
3529
3530 for (i = 0; i < module_index; i++) {
3531 vram_module = (ATOM_VRAM_MODULE_V3 *)p;
3532 if (le16_to_cpu(vram_module->usSize) == 0)
3533 return -EINVAL;
3534 p += le16_to_cpu(vram_module->usSize);
3535 }
3536 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3537 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3538 } else
3539 return -EINVAL;
3540 break;
3541 case 4:
3542 /* r7xx, evergreen */
3543 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3544 ATOM_VRAM_MODULE_V4 *vram_module =
3545 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3546 p = (u8 *)vram_info->v1_4.aVramInfo;
3547
3548 for (i = 0; i < module_index; i++) {
3549 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3550 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3551 return -EINVAL;
3552 p += le16_to_cpu(vram_module->usModuleSize);
3553 }
3554 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3555 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3556 } else
3557 return -EINVAL;
3558 break;
3559 default:
3560 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3561 return -EINVAL;
3562 }
3563 break;
3564 case 2:
3565 switch (crev) {
3566 case 1:
3567 /* ni */
3568 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3569 ATOM_VRAM_MODULE_V7 *vram_module =
3570 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3571 p = (u8 *)vram_info->v2_1.aVramInfo;
3572
3573 for (i = 0; i < module_index; i++) {
3574 vram_module = (ATOM_VRAM_MODULE_V7 *)p;
3575 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3576 return -EINVAL;
3577 p += le16_to_cpu(vram_module->usModuleSize);
3578 }
3579 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3580 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3581 } else
3582 return -EINVAL;
3583 break;
3584 default:
3585 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3586 return -EINVAL;
3587 }
3588 break;
3589 default:
3590 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3591 return -EINVAL;
3592 }
3593 return 0;
3594 }
3595 return -EINVAL;
3596}
3597
3598int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3599 bool gddr5, u8 module_index,
3600 struct atom_memory_clock_range_table *mclk_range_table)
3601{
3602 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3603 u8 frev, crev, i;
3604 u16 data_offset, size;
3605 union vram_info *vram_info;
3606 u32 mem_timing_size = gddr5 ?
3607 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3608 u8 *p;
3609
3610 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3611
3612 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3613 &frev, &crev, &data_offset)) {
3614 vram_info = (union vram_info *)
3615 (rdev->mode_info.atom_context->bios + data_offset);
3616 switch (frev) {
3617 case 1:
3618 switch (crev) {
3619 case 3:
3620 DRM_ERROR("old table version %d, %d\n", frev, crev);
3621 return -EINVAL;
3622 case 4:
3623 /* r7xx, evergreen */
3624 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3625 ATOM_VRAM_MODULE_V4 *vram_module =
3626 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3627 ATOM_MEMORY_TIMING_FORMAT *format;
3628 p = (u8 *)vram_info->v1_4.aVramInfo;
3629
3630 for (i = 0; i < module_index; i++) {
3631 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3632 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3633 return -EINVAL;
3634 p += le16_to_cpu(vram_module->usModuleSize);
3635 }
3636 mclk_range_table->num_entries = (u8)
3637 ((vram_module->usModuleSize - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3638 mem_timing_size);
3639 p = (u8 *)vram_module->asMemTiming;
3640 for (i = 0; i < mclk_range_table->num_entries; i++) {
3641 format = (ATOM_MEMORY_TIMING_FORMAT *)p;
3642 mclk_range_table->mclk[i] = format->ulClkRange;
3643 p += mem_timing_size;
3644 }
3645 } else
3646 return -EINVAL;
3647 break;
3648 default:
3649 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3650 return -EINVAL;
3651 }
3652 break;
3653 case 2:
3654 DRM_ERROR("new table version %d, %d\n", frev, crev);
3655 return -EINVAL;
3656 default:
3657 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3658 return -EINVAL;
3659 }
3660 return 0;
3661 }
3662 return -EINVAL;
3663}
3664
3665#define MEM_ID_MASK 0xff000000
3666#define MEM_ID_SHIFT 24
3667#define CLOCK_RANGE_MASK 0x00ffffff
3668#define CLOCK_RANGE_SHIFT 0
3669#define LOW_NIBBLE_MASK 0xf
3670#define DATA_EQU_PREV 0
3671#define DATA_FROM_TABLE 4
3672
3673int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3674 u8 module_index,
3675 struct atom_mc_reg_table *reg_table)
3676{
3677 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3678 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3679 u32 i = 0, j;
3680 u16 data_offset, size;
3681 union vram_info *vram_info;
3682
3683 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3684
3685 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3686 &frev, &crev, &data_offset)) {
3687 vram_info = (union vram_info *)
3688 (rdev->mode_info.atom_context->bios + data_offset);
3689 switch (frev) {
3690 case 1:
3691 DRM_ERROR("old table version %d, %d\n", frev, crev);
3692 return -EINVAL;
3693 case 2:
3694 switch (crev) {
3695 case 1:
3696 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3697 ATOM_INIT_REG_BLOCK *reg_block =
3698 (ATOM_INIT_REG_BLOCK *)
3699 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3700 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3701 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3702 ((u8 *)reg_block + (2 * sizeof(u16)) +
3703 le16_to_cpu(reg_block->usRegIndexTblSize));
3704 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3705 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3706 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3707 return -EINVAL;
3708 while (!(reg_block->asRegIndexBuf[i].ucPreRegDataLength & ACCESS_PLACEHOLDER) &&
3709 (i < num_entries)) {
3710 reg_table->mc_reg_address[i].s1 =
3711 (u16)(reg_block->asRegIndexBuf[i].usRegIndex);
3712 reg_table->mc_reg_address[i].pre_reg_data =
3713 (u8)(reg_block->asRegIndexBuf[i].ucPreRegDataLength);
3714 i++;
3715 }
3716 reg_table->last = i;
3717 while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
3718 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3719 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
3720 if (module_index == t_mem_id) {
3721 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3722 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
3723 for (i = 0, j = 1; i < reg_table->last; i++) {
3724 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3725 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3726 (u32)*((u32 *)reg_data + j);
3727 j++;
3728 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3729 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3730 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3731 }
3732 }
3733 num_ranges++;
3734 }
3735 reg_data += reg_block->usRegDataBlkSize;
3736 }
3737 if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
3738 return -EINVAL;
3739 reg_table->num_entries = num_ranges;
3740 } else
3741 return -EINVAL;
3742 break;
3743 default:
3744 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3745 return -EINVAL;
3746 }
3747 break;
3748 default:
3749 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3750 return -EINVAL;
3751 }
3752 return 0;
3753 }
3754 return -EINVAL;
3755}
3756
771fe6b9
JG		 3757void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3758{
3759 struct radeon_device *rdev = dev->dev_private;
3760 uint32_t bios_2_scratch, bios_6_scratch;
3761
3762 if (rdev->family >= CHIP_R600) {
4ce001ab 3763 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 3764 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3765 } else {
4ce001ab 3766 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 3767 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3768 }
3769
3770 /* let the bios control the backlight */
3771 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
3772
3773 /* tell the bios not to handle mode switching */
87364760 3774 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
771fe6b9
JG		 3775
3776 if (rdev->family >= CHIP_R600) {
3777 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3778 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3779 } else {
3780 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3781 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3782 }
3783
3784}
3785
f657c2a7
YZ		 3786void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
3787{
3788 uint32_t scratch_reg;
3789 int i;
3790
3791 if (rdev->family >= CHIP_R600)
3792 scratch_reg = R600_BIOS_0_SCRATCH;
3793 else
3794 scratch_reg = RADEON_BIOS_0_SCRATCH;
3795
3796 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3797 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
3798}
3799
3800void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
3801{
3802 uint32_t scratch_reg;
3803 int i;
3804
3805 if (rdev->family >= CHIP_R600)
3806 scratch_reg = R600_BIOS_0_SCRATCH;
3807 else
3808 scratch_reg = RADEON_BIOS_0_SCRATCH;
3809
3810 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3811 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
3812}
3813
771fe6b9
JG		 3814void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
3815{
3816 struct drm_device *dev = encoder->dev;
3817 struct radeon_device *rdev = dev->dev_private;
3818 uint32_t bios_6_scratch;
3819
3820 if (rdev->family >= CHIP_R600)
3821 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3822 else
3823 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3824
87364760 3825 if (lock) {
771fe6b9 3826 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
87364760
AD		 3827 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
3828 } else {
771fe6b9 3829 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
87364760
AD		 3830 bios_6_scratch |= ATOM_S6_ACC_MODE;
3831 }
771fe6b9
JG		 3832
3833 if (rdev->family >= CHIP_R600)
3834 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3835 else
3836 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3837}
3838
3839/* at some point we may want to break this out into individual functions */
3840void
3841radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
3842 struct drm_encoder *encoder,
3843 bool connected)
3844{
3845 struct drm_device *dev = connector->dev;
3846 struct radeon_device *rdev = dev->dev_private;
3847 struct radeon_connector *radeon_connector =
3848 to_radeon_connector(connector);
3849 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3850 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
3851
3852 if (rdev->family >= CHIP_R600) {
3853 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
3854 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3855 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3856 } else {
3857 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3858 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3859 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3860 }
3861
3862 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3863 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3864 if (connected) {
d9fdaafb 3865 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3866 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
3867 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
3868 } else {
d9fdaafb 3869 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3870 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
3871 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
3872 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
3873 }
3874 }
3875 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
3876 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
3877 if (connected) {
d9fdaafb 3878 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 3879 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
3880 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
3881 } else {
d9fdaafb 3882 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 3883 bios_0_scratch &= ~ATOM_S0_CV_MASK;
3884 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
3885 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
3886 }
3887 }
3888 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3889 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3890 if (connected) {
d9fdaafb 3891 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3892 bios_0_scratch |= ATOM_S0_LCD1;
3893 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
3894 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
3895 } else {
d9fdaafb 3896 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3897 bios_0_scratch &= ~ATOM_S0_LCD1;
3898 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
3899 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
3900 }
3901 }
3902 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3903 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3904 if (connected) {
d9fdaafb 3905 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3906 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
3907 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
3908 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
3909 } else {
d9fdaafb 3910 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3911 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
3912 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
3913 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
3914 }
3915 }
3916 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3917 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3918 if (connected) {
d9fdaafb 3919 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3920 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
3921 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
3922 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
3923 } else {
d9fdaafb 3924 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3925 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
3926 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
3927 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
3928 }
3929 }
3930 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3931 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3932 if (connected) {
d9fdaafb 3933 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3934 bios_0_scratch |= ATOM_S0_DFP1;
3935 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
3936 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
3937 } else {
d9fdaafb 3938 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3939 bios_0_scratch &= ~ATOM_S0_DFP1;
3940 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
3941 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
3942 }
3943 }
3944 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3945 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3946 if (connected) {
d9fdaafb 3947 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3948 bios_0_scratch |= ATOM_S0_DFP2;
3949 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
3950 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
3951 } else {
d9fdaafb 3952 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3953 bios_0_scratch &= ~ATOM_S0_DFP2;
3954 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
3955 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
3956 }
3957 }
3958 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
3959 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
3960 if (connected) {
d9fdaafb 3961 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 3962 bios_0_scratch |= ATOM_S0_DFP3;
3963 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
3964 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
3965 } else {
d9fdaafb 3966 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 3967 bios_0_scratch &= ~ATOM_S0_DFP3;
3968 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
3969 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
3970 }
3971 }
3972 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3973 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3974 if (connected) {
d9fdaafb 3975 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 3976 bios_0_scratch |= ATOM_S0_DFP4;
3977 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3978 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3979 } else {
d9fdaafb 3980 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 3981 bios_0_scratch &= ~ATOM_S0_DFP4;
3982 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3983 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3984 }
3985 }
3986 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3987 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3988 if (connected) {
d9fdaafb 3989 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 3990 bios_0_scratch |= ATOM_S0_DFP5;
3991 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3992 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3993 } else {
d9fdaafb 3994 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 3995 bios_0_scratch &= ~ATOM_S0_DFP5;
3996 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3997 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3998 }
3999 }
6f9f8a61
AD		 4000 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4001 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4002 if (connected) {
4003 DRM_DEBUG_KMS("DFP6 connected\n");
4004 bios_0_scratch |= ATOM_S0_DFP6;
4005 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4006 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4007 } else {
4008 DRM_DEBUG_KMS("DFP6 disconnected\n");
4009 bios_0_scratch &= ~ATOM_S0_DFP6;
4010 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4011 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4012 }
4013 }
771fe6b9
JG		 4014
4015 if (rdev->family >= CHIP_R600) {
4016 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4017 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4018 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4019 } else {
4020 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4021 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4022 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4023 }
4024}
4025
4026void
4027radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4028{
4029 struct drm_device *dev = encoder->dev;
4030 struct radeon_device *rdev = dev->dev_private;
4031 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4032 uint32_t bios_3_scratch;
4033
6f9f8a61
AD		 4034 if (ASIC_IS_DCE4(rdev))
4035 return;
4036
771fe6b9
JG		 4037 if (rdev->family >= CHIP_R600)
4038 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4039 else
4040 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4041
4042 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4043 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4044 bios_3_scratch |= (crtc << 18);
4045 }
4046 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4047 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4048 bios_3_scratch |= (crtc << 24);
4049 }
4050 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4051 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4052 bios_3_scratch |= (crtc << 16);
4053 }
4054 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4055 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4056 bios_3_scratch |= (crtc << 20);
4057 }
4058 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4059 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4060 bios_3_scratch |= (crtc << 17);
4061 }
4062 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4063 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4064 bios_3_scratch |= (crtc << 19);
4065 }
4066 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4067 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4068 bios_3_scratch |= (crtc << 23);
4069 }
4070 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4071 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4072 bios_3_scratch |= (crtc << 25);
4073 }
4074
4075 if (rdev->family >= CHIP_R600)
4076 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4077 else
4078 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4079}
4080
4081void
4082radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4083{
4084 struct drm_device *dev = encoder->dev;
4085 struct radeon_device *rdev = dev->dev_private;
4086 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4087 uint32_t bios_2_scratch;
4088
3ac0eb6d
AD		 4089 if (ASIC_IS_DCE4(rdev))
4090 return;
4091
771fe6b9
JG		 4092 if (rdev->family >= CHIP_R600)
4093 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4094 else
4095 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4096
4097 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4098 if (on)
4099 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4100 else
4101 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4102 }
4103 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4104 if (on)
4105 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4106 else
4107 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4108 }
4109 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4110 if (on)
4111 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4112 else
4113 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4114 }
4115 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4116 if (on)
4117 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4118 else
4119 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4120 }
4121 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4122 if (on)
4123 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4124 else
4125 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4126 }
4127 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4128 if (on)
4129 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4130 else
4131 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4132 }
4133 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4134 if (on)
4135 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4136 else
4137 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4138 }
4139 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4140 if (on)
4141 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4142 else
4143 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4144 }
4145 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4146 if (on)
4147 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4148 else
4149 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4150 }
4151 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4152 if (on)
4153 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4154 else
4155 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4156 }
4157
4158 if (rdev->family >= CHIP_R600)
4159 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4160 else
4161 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4162}
Linux kernel - Deliverables
This page took 0.882492 seconds and 5 git commands to generate.