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drm/radeon/kms: fix s/r issues with bios scratch regs
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36868bda 40 uint32_t supported_device, u16 caps);
771fe6b9
JG		 41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
3074adc8
AD		 101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
a084e6ee
AD		 109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
f376b94f
AD		 139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
a084e6ee
AD		 141 break;
142 }
d3f420d1
AD		 143 }
144 }
771fe6b9
JG		 145
146 return i2c;
147}
148
f376b94f
AD		 149void radeon_atombios_i2c_init(struct radeon_device *rdev)
150{
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
ea39302b
AD		 171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (gpio->usClkMaskRegisterIndex == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
3074adc8
AD		 185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
f376b94f
AD		 193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229}
230
eed45b30
AD		 231static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233{
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
a084e6ee
AD		 245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 247
a084e6ee
AD		 248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 250
a084e6ee
AD		 251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = pin->usGpioPin_AIndex * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
eed45b30
AD		 260 }
261 }
262
263 return gpio;
264}
265
266static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268{
269 struct radeon_hpd hpd;
bcc1c2a1
AD		 270 u32 reg;
271
1d978dac
JD		 272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
bcc1c2a1
AD		 274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
eed45b30 279 hpd.gpio = *gpio;
bcc1c2a1 280 if (gpio->reg == reg) {
eed45b30
AD		 281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307}
308
771fe6b9
JG		 309static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
848577ee 312 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
771fe6b9
JG		 315{
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
c86a9038
AD		 326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
f36fce0f
AD		 335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
771fe6b9
JG		 344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 357 i2c_bus->valid = false;
848577ee
AD		 358 *line_mux = 53;
359 }
771fe6b9
JG		 360 }
361
4e3f9b78
AD		 362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
aa1a750e
DA		 370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
771fe6b9
JG		 379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
e1e8a5dd
AD		 386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
771fe6b9
JG		 388 }
389
be23da8a
AD		 390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
f598aa75
AD		 395 }
396
771fe6b9
JG		 397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 402 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 403 }
404 }
405
e153b70b
AD		 406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
705af9c7
AD		 415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 420 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 421 }
422 }
423
705af9c7
AD		 424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
2f299d5d
AD		 434 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
3e5f8ff3
AD		 443 if ((dev->pdev->device == 0x95c4) &&
444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be 447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
2f299d5d 448 /* actually it's a DVI-D port not DVI-I */
3e5f8ff3 449 *connector_type = DRM_MODE_CONNECTOR_DVID;
2f299d5d 450 return false;
9ea2c4be 451 }
3e5f8ff3
AD		 452 }
453
efa8450f
DA		 454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
771fe6b9
JG		 463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
b75fad06
AD		 485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
771fe6b9
JG		 502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
705af9c7 512 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 533 u16 size, data_offset;
534 u8 frev, crev;
771fe6b9 535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
36868bda 536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
26b5bc98 537 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 540 int i, j, k, path_size, device_support;
771fe6b9 541 int connector_type;
eed45b30 542 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 543 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 544 struct radeon_router router;
eed45b30
AD		 545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
a084e6ee 548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
36868bda
AD		 561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
26b5bc98
AD		 564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
5137ee94 576
771fe6b9
JG		 577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
4bbd4973
DA		 590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 593 continue;
594
ee59f2b4
AD		 595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
a084e6ee
AD		 606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
771fe6b9
JG		 635 } else
636 continue;
a084e6ee
AD		 637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
771fe6b9
JG		 643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
b75fad06 647 connector_object_id = con_obj_id;
771fe6b9
JG		 648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
bdd91b2b
TW		 653 router.ddc_valid = false;
654 router.cd_valid = false;
26b5bc98
AD		 655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 657
26b5bc98 658 grph_obj_id =
771fe6b9
JG		 659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 661 grph_obj_num =
771fe6b9
JG		 662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 664 grph_obj_type =
771fe6b9
JG		 665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
26b5bc98 668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
36868bda
AD		 669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
771fe6b9 677
36868bda
AD		 678 while (record->ucRecordType > 0 &&
679 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
680 switch (record->ucRecordType) {
681 case ATOM_ENCODER_CAP_RECORD_TYPE:
682 cap_record =(ATOM_ENCODER_CAP_RECORD *)
683 record;
684 caps = le16_to_cpu(cap_record->usEncoderCap);
685 break;
686 }
687 record = (ATOM_COMMON_RECORD_HEADER *)
688 ((char *)record + record->ucRecordSize);
689 }
690 radeon_add_atom_encoder(dev,
691 encoder_obj,
692 le16_to_cpu
693 (path->
694 usDeviceTag),
695 caps);
696 }
697 }
26b5bc98 698 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 699 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 700 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 701 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
702 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
703 (ctx->bios + data_offset +
704 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
705 ATOM_I2C_RECORD *i2c_record;
706 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
707 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 708 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 709 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
710 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
711 (ctx->bios + data_offset +
712 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
713 int enum_id;
714
715 router.router_id = router_obj_id;
716 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
717 enum_id++) {
718 if (le16_to_cpu(path->usConnObjectId) ==
719 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
720 break;
721 }
722
723 while (record->ucRecordType > 0 &&
724 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
725 switch (record->ucRecordType) {
726 case ATOM_I2C_RECORD_TYPE:
727 i2c_record =
728 (ATOM_I2C_RECORD *)
729 record;
730 i2c_config =
731 (ATOM_I2C_ID_CONFIG_ACCESS *)
732 &i2c_record->sucI2cId;
733 router.i2c_info =
734 radeon_lookup_i2c_gpio(rdev,
735 i2c_config->
736 ucAccess);
737 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
738 break;
739 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
740 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
741 record;
fb939dfc
AD		 742 router.ddc_valid = true;
743 router.ddc_mux_type = ddc_path->ucMuxType;
744 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
745 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
746 break;
747 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
748 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
749 record;
750 router.cd_valid = true;
751 router.cd_mux_type = cd_path->ucMuxType;
752 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
753 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 754 break;
755 }
756 record = (ATOM_COMMON_RECORD_HEADER *)
757 ((char *)record + record->ucRecordSize);
758 }
759 }
760 }
771fe6b9
JG		 761 }
762 }
763
eed45b30 764 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 765 ddc_bus.valid = false;
766 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 767 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 768 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 769 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
770 if (le16_to_cpu(path->usConnObjectId) ==
771 le16_to_cpu(con_obj->asObjects[j].
772 usObjectID)) {
773 ATOM_COMMON_RECORD_HEADER
774 *record =
775 (ATOM_COMMON_RECORD_HEADER
776 *)
777 (ctx->bios + data_offset +
778 le16_to_cpu(con_obj->
779 asObjects[j].
780 usRecordOffset));
781 ATOM_I2C_RECORD *i2c_record;
eed45b30 782 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 783 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 784
771fe6b9
JG		 785 while (record->ucRecordType > 0
786 && record->
787 ucRecordType <=
788 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 789 switch (record->ucRecordType) {
771fe6b9
JG		 790 case ATOM_I2C_RECORD_TYPE:
791 i2c_record =
eed45b30
AD		 792 (ATOM_I2C_RECORD *)
793 record;
d3f420d1
AD		 794 i2c_config =
795 (ATOM_I2C_ID_CONFIG_ACCESS *)
796 &i2c_record->sucI2cId;
eed45b30 797 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 798 i2c_config->
799 ucAccess);
eed45b30
AD		 800 break;
801 case ATOM_HPD_INT_RECORD_TYPE:
802 hpd_record =
803 (ATOM_HPD_INT_RECORD *)
804 record;
805 gpio = radeon_lookup_gpio(rdev,
806 hpd_record->ucHPDIntGPIOID);
807 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
808 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 809 break;
810 }
811 record =
812 (ATOM_COMMON_RECORD_HEADER
813 *) ((char *)record
814 +
815 record->
816 ucRecordSize);
817 }
818 break;
819 }
820 }
eed45b30 821 }
771fe6b9 822
bcc1c2a1 823 /* needed for aux chan transactions */
8e36ed00 824 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 825
705af9c7
AD		 826 conn_id = le16_to_cpu(path->usConnObjectId);
827
828 if (!radeon_atom_apply_quirks
829 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 830 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 831 continue;
832
771fe6b9 833 radeon_add_atom_connector(dev,
705af9c7 834 conn_id,
771fe6b9
JG		 835 le16_to_cpu(path->
836 usDeviceTag),
837 connector_type, &ddc_bus,
5137ee94 838 igp_lane_info,
eed45b30 839 connector_object_id,
26b5bc98
AD		 840 &hpd,
841 &router);
771fe6b9
JG		 842
843 }
844 }
845
846 radeon_link_encoder_connector(dev);
847
848 return true;
849}
850
b75fad06
AD		 851static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
852 int connector_type,
853 uint16_t devices)
854{
855 struct radeon_device *rdev = dev->dev_private;
856
857 if (rdev->flags & RADEON_IS_IGP) {
858 return supported_devices_connector_object_id_convert
859 [connector_type];
860 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
861 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
862 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
863 struct radeon_mode_info *mode_info = &rdev->mode_info;
864 struct atom_context *ctx = mode_info->atom_context;
865 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
866 uint16_t size, data_offset;
867 uint8_t frev, crev;
868 ATOM_XTMDS_INFO *xtmds;
869
a084e6ee
AD		 870 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
871 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 872
a084e6ee
AD		 873 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
874 if (connector_type == DRM_MODE_CONNECTOR_DVII)
875 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
876 else
877 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
878 } else {
879 if (connector_type == DRM_MODE_CONNECTOR_DVII)
880 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
881 else
882 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
883 }
884 } else
885 return supported_devices_connector_object_id_convert
886 [connector_type];
b75fad06
AD		 887 } else {
888 return supported_devices_connector_object_id_convert
889 [connector_type];
890 }
891}
892
771fe6b9
JG		 893struct bios_connector {
894 bool valid;
705af9c7 895 uint16_t line_mux;
771fe6b9
JG		 896 uint16_t devices;
897 int connector_type;
898 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 899 struct radeon_hpd hpd;
771fe6b9
JG		 900};
901
902bool radeon_get_atom_connector_info_from_supported_devices_table(struct
903 drm_device
904 *dev)
905{
906 struct radeon_device *rdev = dev->dev_private;
907 struct radeon_mode_info *mode_info = &rdev->mode_info;
908 struct atom_context *ctx = mode_info->atom_context;
909 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
910 uint16_t size, data_offset;
911 uint8_t frev, crev;
912 uint16_t device_support;
913 uint8_t dac;
914 union atom_supported_devices *supported_devices;
eed45b30 915 int i, j, max_device;
f49d273d
PB		 916 struct bios_connector *bios_connectors;
917 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 918 struct radeon_router router;
919
fb939dfc
AD		 920 router.ddc_valid = false;
921 router.cd_valid = false;
771fe6b9 922
f49d273d
PB		 923 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
924 if (!bios_connectors)
925 return false;
926
927 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
928 &data_offset)) {
929 kfree(bios_connectors);
a084e6ee 930 return false;
f49d273d 931 }
771fe6b9
JG		 932
933 supported_devices =
934 (union atom_supported_devices *)(ctx->bios + data_offset);
935
936 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
937
eed45b30
AD		 938 if (frev > 1)
939 max_device = ATOM_MAX_SUPPORTED_DEVICE;
940 else
941 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
942
943 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 944 ATOM_CONNECTOR_INFO_I2C ci =
945 supported_devices->info.asConnInfo[i];
946
947 bios_connectors[i].valid = false;
948
949 if (!(device_support & (1 << i))) {
950 continue;
951 }
952
953 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 954 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 955 continue;
956 }
957
771fe6b9
JG		 958 bios_connectors[i].connector_type =
959 supported_devices_connector_convert[ci.sucConnectorInfo.
960 sbfAccess.
961 bfConnectorType];
962
963 if (bios_connectors[i].connector_type ==
964 DRM_MODE_CONNECTOR_Unknown)
965 continue;
966
967 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
968
d3f420d1
AD		 969 bios_connectors[i].line_mux =
970 ci.sucI2cId.ucAccess;
771fe6b9
JG		 971
972 /* give tv unique connector ids */
973 if (i == ATOM_DEVICE_TV1_INDEX) {
974 bios_connectors[i].ddc_bus.valid = false;
975 bios_connectors[i].line_mux = 50;
976 } else if (i == ATOM_DEVICE_TV2_INDEX) {
977 bios_connectors[i].ddc_bus.valid = false;
978 bios_connectors[i].line_mux = 51;
979 } else if (i == ATOM_DEVICE_CV_INDEX) {
980 bios_connectors[i].ddc_bus.valid = false;
981 bios_connectors[i].line_mux = 52;
982 } else
983 bios_connectors[i].ddc_bus =
eed45b30
AD		 984 radeon_lookup_i2c_gpio(rdev,
985 bios_connectors[i].line_mux);
986
987 if ((crev > 1) && (frev > 1)) {
988 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
989 switch (isb) {
990 case 0x4:
991 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
992 break;
993 case 0xa:
994 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
995 break;
996 default:
997 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
998 break;
999 }
1000 } else {
1001 if (i == ATOM_DEVICE_DFP1_INDEX)
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1003 else if (i == ATOM_DEVICE_DFP2_INDEX)
1004 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1005 else
1006 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1007 }
771fe6b9
JG		 1008
1009 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1010 * shared with a DVI port, we'll pick up the DVI connector when we
1011 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1012 */
1013 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1014 bios_connectors[i].connector_type =
1015 DRM_MODE_CONNECTOR_VGA;
1016
1017 if (!radeon_atom_apply_quirks
1018 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 1019 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1020 &bios_connectors[i].hpd))
771fe6b9
JG		 1021 continue;
1022
1023 bios_connectors[i].valid = true;
1024 bios_connectors[i].devices = (1 << i);
1025
1026 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1027 radeon_add_atom_encoder(dev,
5137ee94 1028 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1029 (1 << i),
1030 dac),
36868bda
AD		 1031 (1 << i),
1032 0);
771fe6b9
JG		 1033 else
1034 radeon_add_legacy_encoder(dev,
5137ee94 1035 radeon_get_encoder_enum(dev,
f56cd64f 1036 (1 << i),
771fe6b9
JG		 1037 dac),
1038 (1 << i));
1039 }
1040
1041 /* combine shared connectors */
eed45b30 1042 for (i = 0; i < max_device; i++) {
771fe6b9 1043 if (bios_connectors[i].valid) {
eed45b30 1044 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 1045 if (bios_connectors[j].valid && (i != j)) {
1046 if (bios_connectors[i].line_mux ==
1047 bios_connectors[j].line_mux) {
f56cd64f
AD		 1048 /* make sure not to combine LVDS */
1049 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1050 bios_connectors[i].line_mux = 53;
1051 bios_connectors[i].ddc_bus.valid = false;
1052 continue;
1053 }
1054 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1055 bios_connectors[j].line_mux = 53;
1056 bios_connectors[j].ddc_bus.valid = false;
1057 continue;
1058 }
1059 /* combine analog and digital for DVI-I */
1060 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1061 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1062 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1063 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1064 bios_connectors[i].devices |=
1065 bios_connectors[j].devices;
1066 bios_connectors[i].connector_type =
1067 DRM_MODE_CONNECTOR_DVII;
1068 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1069 bios_connectors[i].hpd =
1070 bios_connectors[j].hpd;
f56cd64f 1071 bios_connectors[j].valid = false;
771fe6b9
JG		 1072 }
1073 }
1074 }
1075 }
1076 }
1077 }
1078
1079 /* add the connectors */
eed45b30 1080 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1081 if (bios_connectors[i].valid) {
1082 uint16_t connector_object_id =
1083 atombios_get_connector_object_id(dev,
1084 bios_connectors[i].connector_type,
1085 bios_connectors[i].devices);
771fe6b9
JG		 1086 radeon_add_atom_connector(dev,
1087 bios_connectors[i].line_mux,
1088 bios_connectors[i].devices,
1089 bios_connectors[i].
1090 connector_type,
1091 &bios_connectors[i].ddc_bus,
5137ee94 1092 0,
eed45b30 1093 connector_object_id,
26b5bc98
AD		 1094 &bios_connectors[i].hpd,
1095 &router);
b75fad06 1096 }
771fe6b9
JG		 1097 }
1098
1099 radeon_link_encoder_connector(dev);
1100
f49d273d 1101 kfree(bios_connectors);
771fe6b9
JG		 1102 return true;
1103}
1104
1105union firmware_info {
1106 ATOM_FIRMWARE_INFO info;
1107 ATOM_FIRMWARE_INFO_V1_2 info_12;
1108 ATOM_FIRMWARE_INFO_V1_3 info_13;
1109 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1110 ATOM_FIRMWARE_INFO_V2_1 info_21;
f82b3ddc 1111 ATOM_FIRMWARE_INFO_V2_2 info_22;
771fe6b9
JG		 1112};
1113
1114bool radeon_atom_get_clock_info(struct drm_device *dev)
1115{
1116 struct radeon_device *rdev = dev->dev_private;
1117 struct radeon_mode_info *mode_info = &rdev->mode_info;
1118 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1119 union firmware_info *firmware_info;
1120 uint8_t frev, crev;
1121 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1122 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1123 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1124 struct radeon_pll *spll = &rdev->clock.spll;
1125 struct radeon_pll *mpll = &rdev->clock.mpll;
1126 uint16_t data_offset;
1127
a084e6ee
AD		 1128 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1129 &frev, &crev, &data_offset)) {
1130 firmware_info =
1131 (union firmware_info *)(mode_info->atom_context->bios +
1132 data_offset);
771fe6b9
JG		 1133 /* pixel clocks */
1134 p1pll->reference_freq =
1135 le16_to_cpu(firmware_info->info.usReferenceClock);
1136 p1pll->reference_div = 0;
1137
bc293e58
MF		 1138 if (crev < 2)
1139 p1pll->pll_out_min =
1140 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1141 else
1142 p1pll->pll_out_min =
1143 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1144 p1pll->pll_out_max =
1145 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1146
86cb2bbf
AD		 1147 if (crev >= 4) {
1148 p1pll->lcd_pll_out_min =
1149 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1150 if (p1pll->lcd_pll_out_min == 0)
1151 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1152 p1pll->lcd_pll_out_max =
1153 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1154 if (p1pll->lcd_pll_out_max == 0)
1155 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1156 } else {
1157 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1158 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1159 }
1160
771fe6b9
JG		 1161 if (p1pll->pll_out_min == 0) {
1162 if (ASIC_IS_AVIVO(rdev))
1163 p1pll->pll_out_min = 64800;
1164 else
1165 p1pll->pll_out_min = 20000;
1166 }
1167
1168 p1pll->pll_in_min =
1169 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1170 p1pll->pll_in_max =
1171 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1172
1173 *p2pll = *p1pll;
1174
1175 /* system clock */
f82b3ddc
AD		 1176 if (ASIC_IS_DCE4(rdev))
1177 spll->reference_freq =
1178 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1179 else
1180 spll->reference_freq =
1181 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1182 spll->reference_div = 0;
1183
1184 spll->pll_out_min =
1185 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1186 spll->pll_out_max =
1187 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1188
1189 /* ??? */
1190 if (spll->pll_out_min == 0) {
1191 if (ASIC_IS_AVIVO(rdev))
1192 spll->pll_out_min = 64800;
1193 else
1194 spll->pll_out_min = 20000;
1195 }
1196
1197 spll->pll_in_min =
1198 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1199 spll->pll_in_max =
1200 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1201
1202 /* memory clock */
f82b3ddc
AD		 1203 if (ASIC_IS_DCE4(rdev))
1204 mpll->reference_freq =
1205 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1206 else
1207 mpll->reference_freq =
1208 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1209 mpll->reference_div = 0;
1210
1211 mpll->pll_out_min =
1212 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1213 mpll->pll_out_max =
1214 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1215
1216 /* ??? */
1217 if (mpll->pll_out_min == 0) {
1218 if (ASIC_IS_AVIVO(rdev))
1219 mpll->pll_out_min = 64800;
1220 else
1221 mpll->pll_out_min = 20000;
1222 }
1223
1224 mpll->pll_in_min =
1225 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1226 mpll->pll_in_max =
1227 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1228
1229 rdev->clock.default_sclk =
1230 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1231 rdev->clock.default_mclk =
1232 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1233
bcc1c2a1
AD		 1234 if (ASIC_IS_DCE4(rdev)) {
1235 rdev->clock.default_dispclk =
1236 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
f82b3ddc
AD		 1237 if (rdev->clock.default_dispclk == 0) {
1238 if (ASIC_IS_DCE5(rdev))
1239 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1240 else
1241 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1242 }
bcc1c2a1
AD		 1243 rdev->clock.dp_extclk =
1244 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1245 }
1246 *dcpll = *p1pll;
1247
771fe6b9
JG		 1248 return true;
1249 }
bcc1c2a1 1250
771fe6b9
JG		 1251 return false;
1252}
1253
06b6476d
AD		 1254union igp_info {
1255 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1256 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1257};
1258
1259bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1260{
1261 struct radeon_mode_info *mode_info = &rdev->mode_info;
1262 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1263 union igp_info *igp_info;
1264 u8 frev, crev;
1265 u16 data_offset;
1266
4c70b2ea
AD		 1267 /* sideport is AMD only */
1268 if (rdev->family == CHIP_RS600)
1269 return false;
1270
a084e6ee
AD		 1271 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1272 &frev, &crev, &data_offset)) {
1273 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1274 data_offset);
06b6476d
AD		 1275 switch (crev) {
1276 case 1:
4c70b2ea
AD		 1277 if (igp_info->info.ulBootUpMemoryClock)
1278 return true;
06b6476d
AD		 1279 break;
1280 case 2:
4b80d954 1281 if (igp_info->info_2.ulBootUpSidePortClock)
06b6476d
AD		 1282 return true;
1283 break;
1284 default:
1285 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1286 break;
1287 }
1288 }
1289 return false;
1290}
1291
445282db
DA		 1292bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1293 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1294{
1295 struct drm_device *dev = encoder->base.dev;
1296 struct radeon_device *rdev = dev->dev_private;
1297 struct radeon_mode_info *mode_info = &rdev->mode_info;
1298 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1299 uint16_t data_offset;
1300 struct _ATOM_TMDS_INFO *tmds_info;
1301 uint8_t frev, crev;
1302 uint16_t maxfreq;
1303 int i;
771fe6b9 1304
a084e6ee
AD		 1305 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1306 &frev, &crev, &data_offset)) {
1307 tmds_info =
1308 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1309 data_offset);
771fe6b9 1310
771fe6b9
JG		 1311 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1312 for (i = 0; i < 4; i++) {
1313 tmds->tmds_pll[i].freq =
1314 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1315 tmds->tmds_pll[i].value =
1316 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1317 tmds->tmds_pll[i].value |=
1318 (tmds_info->asMiscInfo[i].
1319 ucPLL_VCO_Gain & 0x3f) << 6;
1320 tmds->tmds_pll[i].value |=
1321 (tmds_info->asMiscInfo[i].
1322 ucPLL_DutyCycle & 0xf) << 12;
1323 tmds->tmds_pll[i].value |=
1324 (tmds_info->asMiscInfo[i].
1325 ucPLL_VoltageSwing & 0xf) << 16;
1326
d9fdaafb 1327 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1328 tmds->tmds_pll[i].freq,
1329 tmds->tmds_pll[i].value);
1330
1331 if (maxfreq == tmds->tmds_pll[i].freq) {
1332 tmds->tmds_pll[i].freq = 0xffffffff;
1333 break;
1334 }
1335 }
445282db 1336 return true;
771fe6b9 1337 }
445282db 1338 return false;
771fe6b9
JG		 1339}
1340
ba032a58
AD		 1341bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1342 struct radeon_atom_ss *ss,
1343 int id)
ebbe1cb9 1344{
ebbe1cb9
AD		 1345 struct radeon_mode_info *mode_info = &rdev->mode_info;
1346 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1347 uint16_t data_offset, size;
ebbe1cb9
AD		 1348 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1349 uint8_t frev, crev;
ba032a58 1350 int i, num_indices;
ebbe1cb9 1351
ba032a58
AD		 1352 memset(ss, 0, sizeof(struct radeon_atom_ss));
1353 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1354 &frev, &crev, &data_offset)) {
1355 ss_info =
1356 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1357
ba032a58
AD		 1358 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1359 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1360
ba032a58 1361 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1362 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1363 ss->percentage =
1364 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1365 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1366 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1367 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1368 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1369 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1370 return true;
1371 }
1372 }
1373 }
1374 return false;
1375}
1376
4339c442
AD		 1377static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1378 struct radeon_atom_ss *ss,
1379 int id)
1380{
1381 struct radeon_mode_info *mode_info = &rdev->mode_info;
1382 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1383 u16 data_offset, size;
1384 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1385 u8 frev, crev;
1386 u16 percentage = 0, rate = 0;
1387
1388 /* get any igp specific overrides */
1389 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1390 &frev, &crev, &data_offset)) {
1391 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1392 (mode_info->atom_context->bios + data_offset);
1393 switch (id) {
1394 case ASIC_INTERNAL_SS_ON_TMDS:
1395 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1396 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1397 break;
1398 case ASIC_INTERNAL_SS_ON_HDMI:
1399 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1400 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1401 break;
1402 case ASIC_INTERNAL_SS_ON_LVDS:
1403 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1404 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1405 break;
1406 }
1407 if (percentage)
1408 ss->percentage = percentage;
1409 if (rate)
1410 ss->rate = rate;
1411 }
1412}
1413
ba032a58
AD		 1414union asic_ss_info {
1415 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1416 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1417 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1418};
1419
1420bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1421 struct radeon_atom_ss *ss,
1422 int id, u32 clock)
1423{
1424 struct radeon_mode_info *mode_info = &rdev->mode_info;
1425 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1426 uint16_t data_offset, size;
1427 union asic_ss_info *ss_info;
1428 uint8_t frev, crev;
1429 int i, num_indices;
1430
1431 memset(ss, 0, sizeof(struct radeon_atom_ss));
1432 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1433 &frev, &crev, &data_offset)) {
1434
1435 ss_info =
1436 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1437
1438 switch (frev) {
1439 case 1:
1440 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1441 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1442
1443 for (i = 0; i < num_indices; i++) {
1444 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1445 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1446 ss->percentage =
1447 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1448 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1449 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1450 return true;
1451 }
279b215e 1452 }
ba032a58
AD		 1453 break;
1454 case 2:
1455 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1456 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1457 for (i = 0; i < num_indices; i++) {
1458 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1459 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1460 ss->percentage =
1461 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1462 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1463 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1464 return true;
1465 }
1466 }
1467 break;
1468 case 3:
1469 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1470 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1471 for (i = 0; i < num_indices; i++) {
1472 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1473 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1474 ss->percentage =
1475 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1476 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1477 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
4339c442
AD		 1478 if (rdev->flags & RADEON_IS_IGP)
1479 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
ba032a58
AD		 1480 return true;
1481 }
1482 }
1483 break;
1484 default:
1485 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1486 break;
279b215e 1487 }
ba032a58 1488
ebbe1cb9 1489 }
ba032a58 1490 return false;
ebbe1cb9
AD		 1491}
1492
771fe6b9
JG		 1493union lvds_info {
1494 struct _ATOM_LVDS_INFO info;
1495 struct _ATOM_LVDS_INFO_V12 info_12;
1496};
1497
1498struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1499 radeon_encoder
1500 *encoder)
1501{
1502 struct drm_device *dev = encoder->base.dev;
1503 struct radeon_device *rdev = dev->dev_private;
1504 struct radeon_mode_info *mode_info = &rdev->mode_info;
1505 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1506 uint16_t data_offset, misc;
771fe6b9
JG		 1507 union lvds_info *lvds_info;
1508 uint8_t frev, crev;
1509 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1510 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1511
a084e6ee
AD		 1512 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1513 &frev, &crev, &data_offset)) {
1514 lvds_info =
1515 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1516 lvds =
1517 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1518
1519 if (!lvds)
1520 return NULL;
1521
de2103e4 1522 lvds->native_mode.clock =
771fe6b9 1523 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1524 lvds->native_mode.hdisplay =
771fe6b9 1525 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1526 lvds->native_mode.vdisplay =
771fe6b9 1527 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1528 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1529 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1530 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1531 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1532 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1533 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1534 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1535 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1536 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1537 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1538 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1539 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1540 lvds->panel_pwr_delay =
1541 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1542 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1543
1544 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1545 if (misc & ATOM_VSYNC_POLARITY)
1546 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1547 if (misc & ATOM_HSYNC_POLARITY)
1548 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1549 if (misc & ATOM_COMPOSITESYNC)
1550 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1551 if (misc & ATOM_INTERLACE)
1552 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1553 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1554 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1555
7a868e18
AD		 1556 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1557 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1558
de2103e4
AD		 1559 /* set crtc values */
1560 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1561
ba032a58 1562 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1563
771fe6b9 1564 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1565
1566 if (encoder_enum == 2)
1567 lvds->linkb = true;
1568 else
1569 lvds->linkb = false;
1570
c324acd5
AD		 1571 /* parse the lcd record table */
1572 if (lvds_info->info.usModePatchTableOffset) {
1573 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1574 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1575 bool bad_record = false;
1576 u8 *record = (u8 *)(mode_info->atom_context->bios +
1577 data_offset +
1578 lvds_info->info.usModePatchTableOffset);
1579 while (*record != ATOM_RECORD_END_TYPE) {
1580 switch (*record) {
1581 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1582 record += sizeof(ATOM_PATCH_RECORD_MODE);
1583 break;
1584 case LCD_RTS_RECORD_TYPE:
1585 record += sizeof(ATOM_LCD_RTS_RECORD);
1586 break;
1587 case LCD_CAP_RECORD_TYPE:
1588 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1589 break;
1590 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1591 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1592 if (fake_edid_record->ucFakeEDIDLength) {
1593 struct edid *edid;
1594 int edid_size =
1595 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1596 edid = kmalloc(edid_size, GFP_KERNEL);
1597 if (edid) {
1598 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1599 fake_edid_record->ucFakeEDIDLength);
1600
1601 if (drm_edid_is_valid(edid))
1602 rdev->mode_info.bios_hardcoded_edid = edid;
1603 else
1604 kfree(edid);
1605 }
1606 }
1607 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1608 break;
1609 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1610 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1611 lvds->native_mode.width_mm = panel_res_record->usHSize;
1612 lvds->native_mode.height_mm = panel_res_record->usVSize;
1613 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1614 break;
1615 default:
1616 DRM_ERROR("Bad LCD record %d\n", *record);
1617 bad_record = true;
1618 break;
1619 }
1620 if (bad_record)
1621 break;
1622 }
1623 }
771fe6b9
JG		 1624 }
1625 return lvds;
1626}
1627
6fe7ac3f
AD		 1628struct radeon_encoder_primary_dac *
1629radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1630{
1631 struct drm_device *dev = encoder->base.dev;
1632 struct radeon_device *rdev = dev->dev_private;
1633 struct radeon_mode_info *mode_info = &rdev->mode_info;
1634 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1635 uint16_t data_offset;
1636 struct _COMPASSIONATE_DATA *dac_info;
1637 uint8_t frev, crev;
1638 uint8_t bg, dac;
6fe7ac3f
AD		 1639 struct radeon_encoder_primary_dac *p_dac = NULL;
1640
a084e6ee
AD		 1641 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1642 &frev, &crev, &data_offset)) {
1643 dac_info = (struct _COMPASSIONATE_DATA *)
1644 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1645
6fe7ac3f
AD		 1646 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1647
1648 if (!p_dac)
1649 return NULL;
1650
1651 bg = dac_info->ucDAC1_BG_Adjustment;
1652 dac = dac_info->ucDAC1_DAC_Adjustment;
1653 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1654
1655 }
1656 return p_dac;
1657}
1658
4ce001ab 1659bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1660 struct drm_display_mode *mode)
4ce001ab
DA		 1661{
1662 struct radeon_mode_info *mode_info = &rdev->mode_info;
1663 ATOM_ANALOG_TV_INFO *tv_info;
1664 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1665 ATOM_DTD_FORMAT *dtd_timings;
1666 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1667 u8 frev, crev;
5a9bcacc 1668 u16 data_offset, misc;
4ce001ab 1669
a084e6ee
AD		 1670 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1671 &frev, &crev, &data_offset))
1672 return false;
4ce001ab
DA		 1673
1674 switch (crev) {
1675 case 1:
1676 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1677 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1678 return false;
1679
5a9bcacc
AD		 1680 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1681 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1682 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1683 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1684 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1685
1686 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1687 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1688 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1689 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1690 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1691
1692 mode->flags = 0;
1693 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1694 if (misc & ATOM_VSYNC_POLARITY)
1695 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1696 if (misc & ATOM_HSYNC_POLARITY)
1697 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1698 if (misc & ATOM_COMPOSITESYNC)
1699 mode->flags |= DRM_MODE_FLAG_CSYNC;
1700 if (misc & ATOM_INTERLACE)
1701 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1702 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1703 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1704
1705 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1706
1707 if (index == 1) {
1708 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1709 mode->crtc_htotal -= 1;
1710 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1711 }
1712 break;
1713 case 2:
1714 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1715 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1716 return false;
1717
1718 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1719 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1720 le16_to_cpu(dtd_timings->usHBlanking_Time);
1721 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1722 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1723 le16_to_cpu(dtd_timings->usHSyncOffset);
1724 mode->crtc_hsync_end = mode->crtc_hsync_start +
1725 le16_to_cpu(dtd_timings->usHSyncWidth);
1726
1727 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1728 le16_to_cpu(dtd_timings->usVBlanking_Time);
1729 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1730 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1731 le16_to_cpu(dtd_timings->usVSyncOffset);
1732 mode->crtc_vsync_end = mode->crtc_vsync_start +
1733 le16_to_cpu(dtd_timings->usVSyncWidth);
1734
1735 mode->flags = 0;
1736 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1737 if (misc & ATOM_VSYNC_POLARITY)
1738 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1739 if (misc & ATOM_HSYNC_POLARITY)
1740 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1741 if (misc & ATOM_COMPOSITESYNC)
1742 mode->flags |= DRM_MODE_FLAG_CSYNC;
1743 if (misc & ATOM_INTERLACE)
1744 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1745 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1746 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1747
1748 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1749 break;
1750 }
1751 return true;
1752}
1753
d79766fa
AD		 1754enum radeon_tv_std
1755radeon_atombios_get_tv_info(struct radeon_device *rdev)
1756{
1757 struct radeon_mode_info *mode_info = &rdev->mode_info;
1758 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1759 uint16_t data_offset;
1760 uint8_t frev, crev;
1761 struct _ATOM_ANALOG_TV_INFO *tv_info;
1762 enum radeon_tv_std tv_std = TV_STD_NTSC;
1763
a084e6ee
AD		 1764 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1765 &frev, &crev, &data_offset)) {
d79766fa 1766
a084e6ee
AD		 1767 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1768 (mode_info->atom_context->bios + data_offset);
d79766fa 1769
a084e6ee
AD		 1770 switch (tv_info->ucTV_BootUpDefaultStandard) {
1771 case ATOM_TV_NTSC:
1772 tv_std = TV_STD_NTSC;
40f76d81 1773 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1774 break;
1775 case ATOM_TV_NTSCJ:
1776 tv_std = TV_STD_NTSC_J;
40f76d81 1777 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1778 break;
1779 case ATOM_TV_PAL:
1780 tv_std = TV_STD_PAL;
40f76d81 1781 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1782 break;
1783 case ATOM_TV_PALM:
1784 tv_std = TV_STD_PAL_M;
40f76d81 1785 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1786 break;
1787 case ATOM_TV_PALN:
1788 tv_std = TV_STD_PAL_N;
40f76d81 1789 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1790 break;
1791 case ATOM_TV_PALCN:
1792 tv_std = TV_STD_PAL_CN;
40f76d81 1793 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1794 break;
1795 case ATOM_TV_PAL60:
1796 tv_std = TV_STD_PAL_60;
40f76d81 1797 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1798 break;
1799 case ATOM_TV_SECAM:
1800 tv_std = TV_STD_SECAM;
40f76d81 1801 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1802 break;
1803 default:
1804 tv_std = TV_STD_NTSC;
40f76d81 1805 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1806 break;
1807 }
d79766fa
AD		 1808 }
1809 return tv_std;
1810}
1811
6fe7ac3f
AD		 1812struct radeon_encoder_tv_dac *
1813radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1814{
1815 struct drm_device *dev = encoder->base.dev;
1816 struct radeon_device *rdev = dev->dev_private;
1817 struct radeon_mode_info *mode_info = &rdev->mode_info;
1818 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1819 uint16_t data_offset;
1820 struct _COMPASSIONATE_DATA *dac_info;
1821 uint8_t frev, crev;
1822 uint8_t bg, dac;
6fe7ac3f
AD		 1823 struct radeon_encoder_tv_dac *tv_dac = NULL;
1824
a084e6ee
AD		 1825 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1826 &frev, &crev, &data_offset)) {
6fe7ac3f 1827
a084e6ee
AD		 1828 dac_info = (struct _COMPASSIONATE_DATA *)
1829 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1830
6fe7ac3f
AD		 1831 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1832
1833 if (!tv_dac)
1834 return NULL;
1835
1836 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1837 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1838 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1839
1840 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1841 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1842 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1843
1844 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1845 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1846 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1847
d79766fa 1848 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1849 }
1850 return tv_dac;
1851}
1852
29fb52ca
AD		 1853static const char *thermal_controller_names[] = {
1854 "NONE",
678e7dfa
AD		 1855 "lm63",
1856 "adm1032",
1857 "adm1030",
1858 "max6649",
1859 "lm64",
1860 "f75375",
1861 "asc7xxx",
29fb52ca
AD		 1862};
1863
1864static const char *pp_lib_thermal_controller_names[] = {
1865 "NONE",
678e7dfa
AD		 1866 "lm63",
1867 "adm1032",
1868 "adm1030",
1869 "max6649",
1870 "lm64",
1871 "f75375",
29fb52ca
AD		 1872 "RV6xx",
1873 "RV770",
678e7dfa 1874 "adt7473",
560154e9 1875 "NONE",
49f65982
AD		 1876 "External GPIO",
1877 "Evergreen",
b0e66414
AD		 1878 "emc2103",
1879 "Sumo",
4fddba1f 1880 "Northern Islands",
29fb52ca
AD		 1881};
1882
56278a8e
AD		 1883union power_info {
1884 struct _ATOM_POWERPLAY_INFO info;
1885 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1886 struct _ATOM_POWERPLAY_INFO_V3 info_3;
560154e9 1887 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
b0e66414
AD		 1888 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1889 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
56278a8e
AD		 1890};
1891
560154e9
AD		 1892union pplib_clock_info {
1893 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1894 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1895 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
b0e66414 1896 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
560154e9
AD		 1897};
1898
1899union pplib_power_state {
1900 struct _ATOM_PPLIB_STATE v1;
1901 struct _ATOM_PPLIB_STATE_V2 v2;
1902};
1903
1904static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1905 int state_index,
1906 u32 misc, u32 misc2)
1907{
1908 rdev->pm.power_state[state_index].misc = misc;
1909 rdev->pm.power_state[state_index].misc2 = misc2;
1910 /* order matters! */
1911 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1912 rdev->pm.power_state[state_index].type =
1913 POWER_STATE_TYPE_POWERSAVE;
1914 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1915 rdev->pm.power_state[state_index].type =
1916 POWER_STATE_TYPE_BATTERY;
1917 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1918 rdev->pm.power_state[state_index].type =
1919 POWER_STATE_TYPE_BATTERY;
1920 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1921 rdev->pm.power_state[state_index].type =
1922 POWER_STATE_TYPE_BALANCED;
1923 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1924 rdev->pm.power_state[state_index].type =
1925 POWER_STATE_TYPE_PERFORMANCE;
1926 rdev->pm.power_state[state_index].flags &=
1927 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1928 }
1929 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1930 rdev->pm.power_state[state_index].type =
1931 POWER_STATE_TYPE_BALANCED;
1932 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1933 rdev->pm.power_state[state_index].type =
1934 POWER_STATE_TYPE_DEFAULT;
1935 rdev->pm.default_power_state_index = state_index;
1936 rdev->pm.power_state[state_index].default_clock_mode =
1937 &rdev->pm.power_state[state_index].clock_info[0];
1938 } else if (state_index == 0) {
1939 rdev->pm.power_state[state_index].clock_info[0].flags |=
1940 RADEON_PM_MODE_NO_DISPLAY;
1941 }
1942}
1943
1944static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
771fe6b9 1945{
56278a8e 1946 struct radeon_mode_info *mode_info = &rdev->mode_info;
560154e9
AD		 1947 u32 misc, misc2 = 0;
1948 int num_modes = 0, i;
1949 int state_index = 0;
1950 struct radeon_i2c_bus_rec i2c_bus;
1951 union power_info *power_info;
56278a8e 1952 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
560154e9 1953 u16 data_offset;
56278a8e 1954 u8 frev, crev;
771fe6b9 1955
560154e9
AD		 1956 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1957 &frev, &crev, &data_offset))
1958 return state_index;
1959 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1960
1961 /* add the i2c bus for thermal/fan chip */
1962 if (power_info->info.ucOverdriveThermalController > 0) {
1963 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1964 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1965 power_info->info.ucOverdriveControllerAddress >> 1);
1966 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1967 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1968 if (rdev->pm.i2c_bus) {
1969 struct i2c_board_info info = { };
1970 const char *name = thermal_controller_names[power_info->info.
1971 ucOverdriveThermalController];
1972 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1973 strlcpy(info.type, name, sizeof(info.type));
1974 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1975 }
1976 }
1977 num_modes = power_info->info.ucNumOfPowerModeEntries;
1978 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1979 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1980 /* last mode is usually default, array is low to high */
1981 for (i = 0; i < num_modes; i++) {
1982 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1983 switch (frev) {
1984 case 1:
1985 rdev->pm.power_state[state_index].num_clock_modes = 1;
1986 rdev->pm.power_state[state_index].clock_info[0].mclk =
1987 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1988 rdev->pm.power_state[state_index].clock_info[0].sclk =
1989 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1990 /* skip invalid modes */
1991 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1992 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1993 continue;
1994 rdev->pm.power_state[state_index].pcie_lanes =
1995 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1996 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1997 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1998 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2000 VOLTAGE_GPIO;
2001 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2002 radeon_lookup_gpio(rdev,
2003 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2004 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2005 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2006 true;
2007 else
2008 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2009 false;
2010 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2011 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2012 VOLTAGE_VDDC;
2013 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2014 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
29fb52ca 2015 }
560154e9
AD		 2016 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2017 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2018 state_index++;
2019 break;
2020 case 2:
2021 rdev->pm.power_state[state_index].num_clock_modes = 1;
2022 rdev->pm.power_state[state_index].clock_info[0].mclk =
2023 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2024 rdev->pm.power_state[state_index].clock_info[0].sclk =
2025 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2026 /* skip invalid modes */
2027 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2028 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2029 continue;
2030 rdev->pm.power_state[state_index].pcie_lanes =
2031 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2032 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2033 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2034 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2035 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2036 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2037 VOLTAGE_GPIO;
2038 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2039 radeon_lookup_gpio(rdev,
2040 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2041 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2042 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2043 true;
2044 else
2045 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2046 false;
2047 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2048 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2049 VOLTAGE_VDDC;
2050 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2051 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
56278a8e 2052 }
560154e9
AD		 2053 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2054 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2055 state_index++;
2056 break;
2057 case 3:
2058 rdev->pm.power_state[state_index].num_clock_modes = 1;
2059 rdev->pm.power_state[state_index].clock_info[0].mclk =
2060 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2061 rdev->pm.power_state[state_index].clock_info[0].sclk =
2062 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2063 /* skip invalid modes */
2064 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2065 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2066 continue;
2067 rdev->pm.power_state[state_index].pcie_lanes =
2068 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2069 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2070 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2071 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2072 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2073 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2074 VOLTAGE_GPIO;
2075 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2076 radeon_lookup_gpio(rdev,
2077 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2078 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2080 true;
2081 else
2082 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2083 false;
2084 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2085 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2086 VOLTAGE_VDDC;
2087 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2088 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2089 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2091 true;
2092 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2093 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2094 }
02b17cc0 2095 }
560154e9
AD		 2096 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2097 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2098 state_index++;
2099 break;
2100 }
2101 }
2102 /* last mode is usually default */
2103 if (rdev->pm.default_power_state_index == -1) {
2104 rdev->pm.power_state[state_index - 1].type =
2105 POWER_STATE_TYPE_DEFAULT;
2106 rdev->pm.default_power_state_index = state_index - 1;
2107 rdev->pm.power_state[state_index - 1].default_clock_mode =
2108 &rdev->pm.power_state[state_index - 1].clock_info[0];
2109 rdev->pm.power_state[state_index].flags &=
2110 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2111 rdev->pm.power_state[state_index].misc = 0;
2112 rdev->pm.power_state[state_index].misc2 = 0;
2113 }
2114 return state_index;
2115}
2116
2117static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2118 ATOM_PPLIB_THERMALCONTROLLER *controller)
2119{
2120 struct radeon_i2c_bus_rec i2c_bus;
2121
2122 /* add the i2c bus for thermal/fan chip */
2123 if (controller->ucType > 0) {
2124 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2125 DRM_INFO("Internal thermal controller %s fan control\n",
2126 (controller->ucFanParameters &
2127 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2128 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2129 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2130 DRM_INFO("Internal thermal controller %s fan control\n",
2131 (controller->ucFanParameters &
2132 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2133 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2134 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2135 DRM_INFO("Internal thermal controller %s fan control\n",
2136 (controller->ucFanParameters &
2137 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2138 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
b0e66414
AD		 2139 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2140 DRM_INFO("Internal thermal controller %s fan control\n",
2141 (controller->ucFanParameters &
2142 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2143 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
4fddba1f
AD		 2144 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2145 DRM_INFO("Internal thermal controller %s fan control\n",
2146 (controller->ucFanParameters &
2147 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2148 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
560154e9
AD		 2149 } else if ((controller->ucType ==
2150 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2151 (controller->ucType ==
b0e66414
AD		 2152 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2153 (controller->ucType ==
2154 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
560154e9 2155 DRM_INFO("Special thermal controller config\n");
49f65982 2156 } else {
560154e9
AD		 2157 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2158 pp_lib_thermal_controller_names[controller->ucType],
2159 controller->ucI2cAddress >> 1,
2160 (controller->ucFanParameters &
2161 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2162 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2163 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2164 if (rdev->pm.i2c_bus) {
2165 struct i2c_board_info info = { };
2166 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2167 info.addr = controller->ucI2cAddress >> 1;
2168 strlcpy(info.type, name, sizeof(info.type));
2169 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
c5e8ce61 2170 }
560154e9
AD		 2171 }
2172 }
2173}
c5e8ce61 2174
560154e9
AD		 2175static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2176{
2177 struct radeon_mode_info *mode_info = &rdev->mode_info;
2178 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2179 u8 frev, crev;
2180 u16 data_offset;
2181 union firmware_info *firmware_info;
2182 u16 vddc = 0;
678e7dfa 2183
560154e9
AD		 2184 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2185 &frev, &crev, &data_offset)) {
2186 firmware_info =
2187 (union firmware_info *)(mode_info->atom_context->bios +
2188 data_offset);
2189 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2190 }
2191
2192 return vddc;
2193}
2194
2195static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2196 int state_index, int mode_index,
2197 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2198{
2199 int j;
2200 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2201 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2202 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2203
2204 rdev->pm.power_state[state_index].misc = misc;
2205 rdev->pm.power_state[state_index].misc2 = misc2;
2206 rdev->pm.power_state[state_index].pcie_lanes =
2207 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2208 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2209 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2210 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2211 rdev->pm.power_state[state_index].type =
2212 POWER_STATE_TYPE_BATTERY;
2213 break;
2214 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2215 rdev->pm.power_state[state_index].type =
2216 POWER_STATE_TYPE_BALANCED;
2217 break;
2218 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2219 rdev->pm.power_state[state_index].type =
2220 POWER_STATE_TYPE_PERFORMANCE;
2221 break;
2222 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2223 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2224 rdev->pm.power_state[state_index].type =
2225 POWER_STATE_TYPE_PERFORMANCE;
2226 break;
2227 }
2228 rdev->pm.power_state[state_index].flags = 0;
2229 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2230 rdev->pm.power_state[state_index].flags |=
2231 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2232 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_DEFAULT;
2235 rdev->pm.default_power_state_index = state_index;
2236 rdev->pm.power_state[state_index].default_clock_mode =
2237 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
9ace9f7b
AD		 2238 if (ASIC_IS_DCE5(rdev)) {
2239 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2240 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2241 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2242 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2243 } else {
2244 /* patch the table values with the default slck/mclk from firmware info */
2245 for (j = 0; j < mode_index; j++) {
2246 rdev->pm.power_state[state_index].clock_info[j].mclk =
2247 rdev->clock.default_mclk;
2248 rdev->pm.power_state[state_index].clock_info[j].sclk =
2249 rdev->clock.default_sclk;
2250 if (vddc)
2251 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2252 vddc;
2253 }
560154e9
AD		 2254 }
2255 }
2256}
2257
2258static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2259 int state_index, int mode_index,
2260 union pplib_clock_info *clock_info)
2261{
2262 u32 sclk, mclk;
2263
2264 if (rdev->flags & RADEON_IS_IGP) {
b0e66414
AD		 2265 if (rdev->family >= CHIP_PALM) {
2266 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2267 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2268 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2269 } else {
2270 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2271 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2272 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2273 }
560154e9
AD		 2274 } else if (ASIC_IS_DCE4(rdev)) {
2275 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2276 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2277 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2278 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2279 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2280 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2281 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2282 VOLTAGE_SW;
2283 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2284 clock_info->evergreen.usVDDC;
2285 } else {
2286 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2287 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2288 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2289 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2290 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2291 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2292 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2293 VOLTAGE_SW;
2294 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2295 clock_info->r600.usVDDC;
2296 }
2297
2298 if (rdev->flags & RADEON_IS_IGP) {
2299 /* skip invalid modes */
2300 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2301 return false;
2302 } else {
2303 /* skip invalid modes */
2304 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2305 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2306 return false;
2307 }
2308 return true;
2309}
2310
2311static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2312{
2313 struct radeon_mode_info *mode_info = &rdev->mode_info;
2314 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2315 union pplib_power_state *power_state;
2316 int i, j;
2317 int state_index = 0, mode_index = 0;
2318 union pplib_clock_info *clock_info;
2319 bool valid;
2320 union power_info *power_info;
2321 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2322 u16 data_offset;
2323 u8 frev, crev;
2324
2325 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2326 &frev, &crev, &data_offset))
2327 return state_index;
2328 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2329
2330 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2331 /* first mode is usually default, followed by low to high */
2332 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2333 mode_index = 0;
2334 power_state = (union pplib_power_state *)
2335 (mode_info->atom_context->bios + data_offset +
2336 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2337 i * power_info->pplib.ucStateEntrySize);
2338 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2339 (mode_info->atom_context->bios + data_offset +
2340 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2341 (power_state->v1.ucNonClockStateIndex *
2342 power_info->pplib.ucNonClockSize));
2343 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2344 clock_info = (union pplib_clock_info *)
2345 (mode_info->atom_context->bios + data_offset +
2346 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2347 (power_state->v1.ucClockStateIndices[j] *
2348 power_info->pplib.ucClockInfoSize));
2349 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2350 state_index, mode_index,
2351 clock_info);
2352 if (valid)
2353 mode_index++;
2354 }
2355 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2356 if (mode_index) {
2357 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2358 non_clock_info);
2359 state_index++;
2360 }
2361 }
2362 /* if multiple clock modes, mark the lowest as no display */
2363 for (i = 0; i < state_index; i++) {
2364 if (rdev->pm.power_state[i].num_clock_modes > 1)
2365 rdev->pm.power_state[i].clock_info[0].flags |=
2366 RADEON_PM_MODE_NO_DISPLAY;
2367 }
2368 /* first mode is usually default */
2369 if (rdev->pm.default_power_state_index == -1) {
2370 rdev->pm.power_state[0].type =
2371 POWER_STATE_TYPE_DEFAULT;
2372 rdev->pm.default_power_state_index = 0;
2373 rdev->pm.power_state[0].default_clock_mode =
2374 &rdev->pm.power_state[0].clock_info[0];
2375 }
2376 return state_index;
2377}
2378
b0e66414
AD		 2379static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2380{
2381 struct radeon_mode_info *mode_info = &rdev->mode_info;
2382 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2383 union pplib_power_state *power_state;
2384 int i, j, non_clock_array_index, clock_array_index;
2385 int state_index = 0, mode_index = 0;
2386 union pplib_clock_info *clock_info;
2387 struct StateArray *state_array;
2388 struct ClockInfoArray *clock_info_array;
2389 struct NonClockInfoArray *non_clock_info_array;
2390 bool valid;
2391 union power_info *power_info;
2392 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2393 u16 data_offset;
2394 u8 frev, crev;
2395
2396 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2397 &frev, &crev, &data_offset))
2398 return state_index;
2399 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2400
2401 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2402 state_array = (struct StateArray *)
2403 (mode_info->atom_context->bios + data_offset +
2404 power_info->pplib.usStateArrayOffset);
2405 clock_info_array = (struct ClockInfoArray *)
2406 (mode_info->atom_context->bios + data_offset +
2407 power_info->pplib.usClockInfoArrayOffset);
2408 non_clock_info_array = (struct NonClockInfoArray *)
2409 (mode_info->atom_context->bios + data_offset +
2410 power_info->pplib.usNonClockInfoArrayOffset);
2411 for (i = 0; i < state_array->ucNumEntries; i++) {
2412 mode_index = 0;
2413 power_state = (union pplib_power_state *)&state_array->states[i];
2414 /* XXX this might be an inagua bug... */
2415 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2416 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2417 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2418 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2419 clock_array_index = power_state->v2.clockInfoIndex[j];
2420 /* XXX this might be an inagua bug... */
2421 if (clock_array_index >= clock_info_array->ucNumEntries)
2422 continue;
2423 clock_info = (union pplib_clock_info *)
2424 &clock_info_array->clockInfo[clock_array_index];
2425 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2426 state_index, mode_index,
2427 clock_info);
2428 if (valid)
2429 mode_index++;
2430 }
2431 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2432 if (mode_index) {
2433 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2434 non_clock_info);
2435 state_index++;
2436 }
2437 }
2438 /* if multiple clock modes, mark the lowest as no display */
2439 for (i = 0; i < state_index; i++) {
2440 if (rdev->pm.power_state[i].num_clock_modes > 1)
2441 rdev->pm.power_state[i].clock_info[0].flags |=
2442 RADEON_PM_MODE_NO_DISPLAY;
2443 }
2444 /* first mode is usually default */
2445 if (rdev->pm.default_power_state_index == -1) {
2446 rdev->pm.power_state[0].type =
2447 POWER_STATE_TYPE_DEFAULT;
2448 rdev->pm.default_power_state_index = 0;
2449 rdev->pm.power_state[0].default_clock_mode =
2450 &rdev->pm.power_state[0].clock_info[0];
2451 }
2452 return state_index;
2453}
2454
560154e9
AD		 2455void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2456{
2457 struct radeon_mode_info *mode_info = &rdev->mode_info;
2458 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2459 u16 data_offset;
2460 u8 frev, crev;
2461 int state_index = 0;
2462
2463 rdev->pm.default_power_state_index = -1;
2464
2465 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2466 &frev, &crev, &data_offset)) {
2467 switch (frev) {
2468 case 1:
2469 case 2:
2470 case 3:
2471 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2472 break;
2473 case 4:
2474 case 5:
2475 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2476 break;
b0e66414
AD		 2477 case 6:
2478 state_index = radeon_atombios_parse_power_table_6(rdev);
2479 break;
560154e9
AD		 2480 default:
2481 break;
56278a8e
AD		 2482 }
2483 } else {
56278a8e 2484 /* add the default mode */
0ec0e74f
AD		 2485 rdev->pm.power_state[state_index].type =
2486 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2487 rdev->pm.power_state[state_index].num_clock_modes = 1;
2488 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2489 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2490 rdev->pm.power_state[state_index].default_clock_mode =
2491 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2492 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2493 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2494 rdev->pm.default_power_state_index = state_index;
2495 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2496 state_index++;
2497 }
02b17cc0 2498
56278a8e 2499 rdev->pm.num_power_states = state_index;
9038dfdf 2500
a48b9b4e
AD		 2501 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2502 rdev->pm.current_clock_mode_index = 0;
4d60173f 2503 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2504}
2505
771fe6b9 2506void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2507{
771fe6b9
JG		 2508 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2509 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2510
2511 args.ucEnable = enable;
2512
2513 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2514}
2515
7433874e
RM		 2516uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2517{
2518 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2519 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2520
2521 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2522 return args.ulReturnEngineClock;
2523}
2524
2525uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2526{
2527 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2528 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2529
2530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2531 return args.ulReturnMemoryClock;
2532}
2533
771fe6b9
JG		 2534void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2535 uint32_t eng_clock)
2536{
2537 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2538 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2539
2540 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2541
2542 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2543}
2544
2545void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2546 uint32_t mem_clock)
2547{
2548 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2549 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2550
2551 if (rdev->flags & RADEON_IS_IGP)
2552 return;
2553
2554 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2555
2556 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2557}
2558
7ac9aa5a
AD		 2559union set_voltage {
2560 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2561 struct _SET_VOLTAGE_PARAMETERS v1;
2562 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2563};
2564
2565void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2566{
2567 union set_voltage args;
2568 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2569 u8 frev, crev, volt_index = level;
2570
2571 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2572 return;
2573
2574 switch (crev) {
2575 case 1:
2576 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2577 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2578 args.v1.ucVoltageIndex = volt_index;
2579 break;
2580 case 2:
2581 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2582 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2583 args.v2.usVoltageLevel = cpu_to_le16(level);
2584 break;
2585 default:
2586 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2587 return;
2588 }
2589
2590 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2591}
2592
2593
2594
771fe6b9
JG		 2595void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2596{
2597 struct radeon_device *rdev = dev->dev_private;
2598 uint32_t bios_2_scratch, bios_6_scratch;
2599
2600 if (rdev->family >= CHIP_R600) {
4ce001ab 2601 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2602 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2603 } else {
4ce001ab 2604 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2605 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2606 }
2607
2608 /* let the bios control the backlight */
2609 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2610
2611 /* tell the bios not to handle mode switching */
87364760 2612 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
771fe6b9
JG		 2613
2614 if (rdev->family >= CHIP_R600) {
2615 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2616 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2617 } else {
2618 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2619 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2620 }
2621
2622}
2623
f657c2a7
YZ		 2624void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2625{
2626 uint32_t scratch_reg;
2627 int i;
2628
2629 if (rdev->family >= CHIP_R600)
2630 scratch_reg = R600_BIOS_0_SCRATCH;
2631 else
2632 scratch_reg = RADEON_BIOS_0_SCRATCH;
2633
2634 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2635 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2636}
2637
2638void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2639{
2640 uint32_t scratch_reg;
2641 int i;
2642
2643 if (rdev->family >= CHIP_R600)
2644 scratch_reg = R600_BIOS_0_SCRATCH;
2645 else
2646 scratch_reg = RADEON_BIOS_0_SCRATCH;
2647
2648 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2649 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2650}
2651
771fe6b9
JG		 2652void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2653{
2654 struct drm_device *dev = encoder->dev;
2655 struct radeon_device *rdev = dev->dev_private;
2656 uint32_t bios_6_scratch;
2657
2658 if (rdev->family >= CHIP_R600)
2659 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2660 else
2661 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2662
87364760 2663 if (lock) {
771fe6b9 2664 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
87364760
AD		 2665 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2666 } else {
771fe6b9 2667 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
87364760
AD		 2668 bios_6_scratch |= ATOM_S6_ACC_MODE;
2669 }
771fe6b9
JG		 2670
2671 if (rdev->family >= CHIP_R600)
2672 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2673 else
2674 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2675}
2676
2677/* at some point we may want to break this out into individual functions */
2678void
2679radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2680 struct drm_encoder *encoder,
2681 bool connected)
2682{
2683 struct drm_device *dev = connector->dev;
2684 struct radeon_device *rdev = dev->dev_private;
2685 struct radeon_connector *radeon_connector =
2686 to_radeon_connector(connector);
2687 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2688 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2689
2690 if (rdev->family >= CHIP_R600) {
2691 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2692 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2693 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2694 } else {
2695 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2696 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2697 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2698 }
2699
2700 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2701 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2702 if (connected) {
d9fdaafb 2703 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2704 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2705 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2706 } else {
d9fdaafb 2707 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2708 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2709 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2710 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2711 }
2712 }
2713 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2714 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2715 if (connected) {
d9fdaafb 2716 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2717 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2718 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2719 } else {
d9fdaafb 2720 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2721 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2722 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2723 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2724 }
2725 }
2726 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2727 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2728 if (connected) {
d9fdaafb 2729 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2730 bios_0_scratch |= ATOM_S0_LCD1;
2731 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2732 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2733 } else {
d9fdaafb 2734 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2735 bios_0_scratch &= ~ATOM_S0_LCD1;
2736 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2737 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2738 }
2739 }
2740 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2741 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2742 if (connected) {
d9fdaafb 2743 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2744 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2745 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2746 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2747 } else {
d9fdaafb 2748 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2749 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2750 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2751 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2752 }
2753 }
2754 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2755 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2756 if (connected) {
d9fdaafb 2757 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2758 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2759 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2760 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2761 } else {
d9fdaafb 2762 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2763 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2764 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2765 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2766 }
2767 }
2768 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2769 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2770 if (connected) {
d9fdaafb 2771 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2772 bios_0_scratch |= ATOM_S0_DFP1;
2773 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2774 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2775 } else {
d9fdaafb 2776 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2777 bios_0_scratch &= ~ATOM_S0_DFP1;
2778 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2779 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2780 }
2781 }
2782 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2783 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2784 if (connected) {
d9fdaafb 2785 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2786 bios_0_scratch |= ATOM_S0_DFP2;
2787 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2788 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2789 } else {
d9fdaafb 2790 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2791 bios_0_scratch &= ~ATOM_S0_DFP2;
2792 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2793 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2794 }
2795 }
2796 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2797 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2798 if (connected) {
d9fdaafb 2799 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2800 bios_0_scratch |= ATOM_S0_DFP3;
2801 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2802 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2803 } else {
d9fdaafb 2804 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2805 bios_0_scratch &= ~ATOM_S0_DFP3;
2806 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2807 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2808 }
2809 }
2810 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2811 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2812 if (connected) {
d9fdaafb 2813 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2814 bios_0_scratch |= ATOM_S0_DFP4;
2815 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2816 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2817 } else {
d9fdaafb 2818 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2819 bios_0_scratch &= ~ATOM_S0_DFP4;
2820 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2821 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2822 }
2823 }
2824 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2825 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2826 if (connected) {
d9fdaafb 2827 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2828 bios_0_scratch |= ATOM_S0_DFP5;
2829 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2830 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2831 } else {
d9fdaafb 2832 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2833 bios_0_scratch &= ~ATOM_S0_DFP5;
2834 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2835 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2836 }
2837 }
2838
2839 if (rdev->family >= CHIP_R600) {
2840 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2841 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2842 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2843 } else {
2844 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2845 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2846 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2847 }
2848}
2849
2850void
2851radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2852{
2853 struct drm_device *dev = encoder->dev;
2854 struct radeon_device *rdev = dev->dev_private;
2855 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2856 uint32_t bios_3_scratch;
2857
2858 if (rdev->family >= CHIP_R600)
2859 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2860 else
2861 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2862
2863 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2864 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2865 bios_3_scratch |= (crtc << 18);
2866 }
2867 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2868 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2869 bios_3_scratch |= (crtc << 24);
2870 }
2871 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2872 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2873 bios_3_scratch |= (crtc << 16);
2874 }
2875 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2876 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2877 bios_3_scratch |= (crtc << 20);
2878 }
2879 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2880 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2881 bios_3_scratch |= (crtc << 17);
2882 }
2883 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2884 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2885 bios_3_scratch |= (crtc << 19);
2886 }
2887 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2888 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2889 bios_3_scratch |= (crtc << 23);
2890 }
2891 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2892 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2893 bios_3_scratch |= (crtc << 25);
2894 }
2895
2896 if (rdev->family >= CHIP_R600)
2897 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2898 else
2899 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2900}
2901
2902void
2903radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2904{
2905 struct drm_device *dev = encoder->dev;
2906 struct radeon_device *rdev = dev->dev_private;
2907 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2908 uint32_t bios_2_scratch;
2909
2910 if (rdev->family >= CHIP_R600)
2911 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2912 else
2913 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2914
2915 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2916 if (on)
2917 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2918 else
2919 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2920 }
2921 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2922 if (on)
2923 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2924 else
2925 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2926 }
2927 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2928 if (on)
2929 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2930 else
2931 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2932 }
2933 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2934 if (on)
2935 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2936 else
2937 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2938 }
2939 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2940 if (on)
2941 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2942 else
2943 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2944 }
2945 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2946 if (on)
2947 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2948 else
2949 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2950 }
2951 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2952 if (on)
2953 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2954 else
2955 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2956 }
2957 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2958 if (on)
2959 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2960 else
2961 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2962 }
2963 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2964 if (on)
2965 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2966 else
2967 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2968 }
2969 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2970 if (on)
2971 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2972 else
2973 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2974 }
2975
2976 if (rdev->family >= CHIP_R600)
2977 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2978 else
2979 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2980}
Linux kernel - Deliverables
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