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ttm: Fix caching mode selection.
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51/* from radeon_legacy_encoder.c */
52extern void
53radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60};
61
62static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64{
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101}
102
103static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
106 struct radeon_i2c_bus_rec *i2c_bus)
107{
108
109 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
110 if ((dev->pdev->device == 0x791e) &&
111 (dev->pdev->subsystem_vendor == 0x1043) &&
112 (dev->pdev->subsystem_device == 0x826d)) {
113 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
114 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
115 *connector_type = DRM_MODE_CONNECTOR_DVID;
116 }
117
118 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
119 if ((dev->pdev->device == 0x7941) &&
120 (dev->pdev->subsystem_vendor == 0x147b) &&
121 (dev->pdev->subsystem_device == 0x2412)) {
122 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
123 return false;
124 }
125
126 /* Falcon NW laptop lists vga ddc line for LVDS */
127 if ((dev->pdev->device == 0x5653) &&
128 (dev->pdev->subsystem_vendor == 0x1462) &&
129 (dev->pdev->subsystem_device == 0x0291)) {
130 if (*connector_type == DRM_MODE_CONNECTOR_LVDS)
131 i2c_bus->valid = false;
132 }
133
134 /* Funky macbooks */
135 if ((dev->pdev->device == 0x71C5) &&
136 (dev->pdev->subsystem_vendor == 0x106b) &&
137 (dev->pdev->subsystem_device == 0x0080)) {
138 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
139 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
140 return false;
141 }
142
143 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
144 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
145 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
146 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
147 return false;
148 }
149 }
150
151 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
152 if ((dev->pdev->device == 0x9598) &&
153 (dev->pdev->subsystem_vendor == 0x1043) &&
154 (dev->pdev->subsystem_device == 0x01da)) {
155 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
156 *connector_type = DRM_MODE_CONNECTOR_DVID;
157 }
158 }
159
160 return true;
161}
162
163const int supported_devices_connector_convert[] = {
164 DRM_MODE_CONNECTOR_Unknown,
165 DRM_MODE_CONNECTOR_VGA,
166 DRM_MODE_CONNECTOR_DVII,
167 DRM_MODE_CONNECTOR_DVID,
168 DRM_MODE_CONNECTOR_DVIA,
169 DRM_MODE_CONNECTOR_SVIDEO,
170 DRM_MODE_CONNECTOR_Composite,
171 DRM_MODE_CONNECTOR_LVDS,
172 DRM_MODE_CONNECTOR_Unknown,
173 DRM_MODE_CONNECTOR_Unknown,
174 DRM_MODE_CONNECTOR_HDMIA,
175 DRM_MODE_CONNECTOR_HDMIB,
176 DRM_MODE_CONNECTOR_Unknown,
177 DRM_MODE_CONNECTOR_Unknown,
178 DRM_MODE_CONNECTOR_9PinDIN,
179 DRM_MODE_CONNECTOR_DisplayPort
180};
181
182const int object_connector_convert[] = {
183 DRM_MODE_CONNECTOR_Unknown,
184 DRM_MODE_CONNECTOR_DVII,
185 DRM_MODE_CONNECTOR_DVII,
186 DRM_MODE_CONNECTOR_DVID,
187 DRM_MODE_CONNECTOR_DVID,
188 DRM_MODE_CONNECTOR_VGA,
189 DRM_MODE_CONNECTOR_Composite,
190 DRM_MODE_CONNECTOR_SVIDEO,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_9PinDIN,
193 DRM_MODE_CONNECTOR_Unknown,
194 DRM_MODE_CONNECTOR_HDMIA,
195 DRM_MODE_CONNECTOR_HDMIB,
196 DRM_MODE_CONNECTOR_HDMIB,
197 DRM_MODE_CONNECTOR_LVDS,
198 DRM_MODE_CONNECTOR_9PinDIN,
199 DRM_MODE_CONNECTOR_Unknown,
200 DRM_MODE_CONNECTOR_Unknown,
201 DRM_MODE_CONNECTOR_Unknown,
202 DRM_MODE_CONNECTOR_DisplayPort
203};
204
205bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
206{
207 struct radeon_device *rdev = dev->dev_private;
208 struct radeon_mode_info *mode_info = &rdev->mode_info;
209 struct atom_context *ctx = mode_info->atom_context;
210 int index = GetIndexIntoMasterTable(DATA, Object_Header);
211 uint16_t size, data_offset;
212 uint8_t frev, crev, line_mux = 0;
213 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
214 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
215 ATOM_OBJECT_HEADER *obj_header;
216 int i, j, path_size, device_support;
217 int connector_type;
218 uint16_t igp_lane_info;
219 bool linkb;
220 struct radeon_i2c_bus_rec ddc_bus;
221
222 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
223
224 if (data_offset == 0)
225 return false;
226
227 if (crev < 2)
228 return false;
229
230 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
231 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
232 (ctx->bios + data_offset +
233 le16_to_cpu(obj_header->usDisplayPathTableOffset));
234 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
235 (ctx->bios + data_offset +
236 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
237 device_support = le16_to_cpu(obj_header->usDeviceSupport);
238
239 path_size = 0;
240 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
241 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
242 ATOM_DISPLAY_OBJECT_PATH *path;
243 addr += path_size;
244 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
245 path_size += le16_to_cpu(path->usSize);
246 linkb = false;
247
248 if (device_support & le16_to_cpu(path->usDeviceTag)) {
249 uint8_t con_obj_id, con_obj_num, con_obj_type;
250
251 con_obj_id =
252 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
253 >> OBJECT_ID_SHIFT;
254 con_obj_num =
255 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
256 >> ENUM_ID_SHIFT;
257 con_obj_type =
258 (le16_to_cpu(path->usConnObjectId) &
259 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
260
261 if ((le16_to_cpu(path->usDeviceTag) ==
262 ATOM_DEVICE_TV1_SUPPORT)
263 || (le16_to_cpu(path->usDeviceTag) ==
264 ATOM_DEVICE_TV2_SUPPORT)
265 || (le16_to_cpu(path->usDeviceTag) ==
266 ATOM_DEVICE_CV_SUPPORT))
267 continue;
268
269 if ((rdev->family == CHIP_RS780) &&
270 (con_obj_id ==
271 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
272 uint16_t igp_offset = 0;
273 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
274
275 index =
276 GetIndexIntoMasterTable(DATA,
277 IntegratedSystemInfo);
278
279 atom_parse_data_header(ctx, index, &size, &frev,
280 &crev, &igp_offset);
281
282 if (crev >= 2) {
283 igp_obj =
284 (ATOM_INTEGRATED_SYSTEM_INFO_V2
285 *) (ctx->bios + igp_offset);
286
287 if (igp_obj) {
288 uint32_t slot_config, ct;
289
290 if (con_obj_num == 1)
291 slot_config =
292 igp_obj->
293 ulDDISlot1Config;
294 else
295 slot_config =
296 igp_obj->
297 ulDDISlot2Config;
298
299 ct = (slot_config >> 16) & 0xff;
300 connector_type =
301 object_connector_convert
302 [ct];
303 igp_lane_info =
304 slot_config & 0xffff;
305 } else
306 continue;
307 } else
308 continue;
309 } else {
310 igp_lane_info = 0;
311 connector_type =
312 object_connector_convert[con_obj_id];
313 }
314
315 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
316 continue;
317
318 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
319 j++) {
320 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
321
322 enc_obj_id =
323 (le16_to_cpu(path->usGraphicObjIds[j]) &
324 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
325 enc_obj_num =
326 (le16_to_cpu(path->usGraphicObjIds[j]) &
327 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
328 enc_obj_type =
329 (le16_to_cpu(path->usGraphicObjIds[j]) &
330 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
331
332 /* FIXME: add support for router objects */
333 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
334 if (enc_obj_num == 2)
335 linkb = true;
336 else
337 linkb = false;
338
339 radeon_add_atom_encoder(dev,
340 enc_obj_id,
341 le16_to_cpu
342 (path->
343 usDeviceTag));
344
345 }
346 }
347
348 /* look up gpio for ddc */
349 if ((le16_to_cpu(path->usDeviceTag) &
350 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
351 == 0) {
352 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
353 if (le16_to_cpu(path->usConnObjectId) ==
354 le16_to_cpu(con_obj->asObjects[j].
355 usObjectID)) {
356 ATOM_COMMON_RECORD_HEADER
357 *record =
358 (ATOM_COMMON_RECORD_HEADER
359 *)
360 (ctx->bios + data_offset +
361 le16_to_cpu(con_obj->
362 asObjects[j].
363 usRecordOffset));
364 ATOM_I2C_RECORD *i2c_record;
365
366 while (record->ucRecordType > 0
367 && record->
368 ucRecordType <=
369 ATOM_MAX_OBJECT_RECORD_NUMBER) {
370 DRM_ERROR
371 ("record type %d\n",
372 record->
373 ucRecordType);
374 switch (record->
375 ucRecordType) {
376 case ATOM_I2C_RECORD_TYPE:
377 i2c_record =
378 (ATOM_I2C_RECORD
379 *) record;
380 line_mux =
381 i2c_record->
382 sucI2cId.
383 bfI2C_LineMux;
384 break;
385 }
386 record =
387 (ATOM_COMMON_RECORD_HEADER
388 *) ((char *)record
389 +
390 record->
391 ucRecordSize);
392 }
393 break;
394 }
395 }
396 } else
397 line_mux = 0;
398
399 if ((le16_to_cpu(path->usDeviceTag) ==
400 ATOM_DEVICE_TV1_SUPPORT)
401 || (le16_to_cpu(path->usDeviceTag) ==
402 ATOM_DEVICE_TV2_SUPPORT)
403 || (le16_to_cpu(path->usDeviceTag) ==
404 ATOM_DEVICE_CV_SUPPORT))
405 ddc_bus.valid = false;
406 else
407 ddc_bus = radeon_lookup_gpio(dev, line_mux);
408
409 radeon_add_atom_connector(dev,
410 le16_to_cpu(path->
411 usConnObjectId),
412 le16_to_cpu(path->
413 usDeviceTag),
414 connector_type, &ddc_bus,
415 linkb, igp_lane_info);
416
417 }
418 }
419
420 radeon_link_encoder_connector(dev);
421
422 return true;
423}
424
425struct bios_connector {
426 bool valid;
427 uint8_t line_mux;
428 uint16_t devices;
429 int connector_type;
430 struct radeon_i2c_bus_rec ddc_bus;
431};
432
433bool radeon_get_atom_connector_info_from_supported_devices_table(struct
434 drm_device
435 *dev)
436{
437 struct radeon_device *rdev = dev->dev_private;
438 struct radeon_mode_info *mode_info = &rdev->mode_info;
439 struct atom_context *ctx = mode_info->atom_context;
440 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
441 uint16_t size, data_offset;
442 uint8_t frev, crev;
443 uint16_t device_support;
444 uint8_t dac;
445 union atom_supported_devices *supported_devices;
446 int i, j;
447 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
448
449 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
450
451 supported_devices =
452 (union atom_supported_devices *)(ctx->bios + data_offset);
453
454 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
455
456 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
457 ATOM_CONNECTOR_INFO_I2C ci =
458 supported_devices->info.asConnInfo[i];
459
460 bios_connectors[i].valid = false;
461
462 if (!(device_support & (1 << i))) {
463 continue;
464 }
465
466 if (i == ATOM_DEVICE_CV_INDEX) {
467 DRM_DEBUG("Skipping Component Video\n");
468 continue;
469 }
470
471 if (i == ATOM_DEVICE_TV1_INDEX) {
472 DRM_DEBUG("Skipping TV Out\n");
473 continue;
474 }
475
476 bios_connectors[i].connector_type =
477 supported_devices_connector_convert[ci.sucConnectorInfo.
478 sbfAccess.
479 bfConnectorType];
480
481 if (bios_connectors[i].connector_type ==
482 DRM_MODE_CONNECTOR_Unknown)
483 continue;
484
485 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
486
487 if ((rdev->family == CHIP_RS690) ||
488 (rdev->family == CHIP_RS740)) {
489 if ((i == ATOM_DEVICE_DFP2_INDEX)
490 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
491 bios_connectors[i].line_mux =
492 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
493 else if ((i == ATOM_DEVICE_DFP3_INDEX)
494 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
495 bios_connectors[i].line_mux =
496 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
497 else
498 bios_connectors[i].line_mux =
499 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
500 } else
501 bios_connectors[i].line_mux =
502 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
503
504 /* give tv unique connector ids */
505 if (i == ATOM_DEVICE_TV1_INDEX) {
506 bios_connectors[i].ddc_bus.valid = false;
507 bios_connectors[i].line_mux = 50;
508 } else if (i == ATOM_DEVICE_TV2_INDEX) {
509 bios_connectors[i].ddc_bus.valid = false;
510 bios_connectors[i].line_mux = 51;
511 } else if (i == ATOM_DEVICE_CV_INDEX) {
512 bios_connectors[i].ddc_bus.valid = false;
513 bios_connectors[i].line_mux = 52;
514 } else
515 bios_connectors[i].ddc_bus =
516 radeon_lookup_gpio(dev,
517 bios_connectors[i].line_mux);
518
519 /* Always set the connector type to VGA for CRT1/CRT2. if they are
520 * shared with a DVI port, we'll pick up the DVI connector when we
521 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
522 */
523 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
524 bios_connectors[i].connector_type =
525 DRM_MODE_CONNECTOR_VGA;
526
527 if (!radeon_atom_apply_quirks
528 (dev, (1 << i), &bios_connectors[i].connector_type,
529 &bios_connectors[i].ddc_bus))
530 continue;
531
532 bios_connectors[i].valid = true;
533 bios_connectors[i].devices = (1 << i);
534
535 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
536 radeon_add_atom_encoder(dev,
537 radeon_get_encoder_id(dev,
538 (1 << i),
539 dac),
540 (1 << i));
541 else
542 radeon_add_legacy_encoder(dev,
543 radeon_get_encoder_id(dev,
544 (1 <<
545 i),
546 dac),
547 (1 << i));
548 }
549
550 /* combine shared connectors */
551 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
552 if (bios_connectors[i].valid) {
553 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
554 if (bios_connectors[j].valid && (i != j)) {
555 if (bios_connectors[i].line_mux ==
556 bios_connectors[j].line_mux) {
557 if (((bios_connectors[i].
558 devices &
559 (ATOM_DEVICE_DFP_SUPPORT))
560 && (bios_connectors[j].
561 devices &
562 (ATOM_DEVICE_CRT_SUPPORT)))
563 ||
564 ((bios_connectors[j].
565 devices &
566 (ATOM_DEVICE_DFP_SUPPORT))
567 && (bios_connectors[i].
568 devices &
569 (ATOM_DEVICE_CRT_SUPPORT)))) {
570 bios_connectors[i].
571 devices |=
572 bios_connectors[j].
573 devices;
574 bios_connectors[i].
575 connector_type =
576 DRM_MODE_CONNECTOR_DVII;
577 bios_connectors[j].
578 valid = false;
579 }
580 }
581 }
582 }
583 }
584 }
585
586 /* add the connectors */
587 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
588 if (bios_connectors[i].valid)
589 radeon_add_atom_connector(dev,
590 bios_connectors[i].line_mux,
591 bios_connectors[i].devices,
592 bios_connectors[i].
593 connector_type,
594 &bios_connectors[i].ddc_bus,
595 false, 0);
596 }
597
598 radeon_link_encoder_connector(dev);
599
600 return true;
601}
602
603union firmware_info {
604 ATOM_FIRMWARE_INFO info;
605 ATOM_FIRMWARE_INFO_V1_2 info_12;
606 ATOM_FIRMWARE_INFO_V1_3 info_13;
607 ATOM_FIRMWARE_INFO_V1_4 info_14;
608};
609
610bool radeon_atom_get_clock_info(struct drm_device *dev)
611{
612 struct radeon_device *rdev = dev->dev_private;
613 struct radeon_mode_info *mode_info = &rdev->mode_info;
614 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
615 union firmware_info *firmware_info;
616 uint8_t frev, crev;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 uint16_t data_offset;
622
623 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
624 &crev, &data_offset);
625
626 firmware_info =
627 (union firmware_info *)(mode_info->atom_context->bios +
628 data_offset);
629
630 if (firmware_info) {
631 /* pixel clocks */
632 p1pll->reference_freq =
633 le16_to_cpu(firmware_info->info.usReferenceClock);
634 p1pll->reference_div = 0;
635
636 p1pll->pll_out_min =
637 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
638 p1pll->pll_out_max =
639 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
640
641 if (p1pll->pll_out_min == 0) {
642 if (ASIC_IS_AVIVO(rdev))
643 p1pll->pll_out_min = 64800;
644 else
645 p1pll->pll_out_min = 20000;
646 }
647
648 p1pll->pll_in_min =
649 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
650 p1pll->pll_in_max =
651 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
652
653 *p2pll = *p1pll;
654
655 /* system clock */
656 spll->reference_freq =
657 le16_to_cpu(firmware_info->info.usReferenceClock);
658 spll->reference_div = 0;
659
660 spll->pll_out_min =
661 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
662 spll->pll_out_max =
663 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
664
665 /* ??? */
666 if (spll->pll_out_min == 0) {
667 if (ASIC_IS_AVIVO(rdev))
668 spll->pll_out_min = 64800;
669 else
670 spll->pll_out_min = 20000;
671 }
672
673 spll->pll_in_min =
674 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
675 spll->pll_in_max =
676 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
677
678 /* memory clock */
679 mpll->reference_freq =
680 le16_to_cpu(firmware_info->info.usReferenceClock);
681 mpll->reference_div = 0;
682
683 mpll->pll_out_min =
684 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
685 mpll->pll_out_max =
686 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
687
688 /* ??? */
689 if (mpll->pll_out_min == 0) {
690 if (ASIC_IS_AVIVO(rdev))
691 mpll->pll_out_min = 64800;
692 else
693 mpll->pll_out_min = 20000;
694 }
695
696 mpll->pll_in_min =
697 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
698 mpll->pll_in_max =
699 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
700
701 rdev->clock.default_sclk =
702 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
703 rdev->clock.default_mclk =
704 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
705
706 return true;
707 }
708 return false;
709}
710
711struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
712 radeon_encoder
713 *encoder)
714{
715 struct drm_device *dev = encoder->base.dev;
716 struct radeon_device *rdev = dev->dev_private;
717 struct radeon_mode_info *mode_info = &rdev->mode_info;
718 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
719 uint16_t data_offset;
720 struct _ATOM_TMDS_INFO *tmds_info;
721 uint8_t frev, crev;
722 uint16_t maxfreq;
723 int i;
724 struct radeon_encoder_int_tmds *tmds = NULL;
725
726 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
727 &crev, &data_offset);
728
729 tmds_info =
730 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
731 data_offset);
732
733 if (tmds_info) {
734 tmds =
735 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
736
737 if (!tmds)
738 return NULL;
739
740 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
741 for (i = 0; i < 4; i++) {
742 tmds->tmds_pll[i].freq =
743 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
744 tmds->tmds_pll[i].value =
745 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
746 tmds->tmds_pll[i].value |=
747 (tmds_info->asMiscInfo[i].
748 ucPLL_VCO_Gain & 0x3f) << 6;
749 tmds->tmds_pll[i].value |=
750 (tmds_info->asMiscInfo[i].
751 ucPLL_DutyCycle & 0xf) << 12;
752 tmds->tmds_pll[i].value |=
753 (tmds_info->asMiscInfo[i].
754 ucPLL_VoltageSwing & 0xf) << 16;
755
756 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
757 tmds->tmds_pll[i].freq,
758 tmds->tmds_pll[i].value);
759
760 if (maxfreq == tmds->tmds_pll[i].freq) {
761 tmds->tmds_pll[i].freq = 0xffffffff;
762 break;
763 }
764 }
765 }
766 return tmds;
767}
768
769union lvds_info {
770 struct _ATOM_LVDS_INFO info;
771 struct _ATOM_LVDS_INFO_V12 info_12;
772};
773
774struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
775 radeon_encoder
776 *encoder)
777{
778 struct drm_device *dev = encoder->base.dev;
779 struct radeon_device *rdev = dev->dev_private;
780 struct radeon_mode_info *mode_info = &rdev->mode_info;
781 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
782 uint16_t data_offset;
783 union lvds_info *lvds_info;
784 uint8_t frev, crev;
785 struct radeon_encoder_atom_dig *lvds = NULL;
786
787 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
788 &crev, &data_offset);
789
790 lvds_info =
791 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
792
793 if (lvds_info) {
794 lvds =
795 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
796
797 if (!lvds)
798 return NULL;
799
800 lvds->native_mode.dotclock =
801 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
802 lvds->native_mode.panel_xres =
803 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
804 lvds->native_mode.panel_yres =
805 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
806 lvds->native_mode.hblank =
807 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
808 lvds->native_mode.hoverplus =
809 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
810 lvds->native_mode.hsync_width =
811 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
812 lvds->native_mode.vblank =
813 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
814 lvds->native_mode.voverplus =
815 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
816 lvds->native_mode.vsync_width =
817 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
818 lvds->panel_pwr_delay =
819 le16_to_cpu(lvds_info->info.usOffDelayInMs);
820 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
821
822 encoder->native_mode = lvds->native_mode;
823 }
824 return lvds;
825}
826
6fe7ac3f
AD		 827struct radeon_encoder_primary_dac *
828radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
829{
830 struct drm_device *dev = encoder->base.dev;
831 struct radeon_device *rdev = dev->dev_private;
832 struct radeon_mode_info *mode_info = &rdev->mode_info;
833 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
834 uint16_t data_offset;
835 struct _COMPASSIONATE_DATA *dac_info;
836 uint8_t frev, crev;
837 uint8_t bg, dac;
6fe7ac3f
AD		 838 struct radeon_encoder_primary_dac *p_dac = NULL;
839
840 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
841
842 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
843
844 if (dac_info) {
845 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
846
847 if (!p_dac)
848 return NULL;
849
850 bg = dac_info->ucDAC1_BG_Adjustment;
851 dac = dac_info->ucDAC1_DAC_Adjustment;
852 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
853
854 }
855 return p_dac;
856}
857
858struct radeon_encoder_tv_dac *
859radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
860{
861 struct drm_device *dev = encoder->base.dev;
862 struct radeon_device *rdev = dev->dev_private;
863 struct radeon_mode_info *mode_info = &rdev->mode_info;
864 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
865 uint16_t data_offset;
866 struct _COMPASSIONATE_DATA *dac_info;
867 uint8_t frev, crev;
868 uint8_t bg, dac;
6fe7ac3f
AD		 869 struct radeon_encoder_tv_dac *tv_dac = NULL;
870
871 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
872
873 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
874
875 if (dac_info) {
876 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
877
878 if (!tv_dac)
879 return NULL;
880
881 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
882 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
883 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
884
885 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
886 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
887 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
888
889 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
890 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
891 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
892
893 }
894 return tv_dac;
895}
896
771fe6b9
JG		 897void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
898{
899 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
900 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
901
902 args.ucEnable = enable;
903
904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
905}
906
907void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
908{
909 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
910 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
911
912 args.ucEnable = enable;
913
914 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
915}
916
917void radeon_atom_set_engine_clock(struct radeon_device *rdev,
918 uint32_t eng_clock)
919{
920 SET_ENGINE_CLOCK_PS_ALLOCATION args;
921 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
922
923 args.ulTargetEngineClock = eng_clock; /* 10 khz */
924
925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
926}
927
928void radeon_atom_set_memory_clock(struct radeon_device *rdev,
929 uint32_t mem_clock)
930{
931 SET_MEMORY_CLOCK_PS_ALLOCATION args;
932 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
933
934 if (rdev->flags & RADEON_IS_IGP)
935 return;
936
937 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
938
939 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
940}
941
942void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
943{
944 struct radeon_device *rdev = dev->dev_private;
945 uint32_t bios_2_scratch, bios_6_scratch;
946
947 if (rdev->family >= CHIP_R600) {
948 bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
949 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
950 } else {
951 bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
952 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
953 }
954
955 /* let the bios control the backlight */
956 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
957
958 /* tell the bios not to handle mode switching */
959 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
960
961 if (rdev->family >= CHIP_R600) {
962 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
963 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
964 } else {
965 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
966 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
967 }
968
969}
970
971void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
972{
973 struct drm_device *dev = encoder->dev;
974 struct radeon_device *rdev = dev->dev_private;
975 uint32_t bios_6_scratch;
976
977 if (rdev->family >= CHIP_R600)
978 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
979 else
980 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
981
982 if (lock)
983 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
984 else
985 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
986
987 if (rdev->family >= CHIP_R600)
988 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
989 else
990 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
991}
992
993/* at some point we may want to break this out into individual functions */
994void
995radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
996 struct drm_encoder *encoder,
997 bool connected)
998{
999 struct drm_device *dev = connector->dev;
1000 struct radeon_device *rdev = dev->dev_private;
1001 struct radeon_connector *radeon_connector =
1002 to_radeon_connector(connector);
1003 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1004 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1005
1006 if (rdev->family >= CHIP_R600) {
1007 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1008 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1009 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1010 } else {
1011 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1012 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1013 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1014 }
1015
1016 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1017 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1018 if (connected) {
1019 DRM_DEBUG("TV1 connected\n");
1020 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1021 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1022 } else {
1023 DRM_DEBUG("TV1 disconnected\n");
1024 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1025 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1026 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1027 }
1028 }
1029 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1030 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1031 if (connected) {
1032 DRM_DEBUG("CV connected\n");
1033 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1034 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1035 } else {
1036 DRM_DEBUG("CV disconnected\n");
1037 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1038 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1039 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1040 }
1041 }
1042 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1043 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1044 if (connected) {
1045 DRM_DEBUG("LCD1 connected\n");
1046 bios_0_scratch |= ATOM_S0_LCD1;
1047 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1048 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1049 } else {
1050 DRM_DEBUG("LCD1 disconnected\n");
1051 bios_0_scratch &= ~ATOM_S0_LCD1;
1052 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1053 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1054 }
1055 }
1056 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1057 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1058 if (connected) {
1059 DRM_DEBUG("CRT1 connected\n");
1060 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1061 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1062 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1063 } else {
1064 DRM_DEBUG("CRT1 disconnected\n");
1065 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1066 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1067 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1068 }
1069 }
1070 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1071 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1072 if (connected) {
1073 DRM_DEBUG("CRT2 connected\n");
1074 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1075 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1076 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1077 } else {
1078 DRM_DEBUG("CRT2 disconnected\n");
1079 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1080 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1081 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1082 }
1083 }
1084 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1085 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1086 if (connected) {
1087 DRM_DEBUG("DFP1 connected\n");
1088 bios_0_scratch |= ATOM_S0_DFP1;
1089 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1090 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1091 } else {
1092 DRM_DEBUG("DFP1 disconnected\n");
1093 bios_0_scratch &= ~ATOM_S0_DFP1;
1094 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1095 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1096 }
1097 }
1098 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1099 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1100 if (connected) {
1101 DRM_DEBUG("DFP2 connected\n");
1102 bios_0_scratch |= ATOM_S0_DFP2;
1103 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1104 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1105 } else {
1106 DRM_DEBUG("DFP2 disconnected\n");
1107 bios_0_scratch &= ~ATOM_S0_DFP2;
1108 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1109 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1110 }
1111 }
1112 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1113 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1114 if (connected) {
1115 DRM_DEBUG("DFP3 connected\n");
1116 bios_0_scratch |= ATOM_S0_DFP3;
1117 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1118 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1119 } else {
1120 DRM_DEBUG("DFP3 disconnected\n");
1121 bios_0_scratch &= ~ATOM_S0_DFP3;
1122 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1123 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1124 }
1125 }
1126 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1127 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1128 if (connected) {
1129 DRM_DEBUG("DFP4 connected\n");
1130 bios_0_scratch |= ATOM_S0_DFP4;
1131 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1132 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1133 } else {
1134 DRM_DEBUG("DFP4 disconnected\n");
1135 bios_0_scratch &= ~ATOM_S0_DFP4;
1136 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1137 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1138 }
1139 }
1140 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1141 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1142 if (connected) {
1143 DRM_DEBUG("DFP5 connected\n");
1144 bios_0_scratch |= ATOM_S0_DFP5;
1145 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1146 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1147 } else {
1148 DRM_DEBUG("DFP5 disconnected\n");
1149 bios_0_scratch &= ~ATOM_S0_DFP5;
1150 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1151 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1152 }
1153 }
1154
1155 if (rdev->family >= CHIP_R600) {
1156 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1157 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1158 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1159 } else {
1160 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1161 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1162 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1163 }
1164}
1165
1166void
1167radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1168{
1169 struct drm_device *dev = encoder->dev;
1170 struct radeon_device *rdev = dev->dev_private;
1171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1172 uint32_t bios_3_scratch;
1173
1174 if (rdev->family >= CHIP_R600)
1175 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1176 else
1177 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1178
1179 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1180 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1181 bios_3_scratch |= (crtc << 18);
1182 }
1183 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1184 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1185 bios_3_scratch |= (crtc << 24);
1186 }
1187 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1188 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1189 bios_3_scratch |= (crtc << 16);
1190 }
1191 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1192 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1193 bios_3_scratch |= (crtc << 20);
1194 }
1195 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1196 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1197 bios_3_scratch |= (crtc << 17);
1198 }
1199 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1200 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1201 bios_3_scratch |= (crtc << 19);
1202 }
1203 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1204 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1205 bios_3_scratch |= (crtc << 23);
1206 }
1207 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1208 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1209 bios_3_scratch |= (crtc << 25);
1210 }
1211
1212 if (rdev->family >= CHIP_R600)
1213 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1214 else
1215 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1216}
1217
1218void
1219radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1220{
1221 struct drm_device *dev = encoder->dev;
1222 struct radeon_device *rdev = dev->dev_private;
1223 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1224 uint32_t bios_2_scratch;
1225
1226 if (rdev->family >= CHIP_R600)
1227 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1228 else
1229 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1230
1231 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1232 if (on)
1233 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1234 else
1235 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1236 }
1237 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1238 if (on)
1239 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1240 else
1241 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1242 }
1243 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1244 if (on)
1245 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1246 else
1247 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1248 }
1249 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1250 if (on)
1251 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1252 else
1253 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1254 }
1255 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1256 if (on)
1257 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1258 else
1259 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1260 }
1261 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1262 if (on)
1263 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1264 else
1265 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1266 }
1267 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1268 if (on)
1269 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1270 else
1271 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1272 }
1273 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1274 if (on)
1275 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1276 else
1277 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1278 }
1279 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1280 if (on)
1281 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1282 else
1283 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1284 }
1285 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1286 if (on)
1287 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1288 else
1289 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1290 }
1291
1292 if (rdev->family >= CHIP_R600)
1293 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1294 else
1295 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1296}
Linux kernel - Deliverables
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