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drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30
AD		 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
771fe6b9
JG		 52
53/* from radeon_legacy_encoder.c */
54extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62};
63
eed45b30
AD		 64static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
771fe6b9 66{
771fe6b9 67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
d3f420d1 73 int i;
771fe6b9
JG		 74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
78 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
79
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
6a93cb25 82
d3f420d1
AD		 83 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
84 gpio = &i2c_info->asGPIO_Info[i];
85
86 if (gpio->sucI2cId.ucAccess == id) {
87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
98 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
103
104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
105 i2c.hw_capable = true;
106 else
107 i2c.hw_capable = false;
6a93cb25 108
d3f420d1
AD		 109 if (gpio->sucI2cId.ucAccess == 0xa0)
110 i2c.mm_i2c = true;
111 else
112 i2c.mm_i2c = false;
6a93cb25 113
d3f420d1
AD		 114 i2c.i2c_id = gpio->sucI2cId.ucAccess;
115
116 i2c.valid = true;
1d3d51b6 117 break;
d3f420d1
AD		 118 }
119 }
771fe6b9
JG		 120
121 return i2c;
122}
123
eed45b30
AD		 124static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
125 u8 id)
126{
127 struct atom_context *ctx = rdev->mode_info.atom_context;
128 struct radeon_gpio_rec gpio;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
130 struct _ATOM_GPIO_PIN_LUT *gpio_info;
131 ATOM_GPIO_PIN_ASSIGNMENT *pin;
132 u16 data_offset, size;
133 int i, num_indices;
134
135 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
136 gpio.valid = false;
137
138 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
139
140 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
141
142 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
143
144 for (i = 0; i < num_indices; i++) {
145 pin = &gpio_info->asGPIO_Pin[i];
146 if (id == pin->ucGPIO_ID) {
147 gpio.id = pin->ucGPIO_ID;
148 gpio.reg = pin->usGpioPin_AIndex * 4;
149 gpio.mask = (1 << pin->ucGpioPinBitShift);
150 gpio.valid = true;
151 break;
152 }
153 }
154
155 return gpio;
156}
157
158static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
160{
161 struct radeon_hpd hpd;
bcc1c2a1
AD		 162 u32 reg;
163
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
166 else
167 reg = AVIVO_DC_GPIO_HPD_A;
168
eed45b30 169 hpd.gpio = *gpio;
bcc1c2a1 170 if (gpio->reg == reg) {
eed45b30
AD		 171 switch(gpio->mask) {
172 case (1 << 0):
173 hpd.hpd = RADEON_HPD_1;
174 break;
175 case (1 << 8):
176 hpd.hpd = RADEON_HPD_2;
177 break;
178 case (1 << 16):
179 hpd.hpd = RADEON_HPD_3;
180 break;
181 case (1 << 24):
182 hpd.hpd = RADEON_HPD_4;
183 break;
184 case (1 << 26):
185 hpd.hpd = RADEON_HPD_5;
186 break;
187 case (1 << 28):
188 hpd.hpd = RADEON_HPD_6;
189 break;
190 default:
191 hpd.hpd = RADEON_HPD_NONE;
192 break;
193 }
194 } else
195 hpd.hpd = RADEON_HPD_NONE;
196 return hpd;
197}
198
771fe6b9
JG		 199static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
201 int *connector_type,
848577ee 202 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 203 uint16_t *line_mux,
204 struct radeon_hpd *hpd)
771fe6b9
JG		 205{
206
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
214 }
215
216 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x147b) &&
219 (dev->pdev->subsystem_device == 0x2412)) {
220 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
221 return false;
222 }
223
224 /* Falcon NW laptop lists vga ddc line for LVDS */
225 if ((dev->pdev->device == 0x5653) &&
226 (dev->pdev->subsystem_vendor == 0x1462) &&
227 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 228 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 229 i2c_bus->valid = false;
848577ee
AD		 230 *line_mux = 53;
231 }
771fe6b9
JG		 232 }
233
4e3f9b78
AD		 234 /* HIS X1300 is DVI+VGA, not DVI+DVI */
235 if ((dev->pdev->device == 0x7146) &&
236 (dev->pdev->subsystem_vendor == 0x17af) &&
237 (dev->pdev->subsystem_device == 0x2058)) {
238 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
239 return false;
240 }
241
aa1a750e
DA		 242 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
243 if ((dev->pdev->device == 0x7142) &&
244 (dev->pdev->subsystem_vendor == 0x1458) &&
245 (dev->pdev->subsystem_device == 0x2134)) {
246 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
247 return false;
248 }
249
250
771fe6b9
JG		 251 /* Funky macbooks */
252 if ((dev->pdev->device == 0x71C5) &&
253 (dev->pdev->subsystem_vendor == 0x106b) &&
254 (dev->pdev->subsystem_device == 0x0080)) {
255 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
256 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
257 return false;
258 }
259
771fe6b9
JG		 260 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
261 if ((dev->pdev->device == 0x9598) &&
262 (dev->pdev->subsystem_vendor == 0x1043) &&
263 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 264 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 265 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 266 }
267 }
268
269 /* ASUS HD 3450 board lists the DVI port as HDMI */
270 if ((dev->pdev->device == 0x95C5) &&
271 (dev->pdev->subsystem_vendor == 0x1043) &&
272 (dev->pdev->subsystem_device == 0x01e2)) {
273 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 274 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 275 }
276 }
277
705af9c7
AD		 278 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
279 * HDMI + VGA reporting as HDMI
280 */
281 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
282 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
283 *connector_type = DRM_MODE_CONNECTOR_VGA;
284 *line_mux = 0;
285 }
286 }
287
3e5f8ff3
AD		 288 /* Acer laptop reports DVI-D as DVI-I */
289 if ((dev->pdev->device == 0x95c4) &&
290 (dev->pdev->subsystem_vendor == 0x1025) &&
291 (dev->pdev->subsystem_device == 0x013c)) {
292 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
293 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
294 *connector_type = DRM_MODE_CONNECTOR_DVID;
295 }
296
771fe6b9
JG		 297 return true;
298}
299
300const int supported_devices_connector_convert[] = {
301 DRM_MODE_CONNECTOR_Unknown,
302 DRM_MODE_CONNECTOR_VGA,
303 DRM_MODE_CONNECTOR_DVII,
304 DRM_MODE_CONNECTOR_DVID,
305 DRM_MODE_CONNECTOR_DVIA,
306 DRM_MODE_CONNECTOR_SVIDEO,
307 DRM_MODE_CONNECTOR_Composite,
308 DRM_MODE_CONNECTOR_LVDS,
309 DRM_MODE_CONNECTOR_Unknown,
310 DRM_MODE_CONNECTOR_Unknown,
311 DRM_MODE_CONNECTOR_HDMIA,
312 DRM_MODE_CONNECTOR_HDMIB,
313 DRM_MODE_CONNECTOR_Unknown,
314 DRM_MODE_CONNECTOR_Unknown,
315 DRM_MODE_CONNECTOR_9PinDIN,
316 DRM_MODE_CONNECTOR_DisplayPort
317};
318
b75fad06
AD		 319const uint16_t supported_devices_connector_object_id_convert[] = {
320 CONNECTOR_OBJECT_ID_NONE,
321 CONNECTOR_OBJECT_ID_VGA,
322 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
323 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
324 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
325 CONNECTOR_OBJECT_ID_COMPOSITE,
326 CONNECTOR_OBJECT_ID_SVIDEO,
327 CONNECTOR_OBJECT_ID_LVDS,
328 CONNECTOR_OBJECT_ID_9PIN_DIN,
329 CONNECTOR_OBJECT_ID_9PIN_DIN,
330 CONNECTOR_OBJECT_ID_DISPLAYPORT,
331 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
332 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
333 CONNECTOR_OBJECT_ID_SVIDEO
334};
335
771fe6b9
JG		 336const int object_connector_convert[] = {
337 DRM_MODE_CONNECTOR_Unknown,
338 DRM_MODE_CONNECTOR_DVII,
339 DRM_MODE_CONNECTOR_DVII,
340 DRM_MODE_CONNECTOR_DVID,
341 DRM_MODE_CONNECTOR_DVID,
342 DRM_MODE_CONNECTOR_VGA,
343 DRM_MODE_CONNECTOR_Composite,
344 DRM_MODE_CONNECTOR_SVIDEO,
345 DRM_MODE_CONNECTOR_Unknown,
705af9c7 346 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 347 DRM_MODE_CONNECTOR_9PinDIN,
348 DRM_MODE_CONNECTOR_Unknown,
349 DRM_MODE_CONNECTOR_HDMIA,
350 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 351 DRM_MODE_CONNECTOR_LVDS,
352 DRM_MODE_CONNECTOR_9PinDIN,
353 DRM_MODE_CONNECTOR_Unknown,
354 DRM_MODE_CONNECTOR_Unknown,
355 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 356 DRM_MODE_CONNECTOR_DisplayPort,
357 DRM_MODE_CONNECTOR_eDP,
358 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 359};
360
361bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
362{
363 struct radeon_device *rdev = dev->dev_private;
364 struct radeon_mode_info *mode_info = &rdev->mode_info;
365 struct atom_context *ctx = mode_info->atom_context;
366 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 367 u16 size, data_offset;
368 u8 frev, crev;
771fe6b9
JG		 369 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
370 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
371 ATOM_OBJECT_HEADER *obj_header;
372 int i, j, path_size, device_support;
373 int connector_type;
eed45b30 374 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 375 bool linkb;
376 struct radeon_i2c_bus_rec ddc_bus;
eed45b30
AD		 377 struct radeon_gpio_rec gpio;
378 struct radeon_hpd hpd;
379
771fe6b9
JG		 380 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
381
382 if (data_offset == 0)
383 return false;
384
385 if (crev < 2)
386 return false;
387
388 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
389 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
390 (ctx->bios + data_offset +
391 le16_to_cpu(obj_header->usDisplayPathTableOffset));
392 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
393 (ctx->bios + data_offset +
394 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
395 device_support = le16_to_cpu(obj_header->usDeviceSupport);
396
397 path_size = 0;
398 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
399 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
400 ATOM_DISPLAY_OBJECT_PATH *path;
401 addr += path_size;
402 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
403 path_size += le16_to_cpu(path->usSize);
404 linkb = false;
771fe6b9
JG		 405 if (device_support & le16_to_cpu(path->usDeviceTag)) {
406 uint8_t con_obj_id, con_obj_num, con_obj_type;
407
408 con_obj_id =
409 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
410 >> OBJECT_ID_SHIFT;
411 con_obj_num =
412 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
413 >> ENUM_ID_SHIFT;
414 con_obj_type =
415 (le16_to_cpu(path->usConnObjectId) &
416 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
417
4bbd4973
DA		 418 /* TODO CV support */
419 if (le16_to_cpu(path->usDeviceTag) ==
420 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 421 continue;
422
ee59f2b4
AD		 423 /* IGP chips */
424 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 425 (con_obj_id ==
426 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
427 uint16_t igp_offset = 0;
428 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
429
430 index =
431 GetIndexIntoMasterTable(DATA,
432 IntegratedSystemInfo);
433
434 atom_parse_data_header(ctx, index, &size, &frev,
435 &crev, &igp_offset);
436
437 if (crev >= 2) {
438 igp_obj =
439 (ATOM_INTEGRATED_SYSTEM_INFO_V2
440 *) (ctx->bios + igp_offset);
441
442 if (igp_obj) {
443 uint32_t slot_config, ct;
444
445 if (con_obj_num == 1)
446 slot_config =
447 igp_obj->
448 ulDDISlot1Config;
449 else
450 slot_config =
451 igp_obj->
452 ulDDISlot2Config;
453
454 ct = (slot_config >> 16) & 0xff;
455 connector_type =
456 object_connector_convert
457 [ct];
b75fad06 458 connector_object_id = ct;
771fe6b9
JG		 459 igp_lane_info =
460 slot_config & 0xffff;
461 } else
462 continue;
463 } else
464 continue;
465 } else {
466 igp_lane_info = 0;
467 connector_type =
468 object_connector_convert[con_obj_id];
b75fad06 469 connector_object_id = con_obj_id;
771fe6b9
JG		 470 }
471
472 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
473 continue;
474
475 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
476 j++) {
477 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
478
479 enc_obj_id =
480 (le16_to_cpu(path->usGraphicObjIds[j]) &
481 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
482 enc_obj_num =
483 (le16_to_cpu(path->usGraphicObjIds[j]) &
484 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
485 enc_obj_type =
486 (le16_to_cpu(path->usGraphicObjIds[j]) &
487 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
488
489 /* FIXME: add support for router objects */
490 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
491 if (enc_obj_num == 2)
492 linkb = true;
493 else
494 linkb = false;
495
496 radeon_add_atom_encoder(dev,
497 enc_obj_id,
498 le16_to_cpu
499 (path->
500 usDeviceTag));
501
502 }
503 }
504
eed45b30 505 /* look up gpio for ddc, hpd */
771fe6b9 506 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 507 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 508 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
509 if (le16_to_cpu(path->usConnObjectId) ==
510 le16_to_cpu(con_obj->asObjects[j].
511 usObjectID)) {
512 ATOM_COMMON_RECORD_HEADER
513 *record =
514 (ATOM_COMMON_RECORD_HEADER
515 *)
516 (ctx->bios + data_offset +
517 le16_to_cpu(con_obj->
518 asObjects[j].
519 usRecordOffset));
520 ATOM_I2C_RECORD *i2c_record;
eed45b30 521 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 522 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
eed45b30 523 hpd.hpd = RADEON_HPD_NONE;
6a93cb25 524
771fe6b9
JG		 525 while (record->ucRecordType > 0
526 && record->
527 ucRecordType <=
528 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 529 switch (record->ucRecordType) {
771fe6b9
JG		 530 case ATOM_I2C_RECORD_TYPE:
531 i2c_record =
eed45b30
AD		 532 (ATOM_I2C_RECORD *)
533 record;
d3f420d1
AD		 534 i2c_config =
535 (ATOM_I2C_ID_CONFIG_ACCESS *)
536 &i2c_record->sucI2cId;
eed45b30 537 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 538 i2c_config->
539 ucAccess);
eed45b30
AD		 540 break;
541 case ATOM_HPD_INT_RECORD_TYPE:
542 hpd_record =
543 (ATOM_HPD_INT_RECORD *)
544 record;
545 gpio = radeon_lookup_gpio(rdev,
546 hpd_record->ucHPDIntGPIOID);
547 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
548 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 549 break;
550 }
551 record =
552 (ATOM_COMMON_RECORD_HEADER
553 *) ((char *)record
554 +
555 record->
556 ucRecordSize);
557 }
558 break;
559 }
560 }
eed45b30
AD		 561 } else {
562 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 563 ddc_bus.valid = false;
eed45b30 564 }
771fe6b9 565
bcc1c2a1
AD		 566 /* needed for aux chan transactions */
567 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
568
705af9c7
AD		 569 conn_id = le16_to_cpu(path->usConnObjectId);
570
571 if (!radeon_atom_apply_quirks
572 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 573 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 574 continue;
575
771fe6b9 576 radeon_add_atom_connector(dev,
705af9c7 577 conn_id,
771fe6b9
JG		 578 le16_to_cpu(path->
579 usDeviceTag),
580 connector_type, &ddc_bus,
b75fad06 581 linkb, igp_lane_info,
eed45b30
AD		 582 connector_object_id,
583 &hpd);
771fe6b9
JG		 584
585 }
586 }
587
588 radeon_link_encoder_connector(dev);
589
590 return true;
591}
592
b75fad06
AD		 593static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
594 int connector_type,
595 uint16_t devices)
596{
597 struct radeon_device *rdev = dev->dev_private;
598
599 if (rdev->flags & RADEON_IS_IGP) {
600 return supported_devices_connector_object_id_convert
601 [connector_type];
602 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
603 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
604 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
605 struct radeon_mode_info *mode_info = &rdev->mode_info;
606 struct atom_context *ctx = mode_info->atom_context;
607 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
608 uint16_t size, data_offset;
609 uint8_t frev, crev;
610 ATOM_XTMDS_INFO *xtmds;
611
612 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
613 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
614
615 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
616 if (connector_type == DRM_MODE_CONNECTOR_DVII)
617 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
618 else
619 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
620 } else {
621 if (connector_type == DRM_MODE_CONNECTOR_DVII)
622 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
623 else
624 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
625 }
626 } else {
627 return supported_devices_connector_object_id_convert
628 [connector_type];
629 }
630}
631
771fe6b9
JG		 632struct bios_connector {
633 bool valid;
705af9c7 634 uint16_t line_mux;
771fe6b9
JG		 635 uint16_t devices;
636 int connector_type;
637 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 638 struct radeon_hpd hpd;
771fe6b9
JG		 639};
640
641bool radeon_get_atom_connector_info_from_supported_devices_table(struct
642 drm_device
643 *dev)
644{
645 struct radeon_device *rdev = dev->dev_private;
646 struct radeon_mode_info *mode_info = &rdev->mode_info;
647 struct atom_context *ctx = mode_info->atom_context;
648 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
649 uint16_t size, data_offset;
650 uint8_t frev, crev;
651 uint16_t device_support;
652 uint8_t dac;
653 union atom_supported_devices *supported_devices;
eed45b30 654 int i, j, max_device;
771fe6b9
JG		 655 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
656
657 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
658
659 supported_devices =
660 (union atom_supported_devices *)(ctx->bios + data_offset);
661
662 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
663
eed45b30
AD		 664 if (frev > 1)
665 max_device = ATOM_MAX_SUPPORTED_DEVICE;
666 else
667 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
668
669 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 670 ATOM_CONNECTOR_INFO_I2C ci =
671 supported_devices->info.asConnInfo[i];
672
673 bios_connectors[i].valid = false;
674
675 if (!(device_support & (1 << i))) {
676 continue;
677 }
678
679 if (i == ATOM_DEVICE_CV_INDEX) {
680 DRM_DEBUG("Skipping Component Video\n");
681 continue;
682 }
683
771fe6b9
JG		 684 bios_connectors[i].connector_type =
685 supported_devices_connector_convert[ci.sucConnectorInfo.
686 sbfAccess.
687 bfConnectorType];
688
689 if (bios_connectors[i].connector_type ==
690 DRM_MODE_CONNECTOR_Unknown)
691 continue;
692
693 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
694
d3f420d1
AD		 695 bios_connectors[i].line_mux =
696 ci.sucI2cId.ucAccess;
771fe6b9
JG		 697
698 /* give tv unique connector ids */
699 if (i == ATOM_DEVICE_TV1_INDEX) {
700 bios_connectors[i].ddc_bus.valid = false;
701 bios_connectors[i].line_mux = 50;
702 } else if (i == ATOM_DEVICE_TV2_INDEX) {
703 bios_connectors[i].ddc_bus.valid = false;
704 bios_connectors[i].line_mux = 51;
705 } else if (i == ATOM_DEVICE_CV_INDEX) {
706 bios_connectors[i].ddc_bus.valid = false;
707 bios_connectors[i].line_mux = 52;
708 } else
709 bios_connectors[i].ddc_bus =
eed45b30
AD		 710 radeon_lookup_i2c_gpio(rdev,
711 bios_connectors[i].line_mux);
712
713 if ((crev > 1) && (frev > 1)) {
714 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
715 switch (isb) {
716 case 0x4:
717 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
718 break;
719 case 0xa:
720 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
721 break;
722 default:
723 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
724 break;
725 }
726 } else {
727 if (i == ATOM_DEVICE_DFP1_INDEX)
728 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
729 else if (i == ATOM_DEVICE_DFP2_INDEX)
730 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
731 else
732 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
733 }
771fe6b9
JG		 734
735 /* Always set the connector type to VGA for CRT1/CRT2. if they are
736 * shared with a DVI port, we'll pick up the DVI connector when we
737 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
738 */
739 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
740 bios_connectors[i].connector_type =
741 DRM_MODE_CONNECTOR_VGA;
742
743 if (!radeon_atom_apply_quirks
744 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 745 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
746 &bios_connectors[i].hpd))
771fe6b9
JG		 747 continue;
748
749 bios_connectors[i].valid = true;
750 bios_connectors[i].devices = (1 << i);
751
752 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
753 radeon_add_atom_encoder(dev,
754 radeon_get_encoder_id(dev,
755 (1 << i),
756 dac),
757 (1 << i));
758 else
759 radeon_add_legacy_encoder(dev,
760 radeon_get_encoder_id(dev,
f56cd64f 761 (1 << i),
771fe6b9
JG		 762 dac),
763 (1 << i));
764 }
765
766 /* combine shared connectors */
eed45b30 767 for (i = 0; i < max_device; i++) {
771fe6b9 768 if (bios_connectors[i].valid) {
eed45b30 769 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 770 if (bios_connectors[j].valid && (i != j)) {
771 if (bios_connectors[i].line_mux ==
772 bios_connectors[j].line_mux) {
f56cd64f
AD		 773 /* make sure not to combine LVDS */
774 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
775 bios_connectors[i].line_mux = 53;
776 bios_connectors[i].ddc_bus.valid = false;
777 continue;
778 }
779 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
780 bios_connectors[j].line_mux = 53;
781 bios_connectors[j].ddc_bus.valid = false;
782 continue;
783 }
784 /* combine analog and digital for DVI-I */
785 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
786 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
787 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
788 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
789 bios_connectors[i].devices |=
790 bios_connectors[j].devices;
791 bios_connectors[i].connector_type =
792 DRM_MODE_CONNECTOR_DVII;
793 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 794 bios_connectors[i].hpd =
795 bios_connectors[j].hpd;
f56cd64f 796 bios_connectors[j].valid = false;
771fe6b9
JG		 797 }
798 }
799 }
800 }
801 }
802 }
803
804 /* add the connectors */
eed45b30 805 for (i = 0; i < max_device; i++) {
b75fad06
AD		 806 if (bios_connectors[i].valid) {
807 uint16_t connector_object_id =
808 atombios_get_connector_object_id(dev,
809 bios_connectors[i].connector_type,
810 bios_connectors[i].devices);
771fe6b9
JG		 811 radeon_add_atom_connector(dev,
812 bios_connectors[i].line_mux,
813 bios_connectors[i].devices,
814 bios_connectors[i].
815 connector_type,
816 &bios_connectors[i].ddc_bus,
b75fad06 817 false, 0,
eed45b30
AD		 818 connector_object_id,
819 &bios_connectors[i].hpd);
b75fad06 820 }
771fe6b9
JG		 821 }
822
823 radeon_link_encoder_connector(dev);
824
825 return true;
826}
827
828union firmware_info {
829 ATOM_FIRMWARE_INFO info;
830 ATOM_FIRMWARE_INFO_V1_2 info_12;
831 ATOM_FIRMWARE_INFO_V1_3 info_13;
832 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 833 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 834};
835
836bool radeon_atom_get_clock_info(struct drm_device *dev)
837{
838 struct radeon_device *rdev = dev->dev_private;
839 struct radeon_mode_info *mode_info = &rdev->mode_info;
840 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
841 union firmware_info *firmware_info;
842 uint8_t frev, crev;
843 struct radeon_pll *p1pll = &rdev->clock.p1pll;
844 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 845 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 846 struct radeon_pll *spll = &rdev->clock.spll;
847 struct radeon_pll *mpll = &rdev->clock.mpll;
848 uint16_t data_offset;
849
850 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
851 &crev, &data_offset);
852
853 firmware_info =
854 (union firmware_info *)(mode_info->atom_context->bios +
855 data_offset);
856
857 if (firmware_info) {
858 /* pixel clocks */
859 p1pll->reference_freq =
860 le16_to_cpu(firmware_info->info.usReferenceClock);
861 p1pll->reference_div = 0;
862
bc293e58
MF		 863 if (crev < 2)
864 p1pll->pll_out_min =
865 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
866 else
867 p1pll->pll_out_min =
868 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 869 p1pll->pll_out_max =
870 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
871
872 if (p1pll->pll_out_min == 0) {
873 if (ASIC_IS_AVIVO(rdev))
874 p1pll->pll_out_min = 64800;
875 else
876 p1pll->pll_out_min = 20000;
8f552a66
AD		 877 } else if (p1pll->pll_out_min > 64800) {
878 /* Limiting the pll output range is a good thing generally as
879 * it limits the number of possible pll combinations for a given
880 * frequency presumably to the ones that work best on each card.
881 * However, certain duallink DVI monitors seem to like
882 * pll combinations that would be limited by this at least on
883 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
884 * family.
885 */
b27b6375
AD		 886 if (!radeon_new_pll)
887 p1pll->pll_out_min = 64800;
771fe6b9
JG		 888 }
889
890 p1pll->pll_in_min =
891 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
892 p1pll->pll_in_max =
893 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
894
895 *p2pll = *p1pll;
896
897 /* system clock */
898 spll->reference_freq =
899 le16_to_cpu(firmware_info->info.usReferenceClock);
900 spll->reference_div = 0;
901
902 spll->pll_out_min =
903 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
904 spll->pll_out_max =
905 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
906
907 /* ??? */
908 if (spll->pll_out_min == 0) {
909 if (ASIC_IS_AVIVO(rdev))
910 spll->pll_out_min = 64800;
911 else
912 spll->pll_out_min = 20000;
913 }
914
915 spll->pll_in_min =
916 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
917 spll->pll_in_max =
918 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
919
920 /* memory clock */
921 mpll->reference_freq =
922 le16_to_cpu(firmware_info->info.usReferenceClock);
923 mpll->reference_div = 0;
924
925 mpll->pll_out_min =
926 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
927 mpll->pll_out_max =
928 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
929
930 /* ??? */
931 if (mpll->pll_out_min == 0) {
932 if (ASIC_IS_AVIVO(rdev))
933 mpll->pll_out_min = 64800;
934 else
935 mpll->pll_out_min = 20000;
936 }
937
938 mpll->pll_in_min =
939 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
940 mpll->pll_in_max =
941 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
942
943 rdev->clock.default_sclk =
944 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
945 rdev->clock.default_mclk =
946 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
947
bcc1c2a1
AD		 948 if (ASIC_IS_DCE4(rdev)) {
949 rdev->clock.default_dispclk =
950 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
951 if (rdev->clock.default_dispclk == 0)
952 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
953 rdev->clock.dp_extclk =
954 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
955 }
956 *dcpll = *p1pll;
957
771fe6b9
JG		 958 return true;
959 }
bcc1c2a1 960
771fe6b9
JG		 961 return false;
962}
963
06b6476d
AD		 964union igp_info {
965 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
966 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
967};
968
969bool radeon_atombios_sideport_present(struct radeon_device *rdev)
970{
971 struct radeon_mode_info *mode_info = &rdev->mode_info;
972 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
973 union igp_info *igp_info;
974 u8 frev, crev;
975 u16 data_offset;
976
977 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
978 &crev, &data_offset);
979
980 igp_info = (union igp_info *)(mode_info->atom_context->bios +
981 data_offset);
982
983 if (igp_info) {
984 switch (crev) {
985 case 1:
986 if (igp_info->info.ucMemoryType & 0xf0)
987 return true;
988 break;
989 case 2:
990 if (igp_info->info_2.ucMemoryType & 0x0f)
991 return true;
992 break;
993 default:
994 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
995 break;
996 }
997 }
998 return false;
999}
1000
445282db
DA		 1001bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1002 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1003{
1004 struct drm_device *dev = encoder->base.dev;
1005 struct radeon_device *rdev = dev->dev_private;
1006 struct radeon_mode_info *mode_info = &rdev->mode_info;
1007 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1008 uint16_t data_offset;
1009 struct _ATOM_TMDS_INFO *tmds_info;
1010 uint8_t frev, crev;
1011 uint16_t maxfreq;
1012 int i;
771fe6b9
JG		 1013
1014 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1015 &crev, &data_offset);
1016
1017 tmds_info =
1018 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1019 data_offset);
1020
1021 if (tmds_info) {
771fe6b9
JG		 1022 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1023 for (i = 0; i < 4; i++) {
1024 tmds->tmds_pll[i].freq =
1025 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1026 tmds->tmds_pll[i].value =
1027 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1028 tmds->tmds_pll[i].value |=
1029 (tmds_info->asMiscInfo[i].
1030 ucPLL_VCO_Gain & 0x3f) << 6;
1031 tmds->tmds_pll[i].value |=
1032 (tmds_info->asMiscInfo[i].
1033 ucPLL_DutyCycle & 0xf) << 12;
1034 tmds->tmds_pll[i].value |=
1035 (tmds_info->asMiscInfo[i].
1036 ucPLL_VoltageSwing & 0xf) << 16;
1037
1038 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1039 tmds->tmds_pll[i].freq,
1040 tmds->tmds_pll[i].value);
1041
1042 if (maxfreq == tmds->tmds_pll[i].freq) {
1043 tmds->tmds_pll[i].freq = 0xffffffff;
1044 break;
1045 }
1046 }
445282db 1047 return true;
771fe6b9 1048 }
445282db 1049 return false;
771fe6b9
JG		 1050}
1051
ebbe1cb9
AD		 1052static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1053 radeon_encoder
1054 *encoder,
1055 int id)
1056{
1057 struct drm_device *dev = encoder->base.dev;
1058 struct radeon_device *rdev = dev->dev_private;
1059 struct radeon_mode_info *mode_info = &rdev->mode_info;
1060 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1061 uint16_t data_offset;
1062 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1063 uint8_t frev, crev;
1064 struct radeon_atom_ss *ss = NULL;
279b215e 1065 int i;
ebbe1cb9
AD		 1066
1067 if (id > ATOM_MAX_SS_ENTRY)
1068 return NULL;
1069
1070 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1071 &crev, &data_offset);
1072
1073 ss_info =
1074 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1075
1076 if (ss_info) {
1077 ss =
1078 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1079
1080 if (!ss)
1081 return NULL;
1082
279b215e
AD		 1083 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1084 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1085 ss->percentage =
1086 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1087 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1088 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1089 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1090 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1091 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1092 break;
279b215e
AD		 1093 }
1094 }
ebbe1cb9
AD		 1095 }
1096 return ss;
1097}
1098
09397278
AD		 1099static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
1100 struct radeon_encoder_atom_dig *lvds)
1101{
1102
1103 /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1104 if ((dev->pdev->device == 0x95c4) &&
1105 (dev->pdev->subsystem_vendor == 0x1179) &&
1106 (dev->pdev->subsystem_device == 0xff50)) {
1107 if ((lvds->native_mode.hdisplay == 1280) &&
1108 (lvds->native_mode.vdisplay == 800))
1109 lvds->pll_algo = PLL_ALGO_LEGACY;
1110 }
1111
1112}
1113
771fe6b9
JG		 1114union lvds_info {
1115 struct _ATOM_LVDS_INFO info;
1116 struct _ATOM_LVDS_INFO_V12 info_12;
1117};
1118
1119struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1120 radeon_encoder
1121 *encoder)
1122{
1123 struct drm_device *dev = encoder->base.dev;
1124 struct radeon_device *rdev = dev->dev_private;
1125 struct radeon_mode_info *mode_info = &rdev->mode_info;
1126 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1127 uint16_t data_offset, misc;
771fe6b9
JG		 1128 union lvds_info *lvds_info;
1129 uint8_t frev, crev;
1130 struct radeon_encoder_atom_dig *lvds = NULL;
1131
1132 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1133 &crev, &data_offset);
1134
1135 lvds_info =
1136 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1137
1138 if (lvds_info) {
1139 lvds =
1140 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1141
1142 if (!lvds)
1143 return NULL;
1144
de2103e4 1145 lvds->native_mode.clock =
771fe6b9 1146 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1147 lvds->native_mode.hdisplay =
771fe6b9 1148 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1149 lvds->native_mode.vdisplay =
771fe6b9 1150 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1151 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1152 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1153 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1154 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1155 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1156 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1157 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1158 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1159 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1160 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1161 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1162 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1163 lvds->panel_pwr_delay =
1164 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1165 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1166
1167 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1168 if (misc & ATOM_VSYNC_POLARITY)
1169 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1170 if (misc & ATOM_HSYNC_POLARITY)
1171 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1172 if (misc & ATOM_COMPOSITESYNC)
1173 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1174 if (misc & ATOM_INTERLACE)
1175 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1176 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1177 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1178
de2103e4
AD		 1179 /* set crtc values */
1180 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1181
ebbe1cb9
AD		 1182 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1183
7c27f87d
AD		 1184 if (ASIC_IS_AVIVO(rdev)) {
1185 if (radeon_new_pll)
1186 lvds->pll_algo = PLL_ALGO_AVIVO;
1187 else
1188 lvds->pll_algo = PLL_ALGO_LEGACY;
1189 } else
1190 lvds->pll_algo = PLL_ALGO_LEGACY;
1191
09397278
AD		 1192 /* LVDS quirks */
1193 radeon_atom_apply_lvds_quirks(dev, lvds);
1194
771fe6b9
JG		 1195 encoder->native_mode = lvds->native_mode;
1196 }
1197 return lvds;
1198}
1199
6fe7ac3f
AD		 1200struct radeon_encoder_primary_dac *
1201radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1202{
1203 struct drm_device *dev = encoder->base.dev;
1204 struct radeon_device *rdev = dev->dev_private;
1205 struct radeon_mode_info *mode_info = &rdev->mode_info;
1206 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1207 uint16_t data_offset;
1208 struct _COMPASSIONATE_DATA *dac_info;
1209 uint8_t frev, crev;
1210 uint8_t bg, dac;
6fe7ac3f
AD		 1211 struct radeon_encoder_primary_dac *p_dac = NULL;
1212
1213 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1214
1215 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1216
1217 if (dac_info) {
1218 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1219
1220 if (!p_dac)
1221 return NULL;
1222
1223 bg = dac_info->ucDAC1_BG_Adjustment;
1224 dac = dac_info->ucDAC1_DAC_Adjustment;
1225 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1226
1227 }
1228 return p_dac;
1229}
1230
4ce001ab 1231bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1232 struct drm_display_mode *mode)
4ce001ab
DA		 1233{
1234 struct radeon_mode_info *mode_info = &rdev->mode_info;
1235 ATOM_ANALOG_TV_INFO *tv_info;
1236 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1237 ATOM_DTD_FORMAT *dtd_timings;
1238 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1239 u8 frev, crev;
5a9bcacc 1240 u16 data_offset, misc;
4ce001ab
DA		 1241
1242 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1243
1244 switch (crev) {
1245 case 1:
1246 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1247 if (index > MAX_SUPPORTED_TV_TIMING)
1248 return false;
1249
5a9bcacc
AD		 1250 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1251 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1252 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1253 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1254 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1255
1256 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1257 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1258 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1259 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1260 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1261
1262 mode->flags = 0;
1263 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1264 if (misc & ATOM_VSYNC_POLARITY)
1265 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1266 if (misc & ATOM_HSYNC_POLARITY)
1267 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1268 if (misc & ATOM_COMPOSITESYNC)
1269 mode->flags |= DRM_MODE_FLAG_CSYNC;
1270 if (misc & ATOM_INTERLACE)
1271 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1272 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1273 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1274
1275 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1276
1277 if (index == 1) {
1278 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1279 mode->crtc_htotal -= 1;
1280 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1281 }
1282 break;
1283 case 2:
1284 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1285 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1286 return false;
1287
1288 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1289 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1290 le16_to_cpu(dtd_timings->usHBlanking_Time);
1291 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1292 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1293 le16_to_cpu(dtd_timings->usHSyncOffset);
1294 mode->crtc_hsync_end = mode->crtc_hsync_start +
1295 le16_to_cpu(dtd_timings->usHSyncWidth);
1296
1297 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1298 le16_to_cpu(dtd_timings->usVBlanking_Time);
1299 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1300 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1301 le16_to_cpu(dtd_timings->usVSyncOffset);
1302 mode->crtc_vsync_end = mode->crtc_vsync_start +
1303 le16_to_cpu(dtd_timings->usVSyncWidth);
1304
1305 mode->flags = 0;
1306 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1307 if (misc & ATOM_VSYNC_POLARITY)
1308 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1309 if (misc & ATOM_HSYNC_POLARITY)
1310 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1311 if (misc & ATOM_COMPOSITESYNC)
1312 mode->flags |= DRM_MODE_FLAG_CSYNC;
1313 if (misc & ATOM_INTERLACE)
1314 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1315 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1316 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1317
1318 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1319 break;
1320 }
1321 return true;
1322}
1323
d79766fa
AD		 1324enum radeon_tv_std
1325radeon_atombios_get_tv_info(struct radeon_device *rdev)
1326{
1327 struct radeon_mode_info *mode_info = &rdev->mode_info;
1328 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1329 uint16_t data_offset;
1330 uint8_t frev, crev;
1331 struct _ATOM_ANALOG_TV_INFO *tv_info;
1332 enum radeon_tv_std tv_std = TV_STD_NTSC;
1333
1334 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1335
1336 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1337
1338 switch (tv_info->ucTV_BootUpDefaultStandard) {
1339 case ATOM_TV_NTSC:
1340 tv_std = TV_STD_NTSC;
1341 DRM_INFO("Default TV standard: NTSC\n");
1342 break;
1343 case ATOM_TV_NTSCJ:
1344 tv_std = TV_STD_NTSC_J;
1345 DRM_INFO("Default TV standard: NTSC-J\n");
1346 break;
1347 case ATOM_TV_PAL:
1348 tv_std = TV_STD_PAL;
1349 DRM_INFO("Default TV standard: PAL\n");
1350 break;
1351 case ATOM_TV_PALM:
1352 tv_std = TV_STD_PAL_M;
1353 DRM_INFO("Default TV standard: PAL-M\n");
1354 break;
1355 case ATOM_TV_PALN:
1356 tv_std = TV_STD_PAL_N;
1357 DRM_INFO("Default TV standard: PAL-N\n");
1358 break;
1359 case ATOM_TV_PALCN:
1360 tv_std = TV_STD_PAL_CN;
1361 DRM_INFO("Default TV standard: PAL-CN\n");
1362 break;
1363 case ATOM_TV_PAL60:
1364 tv_std = TV_STD_PAL_60;
1365 DRM_INFO("Default TV standard: PAL-60\n");
1366 break;
1367 case ATOM_TV_SECAM:
1368 tv_std = TV_STD_SECAM;
1369 DRM_INFO("Default TV standard: SECAM\n");
1370 break;
1371 default:
1372 tv_std = TV_STD_NTSC;
1373 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1374 break;
1375 }
1376 return tv_std;
1377}
1378
6fe7ac3f
AD		 1379struct radeon_encoder_tv_dac *
1380radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1381{
1382 struct drm_device *dev = encoder->base.dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384 struct radeon_mode_info *mode_info = &rdev->mode_info;
1385 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1386 uint16_t data_offset;
1387 struct _COMPASSIONATE_DATA *dac_info;
1388 uint8_t frev, crev;
1389 uint8_t bg, dac;
6fe7ac3f
AD		 1390 struct radeon_encoder_tv_dac *tv_dac = NULL;
1391
1392 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1393
1394 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1395
1396 if (dac_info) {
1397 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1398
1399 if (!tv_dac)
1400 return NULL;
1401
1402 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1403 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1404 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1405
1406 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1407 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1408 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1409
1410 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1411 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1412 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1413
d79766fa 1414 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1415 }
1416 return tv_dac;
1417}
1418
56278a8e
AD		 1419union power_info {
1420 struct _ATOM_POWERPLAY_INFO info;
1421 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1422 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1423 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1424};
1425
1426void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1427{
1428 struct radeon_mode_info *mode_info = &rdev->mode_info;
1429 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1430 u16 data_offset;
1431 u8 frev, crev;
1432 u32 misc, misc2 = 0, sclk, mclk;
1433 union power_info *power_info;
1434 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1435 struct _ATOM_PPLIB_STATE *power_state;
1436 int num_modes = 0, i, j;
1437 int state_index = 0, mode_index = 0;
1438
1439 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1440
1441 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1442
1443 rdev->pm.default_power_state = NULL;
1444 rdev->pm.current_power_state = NULL;
1445
1446 if (power_info) {
1447 if (frev < 4) {
1448 num_modes = power_info->info.ucNumOfPowerModeEntries;
1449 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1450 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1451 for (i = 0; i < num_modes; i++) {
1452 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1453 switch (frev) {
1454 case 1:
1455 rdev->pm.power_state[state_index].num_clock_modes = 1;
1456 rdev->pm.power_state[state_index].clock_info[0].mclk =
1457 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1458 rdev->pm.power_state[state_index].clock_info[0].sclk =
1459 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1460 /* skip invalid modes */
1461 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1462 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1463 continue;
1464 /* skip overclock modes for now */
1465 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1466 rdev->clock.default_mclk) ||
1467 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1468 rdev->clock.default_sclk))
1469 continue;
1470 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1471 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1472 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1473 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1474 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1475 VOLTAGE_GPIO;
1476 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1477 radeon_lookup_gpio(rdev,
1478 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1479 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1480 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1481 true;
1482 else
1483 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1484 false;
1485 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1486 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1487 VOLTAGE_VDDC;
1488 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1489 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1490 }
0ec0e74f
AD		 1491 /* order matters! */
1492 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1493 rdev->pm.power_state[state_index].type =
1494 POWER_STATE_TYPE_POWERSAVE;
1495 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1496 rdev->pm.power_state[state_index].type =
1497 POWER_STATE_TYPE_BATTERY;
1498 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1499 rdev->pm.power_state[state_index].type =
1500 POWER_STATE_TYPE_BATTERY;
1501 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1502 rdev->pm.power_state[state_index].type =
1503 POWER_STATE_TYPE_BALANCED;
1504 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1505 rdev->pm.power_state[state_index].type =
1506 POWER_STATE_TYPE_PERFORMANCE;
56278a8e 1507 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1508 rdev->pm.power_state[state_index].type =
1509 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1510 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1511 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1512 rdev->pm.power_state[state_index].default_clock_mode =
1513 &rdev->pm.power_state[state_index].clock_info[0];
1514 rdev->pm.power_state[state_index].current_clock_mode =
1515 &rdev->pm.power_state[state_index].clock_info[0];
1516 }
1517 state_index++;
1518 break;
1519 case 2:
1520 rdev->pm.power_state[state_index].num_clock_modes = 1;
1521 rdev->pm.power_state[state_index].clock_info[0].mclk =
1522 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1523 rdev->pm.power_state[state_index].clock_info[0].sclk =
1524 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1525 /* skip invalid modes */
1526 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1527 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1528 continue;
1529 /* skip overclock modes for now */
1530 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1531 rdev->clock.default_mclk) ||
1532 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1533 rdev->clock.default_sclk))
1534 continue;
1535 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1536 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1537 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1538 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1539 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1540 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1541 VOLTAGE_GPIO;
1542 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1543 radeon_lookup_gpio(rdev,
1544 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1545 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1546 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1547 true;
1548 else
1549 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1550 false;
1551 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1552 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1553 VOLTAGE_VDDC;
1554 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1555 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1556 }
0ec0e74f
AD		 1557 /* order matters! */
1558 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1559 rdev->pm.power_state[state_index].type =
1560 POWER_STATE_TYPE_POWERSAVE;
1561 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1562 rdev->pm.power_state[state_index].type =
1563 POWER_STATE_TYPE_BATTERY;
1564 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1565 rdev->pm.power_state[state_index].type =
1566 POWER_STATE_TYPE_BATTERY;
1567 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1568 rdev->pm.power_state[state_index].type =
1569 POWER_STATE_TYPE_BALANCED;
1570 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1571 rdev->pm.power_state[state_index].type =
1572 POWER_STATE_TYPE_PERFORMANCE;
1573 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1574 rdev->pm.power_state[state_index].type =
1575 POWER_STATE_TYPE_BALANCED;
56278a8e 1576 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1577 rdev->pm.power_state[state_index].type =
1578 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1579 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1580 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1581 rdev->pm.power_state[state_index].default_clock_mode =
1582 &rdev->pm.power_state[state_index].clock_info[0];
1583 rdev->pm.power_state[state_index].current_clock_mode =
1584 &rdev->pm.power_state[state_index].clock_info[0];
1585 }
1586 state_index++;
1587 break;
1588 case 3:
1589 rdev->pm.power_state[state_index].num_clock_modes = 1;
1590 rdev->pm.power_state[state_index].clock_info[0].mclk =
1591 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1592 rdev->pm.power_state[state_index].clock_info[0].sclk =
1593 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1594 /* skip invalid modes */
1595 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1596 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1597 continue;
1598 /* skip overclock modes for now */
1599 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1600 rdev->clock.default_mclk) ||
1601 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1602 rdev->clock.default_sclk))
1603 continue;
1604 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1605 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1606 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1607 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1608 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1609 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1610 VOLTAGE_GPIO;
1611 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1612 radeon_lookup_gpio(rdev,
1613 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1614 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1615 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1616 true;
1617 else
1618 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1619 false;
1620 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1621 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1622 VOLTAGE_VDDC;
1623 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1624 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1625 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1626 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1627 true;
1628 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1629 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1630 }
1631 }
0ec0e74f
AD		 1632 /* order matters! */
1633 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1634 rdev->pm.power_state[state_index].type =
1635 POWER_STATE_TYPE_POWERSAVE;
1636 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1637 rdev->pm.power_state[state_index].type =
1638 POWER_STATE_TYPE_BATTERY;
1639 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1640 rdev->pm.power_state[state_index].type =
1641 POWER_STATE_TYPE_BATTERY;
1642 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1643 rdev->pm.power_state[state_index].type =
1644 POWER_STATE_TYPE_BALANCED;
1645 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1646 rdev->pm.power_state[state_index].type =
1647 POWER_STATE_TYPE_PERFORMANCE;
1648 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1649 rdev->pm.power_state[state_index].type =
1650 POWER_STATE_TYPE_BALANCED;
56278a8e 1651 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1652 rdev->pm.power_state[state_index].type =
1653 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1654 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1655 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1656 rdev->pm.power_state[state_index].default_clock_mode =
1657 &rdev->pm.power_state[state_index].clock_info[0];
1658 rdev->pm.power_state[state_index].current_clock_mode =
1659 &rdev->pm.power_state[state_index].clock_info[0];
1660 }
1661 state_index++;
1662 break;
1663 }
1664 }
1665 } else if (frev == 4) {
1666 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1667 mode_index = 0;
1668 power_state = (struct _ATOM_PPLIB_STATE *)
1669 (mode_info->atom_context->bios +
1670 data_offset +
1671 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1672 i * power_info->info_4.ucStateEntrySize);
1673 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1674 (mode_info->atom_context->bios +
1675 data_offset +
1676 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1677 (power_state->ucNonClockStateIndex *
1678 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1679 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1680 if (rdev->flags & RADEON_IS_IGP) {
1681 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1682 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1683 (mode_info->atom_context->bios +
1684 data_offset +
1685 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1686 (power_state->ucClockStateIndices[j] *
1687 power_info->info_4.ucClockInfoSize));
1688 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1689 sclk |= clock_info->ucLowEngineClockHigh << 16;
1690 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1691 /* skip invalid modes */
1692 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1693 continue;
1694 /* skip overclock modes for now */
1695 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1696 rdev->clock.default_sclk)
1697 continue;
1698 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1699 VOLTAGE_SW;
1700 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1701 clock_info->usVDDC;
1702 mode_index++;
1703 } else {
1704 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1705 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1706 (mode_info->atom_context->bios +
1707 data_offset +
1708 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1709 (power_state->ucClockStateIndices[j] *
1710 power_info->info_4.ucClockInfoSize));
1711 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1712 sclk |= clock_info->ucEngineClockHigh << 16;
1713 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1714 mclk |= clock_info->ucMemoryClockHigh << 16;
1715 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1716 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1717 /* skip invalid modes */
1718 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1719 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1720 continue;
1721 /* skip overclock modes for now */
1722 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1723 rdev->clock.default_mclk) ||
1724 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1725 rdev->clock.default_sclk))
1726 continue;
1727 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1728 VOLTAGE_SW;
1729 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1730 clock_info->usVDDC;
1731 mode_index++;
1732 }
1733 }
1734 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1735 if (mode_index) {
845db70d 1736 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 1737 misc2 = le16_to_cpu(non_clock_info->usClassification);
845db70d
RM		 1738 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1739 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1740 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 1741 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1742 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1743 rdev->pm.power_state[state_index].type =
1744 POWER_STATE_TYPE_BATTERY;
1745 break;
1746 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1747 rdev->pm.power_state[state_index].type =
1748 POWER_STATE_TYPE_BALANCED;
1749 break;
1750 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1751 rdev->pm.power_state[state_index].type =
1752 POWER_STATE_TYPE_PERFORMANCE;
1753 break;
1754 }
56278a8e 1755 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 1756 rdev->pm.power_state[state_index].type =
1757 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1758 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1759 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1760 rdev->pm.power_state[state_index].default_clock_mode =
1761 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1762 rdev->pm.power_state[state_index].current_clock_mode =
1763 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1764 }
1765 state_index++;
1766 }
1767 }
1768 }
1769 } else {
1770 /* XXX figure out some good default low power mode for cards w/out power tables */
1771 }
1772
1773 if (rdev->pm.default_power_state == NULL) {
1774 /* add the default mode */
0ec0e74f
AD		 1775 rdev->pm.power_state[state_index].type =
1776 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1777 rdev->pm.power_state[state_index].num_clock_modes = 1;
1778 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1779 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1780 rdev->pm.power_state[state_index].default_clock_mode =
1781 &rdev->pm.power_state[state_index].clock_info[0];
1782 rdev->pm.power_state[state_index].current_clock_mode =
1783 &rdev->pm.power_state[state_index].clock_info[0];
1784 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1785 if (rdev->asic->get_pcie_lanes)
1786 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1787 else
1788 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1789 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1790 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1791 state_index++;
1792 }
1793 rdev->pm.num_power_states = state_index;
1794}
1795
771fe6b9
JG		 1796void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1797{
1798 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1799 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1800
1801 args.ucEnable = enable;
1802
1803 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1804}
1805
7433874e
RM		 1806uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1807{
1808 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1809 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1810
1811 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1812 return args.ulReturnEngineClock;
1813}
1814
1815uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1816{
1817 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1818 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1819
1820 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1821 return args.ulReturnMemoryClock;
1822}
1823
771fe6b9
JG		 1824void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1825 uint32_t eng_clock)
1826{
1827 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1828 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1829
1830 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1831
1832 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1833}
1834
1835void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1836 uint32_t mem_clock)
1837{
1838 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1839 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1840
1841 if (rdev->flags & RADEON_IS_IGP)
1842 return;
1843
1844 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1845
1846 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1847}
1848
1849void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1850{
1851 struct radeon_device *rdev = dev->dev_private;
1852 uint32_t bios_2_scratch, bios_6_scratch;
1853
1854 if (rdev->family >= CHIP_R600) {
4ce001ab 1855 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1856 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1857 } else {
4ce001ab 1858 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1859 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1860 }
1861
1862 /* let the bios control the backlight */
1863 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1864
1865 /* tell the bios not to handle mode switching */
1866 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1867
1868 if (rdev->family >= CHIP_R600) {
1869 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1870 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1871 } else {
1872 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1873 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1874 }
1875
1876}
1877
f657c2a7
YZ		 1878void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1879{
1880 uint32_t scratch_reg;
1881 int i;
1882
1883 if (rdev->family >= CHIP_R600)
1884 scratch_reg = R600_BIOS_0_SCRATCH;
1885 else
1886 scratch_reg = RADEON_BIOS_0_SCRATCH;
1887
1888 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1889 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1890}
1891
1892void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1893{
1894 uint32_t scratch_reg;
1895 int i;
1896
1897 if (rdev->family >= CHIP_R600)
1898 scratch_reg = R600_BIOS_0_SCRATCH;
1899 else
1900 scratch_reg = RADEON_BIOS_0_SCRATCH;
1901
1902 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1903 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1904}
1905
771fe6b9
JG		 1906void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1907{
1908 struct drm_device *dev = encoder->dev;
1909 struct radeon_device *rdev = dev->dev_private;
1910 uint32_t bios_6_scratch;
1911
1912 if (rdev->family >= CHIP_R600)
1913 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1914 else
1915 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1916
1917 if (lock)
1918 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1919 else
1920 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1921
1922 if (rdev->family >= CHIP_R600)
1923 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1924 else
1925 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1926}
1927
1928/* at some point we may want to break this out into individual functions */
1929void
1930radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1931 struct drm_encoder *encoder,
1932 bool connected)
1933{
1934 struct drm_device *dev = connector->dev;
1935 struct radeon_device *rdev = dev->dev_private;
1936 struct radeon_connector *radeon_connector =
1937 to_radeon_connector(connector);
1938 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1939 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1940
1941 if (rdev->family >= CHIP_R600) {
1942 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1943 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1944 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1945 } else {
1946 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1947 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1948 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1949 }
1950
1951 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1952 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1953 if (connected) {
1954 DRM_DEBUG("TV1 connected\n");
1955 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1956 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1957 } else {
1958 DRM_DEBUG("TV1 disconnected\n");
1959 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1960 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1961 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1962 }
1963 }
1964 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1965 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1966 if (connected) {
1967 DRM_DEBUG("CV connected\n");
1968 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1969 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1970 } else {
1971 DRM_DEBUG("CV disconnected\n");
1972 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1973 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1974 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1975 }
1976 }
1977 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1978 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1979 if (connected) {
1980 DRM_DEBUG("LCD1 connected\n");
1981 bios_0_scratch |= ATOM_S0_LCD1;
1982 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1983 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1984 } else {
1985 DRM_DEBUG("LCD1 disconnected\n");
1986 bios_0_scratch &= ~ATOM_S0_LCD1;
1987 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1988 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1989 }
1990 }
1991 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1992 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1993 if (connected) {
1994 DRM_DEBUG("CRT1 connected\n");
1995 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1996 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1997 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1998 } else {
1999 DRM_DEBUG("CRT1 disconnected\n");
2000 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2001 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2002 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2003 }
2004 }
2005 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2006 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2007 if (connected) {
2008 DRM_DEBUG("CRT2 connected\n");
2009 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2010 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2011 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2012 } else {
2013 DRM_DEBUG("CRT2 disconnected\n");
2014 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2015 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2016 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2017 }
2018 }
2019 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2020 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2021 if (connected) {
2022 DRM_DEBUG("DFP1 connected\n");
2023 bios_0_scratch |= ATOM_S0_DFP1;
2024 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2025 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2026 } else {
2027 DRM_DEBUG("DFP1 disconnected\n");
2028 bios_0_scratch &= ~ATOM_S0_DFP1;
2029 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2030 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2031 }
2032 }
2033 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2034 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2035 if (connected) {
2036 DRM_DEBUG("DFP2 connected\n");
2037 bios_0_scratch |= ATOM_S0_DFP2;
2038 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2039 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2040 } else {
2041 DRM_DEBUG("DFP2 disconnected\n");
2042 bios_0_scratch &= ~ATOM_S0_DFP2;
2043 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2044 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2045 }
2046 }
2047 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2048 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2049 if (connected) {
2050 DRM_DEBUG("DFP3 connected\n");
2051 bios_0_scratch |= ATOM_S0_DFP3;
2052 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2053 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2054 } else {
2055 DRM_DEBUG("DFP3 disconnected\n");
2056 bios_0_scratch &= ~ATOM_S0_DFP3;
2057 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2058 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2059 }
2060 }
2061 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2062 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2063 if (connected) {
2064 DRM_DEBUG("DFP4 connected\n");
2065 bios_0_scratch |= ATOM_S0_DFP4;
2066 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2067 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2068 } else {
2069 DRM_DEBUG("DFP4 disconnected\n");
2070 bios_0_scratch &= ~ATOM_S0_DFP4;
2071 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2072 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2073 }
2074 }
2075 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2076 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2077 if (connected) {
2078 DRM_DEBUG("DFP5 connected\n");
2079 bios_0_scratch |= ATOM_S0_DFP5;
2080 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2081 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2082 } else {
2083 DRM_DEBUG("DFP5 disconnected\n");
2084 bios_0_scratch &= ~ATOM_S0_DFP5;
2085 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2086 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2087 }
2088 }
2089
2090 if (rdev->family >= CHIP_R600) {
2091 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2092 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2093 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2094 } else {
2095 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2096 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2097 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2098 }
2099}
2100
2101void
2102radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2103{
2104 struct drm_device *dev = encoder->dev;
2105 struct radeon_device *rdev = dev->dev_private;
2106 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2107 uint32_t bios_3_scratch;
2108
2109 if (rdev->family >= CHIP_R600)
2110 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2111 else
2112 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2113
2114 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2115 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2116 bios_3_scratch |= (crtc << 18);
2117 }
2118 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2119 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2120 bios_3_scratch |= (crtc << 24);
2121 }
2122 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2123 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2124 bios_3_scratch |= (crtc << 16);
2125 }
2126 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2127 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2128 bios_3_scratch |= (crtc << 20);
2129 }
2130 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2131 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2132 bios_3_scratch |= (crtc << 17);
2133 }
2134 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2135 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2136 bios_3_scratch |= (crtc << 19);
2137 }
2138 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2139 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2140 bios_3_scratch |= (crtc << 23);
2141 }
2142 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2143 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2144 bios_3_scratch |= (crtc << 25);
2145 }
2146
2147 if (rdev->family >= CHIP_R600)
2148 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2149 else
2150 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2151}
2152
2153void
2154radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2155{
2156 struct drm_device *dev = encoder->dev;
2157 struct radeon_device *rdev = dev->dev_private;
2158 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2159 uint32_t bios_2_scratch;
2160
2161 if (rdev->family >= CHIP_R600)
2162 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2163 else
2164 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2165
2166 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2167 if (on)
2168 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2169 else
2170 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2171 }
2172 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2173 if (on)
2174 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2175 else
2176 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2177 }
2178 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2179 if (on)
2180 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2181 else
2182 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2183 }
2184 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2185 if (on)
2186 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2187 else
2188 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2189 }
2190 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2191 if (on)
2192 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2193 else
2194 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2195 }
2196 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2197 if (on)
2198 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2199 else
2200 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2201 }
2202 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2203 if (on)
2204 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2205 else
2206 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2207 }
2208 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2209 if (on)
2210 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2211 else
2212 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2213 }
2214 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2215 if (on)
2216 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2217 else
2218 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2219 }
2220 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2221 if (on)
2222 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2223 else
2224 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2225 }
2226
2227 if (rdev->family >= CHIP_R600)
2228 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2229 else
2230 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2231}
Linux kernel - Deliverables
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