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drm/radeon/kms/r7xx: add regs for 40 bit CUR/GRPH addresses
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51/* from radeon_legacy_encoder.c */
52extern void
53radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60};
61
62static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64{
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101}
102
103static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
848577ee 106 struct radeon_i2c_bus_rec *i2c_bus,
705af9c7 107 uint16_t *line_mux)
771fe6b9
JG		 108{
109
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev->pdev->device == 0x791e) &&
112 (dev->pdev->subsystem_vendor == 0x1043) &&
113 (dev->pdev->subsystem_device == 0x826d)) {
114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
116 *connector_type = DRM_MODE_CONNECTOR_DVID;
117 }
118
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev->pdev->device == 0x7941) &&
121 (dev->pdev->subsystem_vendor == 0x147b) &&
122 (dev->pdev->subsystem_device == 0x2412)) {
123 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
124 return false;
125 }
126
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev->pdev->device == 0x5653) &&
129 (dev->pdev->subsystem_vendor == 0x1462) &&
130 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 132 i2c_bus->valid = false;
848577ee
AD		 133 *line_mux = 53;
134 }
771fe6b9
JG		 135 }
136
137 /* Funky macbooks */
138 if ((dev->pdev->device == 0x71C5) &&
139 (dev->pdev->subsystem_vendor == 0x106b) &&
140 (dev->pdev->subsystem_device == 0x0080)) {
141 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
142 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
143 return false;
144 }
145
771fe6b9
JG		 146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
147 if ((dev->pdev->device == 0x9598) &&
148 (dev->pdev->subsystem_vendor == 0x1043) &&
149 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 150 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 151 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 152 }
153 }
154
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev->pdev->device == 0x95C5) &&
157 (dev->pdev->subsystem_vendor == 0x1043) &&
158 (dev->pdev->subsystem_device == 0x01e2)) {
159 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 160 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 161 }
162 }
163
705af9c7
AD		 164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
166 */
167 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
168 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
169 *connector_type = DRM_MODE_CONNECTOR_VGA;
170 *line_mux = 0;
171 }
172 }
173
771fe6b9
JG		 174 return true;
175}
176
177const int supported_devices_connector_convert[] = {
178 DRM_MODE_CONNECTOR_Unknown,
179 DRM_MODE_CONNECTOR_VGA,
180 DRM_MODE_CONNECTOR_DVII,
181 DRM_MODE_CONNECTOR_DVID,
182 DRM_MODE_CONNECTOR_DVIA,
183 DRM_MODE_CONNECTOR_SVIDEO,
184 DRM_MODE_CONNECTOR_Composite,
185 DRM_MODE_CONNECTOR_LVDS,
186 DRM_MODE_CONNECTOR_Unknown,
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_HDMIA,
189 DRM_MODE_CONNECTOR_HDMIB,
190 DRM_MODE_CONNECTOR_Unknown,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_9PinDIN,
193 DRM_MODE_CONNECTOR_DisplayPort
194};
195
196const int object_connector_convert[] = {
197 DRM_MODE_CONNECTOR_Unknown,
198 DRM_MODE_CONNECTOR_DVII,
199 DRM_MODE_CONNECTOR_DVII,
200 DRM_MODE_CONNECTOR_DVID,
201 DRM_MODE_CONNECTOR_DVID,
202 DRM_MODE_CONNECTOR_VGA,
203 DRM_MODE_CONNECTOR_Composite,
204 DRM_MODE_CONNECTOR_SVIDEO,
205 DRM_MODE_CONNECTOR_Unknown,
705af9c7 206 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 207 DRM_MODE_CONNECTOR_9PinDIN,
208 DRM_MODE_CONNECTOR_Unknown,
209 DRM_MODE_CONNECTOR_HDMIA,
210 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 211 DRM_MODE_CONNECTOR_LVDS,
212 DRM_MODE_CONNECTOR_9PinDIN,
213 DRM_MODE_CONNECTOR_Unknown,
214 DRM_MODE_CONNECTOR_Unknown,
215 DRM_MODE_CONNECTOR_Unknown,
216 DRM_MODE_CONNECTOR_DisplayPort
217};
218
219bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
220{
221 struct radeon_device *rdev = dev->dev_private;
222 struct radeon_mode_info *mode_info = &rdev->mode_info;
223 struct atom_context *ctx = mode_info->atom_context;
224 int index = GetIndexIntoMasterTable(DATA, Object_Header);
225 uint16_t size, data_offset;
226 uint8_t frev, crev, line_mux = 0;
227 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
228 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
229 ATOM_OBJECT_HEADER *obj_header;
230 int i, j, path_size, device_support;
231 int connector_type;
705af9c7 232 uint16_t igp_lane_info, conn_id;
771fe6b9
JG		 233 bool linkb;
234 struct radeon_i2c_bus_rec ddc_bus;
235
236 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
237
238 if (data_offset == 0)
239 return false;
240
241 if (crev < 2)
242 return false;
243
244 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
245 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
246 (ctx->bios + data_offset +
247 le16_to_cpu(obj_header->usDisplayPathTableOffset));
248 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
249 (ctx->bios + data_offset +
250 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
251 device_support = le16_to_cpu(obj_header->usDeviceSupport);
252
253 path_size = 0;
254 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
255 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
256 ATOM_DISPLAY_OBJECT_PATH *path;
257 addr += path_size;
258 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
259 path_size += le16_to_cpu(path->usSize);
260 linkb = false;
261
262 if (device_support & le16_to_cpu(path->usDeviceTag)) {
263 uint8_t con_obj_id, con_obj_num, con_obj_type;
264
265 con_obj_id =
266 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
267 >> OBJECT_ID_SHIFT;
268 con_obj_num =
269 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
270 >> ENUM_ID_SHIFT;
271 con_obj_type =
272 (le16_to_cpu(path->usConnObjectId) &
273 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
274
4bbd4973
DA		 275 /* TODO CV support */
276 if (le16_to_cpu(path->usDeviceTag) ==
277 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 278 continue;
279
280 if ((rdev->family == CHIP_RS780) &&
281 (con_obj_id ==
282 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
283 uint16_t igp_offset = 0;
284 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
285
286 index =
287 GetIndexIntoMasterTable(DATA,
288 IntegratedSystemInfo);
289
290 atom_parse_data_header(ctx, index, &size, &frev,
291 &crev, &igp_offset);
292
293 if (crev >= 2) {
294 igp_obj =
295 (ATOM_INTEGRATED_SYSTEM_INFO_V2
296 *) (ctx->bios + igp_offset);
297
298 if (igp_obj) {
299 uint32_t slot_config, ct;
300
301 if (con_obj_num == 1)
302 slot_config =
303 igp_obj->
304 ulDDISlot1Config;
305 else
306 slot_config =
307 igp_obj->
308 ulDDISlot2Config;
309
310 ct = (slot_config >> 16) & 0xff;
311 connector_type =
312 object_connector_convert
313 [ct];
314 igp_lane_info =
315 slot_config & 0xffff;
316 } else
317 continue;
318 } else
319 continue;
320 } else {
321 igp_lane_info = 0;
322 connector_type =
323 object_connector_convert[con_obj_id];
324 }
325
326 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
327 continue;
328
329 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
330 j++) {
331 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
332
333 enc_obj_id =
334 (le16_to_cpu(path->usGraphicObjIds[j]) &
335 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
336 enc_obj_num =
337 (le16_to_cpu(path->usGraphicObjIds[j]) &
338 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
339 enc_obj_type =
340 (le16_to_cpu(path->usGraphicObjIds[j]) &
341 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
342
343 /* FIXME: add support for router objects */
344 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
345 if (enc_obj_num == 2)
346 linkb = true;
347 else
348 linkb = false;
349
350 radeon_add_atom_encoder(dev,
351 enc_obj_id,
352 le16_to_cpu
353 (path->
354 usDeviceTag));
355
356 }
357 }
358
359 /* look up gpio for ddc */
360 if ((le16_to_cpu(path->usDeviceTag) &
361 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
362 == 0) {
363 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
364 if (le16_to_cpu(path->usConnObjectId) ==
365 le16_to_cpu(con_obj->asObjects[j].
366 usObjectID)) {
367 ATOM_COMMON_RECORD_HEADER
368 *record =
369 (ATOM_COMMON_RECORD_HEADER
370 *)
371 (ctx->bios + data_offset +
372 le16_to_cpu(con_obj->
373 asObjects[j].
374 usRecordOffset));
375 ATOM_I2C_RECORD *i2c_record;
376
377 while (record->ucRecordType > 0
378 && record->
379 ucRecordType <=
380 ATOM_MAX_OBJECT_RECORD_NUMBER) {
771fe6b9
JG		 381 switch (record->
382 ucRecordType) {
383 case ATOM_I2C_RECORD_TYPE:
384 i2c_record =
385 (ATOM_I2C_RECORD
386 *) record;
387 line_mux =
388 i2c_record->
389 sucI2cId.
390 bfI2C_LineMux;
391 break;
392 }
393 record =
394 (ATOM_COMMON_RECORD_HEADER
395 *) ((char *)record
396 +
397 record->
398 ucRecordSize);
399 }
400 break;
401 }
402 }
403 } else
404 line_mux = 0;
405
406 if ((le16_to_cpu(path->usDeviceTag) ==
407 ATOM_DEVICE_TV1_SUPPORT)
408 || (le16_to_cpu(path->usDeviceTag) ==
409 ATOM_DEVICE_TV2_SUPPORT)
410 || (le16_to_cpu(path->usDeviceTag) ==
411 ATOM_DEVICE_CV_SUPPORT))
412 ddc_bus.valid = false;
413 else
414 ddc_bus = radeon_lookup_gpio(dev, line_mux);
415
705af9c7
AD		 416 conn_id = le16_to_cpu(path->usConnObjectId);
417
418 if (!radeon_atom_apply_quirks
419 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
420 &ddc_bus, &conn_id))
421 continue;
422
771fe6b9 423 radeon_add_atom_connector(dev,
705af9c7 424 conn_id,
771fe6b9
JG		 425 le16_to_cpu(path->
426 usDeviceTag),
427 connector_type, &ddc_bus,
428 linkb, igp_lane_info);
429
430 }
431 }
432
433 radeon_link_encoder_connector(dev);
434
435 return true;
436}
437
438struct bios_connector {
439 bool valid;
705af9c7 440 uint16_t line_mux;
771fe6b9
JG		 441 uint16_t devices;
442 int connector_type;
443 struct radeon_i2c_bus_rec ddc_bus;
444};
445
446bool radeon_get_atom_connector_info_from_supported_devices_table(struct
447 drm_device
448 *dev)
449{
450 struct radeon_device *rdev = dev->dev_private;
451 struct radeon_mode_info *mode_info = &rdev->mode_info;
452 struct atom_context *ctx = mode_info->atom_context;
453 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
454 uint16_t size, data_offset;
455 uint8_t frev, crev;
456 uint16_t device_support;
457 uint8_t dac;
458 union atom_supported_devices *supported_devices;
459 int i, j;
460 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
461
462 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
463
464 supported_devices =
465 (union atom_supported_devices *)(ctx->bios + data_offset);
466
467 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
468
469 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
470 ATOM_CONNECTOR_INFO_I2C ci =
471 supported_devices->info.asConnInfo[i];
472
473 bios_connectors[i].valid = false;
474
475 if (!(device_support & (1 << i))) {
476 continue;
477 }
478
479 if (i == ATOM_DEVICE_CV_INDEX) {
480 DRM_DEBUG("Skipping Component Video\n");
481 continue;
482 }
483
771fe6b9
JG		 484 bios_connectors[i].connector_type =
485 supported_devices_connector_convert[ci.sucConnectorInfo.
486 sbfAccess.
487 bfConnectorType];
488
489 if (bios_connectors[i].connector_type ==
490 DRM_MODE_CONNECTOR_Unknown)
491 continue;
492
493 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
494
495 if ((rdev->family == CHIP_RS690) ||
496 (rdev->family == CHIP_RS740)) {
497 if ((i == ATOM_DEVICE_DFP2_INDEX)
498 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
499 bios_connectors[i].line_mux =
500 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
501 else if ((i == ATOM_DEVICE_DFP3_INDEX)
502 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
503 bios_connectors[i].line_mux =
504 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
505 else
506 bios_connectors[i].line_mux =
507 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
508 } else
509 bios_connectors[i].line_mux =
510 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
511
512 /* give tv unique connector ids */
513 if (i == ATOM_DEVICE_TV1_INDEX) {
514 bios_connectors[i].ddc_bus.valid = false;
515 bios_connectors[i].line_mux = 50;
516 } else if (i == ATOM_DEVICE_TV2_INDEX) {
517 bios_connectors[i].ddc_bus.valid = false;
518 bios_connectors[i].line_mux = 51;
519 } else if (i == ATOM_DEVICE_CV_INDEX) {
520 bios_connectors[i].ddc_bus.valid = false;
521 bios_connectors[i].line_mux = 52;
522 } else
523 bios_connectors[i].ddc_bus =
524 radeon_lookup_gpio(dev,
525 bios_connectors[i].line_mux);
526
527 /* Always set the connector type to VGA for CRT1/CRT2. if they are
528 * shared with a DVI port, we'll pick up the DVI connector when we
529 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
530 */
531 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
532 bios_connectors[i].connector_type =
533 DRM_MODE_CONNECTOR_VGA;
534
535 if (!radeon_atom_apply_quirks
536 (dev, (1 << i), &bios_connectors[i].connector_type,
848577ee 537 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
771fe6b9
JG		 538 continue;
539
540 bios_connectors[i].valid = true;
541 bios_connectors[i].devices = (1 << i);
542
543 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
544 radeon_add_atom_encoder(dev,
545 radeon_get_encoder_id(dev,
546 (1 << i),
547 dac),
548 (1 << i));
549 else
550 radeon_add_legacy_encoder(dev,
551 radeon_get_encoder_id(dev,
552 (1 <<
553 i),
554 dac),
555 (1 << i));
556 }
557
558 /* combine shared connectors */
559 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
560 if (bios_connectors[i].valid) {
561 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
562 if (bios_connectors[j].valid && (i != j)) {
563 if (bios_connectors[i].line_mux ==
564 bios_connectors[j].line_mux) {
565 if (((bios_connectors[i].
566 devices &
567 (ATOM_DEVICE_DFP_SUPPORT))
568 && (bios_connectors[j].
569 devices &
570 (ATOM_DEVICE_CRT_SUPPORT)))
571 ||
572 ((bios_connectors[j].
573 devices &
574 (ATOM_DEVICE_DFP_SUPPORT))
575 && (bios_connectors[i].
576 devices &
577 (ATOM_DEVICE_CRT_SUPPORT)))) {
578 bios_connectors[i].
579 devices |=
580 bios_connectors[j].
581 devices;
582 bios_connectors[i].
583 connector_type =
584 DRM_MODE_CONNECTOR_DVII;
585 bios_connectors[j].
586 valid = false;
587 }
588 }
589 }
590 }
591 }
592 }
593
594 /* add the connectors */
595 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
596 if (bios_connectors[i].valid)
597 radeon_add_atom_connector(dev,
598 bios_connectors[i].line_mux,
599 bios_connectors[i].devices,
600 bios_connectors[i].
601 connector_type,
602 &bios_connectors[i].ddc_bus,
603 false, 0);
604 }
605
606 radeon_link_encoder_connector(dev);
607
608 return true;
609}
610
611union firmware_info {
612 ATOM_FIRMWARE_INFO info;
613 ATOM_FIRMWARE_INFO_V1_2 info_12;
614 ATOM_FIRMWARE_INFO_V1_3 info_13;
615 ATOM_FIRMWARE_INFO_V1_4 info_14;
616};
617
618bool radeon_atom_get_clock_info(struct drm_device *dev)
619{
620 struct radeon_device *rdev = dev->dev_private;
621 struct radeon_mode_info *mode_info = &rdev->mode_info;
622 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
623 union firmware_info *firmware_info;
624 uint8_t frev, crev;
625 struct radeon_pll *p1pll = &rdev->clock.p1pll;
626 struct radeon_pll *p2pll = &rdev->clock.p2pll;
627 struct radeon_pll *spll = &rdev->clock.spll;
628 struct radeon_pll *mpll = &rdev->clock.mpll;
629 uint16_t data_offset;
630
631 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
632 &crev, &data_offset);
633
634 firmware_info =
635 (union firmware_info *)(mode_info->atom_context->bios +
636 data_offset);
637
638 if (firmware_info) {
639 /* pixel clocks */
640 p1pll->reference_freq =
641 le16_to_cpu(firmware_info->info.usReferenceClock);
642 p1pll->reference_div = 0;
643
bc293e58
MF		 644 if (crev < 2)
645 p1pll->pll_out_min =
646 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
647 else
648 p1pll->pll_out_min =
649 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 650 p1pll->pll_out_max =
651 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
652
653 if (p1pll->pll_out_min == 0) {
654 if (ASIC_IS_AVIVO(rdev))
655 p1pll->pll_out_min = 64800;
656 else
657 p1pll->pll_out_min = 20000;
658 }
659
660 p1pll->pll_in_min =
661 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
662 p1pll->pll_in_max =
663 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
664
665 *p2pll = *p1pll;
666
667 /* system clock */
668 spll->reference_freq =
669 le16_to_cpu(firmware_info->info.usReferenceClock);
670 spll->reference_div = 0;
671
672 spll->pll_out_min =
673 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
674 spll->pll_out_max =
675 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
676
677 /* ??? */
678 if (spll->pll_out_min == 0) {
679 if (ASIC_IS_AVIVO(rdev))
680 spll->pll_out_min = 64800;
681 else
682 spll->pll_out_min = 20000;
683 }
684
685 spll->pll_in_min =
686 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
687 spll->pll_in_max =
688 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
689
690 /* memory clock */
691 mpll->reference_freq =
692 le16_to_cpu(firmware_info->info.usReferenceClock);
693 mpll->reference_div = 0;
694
695 mpll->pll_out_min =
696 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
697 mpll->pll_out_max =
698 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
699
700 /* ??? */
701 if (mpll->pll_out_min == 0) {
702 if (ASIC_IS_AVIVO(rdev))
703 mpll->pll_out_min = 64800;
704 else
705 mpll->pll_out_min = 20000;
706 }
707
708 mpll->pll_in_min =
709 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
710 mpll->pll_in_max =
711 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
712
713 rdev->clock.default_sclk =
714 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
715 rdev->clock.default_mclk =
716 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
717
718 return true;
719 }
720 return false;
721}
722
445282db
DA		 723bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
724 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 725{
726 struct drm_device *dev = encoder->base.dev;
727 struct radeon_device *rdev = dev->dev_private;
728 struct radeon_mode_info *mode_info = &rdev->mode_info;
729 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
730 uint16_t data_offset;
731 struct _ATOM_TMDS_INFO *tmds_info;
732 uint8_t frev, crev;
733 uint16_t maxfreq;
734 int i;
771fe6b9
JG		 735
736 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
737 &crev, &data_offset);
738
739 tmds_info =
740 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
741 data_offset);
742
743 if (tmds_info) {
771fe6b9
JG		 744 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
745 for (i = 0; i < 4; i++) {
746 tmds->tmds_pll[i].freq =
747 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
748 tmds->tmds_pll[i].value =
749 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
750 tmds->tmds_pll[i].value |=
751 (tmds_info->asMiscInfo[i].
752 ucPLL_VCO_Gain & 0x3f) << 6;
753 tmds->tmds_pll[i].value |=
754 (tmds_info->asMiscInfo[i].
755 ucPLL_DutyCycle & 0xf) << 12;
756 tmds->tmds_pll[i].value |=
757 (tmds_info->asMiscInfo[i].
758 ucPLL_VoltageSwing & 0xf) << 16;
759
760 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
761 tmds->tmds_pll[i].freq,
762 tmds->tmds_pll[i].value);
763
764 if (maxfreq == tmds->tmds_pll[i].freq) {
765 tmds->tmds_pll[i].freq = 0xffffffff;
766 break;
767 }
768 }
445282db 769 return true;
771fe6b9 770 }
445282db 771 return false;
771fe6b9
JG		 772}
773
774union lvds_info {
775 struct _ATOM_LVDS_INFO info;
776 struct _ATOM_LVDS_INFO_V12 info_12;
777};
778
779struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
780 radeon_encoder
781 *encoder)
782{
783 struct drm_device *dev = encoder->base.dev;
784 struct radeon_device *rdev = dev->dev_private;
785 struct radeon_mode_info *mode_info = &rdev->mode_info;
786 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
787 uint16_t data_offset;
788 union lvds_info *lvds_info;
789 uint8_t frev, crev;
790 struct radeon_encoder_atom_dig *lvds = NULL;
791
792 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
793 &crev, &data_offset);
794
795 lvds_info =
796 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
797
798 if (lvds_info) {
799 lvds =
800 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
801
802 if (!lvds)
803 return NULL;
804
de2103e4 805 lvds->native_mode.clock =
771fe6b9 806 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 807 lvds->native_mode.hdisplay =
771fe6b9 808 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 809 lvds->native_mode.vdisplay =
771fe6b9 810 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 811 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
812 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
813 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
814 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
815 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
816 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
817 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
818 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
819 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
820 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
821 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
822 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 823 lvds->panel_pwr_delay =
824 le16_to_cpu(lvds_info->info.usOffDelayInMs);
825 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
de2103e4
AD		 826 /* set crtc values */
827 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9
JG		 828
829 encoder->native_mode = lvds->native_mode;
830 }
831 return lvds;
832}
833
6fe7ac3f
AD		 834struct radeon_encoder_primary_dac *
835radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
836{
837 struct drm_device *dev = encoder->base.dev;
838 struct radeon_device *rdev = dev->dev_private;
839 struct radeon_mode_info *mode_info = &rdev->mode_info;
840 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
841 uint16_t data_offset;
842 struct _COMPASSIONATE_DATA *dac_info;
843 uint8_t frev, crev;
844 uint8_t bg, dac;
6fe7ac3f
AD		 845 struct radeon_encoder_primary_dac *p_dac = NULL;
846
847 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
848
849 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
850
851 if (dac_info) {
852 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
853
854 if (!p_dac)
855 return NULL;
856
857 bg = dac_info->ucDAC1_BG_Adjustment;
858 dac = dac_info->ucDAC1_DAC_Adjustment;
859 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
860
861 }
862 return p_dac;
863}
864
4ce001ab 865bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 866 struct drm_display_mode *mode)
4ce001ab
DA		 867{
868 struct radeon_mode_info *mode_info = &rdev->mode_info;
869 ATOM_ANALOG_TV_INFO *tv_info;
870 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
871 ATOM_DTD_FORMAT *dtd_timings;
872 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
873 u8 frev, crev;
5a9bcacc 874 u16 data_offset, misc;
4ce001ab
DA		 875
876 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
877
878 switch (crev) {
879 case 1:
880 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
881 if (index > MAX_SUPPORTED_TV_TIMING)
882 return false;
883
5a9bcacc
AD		 884 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
885 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
886 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
887 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
888 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
889
890 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
891 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
892 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
893 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
894 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
895
896 mode->flags = 0;
897 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
898 if (misc & ATOM_VSYNC_POLARITY)
899 mode->flags |= DRM_MODE_FLAG_NVSYNC;
900 if (misc & ATOM_HSYNC_POLARITY)
901 mode->flags |= DRM_MODE_FLAG_NHSYNC;
902 if (misc & ATOM_COMPOSITESYNC)
903 mode->flags |= DRM_MODE_FLAG_CSYNC;
904 if (misc & ATOM_INTERLACE)
905 mode->flags |= DRM_MODE_FLAG_INTERLACE;
906 if (misc & ATOM_DOUBLE_CLOCK_MODE)
907 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
908
909 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 910
911 if (index == 1) {
912 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 913 mode->crtc_htotal -= 1;
914 mode->crtc_vtotal -= 1;
4ce001ab
DA		 915 }
916 break;
917 case 2:
918 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
919 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
920 return false;
921
922 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 923 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
924 le16_to_cpu(dtd_timings->usHBlanking_Time);
925 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
926 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
927 le16_to_cpu(dtd_timings->usHSyncOffset);
928 mode->crtc_hsync_end = mode->crtc_hsync_start +
929 le16_to_cpu(dtd_timings->usHSyncWidth);
930
931 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
932 le16_to_cpu(dtd_timings->usVBlanking_Time);
933 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
934 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
935 le16_to_cpu(dtd_timings->usVSyncOffset);
936 mode->crtc_vsync_end = mode->crtc_vsync_start +
937 le16_to_cpu(dtd_timings->usVSyncWidth);
938
939 mode->flags = 0;
940 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
941 if (misc & ATOM_VSYNC_POLARITY)
942 mode->flags |= DRM_MODE_FLAG_NVSYNC;
943 if (misc & ATOM_HSYNC_POLARITY)
944 mode->flags |= DRM_MODE_FLAG_NHSYNC;
945 if (misc & ATOM_COMPOSITESYNC)
946 mode->flags |= DRM_MODE_FLAG_CSYNC;
947 if (misc & ATOM_INTERLACE)
948 mode->flags |= DRM_MODE_FLAG_INTERLACE;
949 if (misc & ATOM_DOUBLE_CLOCK_MODE)
950 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
951
952 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 953 break;
954 }
955 return true;
956}
957
6fe7ac3f
AD		 958struct radeon_encoder_tv_dac *
959radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
960{
961 struct drm_device *dev = encoder->base.dev;
962 struct radeon_device *rdev = dev->dev_private;
963 struct radeon_mode_info *mode_info = &rdev->mode_info;
964 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
965 uint16_t data_offset;
966 struct _COMPASSIONATE_DATA *dac_info;
967 uint8_t frev, crev;
968 uint8_t bg, dac;
6fe7ac3f
AD		 969 struct radeon_encoder_tv_dac *tv_dac = NULL;
970
971 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
972
973 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
974
975 if (dac_info) {
976 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
977
978 if (!tv_dac)
979 return NULL;
980
981 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
982 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
983 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
984
985 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
986 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
987 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
988
989 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
990 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
991 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
992
993 }
994 return tv_dac;
995}
996
771fe6b9
JG		 997void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
998{
999 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1000 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1001
1002 args.ucEnable = enable;
1003
1004 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1005}
1006
1007void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1008{
1009 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1010 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1011
1012 args.ucEnable = enable;
1013
1014 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1015}
1016
1017void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1018 uint32_t eng_clock)
1019{
1020 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1021 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1022
1023 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1024
1025 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1026}
1027
1028void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1029 uint32_t mem_clock)
1030{
1031 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1032 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1033
1034 if (rdev->flags & RADEON_IS_IGP)
1035 return;
1036
1037 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1038
1039 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1040}
1041
1042void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1043{
1044 struct radeon_device *rdev = dev->dev_private;
1045 uint32_t bios_2_scratch, bios_6_scratch;
1046
1047 if (rdev->family >= CHIP_R600) {
4ce001ab 1048 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1049 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1050 } else {
4ce001ab 1051 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1052 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1053 }
1054
1055 /* let the bios control the backlight */
1056 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1057
1058 /* tell the bios not to handle mode switching */
1059 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1060
1061 if (rdev->family >= CHIP_R600) {
1062 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1063 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1064 } else {
1065 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1066 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1067 }
1068
1069}
1070
f657c2a7
YZ		 1071void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1072{
1073 uint32_t scratch_reg;
1074 int i;
1075
1076 if (rdev->family >= CHIP_R600)
1077 scratch_reg = R600_BIOS_0_SCRATCH;
1078 else
1079 scratch_reg = RADEON_BIOS_0_SCRATCH;
1080
1081 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1082 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1083}
1084
1085void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1086{
1087 uint32_t scratch_reg;
1088 int i;
1089
1090 if (rdev->family >= CHIP_R600)
1091 scratch_reg = R600_BIOS_0_SCRATCH;
1092 else
1093 scratch_reg = RADEON_BIOS_0_SCRATCH;
1094
1095 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1096 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1097}
1098
771fe6b9
JG		 1099void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1100{
1101 struct drm_device *dev = encoder->dev;
1102 struct radeon_device *rdev = dev->dev_private;
1103 uint32_t bios_6_scratch;
1104
1105 if (rdev->family >= CHIP_R600)
1106 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1107 else
1108 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1109
1110 if (lock)
1111 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1112 else
1113 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1114
1115 if (rdev->family >= CHIP_R600)
1116 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1117 else
1118 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1119}
1120
1121/* at some point we may want to break this out into individual functions */
1122void
1123radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1124 struct drm_encoder *encoder,
1125 bool connected)
1126{
1127 struct drm_device *dev = connector->dev;
1128 struct radeon_device *rdev = dev->dev_private;
1129 struct radeon_connector *radeon_connector =
1130 to_radeon_connector(connector);
1131 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1132 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1133
1134 if (rdev->family >= CHIP_R600) {
1135 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1136 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1137 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1138 } else {
1139 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1140 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1141 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1142 }
1143
1144 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1145 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1146 if (connected) {
1147 DRM_DEBUG("TV1 connected\n");
1148 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1149 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1150 } else {
1151 DRM_DEBUG("TV1 disconnected\n");
1152 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1153 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1154 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1155 }
1156 }
1157 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1158 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1159 if (connected) {
1160 DRM_DEBUG("CV connected\n");
1161 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1162 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1163 } else {
1164 DRM_DEBUG("CV disconnected\n");
1165 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1166 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1167 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1168 }
1169 }
1170 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1171 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1172 if (connected) {
1173 DRM_DEBUG("LCD1 connected\n");
1174 bios_0_scratch |= ATOM_S0_LCD1;
1175 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1176 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1177 } else {
1178 DRM_DEBUG("LCD1 disconnected\n");
1179 bios_0_scratch &= ~ATOM_S0_LCD1;
1180 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1181 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1182 }
1183 }
1184 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1185 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1186 if (connected) {
1187 DRM_DEBUG("CRT1 connected\n");
1188 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1189 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1190 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1191 } else {
1192 DRM_DEBUG("CRT1 disconnected\n");
1193 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1194 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1195 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1196 }
1197 }
1198 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1199 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1200 if (connected) {
1201 DRM_DEBUG("CRT2 connected\n");
1202 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1203 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1204 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1205 } else {
1206 DRM_DEBUG("CRT2 disconnected\n");
1207 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1208 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1209 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1210 }
1211 }
1212 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1213 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1214 if (connected) {
1215 DRM_DEBUG("DFP1 connected\n");
1216 bios_0_scratch |= ATOM_S0_DFP1;
1217 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1218 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1219 } else {
1220 DRM_DEBUG("DFP1 disconnected\n");
1221 bios_0_scratch &= ~ATOM_S0_DFP1;
1222 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1223 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1224 }
1225 }
1226 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1227 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1228 if (connected) {
1229 DRM_DEBUG("DFP2 connected\n");
1230 bios_0_scratch |= ATOM_S0_DFP2;
1231 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1232 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1233 } else {
1234 DRM_DEBUG("DFP2 disconnected\n");
1235 bios_0_scratch &= ~ATOM_S0_DFP2;
1236 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1237 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1238 }
1239 }
1240 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1241 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1242 if (connected) {
1243 DRM_DEBUG("DFP3 connected\n");
1244 bios_0_scratch |= ATOM_S0_DFP3;
1245 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1246 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1247 } else {
1248 DRM_DEBUG("DFP3 disconnected\n");
1249 bios_0_scratch &= ~ATOM_S0_DFP3;
1250 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1251 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1252 }
1253 }
1254 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1255 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1256 if (connected) {
1257 DRM_DEBUG("DFP4 connected\n");
1258 bios_0_scratch |= ATOM_S0_DFP4;
1259 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1260 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1261 } else {
1262 DRM_DEBUG("DFP4 disconnected\n");
1263 bios_0_scratch &= ~ATOM_S0_DFP4;
1264 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1265 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1266 }
1267 }
1268 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1269 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1270 if (connected) {
1271 DRM_DEBUG("DFP5 connected\n");
1272 bios_0_scratch |= ATOM_S0_DFP5;
1273 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1274 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1275 } else {
1276 DRM_DEBUG("DFP5 disconnected\n");
1277 bios_0_scratch &= ~ATOM_S0_DFP5;
1278 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1279 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1280 }
1281 }
1282
1283 if (rdev->family >= CHIP_R600) {
1284 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1285 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1286 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1287 } else {
1288 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1289 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1290 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1291 }
1292}
1293
1294void
1295radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1296{
1297 struct drm_device *dev = encoder->dev;
1298 struct radeon_device *rdev = dev->dev_private;
1299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1300 uint32_t bios_3_scratch;
1301
1302 if (rdev->family >= CHIP_R600)
1303 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1304 else
1305 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1306
1307 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1308 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1309 bios_3_scratch |= (crtc << 18);
1310 }
1311 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1312 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1313 bios_3_scratch |= (crtc << 24);
1314 }
1315 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1316 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1317 bios_3_scratch |= (crtc << 16);
1318 }
1319 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1320 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1321 bios_3_scratch |= (crtc << 20);
1322 }
1323 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1324 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1325 bios_3_scratch |= (crtc << 17);
1326 }
1327 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1328 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1329 bios_3_scratch |= (crtc << 19);
1330 }
1331 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1332 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1333 bios_3_scratch |= (crtc << 23);
1334 }
1335 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1336 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1337 bios_3_scratch |= (crtc << 25);
1338 }
1339
1340 if (rdev->family >= CHIP_R600)
1341 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1342 else
1343 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1344}
1345
1346void
1347radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1348{
1349 struct drm_device *dev = encoder->dev;
1350 struct radeon_device *rdev = dev->dev_private;
1351 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1352 uint32_t bios_2_scratch;
1353
1354 if (rdev->family >= CHIP_R600)
1355 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1356 else
1357 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1358
1359 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1360 if (on)
1361 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1362 else
1363 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1364 }
1365 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1366 if (on)
1367 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1368 else
1369 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1370 }
1371 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1372 if (on)
1373 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1374 else
1375 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1376 }
1377 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1378 if (on)
1379 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1380 else
1381 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1382 }
1383 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1384 if (on)
1385 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1386 else
1387 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1388 }
1389 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1390 if (on)
1391 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1392 else
1393 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1394 }
1395 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1396 if (on)
1397 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1398 else
1399 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1400 }
1401 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1402 if (on)
1403 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1404 else
1405 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1406 }
1407 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1408 if (on)
1409 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1410 else
1411 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1412 }
1413 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1414 if (on)
1415 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1416 else
1417 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1418 }
1419
1420 if (rdev->family >= CHIP_R600)
1421 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1422 else
1423 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1424}
Linux kernel - Deliverables
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