Commit | Line | Data |
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bfc1f97d SG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Slava Grigorev <slava.grigorev@amd.com> | |
23 | */ | |
24 | ||
64424d6e | 25 | #include <linux/gcd.h> |
bfc1f97d | 26 | #include <drm/drmP.h> |
1a626b68 | 27 | #include <drm/drm_crtc.h> |
bfc1f97d | 28 | #include "radeon.h" |
1a626b68 SG |
29 | #include "atom.h" |
30 | #include "radeon_audio.h" | |
bfc1f97d SG |
31 | |
32 | void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, | |
33 | u8 enable_mask); | |
8bf59820 SG |
34 | void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
35 | u8 enable_mask); | |
bfc1f97d SG |
36 | void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
37 | u8 enable_mask); | |
1a626b68 SG |
38 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg); |
39 | void dce6_endpoint_wreg(struct radeon_device *rdev, | |
40 | u32 offset, u32 reg, u32 v); | |
070a2e63 AD |
41 | void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, |
42 | struct cea_sad *sads, int sad_count); | |
43 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, | |
44 | struct cea_sad *sads, int sad_count); | |
45 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, | |
46 | struct cea_sad *sads, int sad_count); | |
00a9d4bc SG |
47 | void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
48 | u8 *sadb, int sad_count); | |
49 | void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
50 | u8 *sadb, int sad_count); | |
51 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, | |
52 | u8 *sadb, int sad_count); | |
53 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
54 | u8 *sadb, int sad_count); | |
55 | void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, | |
56 | u8 *sadb, int sad_count); | |
57 | void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
58 | u8 *sadb, int sad_count); | |
87654f87 SG |
59 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
60 | struct drm_connector *connector, struct drm_display_mode *mode); | |
61 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, | |
62 | struct drm_connector *connector, struct drm_display_mode *mode); | |
3cdde027 SG |
63 | struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev); |
64 | struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev); | |
88252d77 | 65 | void dce6_afmt_select_pin(struct drm_encoder *encoder); |
a85d682a SG |
66 | void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
67 | struct radeon_crtc *crtc, unsigned int clock); | |
68 | void dce3_2_audio_set_dto(struct radeon_device *rdev, | |
69 | struct radeon_crtc *crtc, unsigned int clock); | |
70 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, | |
71 | struct radeon_crtc *crtc, unsigned int clock); | |
72 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, | |
73 | struct radeon_crtc *crtc, unsigned int clock); | |
74 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, | |
75 | struct radeon_crtc *crtc, unsigned int clock); | |
76 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, | |
77 | struct radeon_crtc *crtc, unsigned int clock); | |
baa7d8e4 | 78 | void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, |
96ea7afb | 79 | unsigned char *buffer, size_t size); |
baa7d8e4 | 80 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
96ea7afb | 81 | unsigned char *buffer, size_t size); |
64424d6e SG |
82 | void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
83 | const struct radeon_hdmi_acr *acr); | |
84 | void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, | |
85 | const struct radeon_hdmi_acr *acr); | |
86 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, | |
87 | const struct radeon_hdmi_acr *acr); | |
930a9785 AD |
88 | void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset); |
89 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset); | |
be273e58 SG |
90 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, |
91 | u32 offset, int bpc); | |
1852c9a0 SG |
92 | void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset); |
93 | void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset); | |
94 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset); | |
bfc1f97d SG |
95 | |
96 | static const u32 pin_offsets[7] = | |
97 | { | |
98 | (0x5e00 - 0x5e00), | |
99 | (0x5e18 - 0x5e00), | |
100 | (0x5e30 - 0x5e00), | |
101 | (0x5e48 - 0x5e00), | |
102 | (0x5e60 - 0x5e00), | |
103 | (0x5e78 - 0x5e00), | |
104 | (0x5e90 - 0x5e00), | |
105 | }; | |
106 | ||
1a626b68 SG |
107 | static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg) |
108 | { | |
109 | return RREG32(reg); | |
110 | } | |
111 | ||
112 | static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset, | |
113 | u32 reg, u32 v) | |
114 | { | |
115 | WREG32(reg, v); | |
116 | } | |
117 | ||
a85d682a SG |
118 | static struct radeon_audio_basic_funcs r600_funcs = { |
119 | .endpoint_rreg = radeon_audio_rreg, | |
120 | .endpoint_wreg = radeon_audio_wreg, | |
121 | .enable = r600_audio_enable, | |
122 | }; | |
123 | ||
1a626b68 SG |
124 | static struct radeon_audio_basic_funcs dce32_funcs = { |
125 | .endpoint_rreg = radeon_audio_rreg, | |
126 | .endpoint_wreg = radeon_audio_wreg, | |
8bf59820 | 127 | .enable = r600_audio_enable, |
1a626b68 SG |
128 | }; |
129 | ||
130 | static struct radeon_audio_basic_funcs dce4_funcs = { | |
131 | .endpoint_rreg = radeon_audio_rreg, | |
132 | .endpoint_wreg = radeon_audio_wreg, | |
8bf59820 | 133 | .enable = dce4_audio_enable, |
1a626b68 SG |
134 | }; |
135 | ||
136 | static struct radeon_audio_basic_funcs dce6_funcs = { | |
137 | .endpoint_rreg = dce6_endpoint_rreg, | |
138 | .endpoint_wreg = dce6_endpoint_wreg, | |
8bf59820 | 139 | .enable = dce6_audio_enable, |
1a626b68 SG |
140 | }; |
141 | ||
a85d682a SG |
142 | static struct radeon_audio_funcs r600_hdmi_funcs = { |
143 | .get_pin = r600_audio_get_pin, | |
144 | .set_dto = r600_hdmi_audio_set_dto, | |
64424d6e | 145 | .update_acr = r600_hdmi_update_acr, |
930a9785 | 146 | .set_vbi_packet = r600_set_vbi_packet, |
baa7d8e4 | 147 | .set_avi_packet = r600_set_avi_packet, |
1852c9a0 | 148 | .set_audio_packet = r600_set_audio_packet, |
a85d682a SG |
149 | }; |
150 | ||
070a2e63 | 151 | static struct radeon_audio_funcs dce32_hdmi_funcs = { |
3cdde027 | 152 | .get_pin = r600_audio_get_pin, |
070a2e63 | 153 | .write_sad_regs = dce3_2_afmt_write_sad_regs, |
00a9d4bc | 154 | .write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation, |
a85d682a | 155 | .set_dto = dce3_2_audio_set_dto, |
64424d6e | 156 | .update_acr = dce3_2_hdmi_update_acr, |
930a9785 | 157 | .set_vbi_packet = r600_set_vbi_packet, |
baa7d8e4 | 158 | .set_avi_packet = r600_set_avi_packet, |
1852c9a0 | 159 | .set_audio_packet = dce3_2_set_audio_packet, |
070a2e63 AD |
160 | }; |
161 | ||
162 | static struct radeon_audio_funcs dce32_dp_funcs = { | |
3cdde027 | 163 | .get_pin = r600_audio_get_pin, |
070a2e63 | 164 | .write_sad_regs = dce3_2_afmt_write_sad_regs, |
00a9d4bc | 165 | .write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation, |
a85d682a | 166 | .set_dto = dce3_2_audio_set_dto, |
baa7d8e4 | 167 | .set_avi_packet = r600_set_avi_packet, |
070a2e63 AD |
168 | }; |
169 | ||
170 | static struct radeon_audio_funcs dce4_hdmi_funcs = { | |
3cdde027 | 171 | .get_pin = r600_audio_get_pin, |
070a2e63 | 172 | .write_sad_regs = evergreen_hdmi_write_sad_regs, |
00a9d4bc | 173 | .write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation, |
87654f87 | 174 | .write_latency_fields = dce4_afmt_write_latency_fields, |
a85d682a | 175 | .set_dto = dce4_hdmi_audio_set_dto, |
64424d6e | 176 | .update_acr = evergreen_hdmi_update_acr, |
930a9785 | 177 | .set_vbi_packet = dce4_set_vbi_packet, |
be273e58 | 178 | .set_color_depth = dce4_hdmi_set_color_depth, |
baa7d8e4 | 179 | .set_avi_packet = evergreen_set_avi_packet, |
1852c9a0 | 180 | .set_audio_packet = dce4_set_audio_packet, |
070a2e63 AD |
181 | }; |
182 | ||
183 | static struct radeon_audio_funcs dce4_dp_funcs = { | |
3cdde027 | 184 | .get_pin = r600_audio_get_pin, |
070a2e63 | 185 | .write_sad_regs = evergreen_hdmi_write_sad_regs, |
00a9d4bc | 186 | .write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation, |
87654f87 | 187 | .write_latency_fields = dce4_afmt_write_latency_fields, |
a85d682a | 188 | .set_dto = dce4_dp_audio_set_dto, |
baa7d8e4 | 189 | .set_avi_packet = evergreen_set_avi_packet, |
070a2e63 AD |
190 | }; |
191 | ||
192 | static struct radeon_audio_funcs dce6_hdmi_funcs = { | |
88252d77 | 193 | .select_pin = dce6_afmt_select_pin, |
3cdde027 | 194 | .get_pin = dce6_audio_get_pin, |
070a2e63 | 195 | .write_sad_regs = dce6_afmt_write_sad_regs, |
00a9d4bc | 196 | .write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation, |
87654f87 | 197 | .write_latency_fields = dce6_afmt_write_latency_fields, |
a85d682a | 198 | .set_dto = dce6_hdmi_audio_set_dto, |
64424d6e | 199 | .update_acr = evergreen_hdmi_update_acr, |
930a9785 | 200 | .set_vbi_packet = dce4_set_vbi_packet, |
be273e58 | 201 | .set_color_depth = dce4_hdmi_set_color_depth, |
baa7d8e4 | 202 | .set_avi_packet = evergreen_set_avi_packet, |
1852c9a0 | 203 | .set_audio_packet = dce4_set_audio_packet, |
070a2e63 AD |
204 | }; |
205 | ||
206 | static struct radeon_audio_funcs dce6_dp_funcs = { | |
88252d77 | 207 | .select_pin = dce6_afmt_select_pin, |
3cdde027 | 208 | .get_pin = dce6_audio_get_pin, |
070a2e63 | 209 | .write_sad_regs = dce6_afmt_write_sad_regs, |
00a9d4bc | 210 | .write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation, |
87654f87 | 211 | .write_latency_fields = dce6_afmt_write_latency_fields, |
a85d682a | 212 | .set_dto = dce6_dp_audio_set_dto, |
baa7d8e4 | 213 | .set_avi_packet = evergreen_set_avi_packet, |
070a2e63 AD |
214 | }; |
215 | ||
1a626b68 SG |
216 | static void radeon_audio_interface_init(struct radeon_device *rdev) |
217 | { | |
218 | if (ASIC_IS_DCE6(rdev)) { | |
219 | rdev->audio.funcs = &dce6_funcs; | |
070a2e63 AD |
220 | rdev->audio.hdmi_funcs = &dce6_hdmi_funcs; |
221 | rdev->audio.dp_funcs = &dce6_dp_funcs; | |
1a626b68 SG |
222 | } else if (ASIC_IS_DCE4(rdev)) { |
223 | rdev->audio.funcs = &dce4_funcs; | |
070a2e63 AD |
224 | rdev->audio.hdmi_funcs = &dce4_hdmi_funcs; |
225 | rdev->audio.dp_funcs = &dce4_dp_funcs; | |
a85d682a | 226 | } else if (ASIC_IS_DCE32(rdev)) { |
1a626b68 | 227 | rdev->audio.funcs = &dce32_funcs; |
070a2e63 AD |
228 | rdev->audio.hdmi_funcs = &dce32_hdmi_funcs; |
229 | rdev->audio.dp_funcs = &dce32_dp_funcs; | |
a85d682a SG |
230 | } else { |
231 | rdev->audio.funcs = &r600_funcs; | |
232 | rdev->audio.hdmi_funcs = &r600_hdmi_funcs; | |
233 | rdev->audio.dp_funcs = 0; | |
1a626b68 SG |
234 | } |
235 | } | |
236 | ||
bfc1f97d SG |
237 | static int radeon_audio_chipset_supported(struct radeon_device *rdev) |
238 | { | |
239 | return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev); | |
240 | } | |
241 | ||
242 | int radeon_audio_init(struct radeon_device *rdev) | |
243 | { | |
244 | int i; | |
245 | ||
246 | if (!radeon_audio || !radeon_audio_chipset_supported(rdev)) | |
247 | return 0; | |
248 | ||
249 | rdev->audio.enabled = true; | |
250 | ||
251 | if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */ | |
252 | rdev->audio.num_pins = 3; | |
253 | else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */ | |
254 | rdev->audio.num_pins = 7; | |
255 | else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */ | |
256 | rdev->audio.num_pins = 7; | |
257 | else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */ | |
258 | rdev->audio.num_pins = 2; | |
259 | else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */ | |
260 | rdev->audio.num_pins = 6; | |
261 | else if (ASIC_IS_DCE6(rdev)) /* SI: 6 streams, 6 endpoints */ | |
262 | rdev->audio.num_pins = 6; | |
263 | else | |
264 | rdev->audio.num_pins = 1; | |
265 | ||
266 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
267 | rdev->audio.pin[i].channels = -1; | |
268 | rdev->audio.pin[i].rate = -1; | |
269 | rdev->audio.pin[i].bits_per_sample = -1; | |
270 | rdev->audio.pin[i].status_bits = 0; | |
271 | rdev->audio.pin[i].category_code = 0; | |
272 | rdev->audio.pin[i].connected = false; | |
273 | rdev->audio.pin[i].offset = pin_offsets[i]; | |
274 | rdev->audio.pin[i].id = i; | |
1a626b68 SG |
275 | } |
276 | ||
277 | radeon_audio_interface_init(rdev); | |
278 | ||
279 | /* disable audio. it will be set up later */ | |
280 | for (i = 0; i < rdev->audio.num_pins; i++) | |
8bf59820 | 281 | radeon_audio_enable(rdev, &rdev->audio.pin[i], false); |
1a626b68 SG |
282 | |
283 | return 0; | |
284 | } | |
285 | ||
286 | void radeon_audio_detect(struct drm_connector *connector, | |
287 | enum drm_connector_status status) | |
288 | { | |
289 | if (!connector || !connector->encoder) | |
290 | return; | |
291 | ||
292 | if (status == connector_status_connected) { | |
293 | int sink_type; | |
294 | struct radeon_device *rdev = connector->encoder->dev->dev_private; | |
295 | struct radeon_connector *radeon_connector; | |
296 | struct radeon_encoder *radeon_encoder = | |
297 | to_radeon_encoder(connector->encoder); | |
298 | ||
299 | if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) { | |
300 | radeon_encoder->audio = 0; | |
301 | return; | |
302 | } | |
303 | ||
304 | radeon_connector = to_radeon_connector(connector); | |
305 | sink_type = radeon_dp_getsinktype(radeon_connector); | |
306 | ||
307 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && | |
308 | sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
309 | radeon_encoder->audio = rdev->audio.dp_funcs; | |
310 | else | |
311 | radeon_encoder->audio = rdev->audio.hdmi_funcs; | |
312 | /* TODO: set up the sads, etc. and set the audio enable_mask */ | |
313 | } else { | |
314 | /* TODO: reset the audio enable_mask */ | |
bfc1f97d | 315 | } |
1a626b68 SG |
316 | } |
317 | ||
318 | u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg) | |
319 | { | |
320 | if (rdev->audio.funcs->endpoint_rreg) | |
321 | return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg); | |
bfc1f97d SG |
322 | |
323 | return 0; | |
324 | } | |
1a626b68 SG |
325 | |
326 | void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset, | |
327 | u32 reg, u32 v) | |
328 | { | |
329 | if (rdev->audio.funcs->endpoint_wreg) | |
330 | rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v); | |
331 | } | |
070a2e63 AD |
332 | |
333 | void radeon_audio_write_sad_regs(struct drm_encoder *encoder) | |
334 | { | |
335 | struct radeon_encoder *radeon_encoder; | |
336 | struct drm_connector *connector; | |
337 | struct radeon_connector *radeon_connector = NULL; | |
338 | struct cea_sad *sads; | |
339 | int sad_count; | |
340 | ||
341 | list_for_each_entry(connector, | |
342 | &encoder->dev->mode_config.connector_list, head) { | |
343 | if (connector->encoder == encoder) { | |
344 | radeon_connector = to_radeon_connector(connector); | |
345 | break; | |
346 | } | |
347 | } | |
348 | ||
349 | if (!radeon_connector) { | |
350 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
351 | return; | |
352 | } | |
353 | ||
354 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); | |
355 | if (sad_count <= 0) { | |
356 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
357 | return; | |
358 | } | |
359 | BUG_ON(!sads); | |
360 | ||
361 | radeon_encoder = to_radeon_encoder(encoder); | |
362 | ||
363 | if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs) | |
364 | radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count); | |
365 | ||
366 | kfree(sads); | |
367 | } | |
00a9d4bc SG |
368 | |
369 | void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder) | |
370 | { | |
371 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
372 | struct drm_connector *connector; | |
373 | struct radeon_connector *radeon_connector = NULL; | |
374 | u8 *sadb = NULL; | |
375 | int sad_count; | |
376 | ||
377 | list_for_each_entry(connector, | |
378 | &encoder->dev->mode_config.connector_list, head) { | |
379 | if (connector->encoder == encoder) { | |
380 | radeon_connector = to_radeon_connector(connector); | |
381 | break; | |
382 | } | |
383 | } | |
384 | ||
385 | if (!radeon_connector) { | |
386 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
387 | return; | |
388 | } | |
389 | ||
390 | sad_count = drm_edid_to_speaker_allocation( | |
391 | radeon_connector_edid(connector), &sadb); | |
392 | if (sad_count < 0) { | |
393 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", | |
394 | sad_count); | |
395 | sad_count = 0; | |
396 | } | |
397 | ||
398 | if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation) | |
399 | radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count); | |
400 | ||
401 | kfree(sadb); | |
402 | } | |
87654f87 SG |
403 | |
404 | void radeon_audio_write_latency_fields(struct drm_encoder *encoder, | |
405 | struct drm_display_mode *mode) | |
406 | { | |
407 | struct radeon_encoder *radeon_encoder; | |
408 | struct drm_connector *connector; | |
409 | struct radeon_connector *radeon_connector = 0; | |
410 | ||
411 | list_for_each_entry(connector, | |
412 | &encoder->dev->mode_config.connector_list, head) { | |
413 | if (connector->encoder == encoder) { | |
414 | radeon_connector = to_radeon_connector(connector); | |
415 | break; | |
416 | } | |
417 | } | |
418 | ||
419 | if (!radeon_connector) { | |
420 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
421 | return; | |
422 | } | |
423 | ||
424 | radeon_encoder = to_radeon_encoder(encoder); | |
425 | ||
426 | if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields) | |
427 | radeon_encoder->audio->write_latency_fields(encoder, connector, mode); | |
428 | } | |
3cdde027 SG |
429 | |
430 | struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder) | |
431 | { | |
432 | struct radeon_device *rdev = encoder->dev->dev_private; | |
433 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
434 | ||
435 | if (radeon_encoder->audio && radeon_encoder->audio->get_pin) | |
436 | return radeon_encoder->audio->get_pin(rdev); | |
437 | ||
438 | return NULL; | |
439 | } | |
88252d77 SG |
440 | |
441 | void radeon_audio_select_pin(struct drm_encoder *encoder) | |
442 | { | |
443 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
444 | ||
445 | if (radeon_encoder->audio && radeon_encoder->audio->select_pin) | |
446 | radeon_encoder->audio->select_pin(encoder); | |
447 | } | |
8bf59820 SG |
448 | |
449 | void radeon_audio_enable(struct radeon_device *rdev, | |
450 | struct r600_audio_pin *pin, u8 enable_mask) | |
451 | { | |
452 | if (rdev->audio.funcs->enable) | |
453 | rdev->audio.funcs->enable(rdev, pin, enable_mask); | |
454 | } | |
7991d665 SG |
455 | |
456 | void radeon_audio_fini(struct radeon_device *rdev) | |
457 | { | |
458 | int i; | |
459 | ||
460 | if (!rdev->audio.enabled) | |
461 | return; | |
462 | ||
463 | for (i = 0; i < rdev->audio.num_pins; i++) | |
464 | radeon_audio_enable(rdev, &rdev->audio.pin[i], false); | |
465 | ||
466 | rdev->audio.enabled = false; | |
467 | } | |
a85d682a SG |
468 | |
469 | void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock) | |
470 | { | |
471 | struct radeon_device *rdev = encoder->dev->dev_private; | |
472 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
473 | struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc); | |
474 | ||
475 | if (radeon_encoder->audio && radeon_encoder->audio->set_dto) | |
476 | radeon_encoder->audio->set_dto(rdev, crtc, clock); | |
477 | } | |
96ea7afb | 478 | |
baa7d8e4 SG |
479 | int radeon_audio_set_avi_packet(struct drm_encoder *encoder, |
480 | struct drm_display_mode *mode) | |
96ea7afb SG |
481 | { |
482 | struct radeon_device *rdev = encoder->dev->dev_private; | |
483 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
484 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
baa7d8e4 SG |
485 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
486 | struct hdmi_avi_infoframe frame; | |
487 | int err; | |
488 | ||
489 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); | |
490 | if (err < 0) { | |
491 | DRM_ERROR("failed to setup AVI infoframe: %d\n", err); | |
492 | return err; | |
493 | } | |
494 | ||
495 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
496 | if (err < 0) { | |
497 | DRM_ERROR("failed to pack AVI infoframe: %d\n", err); | |
498 | return err; | |
499 | } | |
500 | ||
501 | if (dig && dig->afmt && | |
502 | radeon_encoder->audio && radeon_encoder->audio->set_avi_packet) | |
503 | radeon_encoder->audio->set_avi_packet(rdev, dig->afmt->offset, | |
504 | buffer, sizeof(buffer)); | |
96ea7afb | 505 | |
baa7d8e4 | 506 | return 0; |
96ea7afb | 507 | } |
64424d6e SG |
508 | |
509 | /* | |
510 | * calculate CTS and N values if they are not found in the table | |
511 | */ | |
512 | static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq) | |
513 | { | |
514 | int n, cts; | |
515 | unsigned long div, mul; | |
516 | ||
517 | /* Safe, but overly large values */ | |
518 | n = 128 * freq; | |
519 | cts = clock * 1000; | |
520 | ||
521 | /* Smallest valid fraction */ | |
522 | div = gcd(n, cts); | |
523 | ||
524 | n /= div; | |
525 | cts /= div; | |
526 | ||
527 | /* | |
528 | * The optimal N is 128*freq/1000. Calculate the closest larger | |
529 | * value that doesn't truncate any bits. | |
530 | */ | |
531 | mul = ((128*freq/1000) + (n-1))/n; | |
532 | ||
533 | n *= mul; | |
534 | cts *= mul; | |
535 | ||
536 | /* Check that we are in spec (not always possible) */ | |
537 | if (n < (128*freq/1500)) | |
538 | printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); | |
539 | if (n > (128*freq/300)) | |
540 | printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); | |
541 | ||
542 | *N = n; | |
543 | *CTS = cts; | |
544 | ||
545 | DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", | |
546 | *N, *CTS, freq); | |
547 | } | |
548 | ||
549 | static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock) | |
550 | { | |
551 | static struct radeon_hdmi_acr res; | |
552 | u8 i; | |
553 | ||
554 | static const struct radeon_hdmi_acr hdmi_predefined_acr[] = { | |
555 | /* 32kHz 44.1kHz 48kHz */ | |
556 | /* Clock N CTS N CTS N CTS */ | |
557 | { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ | |
558 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ | |
559 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ | |
560 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ | |
561 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ | |
562 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ | |
563 | { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ | |
564 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ | |
565 | { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ | |
566 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ | |
567 | }; | |
568 | ||
569 | /* Precalculated values for common clocks */ | |
570 | for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++) | |
571 | if (hdmi_predefined_acr[i].clock == clock) | |
572 | return &hdmi_predefined_acr[i]; | |
573 | ||
574 | /* And odd clocks get manually calculated */ | |
575 | radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); | |
576 | radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); | |
577 | radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); | |
578 | ||
579 | return &res; | |
580 | } | |
581 | ||
582 | /* | |
583 | * update the N and CTS parameters for a given pixel clock rate | |
584 | */ | |
585 | void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock) | |
586 | { | |
587 | const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); | |
588 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
589 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
590 | ||
591 | if (!dig || !dig->afmt) | |
592 | return; | |
593 | ||
594 | if (radeon_encoder->audio && radeon_encoder->audio->update_acr) | |
595 | radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); | |
596 | } | |
930a9785 AD |
597 | |
598 | void radeon_audio_set_vbi_packet(struct drm_encoder *encoder) | |
599 | { | |
600 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
601 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
602 | ||
603 | if (!dig || !dig->afmt) | |
604 | return; | |
605 | ||
606 | if (radeon_encoder->audio && radeon_encoder->audio->set_vbi_packet) | |
607 | radeon_encoder->audio->set_vbi_packet(encoder, dig->afmt->offset); | |
608 | } | |
be273e58 SG |
609 | |
610 | void radeon_hdmi_set_color_depth(struct drm_encoder *encoder) | |
611 | { | |
612 | int bpc = 8; | |
613 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
614 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
615 | ||
616 | if (!dig || !dig->afmt) | |
617 | return; | |
618 | ||
619 | if (encoder->crtc) { | |
620 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
621 | bpc = radeon_crtc->bpc; | |
622 | } | |
623 | ||
624 | if (radeon_encoder->audio && radeon_encoder->audio->set_color_depth) | |
625 | radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc); | |
626 | } | |
1852c9a0 SG |
627 | |
628 | void radeon_audio_set_audio_packet(struct drm_encoder *encoder) | |
629 | { | |
630 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
631 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
632 | ||
633 | if (!dig || !dig->afmt) | |
634 | return; | |
635 | ||
636 | if (radeon_encoder->audio && radeon_encoder->audio->set_audio_packet) | |
637 | radeon_encoder->audio->set_audio_packet(encoder, dig->afmt->offset); | |
638 | } |