[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_audio.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Slava Grigorev <slava.grigorev@amd.com>
 */

#include <linux/gcd.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include "radeon.h"
#include "atom.h"
#include "radeon_audio.h"

void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
		u8 enable_mask);
void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
		u8 enable_mask);
void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
		u8 enable_mask);
u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);
void dce6_endpoint_wreg(struct radeon_device *rdev,
		u32 offset, u32 reg, u32 v);
void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
		struct cea_sad *sads, int sad_count);
void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
		struct cea_sad *sads, int sad_count);
void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
		struct cea_sad *sads, int sad_count);
void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
		u8 *sadb, int sad_count);
void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode);
void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode);
struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev);
struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev);
void dce6_afmt_select_pin(struct drm_encoder *encoder);
void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void dce3_2_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock);
void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
	unsigned char *buffer, size_t size);
void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
	unsigned char *buffer, size_t size);
void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	const struct radeon_hdmi_acr *acr);
void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	const struct radeon_hdmi_acr *acr);
void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	const struct radeon_hdmi_acr *acr);

static const u32 pin_offsets[7] =
{
	(0x5e00 - 0x5e00),
	(0x5e18 - 0x5e00),
	(0x5e30 - 0x5e00),
	(0x5e48 - 0x5e00),
	(0x5e60 - 0x5e00),
	(0x5e78 - 0x5e00),
	(0x5e90 - 0x5e00),
};

static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
{
	return RREG32(reg);
}

static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset,
		u32 reg, u32 v)
{
	WREG32(reg, v);
}

static struct radeon_audio_basic_funcs r600_funcs = {
	.endpoint_rreg = radeon_audio_rreg,
	.endpoint_wreg = radeon_audio_wreg,
	.enable = r600_audio_enable,
	.update_avi_infoframe = r600_update_avi_infoframe,
};

static struct radeon_audio_basic_funcs dce32_funcs = {
	.endpoint_rreg = radeon_audio_rreg,
	.endpoint_wreg = radeon_audio_wreg,
	.enable = r600_audio_enable,
	.update_avi_infoframe = r600_update_avi_infoframe,
};

static struct radeon_audio_basic_funcs dce4_funcs = {
	.endpoint_rreg = radeon_audio_rreg,
	.endpoint_wreg = radeon_audio_wreg,
	.enable = dce4_audio_enable,
	.update_avi_infoframe = evergreen_update_avi_infoframe,
};

static struct radeon_audio_basic_funcs dce6_funcs = {
	.endpoint_rreg = dce6_endpoint_rreg,
	.endpoint_wreg = dce6_endpoint_wreg,
	.enable = dce6_audio_enable,
	.update_avi_infoframe = evergreen_update_avi_infoframe,
};

static struct radeon_audio_funcs r600_hdmi_funcs = {
	.get_pin = r600_audio_get_pin,
	.set_dto = r600_hdmi_audio_set_dto,
	.update_acr = r600_hdmi_update_acr,
};

static struct radeon_audio_funcs dce32_hdmi_funcs = {
	.get_pin = r600_audio_get_pin,
	.write_sad_regs = dce3_2_afmt_write_sad_regs,
	.write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation,
	.set_dto = dce3_2_audio_set_dto,
	.update_acr = dce3_2_hdmi_update_acr,
};

static struct radeon_audio_funcs dce32_dp_funcs = {
	.get_pin = r600_audio_get_pin,
	.write_sad_regs = dce3_2_afmt_write_sad_regs,
	.write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation,
	.set_dto = dce3_2_audio_set_dto,
};

static struct radeon_audio_funcs dce4_hdmi_funcs = {
	.get_pin = r600_audio_get_pin,
	.write_sad_regs = evergreen_hdmi_write_sad_regs,
	.write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation,
	.write_latency_fields = dce4_afmt_write_latency_fields,
	.set_dto = dce4_hdmi_audio_set_dto,
	.update_acr = evergreen_hdmi_update_acr,
};

static struct radeon_audio_funcs dce4_dp_funcs = {
	.get_pin = r600_audio_get_pin,
	.write_sad_regs = evergreen_hdmi_write_sad_regs,
	.write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation,
	.write_latency_fields = dce4_afmt_write_latency_fields,
	.set_dto = dce4_dp_audio_set_dto,
};

static struct radeon_audio_funcs dce6_hdmi_funcs = {
	.select_pin = dce6_afmt_select_pin,
	.get_pin = dce6_audio_get_pin,
	.write_sad_regs = dce6_afmt_write_sad_regs,
	.write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation,
	.write_latency_fields = dce6_afmt_write_latency_fields,
	.set_dto = dce6_hdmi_audio_set_dto,
	.update_acr = evergreen_hdmi_update_acr,
};

static struct radeon_audio_funcs dce6_dp_funcs = {
	.select_pin = dce6_afmt_select_pin,
	.get_pin = dce6_audio_get_pin,
	.write_sad_regs = dce6_afmt_write_sad_regs,
	.write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation,
	.write_latency_fields = dce6_afmt_write_latency_fields,
	.set_dto = dce6_dp_audio_set_dto,
};

static void radeon_audio_interface_init(struct radeon_device *rdev)
{
	if (ASIC_IS_DCE6(rdev)) {
		rdev->audio.funcs = &dce6_funcs;
		rdev->audio.hdmi_funcs = &dce6_hdmi_funcs;
		rdev->audio.dp_funcs = &dce6_dp_funcs;
	} else if (ASIC_IS_DCE4(rdev)) {
		rdev->audio.funcs = &dce4_funcs;
		rdev->audio.hdmi_funcs = &dce4_hdmi_funcs;
		rdev->audio.dp_funcs = &dce4_dp_funcs;
	} else if (ASIC_IS_DCE32(rdev)) {
		rdev->audio.funcs = &dce32_funcs;
		rdev->audio.hdmi_funcs = &dce32_hdmi_funcs;
		rdev->audio.dp_funcs = &dce32_dp_funcs;
	} else {
		rdev->audio.funcs = &r600_funcs;
		rdev->audio.hdmi_funcs = &r600_hdmi_funcs;
		rdev->audio.dp_funcs = 0;
	}
}

static int radeon_audio_chipset_supported(struct radeon_device *rdev)
{
	return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
}

int radeon_audio_init(struct radeon_device *rdev)
{
	int i;

	if (!radeon_audio || !radeon_audio_chipset_supported(rdev))
		return 0;

	rdev->audio.enabled = true;

	if (ASIC_IS_DCE83(rdev))		/* KB: 2 streams, 3 endpoints */
		rdev->audio.num_pins = 3;
	else if (ASIC_IS_DCE81(rdev))	/* KV: 4 streams, 7 endpoints */
		rdev->audio.num_pins = 7;
	else if (ASIC_IS_DCE8(rdev))	/* BN/HW: 6 streams, 7 endpoints */
		rdev->audio.num_pins = 7;
	else if (ASIC_IS_DCE64(rdev))	/* OL: 2 streams, 2 endpoints */
		rdev->audio.num_pins = 2;
	else if (ASIC_IS_DCE61(rdev))	/* TN: 4 streams, 6 endpoints */
		rdev->audio.num_pins = 6;
	else if (ASIC_IS_DCE6(rdev))	/* SI: 6 streams, 6 endpoints */
		rdev->audio.num_pins = 6;
	else
		rdev->audio.num_pins = 1;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		rdev->audio.pin[i].channels = -1;
		rdev->audio.pin[i].rate = -1;
		rdev->audio.pin[i].bits_per_sample = -1;
		rdev->audio.pin[i].status_bits = 0;
		rdev->audio.pin[i].category_code = 0;
		rdev->audio.pin[i].connected = false;
		rdev->audio.pin[i].offset = pin_offsets[i];
		rdev->audio.pin[i].id = i;
	}

	radeon_audio_interface_init(rdev);

	/* disable audio.  it will be set up later */
	for (i = 0; i < rdev->audio.num_pins; i++)
		radeon_audio_enable(rdev, &rdev->audio.pin[i], false);

	return 0;
}

void radeon_audio_detect(struct drm_connector *connector,
	enum drm_connector_status status)
{
	if (!connector || !connector->encoder)
		return;

	if (status == connector_status_connected) {
		int sink_type;
		struct radeon_device *rdev = connector->encoder->dev->dev_private;
		struct radeon_connector *radeon_connector;
		struct radeon_encoder *radeon_encoder =
			to_radeon_encoder(connector->encoder);

		if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) {
			radeon_encoder->audio = 0;
			return;
		}

		radeon_connector = to_radeon_connector(connector);
		sink_type = radeon_dp_getsinktype(radeon_connector);

		if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
			sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
			radeon_encoder->audio = rdev->audio.dp_funcs;
		else
			radeon_encoder->audio = rdev->audio.hdmi_funcs;
		/* TODO: set up the sads, etc. and set the audio enable_mask */
	} else {
		/* TODO: reset the audio enable_mask */
	}
}

u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
{
	if (rdev->audio.funcs->endpoint_rreg)
		return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);

	return 0;
}

void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset,
	u32 reg, u32 v)
{
	if (rdev->audio.funcs->endpoint_wreg)
		rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);
}

void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = NULL;
	struct cea_sad *sads;
	int sad_count;

	list_for_each_entry(connector,
		&encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder) {
			radeon_connector = to_radeon_connector(connector);
			break;
		}
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
	if (sad_count <= 0) {
		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
		return;
	}
	BUG_ON(!sads);

	radeon_encoder = to_radeon_encoder(encoder);

	if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs)
		radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count);

	kfree(sads);
}

void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
    struct drm_connector *connector;
    struct radeon_connector *radeon_connector = NULL;
    u8 *sadb = NULL;
    int sad_count;

    list_for_each_entry(connector,
		&encoder->dev->mode_config.connector_list, head) {
        if (connector->encoder == encoder) {
            radeon_connector = to_radeon_connector(connector);
            break;
        }
    }

    if (!radeon_connector) {
        DRM_ERROR("Couldn't find encoder's connector\n");
        return;
    }

    sad_count = drm_edid_to_speaker_allocation(
		radeon_connector_edid(connector), &sadb);
    if (sad_count < 0) {
        DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
			sad_count);
        sad_count = 0;
    }

	if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation)
		radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count);

    kfree(sadb);
}

void radeon_audio_write_latency_fields(struct drm_encoder *encoder,
	struct drm_display_mode *mode)
{
	struct radeon_encoder *radeon_encoder;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = 0;

	list_for_each_entry(connector,
		&encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder) {
			radeon_connector = to_radeon_connector(connector);
			break;
		}
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	radeon_encoder = to_radeon_encoder(encoder);

	if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields)
		radeon_encoder->audio->write_latency_fields(encoder, connector, mode);
}

struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	if (radeon_encoder->audio && radeon_encoder->audio->get_pin)
		return radeon_encoder->audio->get_pin(rdev);

	return NULL;
}

void radeon_audio_select_pin(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	if (radeon_encoder->audio && radeon_encoder->audio->select_pin)
		radeon_encoder->audio->select_pin(encoder);
}

void radeon_audio_enable(struct radeon_device *rdev,
	struct r600_audio_pin *pin, u8 enable_mask)
{
	if (rdev->audio.funcs->enable)
		rdev->audio.funcs->enable(rdev, pin, enable_mask);
}

void radeon_audio_fini(struct radeon_device *rdev)
{
	int i;

	if (!rdev->audio.enabled)
		return;

	for (i = 0; i < rdev->audio.num_pins; i++)
		radeon_audio_enable(rdev, &rdev->audio.pin[i], false);

	rdev->audio.enabled = false;
}

void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);

	if (radeon_encoder->audio && radeon_encoder->audio->set_dto)
		radeon_encoder->audio->set_dto(rdev, crtc, clock);
}

void radeon_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
	size_t size)
{
    struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (dig && dig->afmt && rdev->audio.funcs->update_avi_infoframe)
		rdev->audio.funcs->update_avi_infoframe(rdev, dig->afmt->offset,
			buffer, size);
}

/*
 * calculate CTS and N values if they are not found in the table
 */
static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq)
{
	int n, cts;
	unsigned long div, mul;

	/* Safe, but overly large values */
	n = 128 * freq;
	cts = clock * 1000;

	/* Smallest valid fraction */
	div = gcd(n, cts);

	n /= div;
	cts /= div;

	/*
	 * The optimal N is 128*freq/1000. Calculate the closest larger
	 * value that doesn't truncate any bits.
	 */
	mul = ((128*freq/1000) + (n-1))/n;

	n *= mul;
	cts *= mul;

	/* Check that we are in spec (not always possible) */
	if (n < (128*freq/1500))
		printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
	if (n > (128*freq/300))
		printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");

	*N = n;
	*CTS = cts;

	DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
		*N, *CTS, freq);
}

static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock)
{
	static struct radeon_hdmi_acr res;
	u8 i;

	static const struct radeon_hdmi_acr hdmi_predefined_acr[] = {
		/*       32kHz    44.1kHz   48kHz    */
		/* Clock      N     CTS      N     CTS      N     CTS */
		{  25175,  4096,  25175, 28224, 125875,  6144,  25175 }, /*  25,20/1.001 MHz */
		{  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
		{  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
		{  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
		{  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
		{  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
		{  74176,  4096,  74176,  5733,  75335,  6144,  74176 }, /*  74.25/1.001 MHz */
		{  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
		{ 148352,  4096, 148352,  5733, 150670,  6144, 148352 }, /* 148.50/1.001 MHz */
		{ 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
	};

	/* Precalculated values for common clocks */
	for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++)
		if (hdmi_predefined_acr[i].clock == clock)
			return &hdmi_predefined_acr[i];

	/* And odd clocks get manually calculated */
	radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
	radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
	radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);

	return &res;
}

/*
 * update the N and CTS parameters for a given pixel clock rate
 */
void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock)
{
    const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock);
    struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
    struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (!dig || !dig->afmt)
		return;

	if (radeon_encoder->audio && radeon_encoder->audio->update_acr)
		radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr);
}
Commit	Line	Data
bfc1f97d SG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Slava Grigorev <slava.grigorev@amd.com>
	23	*/
	24
64424d6e	25	#include <linux/gcd.h>
bfc1f97d	26	#include <drm/drmP.h>
1a626b68	27	#include <drm/drm_crtc.h>
bfc1f97d	28	#include "radeon.h"
1a626b68 SG	29	#include "atom.h"
1a626b68 SG	30	#include "radeon_audio.h"
bfc1f97d SG	31
	32	void r600_audio_enable(struct radeon_device rdev, struct r600_audio_pin pin,
	33	u8 enable_mask);
8bf59820 SG	34	void dce4_audio_enable(struct radeon_device rdev, struct r600_audio_pin pin,
8bf59820 SG	35	u8 enable_mask);
bfc1f97d SG	36	void dce6_audio_enable(struct radeon_device rdev, struct r600_audio_pin pin,
bfc1f97d SG	37	u8 enable_mask);
1a626b68 SG	38	u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);
	39	void dce6_endpoint_wreg(struct radeon_device *rdev,
	40	u32 offset, u32 reg, u32 v);
070a2e63 AD	41	void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
	42	struct cea_sad *sads, int sad_count);
	43	void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
	44	struct cea_sad *sads, int sad_count);
	45	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
	46	struct cea_sad *sads, int sad_count);
00a9d4bc SG	47	void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	48	u8 *sadb, int sad_count);
	49	void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	50	u8 *sadb, int sad_count);
	51	void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	52	u8 *sadb, int sad_count);
	53	void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	54	u8 *sadb, int sad_count);
	55	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	56	u8 *sadb, int sad_count);
	57	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	58	u8 *sadb, int sad_count);
87654f87 SG	59	void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
	60	struct drm_connector connector, struct drm_display_mode mode);
	61	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
	62	struct drm_connector connector, struct drm_display_mode mode);
3cdde027 SG	63	struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev);
3cdde027 SG	64	struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev);
88252d77	65	void dce6_afmt_select_pin(struct drm_encoder *encoder);
a85d682a SG	66	void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
	67	struct radeon_crtc *crtc, unsigned int clock);
	68	void dce3_2_audio_set_dto(struct radeon_device *rdev,
	69	struct radeon_crtc *crtc, unsigned int clock);
	70	void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
	71	struct radeon_crtc *crtc, unsigned int clock);
	72	void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	73	struct radeon_crtc *crtc, unsigned int clock);
	74	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	75	struct radeon_crtc *crtc, unsigned int clock);
	76	void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	77	struct radeon_crtc *crtc, unsigned int clock);
96ea7afb SG	78	void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
	79	unsigned char *buffer, size_t size);
	80	void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
	81	unsigned char *buffer, size_t size);
64424d6e SG	82	void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	83	const struct radeon_hdmi_acr *acr);
	84	void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	85	const struct radeon_hdmi_acr *acr);
	86	void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	87	const struct radeon_hdmi_acr *acr);
bfc1f97d SG	88
	89	static const u32 pin_offsets[7] =
	90	{
	91	(0x5e00 - 0x5e00),
	92	(0x5e18 - 0x5e00),
	93	(0x5e30 - 0x5e00),
	94	(0x5e48 - 0x5e00),
	95	(0x5e60 - 0x5e00),
	96	(0x5e78 - 0x5e00),
	97	(0x5e90 - 0x5e00),
	98	};
	99
1a626b68 SG	100	static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
	101	{
	102	return RREG32(reg);
	103	}
	104
	105	static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset,
	106	u32 reg, u32 v)
	107	{
	108	WREG32(reg, v);
	109	}
	110
a85d682a SG	111	static struct radeon_audio_basic_funcs r600_funcs = {
	112	.endpoint_rreg = radeon_audio_rreg,
	113	.endpoint_wreg = radeon_audio_wreg,
	114	.enable = r600_audio_enable,
96ea7afb	115	.update_avi_infoframe = r600_update_avi_infoframe,
a85d682a SG	116	};
a85d682a SG	117
1a626b68 SG	118	static struct radeon_audio_basic_funcs dce32_funcs = {
	119	.endpoint_rreg = radeon_audio_rreg,
	120	.endpoint_wreg = radeon_audio_wreg,
8bf59820	121	.enable = r600_audio_enable,
96ea7afb	122	.update_avi_infoframe = r600_update_avi_infoframe,
1a626b68 SG	123	};
	124
	125	static struct radeon_audio_basic_funcs dce4_funcs = {
	126	.endpoint_rreg = radeon_audio_rreg,
	127	.endpoint_wreg = radeon_audio_wreg,
8bf59820	128	.enable = dce4_audio_enable,
96ea7afb	129	.update_avi_infoframe = evergreen_update_avi_infoframe,
1a626b68 SG	130	};
	131
	132	static struct radeon_audio_basic_funcs dce6_funcs = {
	133	.endpoint_rreg = dce6_endpoint_rreg,
	134	.endpoint_wreg = dce6_endpoint_wreg,
8bf59820	135	.enable = dce6_audio_enable,
96ea7afb	136	.update_avi_infoframe = evergreen_update_avi_infoframe,
1a626b68 SG	137	};
1a626b68 SG	138
a85d682a SG	139	static struct radeon_audio_funcs r600_hdmi_funcs = {
	140	.get_pin = r600_audio_get_pin,
	141	.set_dto = r600_hdmi_audio_set_dto,
64424d6e	142	.update_acr = r600_hdmi_update_acr,
a85d682a SG	143	};
a85d682a SG	144
070a2e63	145	static struct radeon_audio_funcs dce32_hdmi_funcs = {
3cdde027	146	.get_pin = r600_audio_get_pin,
070a2e63	147	.write_sad_regs = dce3_2_afmt_write_sad_regs,
00a9d4bc	148	.write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation,
a85d682a	149	.set_dto = dce3_2_audio_set_dto,
64424d6e	150	.update_acr = dce3_2_hdmi_update_acr,
070a2e63 AD	151	};
	152
	153	static struct radeon_audio_funcs dce32_dp_funcs = {
3cdde027	154	.get_pin = r600_audio_get_pin,
070a2e63	155	.write_sad_regs = dce3_2_afmt_write_sad_regs,
00a9d4bc	156	.write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation,
a85d682a	157	.set_dto = dce3_2_audio_set_dto,
070a2e63 AD	158	};
	159
	160	static struct radeon_audio_funcs dce4_hdmi_funcs = {
3cdde027	161	.get_pin = r600_audio_get_pin,
070a2e63	162	.write_sad_regs = evergreen_hdmi_write_sad_regs,
00a9d4bc	163	.write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation,
87654f87	164	.write_latency_fields = dce4_afmt_write_latency_fields,
a85d682a	165	.set_dto = dce4_hdmi_audio_set_dto,
64424d6e	166	.update_acr = evergreen_hdmi_update_acr,
070a2e63 AD	167	};
	168
	169	static struct radeon_audio_funcs dce4_dp_funcs = {
3cdde027	170	.get_pin = r600_audio_get_pin,
070a2e63	171	.write_sad_regs = evergreen_hdmi_write_sad_regs,
00a9d4bc	172	.write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation,
87654f87	173	.write_latency_fields = dce4_afmt_write_latency_fields,
a85d682a	174	.set_dto = dce4_dp_audio_set_dto,
070a2e63 AD	175	};
	176
	177	static struct radeon_audio_funcs dce6_hdmi_funcs = {
88252d77	178	.select_pin = dce6_afmt_select_pin,
3cdde027	179	.get_pin = dce6_audio_get_pin,
070a2e63	180	.write_sad_regs = dce6_afmt_write_sad_regs,
00a9d4bc	181	.write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation,
87654f87	182	.write_latency_fields = dce6_afmt_write_latency_fields,
a85d682a	183	.set_dto = dce6_hdmi_audio_set_dto,
64424d6e	184	.update_acr = evergreen_hdmi_update_acr,
070a2e63 AD	185	};
	186
	187	static struct radeon_audio_funcs dce6_dp_funcs = {
88252d77	188	.select_pin = dce6_afmt_select_pin,
3cdde027	189	.get_pin = dce6_audio_get_pin,
070a2e63	190	.write_sad_regs = dce6_afmt_write_sad_regs,
00a9d4bc	191	.write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation,
87654f87	192	.write_latency_fields = dce6_afmt_write_latency_fields,
a85d682a	193	.set_dto = dce6_dp_audio_set_dto,
070a2e63 AD	194	};
070a2e63 AD	195
1a626b68 SG	196	static void radeon_audio_interface_init(struct radeon_device *rdev)
	197	{
	198	if (ASIC_IS_DCE6(rdev)) {
	199	rdev->audio.funcs = &dce6_funcs;
070a2e63 AD	200	rdev->audio.hdmi_funcs = &dce6_hdmi_funcs;
070a2e63 AD	201	rdev->audio.dp_funcs = &dce6_dp_funcs;
1a626b68 SG	202	} else if (ASIC_IS_DCE4(rdev)) {
1a626b68 SG	203	rdev->audio.funcs = &dce4_funcs;
070a2e63 AD	204	rdev->audio.hdmi_funcs = &dce4_hdmi_funcs;
070a2e63 AD	205	rdev->audio.dp_funcs = &dce4_dp_funcs;
a85d682a	206	} else if (ASIC_IS_DCE32(rdev)) {
1a626b68	207	rdev->audio.funcs = &dce32_funcs;
070a2e63 AD	208	rdev->audio.hdmi_funcs = &dce32_hdmi_funcs;
070a2e63 AD	209	rdev->audio.dp_funcs = &dce32_dp_funcs;
a85d682a SG	210	} else {
	211	rdev->audio.funcs = &r600_funcs;
	212	rdev->audio.hdmi_funcs = &r600_hdmi_funcs;
	213	rdev->audio.dp_funcs = 0;
1a626b68 SG	214	}
	215	}
	216
bfc1f97d SG	217	static int radeon_audio_chipset_supported(struct radeon_device *rdev)
	218	{
	219	return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
	220	}
	221
	222	int radeon_audio_init(struct radeon_device *rdev)
	223	{
	224	int i;
	225
	226	if (!radeon_audio \|\| !radeon_audio_chipset_supported(rdev))
	227	return 0;
	228
	229	rdev->audio.enabled = true;
	230
	231	if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
	232	rdev->audio.num_pins = 3;
	233	else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
	234	rdev->audio.num_pins = 7;
	235	else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */
	236	rdev->audio.num_pins = 7;
	237	else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */
	238	rdev->audio.num_pins = 2;
	239	else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */
	240	rdev->audio.num_pins = 6;
	241	else if (ASIC_IS_DCE6(rdev)) /* SI: 6 streams, 6 endpoints */
	242	rdev->audio.num_pins = 6;
	243	else
	244	rdev->audio.num_pins = 1;
	245
	246	for (i = 0; i < rdev->audio.num_pins; i++) {
	247	rdev->audio.pin[i].channels = -1;
	248	rdev->audio.pin[i].rate = -1;
	249	rdev->audio.pin[i].bits_per_sample = -1;
	250	rdev->audio.pin[i].status_bits = 0;
	251	rdev->audio.pin[i].category_code = 0;
	252	rdev->audio.pin[i].connected = false;
	253	rdev->audio.pin[i].offset = pin_offsets[i];
	254	rdev->audio.pin[i].id = i;
1a626b68 SG	255	}
	256
	257	radeon_audio_interface_init(rdev);
	258
	259	/* disable audio. it will be set up later */
	260	for (i = 0; i < rdev->audio.num_pins; i++)
8bf59820	261	radeon_audio_enable(rdev, &rdev->audio.pin[i], false);
1a626b68 SG	262
	263	return 0;
	264	}
	265
	266	void radeon_audio_detect(struct drm_connector *connector,
	267	enum drm_connector_status status)
	268	{
	269	if (!connector \|\| !connector->encoder)
	270	return;
	271
	272	if (status == connector_status_connected) {
	273	int sink_type;
	274	struct radeon_device *rdev = connector->encoder->dev->dev_private;
	275	struct radeon_connector *radeon_connector;
	276	struct radeon_encoder *radeon_encoder =
	277	to_radeon_encoder(connector->encoder);
	278
	279	if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) {
	280	radeon_encoder->audio = 0;
	281	return;
	282	}
	283
	284	radeon_connector = to_radeon_connector(connector);
	285	sink_type = radeon_dp_getsinktype(radeon_connector);
	286
	287	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
	288	sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
	289	radeon_encoder->audio = rdev->audio.dp_funcs;
	290	else
	291	radeon_encoder->audio = rdev->audio.hdmi_funcs;
	292	/* TODO: set up the sads, etc. and set the audio enable_mask */
	293	} else {
	294	/* TODO: reset the audio enable_mask */
bfc1f97d	295	}
1a626b68 SG	296	}
	297
	298	u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
	299	{
	300	if (rdev->audio.funcs->endpoint_rreg)
	301	return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);
bfc1f97d SG	302
	303	return 0;
	304	}
1a626b68 SG	305
	306	void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset,
	307	u32 reg, u32 v)
	308	{
	309	if (rdev->audio.funcs->endpoint_wreg)
	310	rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);
	311	}
070a2e63 AD	312
	313	void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
	314	{
	315	struct radeon_encoder *radeon_encoder;
	316	struct drm_connector *connector;
	317	struct radeon_connector *radeon_connector = NULL;
	318	struct cea_sad *sads;
	319	int sad_count;
	320
	321	list_for_each_entry(connector,
	322	&encoder->dev->mode_config.connector_list, head) {
	323	if (connector->encoder == encoder) {
	324	radeon_connector = to_radeon_connector(connector);
	325	break;
	326	}
	327	}
	328
	329	if (!radeon_connector) {
	330	DRM_ERROR("Couldn't find encoder's connector\n");
	331	return;
	332	}
	333
	334	sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
	335	if (sad_count <= 0) {
	336	DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
	337	return;
	338	}
	339	BUG_ON(!sads);
	340
	341	radeon_encoder = to_radeon_encoder(encoder);
	342
	343	if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs)
	344	radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count);
	345
	346	kfree(sads);
	347	}
00a9d4bc SG	348
	349	void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder)
	350	{
	351	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	352	struct drm_connector *connector;
	353	struct radeon_connector *radeon_connector = NULL;
	354	u8 *sadb = NULL;
	355	int sad_count;
	356
	357	list_for_each_entry(connector,
	358	&encoder->dev->mode_config.connector_list, head) {
	359	if (connector->encoder == encoder) {
	360	radeon_connector = to_radeon_connector(connector);
	361	break;
	362	}
	363	}
	364
	365	if (!radeon_connector) {
	366	DRM_ERROR("Couldn't find encoder's connector\n");
	367	return;
	368	}
	369
	370	sad_count = drm_edid_to_speaker_allocation(
	371	radeon_connector_edid(connector), &sadb);
	372	if (sad_count < 0) {
	373	DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
	374	sad_count);
	375	sad_count = 0;
	376	}
	377
	378	if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation)
	379	radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count);
	380
	381	kfree(sadb);
	382	}
87654f87 SG	383
	384	void radeon_audio_write_latency_fields(struct drm_encoder *encoder,
	385	struct drm_display_mode *mode)
	386	{
	387	struct radeon_encoder *radeon_encoder;
	388	struct drm_connector *connector;
	389	struct radeon_connector *radeon_connector = 0;
	390
	391	list_for_each_entry(connector,
	392	&encoder->dev->mode_config.connector_list, head) {
	393	if (connector->encoder == encoder) {
	394	radeon_connector = to_radeon_connector(connector);
	395	break;
	396	}
	397	}
	398
	399	if (!radeon_connector) {
	400	DRM_ERROR("Couldn't find encoder's connector\n");
	401	return;
	402	}
	403
	404	radeon_encoder = to_radeon_encoder(encoder);
	405
	406	if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields)
	407	radeon_encoder->audio->write_latency_fields(encoder, connector, mode);
	408	}
3cdde027 SG	409
	410	struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder)
	411	{
	412	struct radeon_device *rdev = encoder->dev->dev_private;
	413	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	414
	415	if (radeon_encoder->audio && radeon_encoder->audio->get_pin)
	416	return radeon_encoder->audio->get_pin(rdev);
	417
	418	return NULL;
	419	}
88252d77 SG	420
	421	void radeon_audio_select_pin(struct drm_encoder *encoder)
	422	{
	423	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	424
	425	if (radeon_encoder->audio && radeon_encoder->audio->select_pin)
	426	radeon_encoder->audio->select_pin(encoder);
	427	}
8bf59820 SG	428
	429	void radeon_audio_enable(struct radeon_device *rdev,
	430	struct r600_audio_pin *pin, u8 enable_mask)
	431	{
	432	if (rdev->audio.funcs->enable)
	433	rdev->audio.funcs->enable(rdev, pin, enable_mask);
	434	}
7991d665 SG	435
	436	void radeon_audio_fini(struct radeon_device *rdev)
	437	{
	438	int i;
	439
	440	if (!rdev->audio.enabled)
	441	return;
	442
	443	for (i = 0; i < rdev->audio.num_pins; i++)
	444	radeon_audio_enable(rdev, &rdev->audio.pin[i], false);
	445
	446	rdev->audio.enabled = false;
	447	}
a85d682a SG	448
	449	void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock)
	450	{
	451	struct radeon_device *rdev = encoder->dev->dev_private;
	452	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	453	struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);
	454
	455	if (radeon_encoder->audio && radeon_encoder->audio->set_dto)
	456	radeon_encoder->audio->set_dto(rdev, crtc, clock);
	457	}
96ea7afb SG	458
	459	void radeon_update_avi_infoframe(struct drm_encoder encoder, void buffer,
	460	size_t size)
	461	{
	462	struct radeon_device *rdev = encoder->dev->dev_private;
	463	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	464	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	465
	466	if (dig && dig->afmt && rdev->audio.funcs->update_avi_infoframe)
	467	rdev->audio.funcs->update_avi_infoframe(rdev, dig->afmt->offset,
	468	buffer, size);
	469	}
64424d6e SG	470
	471	/*
	472	* calculate CTS and N values if they are not found in the table
	473	*/
	474	static void radeon_audio_calc_cts(unsigned int clock, int CTS, int N, int freq)
	475	{
	476	int n, cts;
	477	unsigned long div, mul;
	478
	479	/* Safe, but overly large values */
	480	n = 128 * freq;
	481	cts = clock * 1000;
	482
	483	/* Smallest valid fraction */
	484	div = gcd(n, cts);
	485
	486	n /= div;
	487	cts /= div;
	488
	489	/*
	490	* The optimal N is 128*freq/1000. Calculate the closest larger
	491	* value that doesn't truncate any bits.
	492	*/
	493	mul = ((128*freq/1000) + (n-1))/n;
	494
	495	n *= mul;
	496	cts *= mul;
	497
	498	/* Check that we are in spec (not always possible) */
	499	if (n < (128*freq/1500))
	500	printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
	501	if (n > (128*freq/300))
	502	printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
	503
	504	*N = n;
	505	*CTS = cts;
	506
	507	DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
	508	N, CTS, freq);
	509	}
	510
	511	static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock)
	512	{
	513	static struct radeon_hdmi_acr res;
	514	u8 i;
	515
	516	static const struct radeon_hdmi_acr hdmi_predefined_acr[] = {
	517	/* 32kHz 44.1kHz 48kHz */
	518	/* Clock N CTS N CTS N CTS */
	519	{ 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
	520	{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
	521	{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
	522	{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.001.001 MHz /
	523	{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
	524	{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.001.001 MHz /
	525	{ 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
	526	{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
	527	{ 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
	528	{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
	529	};
	530
	531	/* Precalculated values for common clocks */
	532	for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++)
	533	if (hdmi_predefined_acr[i].clock == clock)
534	return &hdmi_predefined_acr[i];
535
536	/* And odd clocks get manually calculated */
537	radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
538	radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
539	radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
540
541	return &res;
542	}
543
544	/*
545	* update the N and CTS parameters for a given pixel clock rate
546	*/
547	void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock)
548	{
549	const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock);
550	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
551	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
552
553	if (!dig \|\| !dig->afmt)
554	return;
555
556	if (radeon_encoder->audio && radeon_encoder->audio->update_acr)
557	radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr);
558	}