Commit | Line | Data |
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bfc1f97d SG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Slava Grigorev <slava.grigorev@amd.com> | |
23 | */ | |
24 | ||
25 | #include <drm/drmP.h> | |
1a626b68 | 26 | #include <drm/drm_crtc.h> |
bfc1f97d | 27 | #include "radeon.h" |
1a626b68 SG |
28 | #include "atom.h" |
29 | #include "radeon_audio.h" | |
bfc1f97d SG |
30 | |
31 | void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, | |
32 | u8 enable_mask); | |
8bf59820 SG |
33 | void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
34 | u8 enable_mask); | |
bfc1f97d SG |
35 | void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
36 | u8 enable_mask); | |
1a626b68 SG |
37 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg); |
38 | void dce6_endpoint_wreg(struct radeon_device *rdev, | |
39 | u32 offset, u32 reg, u32 v); | |
070a2e63 AD |
40 | void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, |
41 | struct cea_sad *sads, int sad_count); | |
42 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, | |
43 | struct cea_sad *sads, int sad_count); | |
44 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, | |
45 | struct cea_sad *sads, int sad_count); | |
00a9d4bc SG |
46 | void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
47 | u8 *sadb, int sad_count); | |
48 | void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
49 | u8 *sadb, int sad_count); | |
50 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, | |
51 | u8 *sadb, int sad_count); | |
52 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
53 | u8 *sadb, int sad_count); | |
54 | void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, | |
55 | u8 *sadb, int sad_count); | |
56 | void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, | |
57 | u8 *sadb, int sad_count); | |
87654f87 SG |
58 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
59 | struct drm_connector *connector, struct drm_display_mode *mode); | |
60 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, | |
61 | struct drm_connector *connector, struct drm_display_mode *mode); | |
3cdde027 SG |
62 | struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev); |
63 | struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev); | |
88252d77 | 64 | void dce6_afmt_select_pin(struct drm_encoder *encoder); |
a85d682a SG |
65 | void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
66 | struct radeon_crtc *crtc, unsigned int clock); | |
67 | void dce3_2_audio_set_dto(struct radeon_device *rdev, | |
68 | struct radeon_crtc *crtc, unsigned int clock); | |
69 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, | |
70 | struct radeon_crtc *crtc, unsigned int clock); | |
71 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, | |
72 | struct radeon_crtc *crtc, unsigned int clock); | |
73 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, | |
74 | struct radeon_crtc *crtc, unsigned int clock); | |
75 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, | |
76 | struct radeon_crtc *crtc, unsigned int clock); | |
96ea7afb SG |
77 | void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset, |
78 | unsigned char *buffer, size_t size); | |
79 | void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset, | |
80 | unsigned char *buffer, size_t size); | |
bfc1f97d SG |
81 | |
82 | static const u32 pin_offsets[7] = | |
83 | { | |
84 | (0x5e00 - 0x5e00), | |
85 | (0x5e18 - 0x5e00), | |
86 | (0x5e30 - 0x5e00), | |
87 | (0x5e48 - 0x5e00), | |
88 | (0x5e60 - 0x5e00), | |
89 | (0x5e78 - 0x5e00), | |
90 | (0x5e90 - 0x5e00), | |
91 | }; | |
92 | ||
1a626b68 SG |
93 | static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg) |
94 | { | |
95 | return RREG32(reg); | |
96 | } | |
97 | ||
98 | static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset, | |
99 | u32 reg, u32 v) | |
100 | { | |
101 | WREG32(reg, v); | |
102 | } | |
103 | ||
a85d682a SG |
104 | static struct radeon_audio_basic_funcs r600_funcs = { |
105 | .endpoint_rreg = radeon_audio_rreg, | |
106 | .endpoint_wreg = radeon_audio_wreg, | |
107 | .enable = r600_audio_enable, | |
96ea7afb | 108 | .update_avi_infoframe = r600_update_avi_infoframe, |
a85d682a SG |
109 | }; |
110 | ||
1a626b68 SG |
111 | static struct radeon_audio_basic_funcs dce32_funcs = { |
112 | .endpoint_rreg = radeon_audio_rreg, | |
113 | .endpoint_wreg = radeon_audio_wreg, | |
8bf59820 | 114 | .enable = r600_audio_enable, |
96ea7afb | 115 | .update_avi_infoframe = r600_update_avi_infoframe, |
1a626b68 SG |
116 | }; |
117 | ||
118 | static struct radeon_audio_basic_funcs dce4_funcs = { | |
119 | .endpoint_rreg = radeon_audio_rreg, | |
120 | .endpoint_wreg = radeon_audio_wreg, | |
8bf59820 | 121 | .enable = dce4_audio_enable, |
96ea7afb | 122 | .update_avi_infoframe = evergreen_update_avi_infoframe, |
1a626b68 SG |
123 | }; |
124 | ||
125 | static struct radeon_audio_basic_funcs dce6_funcs = { | |
126 | .endpoint_rreg = dce6_endpoint_rreg, | |
127 | .endpoint_wreg = dce6_endpoint_wreg, | |
8bf59820 | 128 | .enable = dce6_audio_enable, |
96ea7afb | 129 | .update_avi_infoframe = evergreen_update_avi_infoframe, |
1a626b68 SG |
130 | }; |
131 | ||
a85d682a SG |
132 | static struct radeon_audio_funcs r600_hdmi_funcs = { |
133 | .get_pin = r600_audio_get_pin, | |
134 | .set_dto = r600_hdmi_audio_set_dto, | |
135 | }; | |
136 | ||
070a2e63 | 137 | static struct radeon_audio_funcs dce32_hdmi_funcs = { |
3cdde027 | 138 | .get_pin = r600_audio_get_pin, |
070a2e63 | 139 | .write_sad_regs = dce3_2_afmt_write_sad_regs, |
00a9d4bc | 140 | .write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation, |
a85d682a | 141 | .set_dto = dce3_2_audio_set_dto, |
070a2e63 AD |
142 | }; |
143 | ||
144 | static struct radeon_audio_funcs dce32_dp_funcs = { | |
3cdde027 | 145 | .get_pin = r600_audio_get_pin, |
070a2e63 | 146 | .write_sad_regs = dce3_2_afmt_write_sad_regs, |
00a9d4bc | 147 | .write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation, |
a85d682a | 148 | .set_dto = dce3_2_audio_set_dto, |
070a2e63 AD |
149 | }; |
150 | ||
151 | static struct radeon_audio_funcs dce4_hdmi_funcs = { | |
3cdde027 | 152 | .get_pin = r600_audio_get_pin, |
070a2e63 | 153 | .write_sad_regs = evergreen_hdmi_write_sad_regs, |
00a9d4bc | 154 | .write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation, |
87654f87 | 155 | .write_latency_fields = dce4_afmt_write_latency_fields, |
a85d682a | 156 | .set_dto = dce4_hdmi_audio_set_dto, |
070a2e63 AD |
157 | }; |
158 | ||
159 | static struct radeon_audio_funcs dce4_dp_funcs = { | |
3cdde027 | 160 | .get_pin = r600_audio_get_pin, |
070a2e63 | 161 | .write_sad_regs = evergreen_hdmi_write_sad_regs, |
00a9d4bc | 162 | .write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation, |
87654f87 | 163 | .write_latency_fields = dce4_afmt_write_latency_fields, |
a85d682a | 164 | .set_dto = dce4_dp_audio_set_dto, |
070a2e63 AD |
165 | }; |
166 | ||
167 | static struct radeon_audio_funcs dce6_hdmi_funcs = { | |
88252d77 | 168 | .select_pin = dce6_afmt_select_pin, |
3cdde027 | 169 | .get_pin = dce6_audio_get_pin, |
070a2e63 | 170 | .write_sad_regs = dce6_afmt_write_sad_regs, |
00a9d4bc | 171 | .write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation, |
87654f87 | 172 | .write_latency_fields = dce6_afmt_write_latency_fields, |
a85d682a | 173 | .set_dto = dce6_hdmi_audio_set_dto, |
070a2e63 AD |
174 | }; |
175 | ||
176 | static struct radeon_audio_funcs dce6_dp_funcs = { | |
88252d77 | 177 | .select_pin = dce6_afmt_select_pin, |
3cdde027 | 178 | .get_pin = dce6_audio_get_pin, |
070a2e63 | 179 | .write_sad_regs = dce6_afmt_write_sad_regs, |
00a9d4bc | 180 | .write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation, |
87654f87 | 181 | .write_latency_fields = dce6_afmt_write_latency_fields, |
a85d682a | 182 | .set_dto = dce6_dp_audio_set_dto, |
070a2e63 AD |
183 | }; |
184 | ||
1a626b68 SG |
185 | static void radeon_audio_interface_init(struct radeon_device *rdev) |
186 | { | |
187 | if (ASIC_IS_DCE6(rdev)) { | |
188 | rdev->audio.funcs = &dce6_funcs; | |
070a2e63 AD |
189 | rdev->audio.hdmi_funcs = &dce6_hdmi_funcs; |
190 | rdev->audio.dp_funcs = &dce6_dp_funcs; | |
1a626b68 SG |
191 | } else if (ASIC_IS_DCE4(rdev)) { |
192 | rdev->audio.funcs = &dce4_funcs; | |
070a2e63 AD |
193 | rdev->audio.hdmi_funcs = &dce4_hdmi_funcs; |
194 | rdev->audio.dp_funcs = &dce4_dp_funcs; | |
a85d682a | 195 | } else if (ASIC_IS_DCE32(rdev)) { |
1a626b68 | 196 | rdev->audio.funcs = &dce32_funcs; |
070a2e63 AD |
197 | rdev->audio.hdmi_funcs = &dce32_hdmi_funcs; |
198 | rdev->audio.dp_funcs = &dce32_dp_funcs; | |
a85d682a SG |
199 | } else { |
200 | rdev->audio.funcs = &r600_funcs; | |
201 | rdev->audio.hdmi_funcs = &r600_hdmi_funcs; | |
202 | rdev->audio.dp_funcs = 0; | |
1a626b68 SG |
203 | } |
204 | } | |
205 | ||
bfc1f97d SG |
206 | static int radeon_audio_chipset_supported(struct radeon_device *rdev) |
207 | { | |
208 | return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev); | |
209 | } | |
210 | ||
211 | int radeon_audio_init(struct radeon_device *rdev) | |
212 | { | |
213 | int i; | |
214 | ||
215 | if (!radeon_audio || !radeon_audio_chipset_supported(rdev)) | |
216 | return 0; | |
217 | ||
218 | rdev->audio.enabled = true; | |
219 | ||
220 | if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */ | |
221 | rdev->audio.num_pins = 3; | |
222 | else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */ | |
223 | rdev->audio.num_pins = 7; | |
224 | else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */ | |
225 | rdev->audio.num_pins = 7; | |
226 | else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */ | |
227 | rdev->audio.num_pins = 2; | |
228 | else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */ | |
229 | rdev->audio.num_pins = 6; | |
230 | else if (ASIC_IS_DCE6(rdev)) /* SI: 6 streams, 6 endpoints */ | |
231 | rdev->audio.num_pins = 6; | |
232 | else | |
233 | rdev->audio.num_pins = 1; | |
234 | ||
235 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
236 | rdev->audio.pin[i].channels = -1; | |
237 | rdev->audio.pin[i].rate = -1; | |
238 | rdev->audio.pin[i].bits_per_sample = -1; | |
239 | rdev->audio.pin[i].status_bits = 0; | |
240 | rdev->audio.pin[i].category_code = 0; | |
241 | rdev->audio.pin[i].connected = false; | |
242 | rdev->audio.pin[i].offset = pin_offsets[i]; | |
243 | rdev->audio.pin[i].id = i; | |
1a626b68 SG |
244 | } |
245 | ||
246 | radeon_audio_interface_init(rdev); | |
247 | ||
248 | /* disable audio. it will be set up later */ | |
249 | for (i = 0; i < rdev->audio.num_pins; i++) | |
8bf59820 | 250 | radeon_audio_enable(rdev, &rdev->audio.pin[i], false); |
1a626b68 SG |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
255 | void radeon_audio_detect(struct drm_connector *connector, | |
256 | enum drm_connector_status status) | |
257 | { | |
258 | if (!connector || !connector->encoder) | |
259 | return; | |
260 | ||
261 | if (status == connector_status_connected) { | |
262 | int sink_type; | |
263 | struct radeon_device *rdev = connector->encoder->dev->dev_private; | |
264 | struct radeon_connector *radeon_connector; | |
265 | struct radeon_encoder *radeon_encoder = | |
266 | to_radeon_encoder(connector->encoder); | |
267 | ||
268 | if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) { | |
269 | radeon_encoder->audio = 0; | |
270 | return; | |
271 | } | |
272 | ||
273 | radeon_connector = to_radeon_connector(connector); | |
274 | sink_type = radeon_dp_getsinktype(radeon_connector); | |
275 | ||
276 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && | |
277 | sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
278 | radeon_encoder->audio = rdev->audio.dp_funcs; | |
279 | else | |
280 | radeon_encoder->audio = rdev->audio.hdmi_funcs; | |
281 | /* TODO: set up the sads, etc. and set the audio enable_mask */ | |
282 | } else { | |
283 | /* TODO: reset the audio enable_mask */ | |
bfc1f97d | 284 | } |
1a626b68 SG |
285 | } |
286 | ||
287 | u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg) | |
288 | { | |
289 | if (rdev->audio.funcs->endpoint_rreg) | |
290 | return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg); | |
bfc1f97d SG |
291 | |
292 | return 0; | |
293 | } | |
1a626b68 SG |
294 | |
295 | void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset, | |
296 | u32 reg, u32 v) | |
297 | { | |
298 | if (rdev->audio.funcs->endpoint_wreg) | |
299 | rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v); | |
300 | } | |
070a2e63 AD |
301 | |
302 | void radeon_audio_write_sad_regs(struct drm_encoder *encoder) | |
303 | { | |
304 | struct radeon_encoder *radeon_encoder; | |
305 | struct drm_connector *connector; | |
306 | struct radeon_connector *radeon_connector = NULL; | |
307 | struct cea_sad *sads; | |
308 | int sad_count; | |
309 | ||
310 | list_for_each_entry(connector, | |
311 | &encoder->dev->mode_config.connector_list, head) { | |
312 | if (connector->encoder == encoder) { | |
313 | radeon_connector = to_radeon_connector(connector); | |
314 | break; | |
315 | } | |
316 | } | |
317 | ||
318 | if (!radeon_connector) { | |
319 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
320 | return; | |
321 | } | |
322 | ||
323 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); | |
324 | if (sad_count <= 0) { | |
325 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
326 | return; | |
327 | } | |
328 | BUG_ON(!sads); | |
329 | ||
330 | radeon_encoder = to_radeon_encoder(encoder); | |
331 | ||
332 | if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs) | |
333 | radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count); | |
334 | ||
335 | kfree(sads); | |
336 | } | |
00a9d4bc SG |
337 | |
338 | void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder) | |
339 | { | |
340 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
341 | struct drm_connector *connector; | |
342 | struct radeon_connector *radeon_connector = NULL; | |
343 | u8 *sadb = NULL; | |
344 | int sad_count; | |
345 | ||
346 | list_for_each_entry(connector, | |
347 | &encoder->dev->mode_config.connector_list, head) { | |
348 | if (connector->encoder == encoder) { | |
349 | radeon_connector = to_radeon_connector(connector); | |
350 | break; | |
351 | } | |
352 | } | |
353 | ||
354 | if (!radeon_connector) { | |
355 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
356 | return; | |
357 | } | |
358 | ||
359 | sad_count = drm_edid_to_speaker_allocation( | |
360 | radeon_connector_edid(connector), &sadb); | |
361 | if (sad_count < 0) { | |
362 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", | |
363 | sad_count); | |
364 | sad_count = 0; | |
365 | } | |
366 | ||
367 | if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation) | |
368 | radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count); | |
369 | ||
370 | kfree(sadb); | |
371 | } | |
87654f87 SG |
372 | |
373 | void radeon_audio_write_latency_fields(struct drm_encoder *encoder, | |
374 | struct drm_display_mode *mode) | |
375 | { | |
376 | struct radeon_encoder *radeon_encoder; | |
377 | struct drm_connector *connector; | |
378 | struct radeon_connector *radeon_connector = 0; | |
379 | ||
380 | list_for_each_entry(connector, | |
381 | &encoder->dev->mode_config.connector_list, head) { | |
382 | if (connector->encoder == encoder) { | |
383 | radeon_connector = to_radeon_connector(connector); | |
384 | break; | |
385 | } | |
386 | } | |
387 | ||
388 | if (!radeon_connector) { | |
389 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
390 | return; | |
391 | } | |
392 | ||
393 | radeon_encoder = to_radeon_encoder(encoder); | |
394 | ||
395 | if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields) | |
396 | radeon_encoder->audio->write_latency_fields(encoder, connector, mode); | |
397 | } | |
3cdde027 SG |
398 | |
399 | struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder) | |
400 | { | |
401 | struct radeon_device *rdev = encoder->dev->dev_private; | |
402 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
403 | ||
404 | if (radeon_encoder->audio && radeon_encoder->audio->get_pin) | |
405 | return radeon_encoder->audio->get_pin(rdev); | |
406 | ||
407 | return NULL; | |
408 | } | |
88252d77 SG |
409 | |
410 | void radeon_audio_select_pin(struct drm_encoder *encoder) | |
411 | { | |
412 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
413 | ||
414 | if (radeon_encoder->audio && radeon_encoder->audio->select_pin) | |
415 | radeon_encoder->audio->select_pin(encoder); | |
416 | } | |
8bf59820 SG |
417 | |
418 | void radeon_audio_enable(struct radeon_device *rdev, | |
419 | struct r600_audio_pin *pin, u8 enable_mask) | |
420 | { | |
421 | if (rdev->audio.funcs->enable) | |
422 | rdev->audio.funcs->enable(rdev, pin, enable_mask); | |
423 | } | |
7991d665 SG |
424 | |
425 | void radeon_audio_fini(struct radeon_device *rdev) | |
426 | { | |
427 | int i; | |
428 | ||
429 | if (!rdev->audio.enabled) | |
430 | return; | |
431 | ||
432 | for (i = 0; i < rdev->audio.num_pins; i++) | |
433 | radeon_audio_enable(rdev, &rdev->audio.pin[i], false); | |
434 | ||
435 | rdev->audio.enabled = false; | |
436 | } | |
a85d682a SG |
437 | |
438 | void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock) | |
439 | { | |
440 | struct radeon_device *rdev = encoder->dev->dev_private; | |
441 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
442 | struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc); | |
443 | ||
444 | if (radeon_encoder->audio && radeon_encoder->audio->set_dto) | |
445 | radeon_encoder->audio->set_dto(rdev, crtc, clock); | |
446 | } | |
96ea7afb SG |
447 | |
448 | void radeon_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, | |
449 | size_t size) | |
450 | { | |
451 | struct radeon_device *rdev = encoder->dev->dev_private; | |
452 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
453 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
454 | ||
455 | if (dig && dig->afmt && rdev->audio.funcs->update_avi_infoframe) | |
456 | rdev->audio.funcs->update_avi_infoframe(rdev, dig->afmt->offset, | |
457 | buffer, size); | |
458 | } |