Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 JG |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | |
31 | #include "atom.h" | |
32 | ||
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
268ba0a9 | 35 | #include <linux/acpi.h> |
771fe6b9 JG |
36 | /* |
37 | * BIOS. | |
38 | */ | |
b442962a AD |
39 | |
40 | /* If you boot an IGP board with a discrete card as the primary, | |
41 | * the IGP rom is not accessible via the rom bar as the IGP rom is | |
42 | * part of the system bios. On boot, the system bios puts a | |
43 | * copy of the igp rom at the start of vram if a discrete card is | |
44 | * present. | |
45 | */ | |
46 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) | |
47 | { | |
48 | uint8_t __iomem *bios; | |
49 | resource_size_t vram_base; | |
50 | resource_size_t size = 256 * 1024; /* ??? */ | |
51 | ||
8b5d8dec DA |
52 | if (!(rdev->flags & RADEON_IS_IGP)) |
53 | if (!radeon_card_posted(rdev)) | |
54 | return false; | |
55 | ||
b442962a | 56 | rdev->bios = NULL; |
01d73a69 | 57 | vram_base = pci_resource_start(rdev->pdev, 0); |
b442962a AD |
58 | bios = ioremap(vram_base, size); |
59 | if (!bios) { | |
b442962a AD |
60 | return false; |
61 | } | |
62 | ||
63 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
64 | iounmap(bios); | |
b442962a AD |
65 | return false; |
66 | } | |
67 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
68 | if (rdev->bios == NULL) { | |
69 | iounmap(bios); | |
b442962a AD |
70 | return false; |
71 | } | |
6a9ee8af | 72 | memcpy_fromio(rdev->bios, bios, size); |
b442962a AD |
73 | iounmap(bios); |
74 | return true; | |
75 | } | |
76 | ||
771fe6b9 JG |
77 | static bool radeon_read_bios(struct radeon_device *rdev) |
78 | { | |
f2c9e560 | 79 | uint8_t __iomem *bios, val1, val2; |
771fe6b9 JG |
80 | size_t size; |
81 | ||
82 | rdev->bios = NULL; | |
b442962a | 83 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
771fe6b9 JG |
84 | bios = pci_map_rom(rdev->pdev, &size); |
85 | if (!bios) { | |
86 | return false; | |
87 | } | |
88 | ||
f2c9e560 DM |
89 | val1 = readb(&bios[0]); |
90 | val2 = readb(&bios[1]); | |
91 | ||
92 | if (size == 0 || val1 != 0x55 || val2 != 0xaa) { | |
771fe6b9 JG |
93 | pci_unmap_rom(rdev->pdev, bios); |
94 | return false; | |
95 | } | |
f2c9e560 | 96 | rdev->bios = kzalloc(size, GFP_KERNEL); |
771fe6b9 JG |
97 | if (rdev->bios == NULL) { |
98 | pci_unmap_rom(rdev->pdev, bios); | |
99 | return false; | |
100 | } | |
f2c9e560 | 101 | memcpy_fromio(rdev->bios, bios, size); |
771fe6b9 JG |
102 | pci_unmap_rom(rdev->pdev, bios); |
103 | return true; | |
104 | } | |
105 | ||
06a08570 MG |
106 | static bool radeon_read_platform_bios(struct radeon_device *rdev) |
107 | { | |
108 | uint8_t __iomem *bios; | |
109 | size_t size; | |
110 | ||
111 | rdev->bios = NULL; | |
112 | ||
113 | bios = pci_platform_rom(rdev->pdev, &size); | |
114 | if (!bios) { | |
115 | return false; | |
116 | } | |
117 | ||
118 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
119 | return false; | |
120 | } | |
121 | rdev->bios = kmemdup(bios, size, GFP_KERNEL); | |
122 | if (rdev->bios == NULL) { | |
123 | return false; | |
124 | } | |
125 | ||
126 | return true; | |
127 | } | |
128 | ||
c61e2775 | 129 | #ifdef CONFIG_ACPI |
6a9ee8af DA |
130 | /* ATRM is used to get the BIOS on the discrete cards in |
131 | * dual-gpu systems. | |
132 | */ | |
c61e2775 AD |
133 | /* retrieve the ROM in 4k blocks */ |
134 | #define ATRM_BIOS_PAGE 4096 | |
135 | /** | |
136 | * radeon_atrm_call - fetch a chunk of the vbios | |
137 | * | |
138 | * @atrm_handle: acpi ATRM handle | |
139 | * @bios: vbios image pointer | |
140 | * @offset: offset of vbios image data to fetch | |
141 | * @len: length of vbios image data to fetch | |
142 | * | |
143 | * Executes ATRM to fetch a chunk of the discrete | |
144 | * vbios image on PX systems (all asics). | |
145 | * Returns the length of the buffer fetched. | |
146 | */ | |
147 | static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, | |
148 | int offset, int len) | |
149 | { | |
150 | acpi_status status; | |
151 | union acpi_object atrm_arg_elements[2], *obj; | |
152 | struct acpi_object_list atrm_arg; | |
153 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; | |
154 | ||
155 | atrm_arg.count = 2; | |
156 | atrm_arg.pointer = &atrm_arg_elements[0]; | |
157 | ||
158 | atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; | |
159 | atrm_arg_elements[0].integer.value = offset; | |
160 | ||
161 | atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; | |
162 | atrm_arg_elements[1].integer.value = len; | |
163 | ||
164 | status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); | |
165 | if (ACPI_FAILURE(status)) { | |
166 | printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); | |
167 | return -ENODEV; | |
168 | } | |
169 | ||
170 | obj = (union acpi_object *)buffer.pointer; | |
171 | memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); | |
172 | len = obj->buffer.length; | |
173 | kfree(buffer.pointer); | |
174 | return len; | |
175 | } | |
176 | ||
6a9ee8af DA |
177 | static bool radeon_atrm_get_bios(struct radeon_device *rdev) |
178 | { | |
179 | int ret; | |
b271a988 | 180 | int size = 256 * 1024; |
6a9ee8af | 181 | int i; |
c61e2775 AD |
182 | struct pci_dev *pdev = NULL; |
183 | acpi_handle dhandle, atrm_handle; | |
184 | acpi_status status; | |
185 | bool found = false; | |
186 | ||
187 | /* ATRM is for the discrete card only */ | |
188 | if (rdev->flags & RADEON_IS_IGP) | |
189 | return false; | |
190 | ||
191 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { | |
3a83f992 | 192 | dhandle = ACPI_HANDLE(&pdev->dev); |
c61e2775 AD |
193 | if (!dhandle) |
194 | continue; | |
6a9ee8af | 195 | |
c61e2775 AD |
196 | status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); |
197 | if (!ACPI_FAILURE(status)) { | |
198 | found = true; | |
199 | break; | |
200 | } | |
201 | } | |
202 | ||
d8ade352 AD |
203 | if (!found) { |
204 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { | |
205 | dhandle = ACPI_HANDLE(&pdev->dev); | |
206 | if (!dhandle) | |
207 | continue; | |
208 | ||
209 | status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); | |
210 | if (!ACPI_FAILURE(status)) { | |
211 | found = true; | |
212 | break; | |
213 | } | |
214 | } | |
215 | } | |
216 | ||
c61e2775 | 217 | if (!found) |
6a9ee8af DA |
218 | return false; |
219 | ||
220 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
221 | if (!rdev->bios) { | |
222 | DRM_ERROR("Unable to allocate bios\n"); | |
223 | return false; | |
224 | } | |
225 | ||
226 | for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { | |
c61e2775 AD |
227 | ret = radeon_atrm_call(atrm_handle, |
228 | rdev->bios, | |
229 | (i * ATRM_BIOS_PAGE), | |
230 | ATRM_BIOS_PAGE); | |
211fa4fc | 231 | if (ret < ATRM_BIOS_PAGE) |
6a9ee8af DA |
232 | break; |
233 | } | |
234 | ||
235 | if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
236 | kfree(rdev->bios); | |
237 | return false; | |
238 | } | |
239 | return true; | |
240 | } | |
c61e2775 AD |
241 | #else |
242 | static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) | |
243 | { | |
244 | return false; | |
245 | } | |
246 | #endif | |
0ec80d64 | 247 | |
c901bcdd AD |
248 | static bool ni_read_disabled_bios(struct radeon_device *rdev) |
249 | { | |
250 | u32 bus_cntl; | |
251 | u32 d1vga_control; | |
252 | u32 d2vga_control; | |
253 | u32 vga_render_control; | |
254 | u32 rom_cntl; | |
255 | bool r; | |
256 | ||
257 | bus_cntl = RREG32(R600_BUS_CNTL); | |
258 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
259 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
260 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
261 | rom_cntl = RREG32(R600_ROM_CNTL); | |
262 | ||
263 | /* enable the rom */ | |
264 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); | |
5153550a AD |
265 | if (!ASIC_IS_NODCE(rdev)) { |
266 | /* Disable VGA mode */ | |
267 | WREG32(AVIVO_D1VGA_CONTROL, | |
268 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
269 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
270 | WREG32(AVIVO_D2VGA_CONTROL, | |
271 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
272 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
273 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
274 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
275 | } | |
c901bcdd AD |
276 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); |
277 | ||
278 | r = radeon_read_bios(rdev); | |
279 | ||
280 | /* restore regs */ | |
281 | WREG32(R600_BUS_CNTL, bus_cntl); | |
5153550a AD |
282 | if (!ASIC_IS_NODCE(rdev)) { |
283 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
284 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
285 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
286 | } | |
c901bcdd AD |
287 | WREG32(R600_ROM_CNTL, rom_cntl); |
288 | return r; | |
289 | } | |
290 | ||
771fe6b9 JG |
291 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
292 | { | |
293 | uint32_t viph_control; | |
294 | uint32_t bus_cntl; | |
295 | uint32_t d1vga_control; | |
296 | uint32_t d2vga_control; | |
297 | uint32_t vga_render_control; | |
298 | uint32_t rom_cntl; | |
299 | uint32_t cg_spll_func_cntl = 0; | |
300 | uint32_t cg_spll_status; | |
301 | bool r; | |
302 | ||
303 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 304 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
305 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
306 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
307 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
308 | rom_cntl = RREG32(R600_ROM_CNTL); | |
309 | ||
310 | /* disable VIP */ | |
311 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
312 | /* enable the rom */ | |
0ec80d64 | 313 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
314 | /* Disable VGA mode */ |
315 | WREG32(AVIVO_D1VGA_CONTROL, | |
316 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
317 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
318 | WREG32(AVIVO_D2VGA_CONTROL, | |
319 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
320 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
321 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
322 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
323 | ||
324 | if (rdev->family == CHIP_RV730) { | |
325 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); | |
326 | ||
327 | /* enable bypass mode */ | |
328 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | | |
329 | R600_SPLL_BYPASS_EN)); | |
330 | ||
331 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
332 | cg_spll_status = 0; | |
333 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
334 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
335 | ||
336 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); | |
337 | } else | |
338 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); | |
339 | ||
340 | r = radeon_read_bios(rdev); | |
341 | ||
342 | /* restore regs */ | |
343 | if (rdev->family == CHIP_RV730) { | |
344 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); | |
345 | ||
346 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
347 | cg_spll_status = 0; | |
348 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
349 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
350 | } | |
351 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 352 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
353 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
354 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
355 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
356 | WREG32(R600_ROM_CNTL, rom_cntl); | |
357 | return r; | |
358 | } | |
359 | ||
360 | static bool r600_read_disabled_bios(struct radeon_device *rdev) | |
361 | { | |
362 | uint32_t viph_control; | |
363 | uint32_t bus_cntl; | |
364 | uint32_t d1vga_control; | |
365 | uint32_t d2vga_control; | |
366 | uint32_t vga_render_control; | |
367 | uint32_t rom_cntl; | |
368 | uint32_t general_pwrmgt; | |
369 | uint32_t low_vid_lower_gpio_cntl; | |
370 | uint32_t medium_vid_lower_gpio_cntl; | |
371 | uint32_t high_vid_lower_gpio_cntl; | |
372 | uint32_t ctxsw_vid_lower_gpio_cntl; | |
373 | uint32_t lower_gpio_enable; | |
374 | bool r; | |
375 | ||
376 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 377 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
378 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
379 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
380 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
381 | rom_cntl = RREG32(R600_ROM_CNTL); | |
382 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); | |
383 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); | |
384 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); | |
385 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); | |
386 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); | |
387 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); | |
388 | ||
389 | /* disable VIP */ | |
390 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
391 | /* enable the rom */ | |
0ec80d64 | 392 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
393 | /* Disable VGA mode */ |
394 | WREG32(AVIVO_D1VGA_CONTROL, | |
395 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
396 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
397 | WREG32(AVIVO_D2VGA_CONTROL, | |
398 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
399 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
400 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
401 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
402 | ||
403 | WREG32(R600_ROM_CNTL, | |
404 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | | |
405 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | | |
406 | R600_SCK_OVERWRITE)); | |
407 | ||
408 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); | |
409 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, | |
410 | (low_vid_lower_gpio_cntl & ~0x400)); | |
411 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, | |
412 | (medium_vid_lower_gpio_cntl & ~0x400)); | |
413 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, | |
414 | (high_vid_lower_gpio_cntl & ~0x400)); | |
415 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, | |
416 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); | |
417 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); | |
418 | ||
419 | r = radeon_read_bios(rdev); | |
420 | ||
421 | /* restore regs */ | |
422 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 423 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
424 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
425 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
426 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
427 | WREG32(R600_ROM_CNTL, rom_cntl); | |
428 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); | |
429 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); | |
430 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); | |
431 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); | |
432 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); | |
433 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); | |
434 | return r; | |
435 | } | |
436 | ||
437 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) | |
438 | { | |
439 | uint32_t seprom_cntl1; | |
440 | uint32_t viph_control; | |
441 | uint32_t bus_cntl; | |
442 | uint32_t d1vga_control; | |
443 | uint32_t d2vga_control; | |
444 | uint32_t vga_render_control; | |
445 | uint32_t gpiopad_a; | |
446 | uint32_t gpiopad_en; | |
447 | uint32_t gpiopad_mask; | |
448 | bool r; | |
449 | ||
450 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
451 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
4171424e | 452 | bus_cntl = RREG32(RV370_BUS_CNTL); |
771fe6b9 JG |
453 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
454 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
455 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
456 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); | |
457 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); | |
458 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); | |
459 | ||
460 | WREG32(RADEON_SEPROM_CNTL1, | |
461 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
462 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
463 | WREG32(RADEON_GPIOPAD_A, 0); | |
464 | WREG32(RADEON_GPIOPAD_EN, 0); | |
465 | WREG32(RADEON_GPIOPAD_MASK, 0); | |
466 | ||
467 | /* disable VIP */ | |
468 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
469 | ||
470 | /* enable the rom */ | |
4171424e | 471 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
771fe6b9 JG |
472 | |
473 | /* Disable VGA mode */ | |
474 | WREG32(AVIVO_D1VGA_CONTROL, | |
475 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
476 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
477 | WREG32(AVIVO_D2VGA_CONTROL, | |
478 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
479 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
480 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
481 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
482 | ||
483 | r = radeon_read_bios(rdev); | |
484 | ||
485 | /* restore regs */ | |
486 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
487 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
4171424e | 488 | WREG32(RV370_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
489 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
490 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
491 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
492 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); | |
493 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); | |
494 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); | |
495 | return r; | |
496 | } | |
497 | ||
498 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) | |
499 | { | |
500 | uint32_t seprom_cntl1; | |
501 | uint32_t viph_control; | |
502 | uint32_t bus_cntl; | |
503 | uint32_t crtc_gen_cntl; | |
504 | uint32_t crtc2_gen_cntl; | |
505 | uint32_t crtc_ext_cntl; | |
506 | uint32_t fp2_gen_cntl; | |
507 | bool r; | |
508 | ||
509 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
510 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
4171424e AD |
511 | if (rdev->flags & RADEON_IS_PCIE) |
512 | bus_cntl = RREG32(RV370_BUS_CNTL); | |
513 | else | |
514 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
771fe6b9 JG |
515 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
516 | crtc2_gen_cntl = 0; | |
517 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); | |
518 | fp2_gen_cntl = 0; | |
519 | ||
ffbab09b | 520 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
521 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
522 | } | |
523 | ||
524 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
525 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
526 | } | |
527 | ||
528 | WREG32(RADEON_SEPROM_CNTL1, | |
529 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
530 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
531 | ||
532 | /* disable VIP */ | |
533 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
534 | ||
535 | /* enable the rom */ | |
4171424e AD |
536 | if (rdev->flags & RADEON_IS_PCIE) |
537 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); | |
538 | else | |
539 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
771fe6b9 JG |
540 | |
541 | /* Turn off mem requests and CRTC for both controllers */ | |
542 | WREG32(RADEON_CRTC_GEN_CNTL, | |
543 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | | |
544 | (RADEON_CRTC_DISP_REQ_EN_B | | |
545 | RADEON_CRTC_EXT_DISP_EN))); | |
546 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
547 | WREG32(RADEON_CRTC2_GEN_CNTL, | |
548 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | | |
549 | RADEON_CRTC2_DISP_REQ_EN_B)); | |
550 | } | |
551 | /* Turn off CRTC */ | |
552 | WREG32(RADEON_CRTC_EXT_CNTL, | |
553 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | | |
554 | (RADEON_CRTC_SYNC_TRISTAT | | |
555 | RADEON_CRTC_DISPLAY_DIS))); | |
556 | ||
ffbab09b | 557 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
558 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
559 | } | |
560 | ||
561 | r = radeon_read_bios(rdev); | |
562 | ||
563 | /* restore regs */ | |
564 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
565 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
4171424e AD |
566 | if (rdev->flags & RADEON_IS_PCIE) |
567 | WREG32(RV370_BUS_CNTL, bus_cntl); | |
568 | else | |
569 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
771fe6b9 JG |
570 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
571 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
572 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); | |
573 | } | |
574 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); | |
ffbab09b | 575 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
576 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
577 | } | |
578 | return r; | |
579 | } | |
580 | ||
581 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) | |
582 | { | |
b442962a AD |
583 | if (rdev->flags & RADEON_IS_IGP) |
584 | return igp_read_bios_from_vram(rdev); | |
c901bcdd AD |
585 | else if (rdev->family >= CHIP_BARTS) |
586 | return ni_read_disabled_bios(rdev); | |
b442962a | 587 | else if (rdev->family >= CHIP_RV770) |
771fe6b9 JG |
588 | return r700_read_disabled_bios(rdev); |
589 | else if (rdev->family >= CHIP_R600) | |
590 | return r600_read_disabled_bios(rdev); | |
591 | else if (rdev->family >= CHIP_RS600) | |
592 | return avivo_read_disabled_bios(rdev); | |
593 | else | |
594 | return legacy_read_disabled_bios(rdev); | |
595 | } | |
596 | ||
268ba0a9 DL |
597 | #ifdef CONFIG_ACPI |
598 | static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) | |
599 | { | |
600 | bool ret = false; | |
601 | struct acpi_table_header *hdr; | |
7c3906d0 | 602 | acpi_size tbl_size; |
268ba0a9 DL |
603 | UEFI_ACPI_VFCT *vfct; |
604 | GOP_VBIOS_CONTENT *vbios; | |
605 | VFCT_IMAGE_HEADER *vhdr; | |
606 | ||
7c3906d0 | 607 | if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) |
268ba0a9 DL |
608 | return false; |
609 | if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { | |
610 | DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); | |
611 | goto out_unmap; | |
612 | } | |
613 | ||
614 | vfct = (UEFI_ACPI_VFCT *)hdr; | |
615 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { | |
616 | DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); | |
617 | goto out_unmap; | |
618 | } | |
619 | ||
620 | vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); | |
621 | vhdr = &vbios->VbiosHeader; | |
622 | DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", | |
623 | vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, | |
624 | vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); | |
625 | ||
626 | if (vhdr->PCIBus != rdev->pdev->bus->number || | |
627 | vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || | |
628 | vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || | |
629 | vhdr->VendorID != rdev->pdev->vendor || | |
630 | vhdr->DeviceID != rdev->pdev->device) { | |
631 | DRM_INFO("ACPI VFCT table is not for this card\n"); | |
632 | goto out_unmap; | |
10d9b4ed | 633 | } |
268ba0a9 DL |
634 | |
635 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { | |
636 | DRM_ERROR("ACPI VFCT image truncated\n"); | |
637 | goto out_unmap; | |
638 | } | |
639 | ||
640 | rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); | |
641 | ret = !!rdev->bios; | |
642 | ||
643 | out_unmap: | |
268ba0a9 DL |
644 | return ret; |
645 | } | |
646 | #else | |
647 | static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) | |
648 | { | |
649 | return false; | |
650 | } | |
651 | #endif | |
6a9ee8af | 652 | |
771fe6b9 JG |
653 | bool radeon_get_bios(struct radeon_device *rdev) |
654 | { | |
655 | bool r; | |
656 | uint16_t tmp; | |
657 | ||
6a9ee8af | 658 | r = radeon_atrm_get_bios(rdev); |
268ba0a9 DL |
659 | if (r == false) |
660 | r = radeon_acpi_vfct_bios(rdev); | |
6a9ee8af | 661 | if (r == false) |
b442962a | 662 | r = igp_read_bios_from_vram(rdev); |
6a9ee8af | 663 | if (r == false) |
b442962a | 664 | r = radeon_read_bios(rdev); |
c9cb57fe | 665 | if (r == false) |
771fe6b9 | 666 | r = radeon_read_disabled_bios(rdev); |
c9cb57fe | 667 | if (r == false) |
06a08570 | 668 | r = radeon_read_platform_bios(rdev); |
771fe6b9 JG |
669 | if (r == false || rdev->bios == NULL) { |
670 | DRM_ERROR("Unable to locate a BIOS ROM\n"); | |
671 | rdev->bios = NULL; | |
672 | return false; | |
673 | } | |
674 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
6a9ee8af | 675 | printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); |
771fe6b9 JG |
676 | goto free_bios; |
677 | } | |
678 | ||
e3439895 DA |
679 | tmp = RBIOS16(0x18); |
680 | if (RBIOS8(tmp + 0x14) != 0x0) { | |
681 | DRM_INFO("Not an x86 BIOS ROM, not using.\n"); | |
682 | goto free_bios; | |
683 | } | |
684 | ||
771fe6b9 JG |
685 | rdev->bios_header_start = RBIOS16(0x48); |
686 | if (!rdev->bios_header_start) { | |
687 | goto free_bios; | |
688 | } | |
689 | tmp = rdev->bios_header_start + 4; | |
690 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || | |
691 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { | |
692 | rdev->is_atom_bios = true; | |
693 | } else { | |
694 | rdev->is_atom_bios = false; | |
695 | } | |
696 | ||
697 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); | |
698 | return true; | |
699 | free_bios: | |
700 | kfree(rdev->bios); | |
701 | rdev->bios = NULL; | |
702 | return false; | |
703 | } |