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drm/radeon/kms: don't set pcie lanes for ignored power_state
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 switch (table) {
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
157 if (check_offset)
158 offset = check_offset;
159 break;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
162 if (check_offset)
163 offset = check_offset;
164 break;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
167 if (check_offset)
168 offset = check_offset;
169 break;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
172 if (check_offset)
173 offset = check_offset;
174 break;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
177 if (check_offset)
178 offset = check_offset;
179 break;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
182 if (check_offset)
183 offset = check_offset;
184 break;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
187 if (check_offset)
188 offset = check_offset;
189 break;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
192 if (check_offset)
193 offset = check_offset;
194 break;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
197 if (check_offset)
198 offset = check_offset;
199 break;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
202 if (check_offset)
203 offset = check_offset;
204 break;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
207 if (check_offset)
208 offset = check_offset;
209 break;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
212 if (check_offset)
213 offset = check_offset;
214 break;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
217 if (check_offset)
218 offset = check_offset;
219 break;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
222 if (check_offset)
223 offset = check_offset;
224 break;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
227 if (check_offset)
228 offset = check_offset;
229 break;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
232 if (check_offset)
233 offset = check_offset;
234 break;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
237 if (check_offset)
238 offset = check_offset;
239 break;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
242 if (check_offset)
243 offset = check_offset;
244 break;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
247 if (check_offset)
248 offset = check_offset;
249 break;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
252 if (check_offset)
253 offset = check_offset;
254 break;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
257 if (check_offset)
258 offset = check_offset;
259 break;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
262 if (check_offset)
263 offset = check_offset;
264 break;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
267 if (check_offset)
268 offset = check_offset;
269 break;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
272 if (check_offset)
273 offset = check_offset;
274 break;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
277 if (check_offset)
278 offset = check_offset;
279 break;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
282 if (check_offset)
283 offset = check_offset;
284 break;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
287 if (check_offset)
288 offset = check_offset;
289 break;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
292 if (check_offset)
293 offset = check_offset;
294 break;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
297 if (check_offset)
298 offset = check_offset;
299 break;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
302 if (check_offset)
303 offset = check_offset;
304 break;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
307 if (check_offset)
308 offset = check_offset;
309 break;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
312 if (check_offset)
313 offset = check_offset;
314 break;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
317 if (check_offset)
318 offset = check_offset;
319 break;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
322 if (check_offset)
323 offset = check_offset;
324 break;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
327 check_offset =
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
329 if (check_offset) {
330 rev = RBIOS8(check_offset);
331 if (rev > 0) {
332 check_offset = RBIOS16(check_offset + 0x3);
333 if (check_offset)
334 offset = check_offset;
335 }
336 }
337 break;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
339 check_offset =
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
341 if (check_offset) {
342 rev = RBIOS8(check_offset);
343 if (rev > 0) {
344 check_offset = RBIOS16(check_offset + 0x5);
345 if (check_offset)
346 offset = check_offset;
347 }
348 }
349 break;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
351 check_offset =
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
353 if (check_offset) {
354 rev = RBIOS8(check_offset);
355 if (rev > 0) {
356 check_offset = RBIOS16(check_offset + 0x7);
357 if (check_offset)
358 offset = check_offset;
359 }
360 }
361 break;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
363 check_offset =
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
365 if (check_offset) {
366 rev = RBIOS8(check_offset);
367 if (rev == 2) {
368 check_offset = RBIOS16(check_offset + 0x9);
369 if (check_offset)
370 offset = check_offset;
371 }
372 }
373 break;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
375 check_offset =
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
377 if (check_offset) {
378 while (RBIOS8(check_offset++));
379 check_offset += 2;
380 if (check_offset)
381 offset = check_offset;
382 }
383 break;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
385 check_offset =
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
387 if (check_offset) {
388 check_offset = RBIOS16(check_offset + 0x11);
389 if (check_offset)
390 offset = check_offset;
391 }
392 break;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
394 check_offset =
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
396 if (check_offset) {
397 check_offset = RBIOS16(check_offset + 0x13);
398 if (check_offset)
399 offset = check_offset;
400 }
401 break;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
403 check_offset =
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
405 if (check_offset) {
406 check_offset = RBIOS16(check_offset + 0x15);
407 if (check_offset)
408 offset = check_offset;
409 }
410 break;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
412 check_offset =
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
414 if (check_offset) {
415 check_offset = RBIOS16(check_offset + 0x17);
416 if (check_offset)
417 offset = check_offset;
418 }
419 break;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
421 check_offset =
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
423 if (check_offset) {
424 check_offset = RBIOS16(check_offset + 0x2);
425 if (check_offset)
426 offset = check_offset;
427 }
428 break;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
430 check_offset =
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
432 if (check_offset) {
433 check_offset = RBIOS16(check_offset + 0x4);
434 if (check_offset)
435 offset = check_offset;
436 }
437 break;
438 default:
439 break;
440 }
441
442 return offset;
443
444}
445
3c537889
AD		 446bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
447{
448 int edid_info;
449 struct edid *edid;
450 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
451 if (!edid_info)
452 return false;
453
454 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
455 GFP_KERNEL);
456 if (edid == NULL)
457 return false;
458
459 memcpy((unsigned char *)edid,
460 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
461
462 if (!drm_edid_is_valid(edid)) {
463 kfree(edid);
464 return false;
465 }
466
467 rdev->mode_info.bios_hardcoded_edid = edid;
468 return true;
469}
470
471struct edid *
472radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
473{
474 if (rdev->mode_info.bios_hardcoded_edid)
475 return rdev->mode_info.bios_hardcoded_edid;
476 return NULL;
477}
478
6a93cb25
AD		 479static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
480 int ddc_line)
771fe6b9
JG		 481{
482 struct radeon_i2c_bus_rec i2c;
483
6a93cb25
AD		 484 if (ddc_line == RADEON_GPIOPAD_MASK) {
485 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
486 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
487 i2c.a_clk_reg = RADEON_GPIOPAD_A;
488 i2c.a_data_reg = RADEON_GPIOPAD_A;
489 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
490 i2c.en_data_reg = RADEON_GPIOPAD_EN;
491 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
492 i2c.y_data_reg = RADEON_GPIOPAD_Y;
493 } else if (ddc_line == RADEON_MDGPIO_MASK) {
494 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
495 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
496 i2c.a_clk_reg = RADEON_MDGPIO_A;
497 i2c.a_data_reg = RADEON_MDGPIO_A;
498 i2c.en_clk_reg = RADEON_MDGPIO_EN;
499 i2c.en_data_reg = RADEON_MDGPIO_EN;
500 i2c.y_clk_reg = RADEON_MDGPIO_Y;
501 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 502 } else {
6a93cb25
AD		 503 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
504 i2c.mask_data_mask = RADEON_GPIO_EN_0;
505 i2c.a_clk_mask = RADEON_GPIO_A_1;
506 i2c.a_data_mask = RADEON_GPIO_A_0;
507 i2c.en_clk_mask = RADEON_GPIO_EN_1;
508 i2c.en_data_mask = RADEON_GPIO_EN_0;
509 i2c.y_clk_mask = RADEON_GPIO_Y_1;
510 i2c.y_data_mask = RADEON_GPIO_Y_0;
511
771fe6b9
JG		 512 i2c.mask_clk_reg = ddc_line;
513 i2c.mask_data_reg = ddc_line;
514 i2c.a_clk_reg = ddc_line;
515 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 516 i2c.en_clk_reg = ddc_line;
517 i2c.en_data_reg = ddc_line;
518 i2c.y_clk_reg = ddc_line;
519 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 520 }
521
40bacf16
AD		 522 switch (rdev->family) {
523 case CHIP_R100:
524 case CHIP_RV100:
525 case CHIP_RS100:
526 case CHIP_RV200:
527 case CHIP_RS200:
528 case CHIP_RS300:
529 switch (ddc_line) {
530 case RADEON_GPIO_DVI_DDC:
531 /* in theory this should be hw capable,
532 * but it doesn't seem to work
533 */
534 i2c.hw_capable = false;
535 break;
536 default:
537 i2c.hw_capable = false;
538 break;
539 }
540 break;
541 case CHIP_R200:
542 switch (ddc_line) {
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
546 break;
547 default:
548 i2c.hw_capable = false;
549 break;
550 }
551 break;
552 case CHIP_RV250:
553 case CHIP_RV280:
554 switch (ddc_line) {
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R300:
566 case CHIP_R350:
567 switch (ddc_line) {
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
571 break;
572 default:
573 i2c.hw_capable = false;
574 break;
575 }
576 break;
577 case CHIP_RV350:
578 case CHIP_RV380:
579 case CHIP_RS400:
580 case CHIP_RS480:
6a93cb25
AD		 581 switch (ddc_line) {
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
585 break;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
589 */
590 i2c.hw_capable = false;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
40bacf16
AD		 596 break;
597 default:
598 i2c.hw_capable = false;
599 break;
6a93cb25
AD		 600 }
601 i2c.mm_i2c = false;
602 i2c.i2c_id = 0;
603
771fe6b9
JG		 604 if (ddc_line)
605 i2c.valid = true;
606 else
607 i2c.valid = false;
608
609 return i2c;
610}
611
612bool radeon_combios_get_clock_info(struct drm_device *dev)
613{
614 struct radeon_device *rdev = dev->dev_private;
615 uint16_t pll_info;
616 struct radeon_pll *p1pll = &rdev->clock.p1pll;
617 struct radeon_pll *p2pll = &rdev->clock.p2pll;
618 struct radeon_pll *spll = &rdev->clock.spll;
619 struct radeon_pll *mpll = &rdev->clock.mpll;
620 int8_t rev;
621 uint16_t sclk, mclk;
622
623 if (rdev->bios == NULL)
4b30b870 624 return false;
771fe6b9
JG		 625
626 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
627 if (pll_info) {
628 rev = RBIOS8(pll_info);
629
630 /* pixel clocks */
631 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
632 p1pll->reference_div = RBIOS16(pll_info + 0x10);
633 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
634 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
635
636 if (rev > 9) {
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
639 } else {
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
642 }
643 *p2pll = *p1pll;
644
645 /* system clock */
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
650
651 if (rev > 10) {
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
654 } else {
655 /* ??? */
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
658 }
659
660 /* memory clock */
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
665
666 if (rev > 10) {
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
669 } else {
670 /* ??? */
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
673 }
674
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
678 if (sclk == 0)
679 sclk = 200 * 100;
680 if (mclk == 0)
681 mclk = 200 * 100;
682
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
685
686 return true;
687 }
688 return false;
689}
690
06b6476d
AD		 691bool radeon_combios_sideport_present(struct radeon_device *rdev)
692{
693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info;
695
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697
698 if (igp_info) {
699 if (RBIOS16(igp_info + 0x4))
700 return true;
701 }
702 return false;
703}
704
246263cc
AD		 705static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
724};
725
726static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
728{
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
730 return;
731}
732
771fe6b9
JG		 733struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
734 radeon_encoder
735 *encoder)
736{
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
739 uint16_t dac_info;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 742 int found = 0;
771fe6b9 743
246263cc
AD		 744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
745 GFP_KERNEL);
746
747 if (!p_dac)
771fe6b9
JG		 748 return NULL;
749
246263cc
AD		 750 if (rdev->bios == NULL)
751 goto out;
752
771fe6b9
JG		 753 /* check CRT table */
754 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
755 if (dac_info) {
771fe6b9
JG		 756 rev = RBIOS8(dac_info) & 0x3;
757 if (rev < 2) {
758 bg = RBIOS8(dac_info + 0x2) & 0xf;
759 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
760 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
761 } else {
762 bg = RBIOS8(dac_info + 0x2) & 0xf;
763 dac = RBIOS8(dac_info + 0x3) & 0xf;
764 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
765 }
246263cc 766 found = 1;
771fe6b9
JG		 767 }
768
246263cc
AD		 769out:
770 if (!found) /* fallback to defaults */
771 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
772
771fe6b9
JG		 773 return p_dac;
774}
775
d79766fa
AD		 776enum radeon_tv_std
777radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 778{
d79766fa 779 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 780 uint16_t tv_info;
781 enum radeon_tv_std tv_std = TV_STD_NTSC;
782
11f3b59e
MD		 783 if (rdev->bios == NULL)
784 return tv_std;
785
771fe6b9
JG		 786 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
787 if (tv_info) {
788 if (RBIOS8(tv_info + 6) == 'T') {
789 switch (RBIOS8(tv_info + 7) & 0xf) {
790 case 1:
791 tv_std = TV_STD_NTSC;
792 DRM_INFO("Default TV standard: NTSC\n");
793 break;
794 case 2:
795 tv_std = TV_STD_PAL;
796 DRM_INFO("Default TV standard: PAL\n");
797 break;
798 case 3:
799 tv_std = TV_STD_PAL_M;
800 DRM_INFO("Default TV standard: PAL-M\n");
801 break;
802 case 4:
803 tv_std = TV_STD_PAL_60;
804 DRM_INFO("Default TV standard: PAL-60\n");
805 break;
806 case 5:
807 tv_std = TV_STD_NTSC_J;
808 DRM_INFO("Default TV standard: NTSC-J\n");
809 break;
810 case 6:
811 tv_std = TV_STD_SCART_PAL;
812 DRM_INFO("Default TV standard: SCART-PAL\n");
813 break;
814 default:
815 tv_std = TV_STD_NTSC;
816 DRM_INFO
817 ("Unknown TV standard; defaulting to NTSC\n");
818 break;
819 }
820
821 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
822 case 0:
823 DRM_INFO("29.498928713 MHz TV ref clk\n");
824 break;
825 case 1:
826 DRM_INFO("28.636360000 MHz TV ref clk\n");
827 break;
828 case 2:
829 DRM_INFO("14.318180000 MHz TV ref clk\n");
830 break;
831 case 3:
832 DRM_INFO("27.000000000 MHz TV ref clk\n");
833 break;
834 default:
835 break;
836 }
837 }
838 }
839 return tv_std;
840}
841
842static const uint32_t default_tvdac_adj[CHIP_LAST] = {
843 0x00000000, /* r100 */
844 0x00280000, /* rv100 */
845 0x00000000, /* rs100 */
846 0x00880000, /* rv200 */
847 0x00000000, /* rs200 */
848 0x00000000, /* r200 */
849 0x00770000, /* rv250 */
850 0x00290000, /* rs300 */
851 0x00560000, /* rv280 */
852 0x00780000, /* r300 */
853 0x00770000, /* r350 */
854 0x00780000, /* rv350 */
855 0x00780000, /* rv380 */
856 0x01080000, /* r420 */
857 0x01080000, /* r423 */
858 0x01080000, /* rv410 */
859 0x00780000, /* rs400 */
860 0x00780000, /* rs480 */
861};
862
6a719e05
DA		 863static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
864 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 865{
771fe6b9
JG		 866 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
867 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
868 tv_dac->ps2_tvdac_adj = 0x00880000;
869 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
870 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 871 return;
771fe6b9
JG		 872}
873
874struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
875 radeon_encoder
876 *encoder)
877{
878 struct drm_device *dev = encoder->base.dev;
879 struct radeon_device *rdev = dev->dev_private;
880 uint16_t dac_info;
881 uint8_t rev, bg, dac;
882 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 883 int found = 0;
884
885 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
886 if (!tv_dac)
887 return NULL;
771fe6b9
JG		 888
889 if (rdev->bios == NULL)
6a719e05 890 goto out;
771fe6b9
JG		 891
892 /* first check TV table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
894 if (dac_info) {
771fe6b9
JG		 895 rev = RBIOS8(dac_info + 0x3);
896 if (rev > 4) {
897 bg = RBIOS8(dac_info + 0xc) & 0xf;
898 dac = RBIOS8(dac_info + 0xd) & 0xf;
899 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
900
901 bg = RBIOS8(dac_info + 0xe) & 0xf;
902 dac = RBIOS8(dac_info + 0xf) & 0xf;
903 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
904
905 bg = RBIOS8(dac_info + 0x10) & 0xf;
906 dac = RBIOS8(dac_info + 0x11) & 0xf;
907 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 908 found = 1;
771fe6b9
JG		 909 } else if (rev > 1) {
910 bg = RBIOS8(dac_info + 0xc) & 0xf;
911 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
912 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
913
914 bg = RBIOS8(dac_info + 0xd) & 0xf;
915 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
916 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
917
918 bg = RBIOS8(dac_info + 0xe) & 0xf;
919 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
920 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 921 found = 1;
771fe6b9 922 }
d79766fa 923 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 924 }
925 if (!found) {
771fe6b9
JG		 926 /* then check CRT table */
927 dac_info =
928 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
929 if (dac_info) {
771fe6b9
JG		 930 rev = RBIOS8(dac_info) & 0x3;
931 if (rev < 2) {
932 bg = RBIOS8(dac_info + 0x3) & 0xf;
933 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
934 tv_dac->ps2_tvdac_adj =
935 (bg << 16) | (dac << 20);
936 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
937 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 938 found = 1;
771fe6b9
JG		 939 } else {
940 bg = RBIOS8(dac_info + 0x4) & 0xf;
941 dac = RBIOS8(dac_info + 0x5) & 0xf;
942 tv_dac->ps2_tvdac_adj =
943 (bg << 16) | (dac << 20);
944 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
945 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 946 found = 1;
771fe6b9 947 }
6fe7ac3f
AD		 948 } else {
949 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 950 }
951 }
952
6a719e05
DA		 953out:
954 if (!found) /* fallback to defaults */
955 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
956
771fe6b9
JG		 957 return tv_dac;
958}
959
960static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
961 radeon_device
962 *rdev)
963{
964 struct radeon_encoder_lvds *lvds = NULL;
965 uint32_t fp_vert_stretch, fp_horz_stretch;
966 uint32_t ppll_div_sel, ppll_val;
8b5c7444 967 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 968
969 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
970
971 if (!lvds)
972 return NULL;
973
974 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
975 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
976
8b5c7444
MD		 977 /* These should be fail-safe defaults, fingers crossed */
978 lvds->panel_pwr_delay = 200;
979 lvds->panel_vcc_delay = 2000;
980
981 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
982 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
983 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
984
771fe6b9 985 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 986 lvds->native_mode.vdisplay =
771fe6b9
JG		 987 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
988 RADEON_VERT_PANEL_SHIFT) + 1;
989 else
de2103e4 990 lvds->native_mode.vdisplay =
771fe6b9
JG		 991 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
992
993 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 994 lvds->native_mode.hdisplay =
771fe6b9
JG		 995 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
996 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
997 else
de2103e4 998 lvds->native_mode.hdisplay =
771fe6b9
JG		 999 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1000
de2103e4
AD		 1001 if ((lvds->native_mode.hdisplay < 640) ||
1002 (lvds->native_mode.vdisplay < 480)) {
1003 lvds->native_mode.hdisplay = 640;
1004 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1005 }
1006
1007 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1008 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1009 if ((ppll_val & 0x000707ff) == 0x1bb)
1010 lvds->use_bios_dividers = false;
1011 else {
1012 lvds->panel_ref_divider =
1013 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1014 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1015 lvds->panel_fb_divider = ppll_val & 0x7ff;
1016
1017 if ((lvds->panel_ref_divider != 0) &&
1018 (lvds->panel_fb_divider > 3))
1019 lvds->use_bios_dividers = true;
1020 }
1021 lvds->panel_vcc_delay = 200;
1022
1023 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1024 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1025 lvds->native_mode.vdisplay);
771fe6b9
JG		 1026
1027 return lvds;
1028}
1029
1030struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1031 *encoder)
1032{
1033 struct drm_device *dev = encoder->base.dev;
1034 struct radeon_device *rdev = dev->dev_private;
1035 uint16_t lcd_info;
1036 uint32_t panel_setup;
1037 char stmp[30];
1038 int tmp, i;
1039 struct radeon_encoder_lvds *lvds = NULL;
1040
8dfaa8a7
MD		 1041 if (rdev->bios == NULL) {
1042 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1043 goto out;
1044 }
771fe6b9
JG		 1045
1046 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1047
1048 if (lcd_info) {
1049 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1050
1051 if (!lvds)
1052 return NULL;
1053
1054 for (i = 0; i < 24; i++)
1055 stmp[i] = RBIOS8(lcd_info + i + 1);
1056 stmp[24] = 0;
1057
1058 DRM_INFO("Panel ID String: %s\n", stmp);
1059
de2103e4
AD		 1060 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1061 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1062
de2103e4
AD		 1063 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1064 lvds->native_mode.vdisplay);
771fe6b9
JG		 1065
1066 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1067 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1068
1069 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1070 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1071 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1072
1073 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1074 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1075 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1076 if ((lvds->panel_ref_divider != 0) &&
1077 (lvds->panel_fb_divider > 3))
1078 lvds->use_bios_dividers = true;
1079
1080 panel_setup = RBIOS32(lcd_info + 0x39);
1081 lvds->lvds_gen_cntl = 0xff00;
1082 if (panel_setup & 0x1)
1083 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1084
1085 if ((panel_setup >> 4) & 0x1)
1086 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1087
1088 switch ((panel_setup >> 8) & 0x7) {
1089 case 0:
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1091 break;
1092 case 1:
1093 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1094 break;
1095 case 2:
1096 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1097 break;
1098 default:
1099 break;
1100 }
1101
1102 if ((panel_setup >> 16) & 0x1)
1103 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1104
1105 if ((panel_setup >> 17) & 0x1)
1106 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1107
1108 if ((panel_setup >> 18) & 0x1)
1109 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1110
1111 if ((panel_setup >> 23) & 0x1)
1112 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1113
1114 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1115
1116 for (i = 0; i < 32; i++) {
1117 tmp = RBIOS16(lcd_info + 64 + i * 2);
1118 if (tmp == 0)
1119 break;
1120
de2103e4 1121 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 1122 (RBIOS16(tmp + 2) ==
de2103e4
AD		 1123 lvds->native_mode.vdisplay)) {
1124 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1125 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1126 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1127 RBIOS16(tmp + 21)) * 8;
1128
1129 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1130 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1131 lvds->native_mode.vsync_end =
1132 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1133 (RBIOS16(tmp + 28) & 0x7ff);
1134
1135 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1136 lvds->native_mode.flags = 0;
de2103e4
AD		 1137 /* set crtc values */
1138 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1139
771fe6b9
JG		 1140 }
1141 }
6fe7ac3f 1142 } else {
771fe6b9 1143 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1144 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1145 }
8dfaa8a7
MD		 1146out:
1147 if (lvds)
1148 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1149 return lvds;
1150}
1151
1152static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1154 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1155 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1156 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1157 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1158 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1159 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1160 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1161 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1164 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1165 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1166 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1167 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1168 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1169 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1170 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1171};
1172
445282db
DA		 1173bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1174 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1175{
445282db
DA		 1176 struct drm_device *dev = encoder->base.dev;
1177 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1178 int i;
771fe6b9
JG		 1179
1180 for (i = 0; i < 4; i++) {
1181 tmds->tmds_pll[i].value =
445282db 1182 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1183 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1184 }
1185
445282db 1186 return true;
771fe6b9
JG		 1187}
1188
445282db
DA		 1189bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1190 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1191{
1192 struct drm_device *dev = encoder->base.dev;
1193 struct radeon_device *rdev = dev->dev_private;
1194 uint16_t tmds_info;
1195 int i, n;
1196 uint8_t ver;
771fe6b9
JG		 1197
1198 if (rdev->bios == NULL)
445282db 1199 return false;
771fe6b9
JG		 1200
1201 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1202
1203 if (tmds_info) {
771fe6b9
JG		 1204 ver = RBIOS8(tmds_info);
1205 DRM_INFO("DFP table revision: %d\n", ver);
1206 if (ver == 3) {
1207 n = RBIOS8(tmds_info + 5) + 1;
1208 if (n > 4)
1209 n = 4;
1210 for (i = 0; i < n; i++) {
1211 tmds->tmds_pll[i].value =
1212 RBIOS32(tmds_info + i * 10 + 0x08);
1213 tmds->tmds_pll[i].freq =
1214 RBIOS16(tmds_info + i * 10 + 0x10);
1215 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1216 tmds->tmds_pll[i].freq,
1217 tmds->tmds_pll[i].value);
1218 }
1219 } else if (ver == 4) {
1220 int stride = 0;
1221 n = RBIOS8(tmds_info + 5) + 1;
1222 if (n > 4)
1223 n = 4;
1224 for (i = 0; i < n; i++) {
1225 tmds->tmds_pll[i].value =
1226 RBIOS32(tmds_info + stride + 0x08);
1227 tmds->tmds_pll[i].freq =
1228 RBIOS16(tmds_info + stride + 0x10);
1229 if (i == 0)
1230 stride += 10;
1231 else
1232 stride += 6;
1233 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1234 tmds->tmds_pll[i].freq,
1235 tmds->tmds_pll[i].value);
1236 }
1237 }
fcec570b 1238 } else {
771fe6b9 1239 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1240 return false;
1241 }
445282db
DA		 1242 return true;
1243}
1244
fcec570b
AD		 1245bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1246 struct radeon_encoder_ext_tmds *tmds)
445282db 1247{
fcec570b
AD		 1248 struct drm_device *dev = encoder->base.dev;
1249 struct radeon_device *rdev = dev->dev_private;
1250 struct radeon_i2c_bus_rec i2c_bus;
445282db 1251
fcec570b 1252 /* default for macs */
6a93cb25 1253 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1254 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1255
fcec570b
AD		 1256 /* XXX some macs have duallink chips */
1257 switch (rdev->mode_info.connector_table) {
1258 case CT_POWERBOOK_EXTERNAL:
1259 case CT_MINI_EXTERNAL:
1260 default:
1261 tmds->dvo_chip = DVO_SIL164;
1262 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1263 break;
1264 }
445282db 1265
fcec570b 1266 return true;
771fe6b9
JG		 1267}
1268
fcec570b
AD		 1269bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1270 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1271{
1272 struct drm_device *dev = encoder->base.dev;
1273 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1274 uint16_t offset;
1275 uint8_t ver, id, blocks, clk, data;
1276 int i;
1277 enum radeon_combios_ddc gpio;
1278 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1279
1280 if (rdev->bios == NULL)
fcec570b 1281 return false;
771fe6b9 1282
fcec570b
AD		 1283 tmds->i2c_bus = NULL;
1284 if (rdev->flags & RADEON_IS_IGP) {
1285 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1286 if (offset) {
1287 ver = RBIOS8(offset);
1288 DRM_INFO("GPIO Table revision: %d\n", ver);
1289 blocks = RBIOS8(offset + 2);
1290 for (i = 0; i < blocks; i++) {
1291 id = RBIOS8(offset + 3 + (i * 5) + 0);
1292 if (id == 136) {
1293 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1294 data = RBIOS8(offset + 3 + (i * 5) + 4);
1295 i2c_bus.valid = true;
1296 i2c_bus.mask_clk_mask = (1 << clk);
1297 i2c_bus.mask_data_mask = (1 << data);
1298 i2c_bus.a_clk_mask = (1 << clk);
1299 i2c_bus.a_data_mask = (1 << data);
1300 i2c_bus.en_clk_mask = (1 << clk);
1301 i2c_bus.en_data_mask = (1 << data);
1302 i2c_bus.y_clk_mask = (1 << clk);
1303 i2c_bus.y_data_mask = (1 << data);
1304 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1305 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1306 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1307 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1308 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1309 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1310 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1311 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1312 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1313 tmds->dvo_chip = DVO_SIL164;
1314 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1315 break;
1316 }
1317 }
1318 }
1319 } else {
1320 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1321 if (offset) {
1322 ver = RBIOS8(offset);
1323 DRM_INFO("External TMDS Table revision: %d\n", ver);
1324 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1325 tmds->slave_addr >>= 1; /* 7 bit addressing */
1326 gpio = RBIOS8(offset + 4 + 3);
1327 switch (gpio) {
1328 case DDC_MONID:
6a93cb25 1329 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1330 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1331 break;
1332 case DDC_DVI:
6a93cb25 1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1334 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1335 break;
1336 case DDC_VGA:
6a93cb25 1337 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1338 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1339 break;
1340 case DDC_CRT2:
1341 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1342 if (rdev->family >= CHIP_R300)
6a93cb25 1343 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1344 else
6a93cb25 1345 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1346 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1347 break;
1348 case DDC_LCD: /* MM i2c */
40bacf16
AD		 1349 i2c_bus.valid = true;
1350 i2c_bus.hw_capable = true;
1351 i2c_bus.mm_i2c = true;
1352 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
fcec570b
AD		 1353 break;
1354 default:
1355 DRM_ERROR("Unsupported gpio %d\n", gpio);
1356 break;
1357 }
1358 }
771fe6b9 1359 }
fcec570b
AD		 1360
1361 if (!tmds->i2c_bus) {
1362 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1363 return false;
1364 }
1365
1366 return true;
771fe6b9
JG		 1367}
1368
1369bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1370{
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1373 struct radeon_hpd hpd;
771fe6b9
JG		 1374
1375 rdev->mode_info.connector_table = radeon_connector_table;
1376 if (rdev->mode_info.connector_table == CT_NONE) {
1377#ifdef CONFIG_PPC_PMAC
1378 if (machine_is_compatible("PowerBook3,3")) {
1379 /* powerbook with VGA */
1380 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1381 } else if (machine_is_compatible("PowerBook3,4") ||
1382 machine_is_compatible("PowerBook3,5")) {
1383 /* powerbook with internal tmds */
1384 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1385 } else if (machine_is_compatible("PowerBook5,1") ||
1386 machine_is_compatible("PowerBook5,2") ||
1387 machine_is_compatible("PowerBook5,3") ||
1388 machine_is_compatible("PowerBook5,4") ||
1389 machine_is_compatible("PowerBook5,5")) {
1390 /* powerbook with external single link tmds (sil164) */
1391 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1392 } else if (machine_is_compatible("PowerBook5,6")) {
1393 /* powerbook with external dual or single link tmds */
1394 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1395 } else if (machine_is_compatible("PowerBook5,7") ||
1396 machine_is_compatible("PowerBook5,8") ||
1397 machine_is_compatible("PowerBook5,9")) {
1398 /* PowerBook6,2 ? */
1399 /* powerbook with external dual link tmds (sil1178?) */
1400 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1401 } else if (machine_is_compatible("PowerBook4,1") ||
1402 machine_is_compatible("PowerBook4,2") ||
1403 machine_is_compatible("PowerBook4,3") ||
1404 machine_is_compatible("PowerBook6,3") ||
1405 machine_is_compatible("PowerBook6,5") ||
1406 machine_is_compatible("PowerBook6,7")) {
1407 /* ibook */
1408 rdev->mode_info.connector_table = CT_IBOOK;
1409 } else if (machine_is_compatible("PowerMac4,4")) {
1410 /* emac */
1411 rdev->mode_info.connector_table = CT_EMAC;
1412 } else if (machine_is_compatible("PowerMac10,1")) {
1413 /* mini with internal tmds */
1414 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1415 } else if (machine_is_compatible("PowerMac10,2")) {
1416 /* mini with external tmds */
1417 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1418 } else if (machine_is_compatible("PowerMac12,1")) {
1419 /* PowerMac8,1 ? */
1420 /* imac g5 isight */
1421 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1422 } else
1423#endif /* CONFIG_PPC_PMAC */
1424 rdev->mode_info.connector_table = CT_GENERIC;
1425 }
1426
1427 switch (rdev->mode_info.connector_table) {
1428 case CT_GENERIC:
1429 DRM_INFO("Connector Table: %d (generic)\n",
1430 rdev->mode_info.connector_table);
1431 /* these are the most common settings */
1432 if (rdev->flags & RADEON_SINGLE_CRTC) {
1433 /* VGA - primary dac */
6a93cb25 1434 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1435 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1436 radeon_add_legacy_encoder(dev,
1437 radeon_get_encoder_id(dev,
1438 ATOM_DEVICE_CRT1_SUPPORT,
1439 1),
1440 ATOM_DEVICE_CRT1_SUPPORT);
1441 radeon_add_legacy_connector(dev, 0,
1442 ATOM_DEVICE_CRT1_SUPPORT,
1443 DRM_MODE_CONNECTOR_VGA,
b75fad06 1444 &ddc_i2c,
eed45b30
AD		 1445 CONNECTOR_OBJECT_ID_VGA,
1446 &hpd);
771fe6b9
JG		 1447 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1448 /* LVDS */
6a93cb25 1449 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1450 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1451 radeon_add_legacy_encoder(dev,
1452 radeon_get_encoder_id(dev,
1453 ATOM_DEVICE_LCD1_SUPPORT,
1454 0),
1455 ATOM_DEVICE_LCD1_SUPPORT);
1456 radeon_add_legacy_connector(dev, 0,
1457 ATOM_DEVICE_LCD1_SUPPORT,
1458 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1459 &ddc_i2c,
eed45b30
AD		 1460 CONNECTOR_OBJECT_ID_LVDS,
1461 &hpd);
771fe6b9
JG		 1462
1463 /* VGA - primary dac */
6a93cb25 1464 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1465 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1466 radeon_add_legacy_encoder(dev,
1467 radeon_get_encoder_id(dev,
1468 ATOM_DEVICE_CRT1_SUPPORT,
1469 1),
1470 ATOM_DEVICE_CRT1_SUPPORT);
1471 radeon_add_legacy_connector(dev, 1,
1472 ATOM_DEVICE_CRT1_SUPPORT,
1473 DRM_MODE_CONNECTOR_VGA,
b75fad06 1474 &ddc_i2c,
eed45b30
AD		 1475 CONNECTOR_OBJECT_ID_VGA,
1476 &hpd);
771fe6b9
JG		 1477 } else {
1478 /* DVI-I - tv dac, int tmds */
6a93cb25 1479 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1480 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1481 radeon_add_legacy_encoder(dev,
1482 radeon_get_encoder_id(dev,
1483 ATOM_DEVICE_DFP1_SUPPORT,
1484 0),
1485 ATOM_DEVICE_DFP1_SUPPORT);
1486 radeon_add_legacy_encoder(dev,
1487 radeon_get_encoder_id(dev,
1488 ATOM_DEVICE_CRT2_SUPPORT,
1489 2),
1490 ATOM_DEVICE_CRT2_SUPPORT);
1491 radeon_add_legacy_connector(dev, 0,
1492 ATOM_DEVICE_DFP1_SUPPORT |
1493 ATOM_DEVICE_CRT2_SUPPORT,
1494 DRM_MODE_CONNECTOR_DVII,
b75fad06 1495 &ddc_i2c,
eed45b30
AD		 1496 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1497 &hpd);
771fe6b9
JG		 1498
1499 /* VGA - primary dac */
6a93cb25 1500 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1501 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1502 radeon_add_legacy_encoder(dev,
1503 radeon_get_encoder_id(dev,
1504 ATOM_DEVICE_CRT1_SUPPORT,
1505 1),
1506 ATOM_DEVICE_CRT1_SUPPORT);
1507 radeon_add_legacy_connector(dev, 1,
1508 ATOM_DEVICE_CRT1_SUPPORT,
1509 DRM_MODE_CONNECTOR_VGA,
b75fad06 1510 &ddc_i2c,
eed45b30
AD		 1511 CONNECTOR_OBJECT_ID_VGA,
1512 &hpd);
771fe6b9
JG		 1513 }
1514
1515 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1516 /* TV - tv dac */
eed45b30
AD		 1517 ddc_i2c.valid = false;
1518 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1519 radeon_add_legacy_encoder(dev,
1520 radeon_get_encoder_id(dev,
1521 ATOM_DEVICE_TV1_SUPPORT,
1522 2),
1523 ATOM_DEVICE_TV1_SUPPORT);
1524 radeon_add_legacy_connector(dev, 2,
1525 ATOM_DEVICE_TV1_SUPPORT,
1526 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1527 &ddc_i2c,
eed45b30
AD		 1528 CONNECTOR_OBJECT_ID_SVIDEO,
1529 &hpd);
771fe6b9
JG		 1530 }
1531 break;
1532 case CT_IBOOK:
1533 DRM_INFO("Connector Table: %d (ibook)\n",
1534 rdev->mode_info.connector_table);
1535 /* LVDS */
6a93cb25 1536 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1537 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1538 radeon_add_legacy_encoder(dev,
1539 radeon_get_encoder_id(dev,
1540 ATOM_DEVICE_LCD1_SUPPORT,
1541 0),
1542 ATOM_DEVICE_LCD1_SUPPORT);
1543 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1544 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1545 CONNECTOR_OBJECT_ID_LVDS,
1546 &hpd);
771fe6b9 1547 /* VGA - TV DAC */
6a93cb25 1548 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1549 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1550 radeon_add_legacy_encoder(dev,
1551 radeon_get_encoder_id(dev,
1552 ATOM_DEVICE_CRT2_SUPPORT,
1553 2),
1554 ATOM_DEVICE_CRT2_SUPPORT);
1555 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1556 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1557 CONNECTOR_OBJECT_ID_VGA,
1558 &hpd);
771fe6b9 1559 /* TV - TV DAC */
eed45b30
AD		 1560 ddc_i2c.valid = false;
1561 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1562 radeon_add_legacy_encoder(dev,
1563 radeon_get_encoder_id(dev,
1564 ATOM_DEVICE_TV1_SUPPORT,
1565 2),
1566 ATOM_DEVICE_TV1_SUPPORT);
1567 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1568 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1569 &ddc_i2c,
eed45b30
AD		 1570 CONNECTOR_OBJECT_ID_SVIDEO,
1571 &hpd);
771fe6b9
JG		 1572 break;
1573 case CT_POWERBOOK_EXTERNAL:
1574 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1575 rdev->mode_info.connector_table);
1576 /* LVDS */
6a93cb25 1577 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1578 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1579 radeon_add_legacy_encoder(dev,
1580 radeon_get_encoder_id(dev,
1581 ATOM_DEVICE_LCD1_SUPPORT,
1582 0),
1583 ATOM_DEVICE_LCD1_SUPPORT);
1584 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1585 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1586 CONNECTOR_OBJECT_ID_LVDS,
1587 &hpd);
771fe6b9 1588 /* DVI-I - primary dac, ext tmds */
6a93cb25 1589 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1590 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1591 radeon_add_legacy_encoder(dev,
1592 radeon_get_encoder_id(dev,
1593 ATOM_DEVICE_DFP2_SUPPORT,
1594 0),
1595 ATOM_DEVICE_DFP2_SUPPORT);
1596 radeon_add_legacy_encoder(dev,
1597 radeon_get_encoder_id(dev,
1598 ATOM_DEVICE_CRT1_SUPPORT,
1599 1),
1600 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1601 /* XXX some are SL */
771fe6b9
JG		 1602 radeon_add_legacy_connector(dev, 1,
1603 ATOM_DEVICE_DFP2_SUPPORT |
1604 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1605 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1606 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1607 &hpd);
771fe6b9 1608 /* TV - TV DAC */
eed45b30
AD		 1609 ddc_i2c.valid = false;
1610 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1611 radeon_add_legacy_encoder(dev,
1612 radeon_get_encoder_id(dev,
1613 ATOM_DEVICE_TV1_SUPPORT,
1614 2),
1615 ATOM_DEVICE_TV1_SUPPORT);
1616 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1617 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1618 &ddc_i2c,
eed45b30
AD		 1619 CONNECTOR_OBJECT_ID_SVIDEO,
1620 &hpd);
771fe6b9
JG		 1621 break;
1622 case CT_POWERBOOK_INTERNAL:
1623 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1624 rdev->mode_info.connector_table);
1625 /* LVDS */
6a93cb25 1626 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1627 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1628 radeon_add_legacy_encoder(dev,
1629 radeon_get_encoder_id(dev,
1630 ATOM_DEVICE_LCD1_SUPPORT,
1631 0),
1632 ATOM_DEVICE_LCD1_SUPPORT);
1633 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1634 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1635 CONNECTOR_OBJECT_ID_LVDS,
1636 &hpd);
771fe6b9 1637 /* DVI-I - primary dac, int tmds */
6a93cb25 1638 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1639 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1640 radeon_add_legacy_encoder(dev,
1641 radeon_get_encoder_id(dev,
1642 ATOM_DEVICE_DFP1_SUPPORT,
1643 0),
1644 ATOM_DEVICE_DFP1_SUPPORT);
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_id(dev,
1647 ATOM_DEVICE_CRT1_SUPPORT,
1648 1),
1649 ATOM_DEVICE_CRT1_SUPPORT);
1650 radeon_add_legacy_connector(dev, 1,
1651 ATOM_DEVICE_DFP1_SUPPORT |
1652 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1653 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1654 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1655 &hpd);
771fe6b9 1656 /* TV - TV DAC */
eed45b30
AD		 1657 ddc_i2c.valid = false;
1658 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1659 radeon_add_legacy_encoder(dev,
1660 radeon_get_encoder_id(dev,
1661 ATOM_DEVICE_TV1_SUPPORT,
1662 2),
1663 ATOM_DEVICE_TV1_SUPPORT);
1664 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1665 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1666 &ddc_i2c,
eed45b30
AD		 1667 CONNECTOR_OBJECT_ID_SVIDEO,
1668 &hpd);
771fe6b9
JG		 1669 break;
1670 case CT_POWERBOOK_VGA:
1671 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1672 rdev->mode_info.connector_table);
1673 /* LVDS */
6a93cb25 1674 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1675 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1676 radeon_add_legacy_encoder(dev,
1677 radeon_get_encoder_id(dev,
1678 ATOM_DEVICE_LCD1_SUPPORT,
1679 0),
1680 ATOM_DEVICE_LCD1_SUPPORT);
1681 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1682 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1683 CONNECTOR_OBJECT_ID_LVDS,
1684 &hpd);
771fe6b9 1685 /* VGA - primary dac */
6a93cb25 1686 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1687 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1688 radeon_add_legacy_encoder(dev,
1689 radeon_get_encoder_id(dev,
1690 ATOM_DEVICE_CRT1_SUPPORT,
1691 1),
1692 ATOM_DEVICE_CRT1_SUPPORT);
1693 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1694 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1695 CONNECTOR_OBJECT_ID_VGA,
1696 &hpd);
771fe6b9 1697 /* TV - TV DAC */
eed45b30
AD		 1698 ddc_i2c.valid = false;
1699 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1700 radeon_add_legacy_encoder(dev,
1701 radeon_get_encoder_id(dev,
1702 ATOM_DEVICE_TV1_SUPPORT,
1703 2),
1704 ATOM_DEVICE_TV1_SUPPORT);
1705 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1706 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1707 &ddc_i2c,
eed45b30
AD		 1708 CONNECTOR_OBJECT_ID_SVIDEO,
1709 &hpd);
771fe6b9
JG		 1710 break;
1711 case CT_MINI_EXTERNAL:
1712 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1713 rdev->mode_info.connector_table);
1714 /* DVI-I - tv dac, ext tmds */
6a93cb25 1715 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1716 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1717 radeon_add_legacy_encoder(dev,
1718 radeon_get_encoder_id(dev,
1719 ATOM_DEVICE_DFP2_SUPPORT,
1720 0),
1721 ATOM_DEVICE_DFP2_SUPPORT);
1722 radeon_add_legacy_encoder(dev,
1723 radeon_get_encoder_id(dev,
1724 ATOM_DEVICE_CRT2_SUPPORT,
1725 2),
1726 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1727 /* XXX are any DL? */
771fe6b9
JG		 1728 radeon_add_legacy_connector(dev, 0,
1729 ATOM_DEVICE_DFP2_SUPPORT |
1730 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1731 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1732 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1733 &hpd);
771fe6b9 1734 /* TV - TV DAC */
eed45b30
AD		 1735 ddc_i2c.valid = false;
1736 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1737 radeon_add_legacy_encoder(dev,
1738 radeon_get_encoder_id(dev,
1739 ATOM_DEVICE_TV1_SUPPORT,
1740 2),
1741 ATOM_DEVICE_TV1_SUPPORT);
1742 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1743 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1744 &ddc_i2c,
eed45b30
AD		 1745 CONNECTOR_OBJECT_ID_SVIDEO,
1746 &hpd);
771fe6b9
JG		 1747 break;
1748 case CT_MINI_INTERNAL:
1749 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1750 rdev->mode_info.connector_table);
1751 /* DVI-I - tv dac, int tmds */
6a93cb25 1752 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1753 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_id(dev,
1756 ATOM_DEVICE_DFP1_SUPPORT,
1757 0),
1758 ATOM_DEVICE_DFP1_SUPPORT);
1759 radeon_add_legacy_encoder(dev,
1760 radeon_get_encoder_id(dev,
1761 ATOM_DEVICE_CRT2_SUPPORT,
1762 2),
1763 ATOM_DEVICE_CRT2_SUPPORT);
1764 radeon_add_legacy_connector(dev, 0,
1765 ATOM_DEVICE_DFP1_SUPPORT |
1766 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1767 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1768 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1769 &hpd);
771fe6b9 1770 /* TV - TV DAC */
eed45b30
AD		 1771 ddc_i2c.valid = false;
1772 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1773 radeon_add_legacy_encoder(dev,
1774 radeon_get_encoder_id(dev,
1775 ATOM_DEVICE_TV1_SUPPORT,
1776 2),
1777 ATOM_DEVICE_TV1_SUPPORT);
1778 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1779 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1780 &ddc_i2c,
eed45b30
AD		 1781 CONNECTOR_OBJECT_ID_SVIDEO,
1782 &hpd);
771fe6b9
JG		 1783 break;
1784 case CT_IMAC_G5_ISIGHT:
1785 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1786 rdev->mode_info.connector_table);
1787 /* DVI-D - int tmds */
6a93cb25 1788 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1789 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1790 radeon_add_legacy_encoder(dev,
1791 radeon_get_encoder_id(dev,
1792 ATOM_DEVICE_DFP1_SUPPORT,
1793 0),
1794 ATOM_DEVICE_DFP1_SUPPORT);
1795 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1796 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1797 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1798 &hpd);
771fe6b9 1799 /* VGA - tv dac */
6a93cb25 1800 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1801 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1802 radeon_add_legacy_encoder(dev,
1803 radeon_get_encoder_id(dev,
1804 ATOM_DEVICE_CRT2_SUPPORT,
1805 2),
1806 ATOM_DEVICE_CRT2_SUPPORT);
1807 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1808 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1809 CONNECTOR_OBJECT_ID_VGA,
1810 &hpd);
771fe6b9 1811 /* TV - TV DAC */
eed45b30
AD		 1812 ddc_i2c.valid = false;
1813 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1814 radeon_add_legacy_encoder(dev,
1815 radeon_get_encoder_id(dev,
1816 ATOM_DEVICE_TV1_SUPPORT,
1817 2),
1818 ATOM_DEVICE_TV1_SUPPORT);
1819 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1820 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1821 &ddc_i2c,
eed45b30
AD		 1822 CONNECTOR_OBJECT_ID_SVIDEO,
1823 &hpd);
771fe6b9
JG		 1824 break;
1825 case CT_EMAC:
1826 DRM_INFO("Connector Table: %d (emac)\n",
1827 rdev->mode_info.connector_table);
1828 /* VGA - primary dac */
6a93cb25 1829 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1830 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1831 radeon_add_legacy_encoder(dev,
1832 radeon_get_encoder_id(dev,
1833 ATOM_DEVICE_CRT1_SUPPORT,
1834 1),
1835 ATOM_DEVICE_CRT1_SUPPORT);
1836 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1837 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1838 CONNECTOR_OBJECT_ID_VGA,
1839 &hpd);
771fe6b9 1840 /* VGA - tv dac */
6a93cb25 1841 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1842 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1843 radeon_add_legacy_encoder(dev,
1844 radeon_get_encoder_id(dev,
1845 ATOM_DEVICE_CRT2_SUPPORT,
1846 2),
1847 ATOM_DEVICE_CRT2_SUPPORT);
1848 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1849 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1850 CONNECTOR_OBJECT_ID_VGA,
1851 &hpd);
771fe6b9 1852 /* TV - TV DAC */
eed45b30
AD		 1853 ddc_i2c.valid = false;
1854 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1855 radeon_add_legacy_encoder(dev,
1856 radeon_get_encoder_id(dev,
1857 ATOM_DEVICE_TV1_SUPPORT,
1858 2),
1859 ATOM_DEVICE_TV1_SUPPORT);
1860 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1861 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1862 &ddc_i2c,
eed45b30
AD		 1863 CONNECTOR_OBJECT_ID_SVIDEO,
1864 &hpd);
771fe6b9
JG		 1865 break;
1866 default:
1867 DRM_INFO("Connector table: %d (invalid)\n",
1868 rdev->mode_info.connector_table);
1869 return false;
1870 }
1871
1872 radeon_link_encoder_connector(dev);
1873
1874 return true;
1875}
1876
1877static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1878 int bios_index,
1879 enum radeon_combios_connector
1880 *legacy_connector,
eed45b30
AD		 1881 struct radeon_i2c_bus_rec *ddc_i2c,
1882 struct radeon_hpd *hpd)
771fe6b9
JG		 1883{
1884 struct radeon_device *rdev = dev->dev_private;
1885
1886 /* XPRESS DDC quirks */
1887 if ((rdev->family == CHIP_RS400 ||
1888 rdev->family == CHIP_RS480) &&
1889 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1890 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1891 else if ((rdev->family == CHIP_RS400 ||
1892 rdev->family == CHIP_RS480) &&
1893 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1894 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1895 ddc_i2c->mask_clk_mask = (0x20 << 8);
1896 ddc_i2c->mask_data_mask = 0x80;
1897 ddc_i2c->a_clk_mask = (0x20 << 8);
1898 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1899 ddc_i2c->en_clk_mask = (0x20 << 8);
1900 ddc_i2c->en_data_mask = 0x80;
1901 ddc_i2c->y_clk_mask = (0x20 << 8);
1902 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1903 }
1904
fcec570b
AD		 1905 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1906 if ((rdev->family >= CHIP_R300) &&
1907 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1908 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1909
771fe6b9
JG		 1910 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1911 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1912 if (dev->pdev->device == 0x515e &&
1913 dev->pdev->subsystem_vendor == 0x1014) {
1914 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1916 return false;
1917 }
1918
1919 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1920 if (dev->pdev->device == 0x5159 &&
1921 dev->pdev->subsystem_vendor == 0x1002 &&
1922 dev->pdev->subsystem_device == 0x013a) {
1923 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1924 *legacy_connector = CONNECTOR_CRT_LEGACY;
1925
1926 }
1927
1928 /* X300 card with extra non-existent DVI port */
1929 if (dev->pdev->device == 0x5B60 &&
1930 dev->pdev->subsystem_vendor == 0x17af &&
1931 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1932 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1933 return false;
1934 }
1935
1936 return true;
1937}
1938
790cfb34
AD		 1939static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1940{
1941 /* Acer 5102 has non-existent TV port */
1942 if (dev->pdev->device == 0x5975 &&
1943 dev->pdev->subsystem_vendor == 0x1025 &&
1944 dev->pdev->subsystem_device == 0x009f)
1945 return false;
1946
fc7f7119
AD		 1947 /* HP dc5750 has non-existent TV port */
1948 if (dev->pdev->device == 0x5974 &&
1949 dev->pdev->subsystem_vendor == 0x103c &&
1950 dev->pdev->subsystem_device == 0x280a)
1951 return false;
1952
fd874ad0
AD		 1953 /* MSI S270 has non-existent TV port */
1954 if (dev->pdev->device == 0x5955 &&
1955 dev->pdev->subsystem_vendor == 0x1462 &&
1956 dev->pdev->subsystem_device == 0x0131)
1957 return false;
1958
790cfb34
AD		 1959 return true;
1960}
1961
b75fad06
AD		 1962static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1963{
1964 struct radeon_device *rdev = dev->dev_private;
1965 uint32_t ext_tmds_info;
1966
1967 if (rdev->flags & RADEON_IS_IGP) {
1968 if (is_dvi_d)
1969 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1970 else
1971 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1972 }
1973 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1974 if (ext_tmds_info) {
1975 uint8_t rev = RBIOS8(ext_tmds_info);
1976 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1977 if (rev >= 3) {
1978 if (is_dvi_d)
1979 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1980 else
1981 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1982 } else {
1983 if (flags & 1) {
1984 if (is_dvi_d)
1985 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1986 else
1987 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1988 }
1989 }
1990 }
1991 if (is_dvi_d)
1992 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1993 else
1994 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1995}
1996
771fe6b9
JG		 1997bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1998{
1999 struct radeon_device *rdev = dev->dev_private;
2000 uint32_t conn_info, entry, devices;
b75fad06 2001 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2002 enum radeon_combios_ddc ddc_type;
2003 enum radeon_combios_connector connector;
2004 int i = 0;
2005 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2006 struct radeon_hpd hpd;
771fe6b9
JG		 2007
2008 if (rdev->bios == NULL)
2009 return false;
2010
2011 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2012 if (conn_info) {
2013 for (i = 0; i < 4; i++) {
2014 entry = conn_info + 2 + i * 2;
2015
2016 if (!RBIOS16(entry))
2017 break;
2018
2019 tmp = RBIOS16(entry);
2020
2021 connector = (tmp >> 12) & 0xf;
2022
2023 ddc_type = (tmp >> 8) & 0xf;
2024 switch (ddc_type) {
2025 case DDC_MONID:
2026 ddc_i2c =
6a93cb25 2027 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2028 break;
2029 case DDC_DVI:
2030 ddc_i2c =
6a93cb25 2031 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2032 break;
2033 case DDC_VGA:
2034 ddc_i2c =
6a93cb25 2035 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2036 break;
2037 case DDC_CRT2:
2038 ddc_i2c =
6a93cb25 2039 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2040 break;
2041 default:
2042 break;
2043 }
2044
eed45b30
AD		 2045 switch (connector) {
2046 case CONNECTOR_PROPRIETARY_LEGACY:
2047 case CONNECTOR_DVI_I_LEGACY:
2048 case CONNECTOR_DVI_D_LEGACY:
2049 if ((tmp >> 4) & 0x1)
2050 hpd.hpd = RADEON_HPD_2;
2051 else
2052 hpd.hpd = RADEON_HPD_1;
2053 break;
2054 default:
2055 hpd.hpd = RADEON_HPD_NONE;
2056 break;
2057 }
2058
2d152c6b 2059 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2060 &ddc_i2c, &hpd))
2d152c6b 2061 continue;
771fe6b9
JG		 2062
2063 switch (connector) {
2064 case CONNECTOR_PROPRIETARY_LEGACY:
2065 if ((tmp >> 4) & 0x1)
2066 devices = ATOM_DEVICE_DFP2_SUPPORT;
2067 else
2068 devices = ATOM_DEVICE_DFP1_SUPPORT;
2069 radeon_add_legacy_encoder(dev,
2070 radeon_get_encoder_id
2071 (dev, devices, 0),
2072 devices);
2073 radeon_add_legacy_connector(dev, i, devices,
2074 legacy_connector_convert
2075 [connector],
b75fad06 2076 &ddc_i2c,
eed45b30
AD		 2077 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2078 &hpd);
771fe6b9
JG		 2079 break;
2080 case CONNECTOR_CRT_LEGACY:
2081 if (tmp & 0x1) {
2082 devices = ATOM_DEVICE_CRT2_SUPPORT;
2083 radeon_add_legacy_encoder(dev,
2084 radeon_get_encoder_id
2085 (dev,
2086 ATOM_DEVICE_CRT2_SUPPORT,
2087 2),
2088 ATOM_DEVICE_CRT2_SUPPORT);
2089 } else {
2090 devices = ATOM_DEVICE_CRT1_SUPPORT;
2091 radeon_add_legacy_encoder(dev,
2092 radeon_get_encoder_id
2093 (dev,
2094 ATOM_DEVICE_CRT1_SUPPORT,
2095 1),
2096 ATOM_DEVICE_CRT1_SUPPORT);
2097 }
2098 radeon_add_legacy_connector(dev,
2099 i,
2100 devices,
2101 legacy_connector_convert
2102 [connector],
b75fad06 2103 &ddc_i2c,
eed45b30
AD		 2104 CONNECTOR_OBJECT_ID_VGA,
2105 &hpd);
771fe6b9
JG		 2106 break;
2107 case CONNECTOR_DVI_I_LEGACY:
2108 devices = 0;
2109 if (tmp & 0x1) {
2110 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2111 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_id
2113 (dev,
2114 ATOM_DEVICE_CRT2_SUPPORT,
2115 2),
2116 ATOM_DEVICE_CRT2_SUPPORT);
2117 } else {
2118 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2119 radeon_add_legacy_encoder(dev,
2120 radeon_get_encoder_id
2121 (dev,
2122 ATOM_DEVICE_CRT1_SUPPORT,
2123 1),
2124 ATOM_DEVICE_CRT1_SUPPORT);
2125 }
2126 if ((tmp >> 4) & 0x1) {
2127 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2128 radeon_add_legacy_encoder(dev,
2129 radeon_get_encoder_id
2130 (dev,
2131 ATOM_DEVICE_DFP2_SUPPORT,
2132 0),
2133 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2134 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2135 } else {
2136 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2137 radeon_add_legacy_encoder(dev,
2138 radeon_get_encoder_id
2139 (dev,
2140 ATOM_DEVICE_DFP1_SUPPORT,
2141 0),
2142 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2143 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2144 }
2145 radeon_add_legacy_connector(dev,
2146 i,
2147 devices,
2148 legacy_connector_convert
2149 [connector],
b75fad06 2150 &ddc_i2c,
eed45b30
AD		 2151 connector_object_id,
2152 &hpd);
771fe6b9
JG		 2153 break;
2154 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2155 if ((tmp >> 4) & 0x1) {
771fe6b9 2156 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2157 connector_object_id = combios_check_dl_dvi(dev, 1);
2158 } else {
771fe6b9 2159 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2160 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2161 }
771fe6b9
JG		 2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_id
2164 (dev, devices, 0),
2165 devices);
2166 radeon_add_legacy_connector(dev, i, devices,
2167 legacy_connector_convert
2168 [connector],
b75fad06 2169 &ddc_i2c,
eed45b30
AD		 2170 connector_object_id,
2171 &hpd);
771fe6b9
JG		 2172 break;
2173 case CONNECTOR_CTV_LEGACY:
2174 case CONNECTOR_STV_LEGACY:
2175 radeon_add_legacy_encoder(dev,
2176 radeon_get_encoder_id
2177 (dev,
2178 ATOM_DEVICE_TV1_SUPPORT,
2179 2),
2180 ATOM_DEVICE_TV1_SUPPORT);
2181 radeon_add_legacy_connector(dev, i,
2182 ATOM_DEVICE_TV1_SUPPORT,
2183 legacy_connector_convert
2184 [connector],
b75fad06 2185 &ddc_i2c,
eed45b30
AD		 2186 CONNECTOR_OBJECT_ID_SVIDEO,
2187 &hpd);
771fe6b9
JG		 2188 break;
2189 default:
2190 DRM_ERROR("Unknown connector type: %d\n",
2191 connector);
2192 continue;
2193 }
2194
2195 }
2196 } else {
2197 uint16_t tmds_info =
2198 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2199 if (tmds_info) {
2200 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2201
2202 radeon_add_legacy_encoder(dev,
2203 radeon_get_encoder_id(dev,
2204 ATOM_DEVICE_CRT1_SUPPORT,
2205 1),
2206 ATOM_DEVICE_CRT1_SUPPORT);
2207 radeon_add_legacy_encoder(dev,
2208 radeon_get_encoder_id(dev,
2209 ATOM_DEVICE_DFP1_SUPPORT,
2210 0),
2211 ATOM_DEVICE_DFP1_SUPPORT);
2212
6a93cb25 2213 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 2214 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2215 radeon_add_legacy_connector(dev,
2216 0,
2217 ATOM_DEVICE_CRT1_SUPPORT |
2218 ATOM_DEVICE_DFP1_SUPPORT,
2219 DRM_MODE_CONNECTOR_DVII,
b75fad06 2220 &ddc_i2c,
eed45b30
AD		 2221 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2222 &hpd);
771fe6b9 2223 } else {
d0c403e9
AD		 2224 uint16_t crt_info =
2225 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2226 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2227 if (crt_info) {
2228 radeon_add_legacy_encoder(dev,
2229 radeon_get_encoder_id(dev,
2230 ATOM_DEVICE_CRT1_SUPPORT,
2231 1),
2232 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2233 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2234 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2235 radeon_add_legacy_connector(dev,
2236 0,
2237 ATOM_DEVICE_CRT1_SUPPORT,
2238 DRM_MODE_CONNECTOR_VGA,
b75fad06 2239 &ddc_i2c,
eed45b30
AD		 2240 CONNECTOR_OBJECT_ID_VGA,
2241 &hpd);
d0c403e9
AD		 2242 } else {
2243 DRM_DEBUG("No connector info found\n");
2244 return false;
2245 }
771fe6b9
JG		 2246 }
2247 }
2248
2249 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2250 uint16_t lcd_info =
2251 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2252 if (lcd_info) {
2253 uint16_t lcd_ddc_info =
2254 combios_get_table_offset(dev,
2255 COMBIOS_LCD_DDC_INFO_TABLE);
2256
2257 radeon_add_legacy_encoder(dev,
2258 radeon_get_encoder_id(dev,
2259 ATOM_DEVICE_LCD1_SUPPORT,
2260 0),
2261 ATOM_DEVICE_LCD1_SUPPORT);
2262
2263 if (lcd_ddc_info) {
2264 ddc_type = RBIOS8(lcd_ddc_info + 2);
2265 switch (ddc_type) {
2266 case DDC_MONID:
2267 ddc_i2c =
2268 combios_setup_i2c_bus
6a93cb25 2269 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2270 break;
2271 case DDC_DVI:
2272 ddc_i2c =
2273 combios_setup_i2c_bus
6a93cb25 2274 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2275 break;
2276 case DDC_VGA:
2277 ddc_i2c =
2278 combios_setup_i2c_bus
6a93cb25 2279 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2280 break;
2281 case DDC_CRT2:
2282 ddc_i2c =
2283 combios_setup_i2c_bus
6a93cb25 2284 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2285 break;
2286 case DDC_LCD:
2287 ddc_i2c =
2288 combios_setup_i2c_bus
6a93cb25 2289 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2290 ddc_i2c.mask_clk_mask =
2291 RBIOS32(lcd_ddc_info + 3);
2292 ddc_i2c.mask_data_mask =
2293 RBIOS32(lcd_ddc_info + 7);
2294 ddc_i2c.a_clk_mask =
2295 RBIOS32(lcd_ddc_info + 3);
2296 ddc_i2c.a_data_mask =
2297 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2298 ddc_i2c.en_clk_mask =
771fe6b9 2299 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2300 ddc_i2c.en_data_mask =
771fe6b9 2301 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2302 ddc_i2c.y_clk_mask =
771fe6b9 2303 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2304 ddc_i2c.y_data_mask =
771fe6b9
JG		 2305 RBIOS32(lcd_ddc_info + 7);
2306 break;
2307 case DDC_GPIO:
2308 ddc_i2c =
2309 combios_setup_i2c_bus
6a93cb25 2310 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2311 ddc_i2c.mask_clk_mask =
2312 RBIOS32(lcd_ddc_info + 3);
2313 ddc_i2c.mask_data_mask =
2314 RBIOS32(lcd_ddc_info + 7);
2315 ddc_i2c.a_clk_mask =
2316 RBIOS32(lcd_ddc_info + 3);
2317 ddc_i2c.a_data_mask =
2318 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2319 ddc_i2c.en_clk_mask =
771fe6b9 2320 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2321 ddc_i2c.en_data_mask =
771fe6b9 2322 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2323 ddc_i2c.y_clk_mask =
771fe6b9 2324 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2325 ddc_i2c.y_data_mask =
771fe6b9
JG		 2326 RBIOS32(lcd_ddc_info + 7);
2327 break;
2328 default:
2329 ddc_i2c.valid = false;
2330 break;
2331 }
2332 DRM_DEBUG("LCD DDC Info Table found!\n");
2333 } else
2334 ddc_i2c.valid = false;
2335
eed45b30 2336 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2337 radeon_add_legacy_connector(dev,
2338 5,
2339 ATOM_DEVICE_LCD1_SUPPORT,
2340 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2341 &ddc_i2c,
eed45b30
AD		 2342 CONNECTOR_OBJECT_ID_LVDS,
2343 &hpd);
771fe6b9
JG		 2344 }
2345 }
2346
2347 /* check TV table */
2348 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2349 uint32_t tv_info =
2350 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2351 if (tv_info) {
2352 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2353 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2354 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2355 radeon_add_legacy_encoder(dev,
2356 radeon_get_encoder_id
2357 (dev,
2358 ATOM_DEVICE_TV1_SUPPORT,
2359 2),
2360 ATOM_DEVICE_TV1_SUPPORT);
2361 radeon_add_legacy_connector(dev, 6,
2362 ATOM_DEVICE_TV1_SUPPORT,
2363 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2364 &ddc_i2c,
eed45b30
AD		 2365 CONNECTOR_OBJECT_ID_SVIDEO,
2366 &hpd);
790cfb34 2367 }
771fe6b9
JG		 2368 }
2369 }
2370 }
2371
2372 radeon_link_encoder_connector(dev);
2373
2374 return true;
2375}
2376
56278a8e
AD		 2377void radeon_combios_get_power_modes(struct radeon_device *rdev)
2378{
2379 struct drm_device *dev = rdev->ddev;
2380 u16 offset, misc, misc2 = 0;
2381 u8 rev, blocks, tmp;
2382 int state_index = 0;
2383
2384 rdev->pm.default_power_state = NULL;
2385 rdev->pm.current_power_state = NULL;
2386
2387 /* XXX mac/sparc cards */
2388 if (rdev->bios == NULL)
2389 goto default_mode;
2390
2391 if (rdev->flags & RADEON_IS_MOBILITY) {
2392 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2393 if (offset) {
2394 rev = RBIOS8(offset);
2395 blocks = RBIOS8(offset + 0x2);
2396 /* power mode 0 tends to be the only valid one */
2397 rdev->pm.power_state[state_index].num_clock_modes = 1;
2398 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2399 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2400 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2401 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2402 goto default_mode;
2403 /* skip overclock modes for now */
2404 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2405 rdev->clock.default_mclk) ||
2406 (rdev->pm.power_state[state_index].clock_info[0].sclk >
2407 rdev->clock.default_sclk))
2408 goto default_mode;
2409 misc = RBIOS16(offset + 0x5 + 0x0);
2410 if (rev > 4)
2411 misc2 = RBIOS16(offset + 0x5 + 0xe);
2412 if (misc & 0x4) {
2413 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2414 if (misc & 0x8)
2415 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2416 true;
2417 else
2418 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2419 false;
2420 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2421 if (rev < 6) {
2422 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2423 RBIOS16(offset + 0x5 + 0xb) * 4;
2424 tmp = RBIOS8(offset + 0x5 + 0xd);
2425 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2426 } else {
2427 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2428 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2429 if (entries && voltage_table_offset) {
2430 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2431 RBIOS16(voltage_table_offset) * 4;
2432 tmp = RBIOS8(voltage_table_offset + 0x2);
2433 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2434 } else
2435 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2436 }
2437 switch ((misc2 & 0x700) >> 8) {
2438 case 0:
2439 default:
2440 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2441 break;
2442 case 1:
2443 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2444 break;
2445 case 2:
2446 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2447 break;
2448 case 3:
2449 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2450 break;
2451 case 4:
2452 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2453 break;
2454 }
2455 } else
2456 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2457 if (rev > 6)
2458 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2459 RBIOS8(offset + 0x5 + 0x10);
2460 state_index++;
2461 } else {
2462 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2463 }
2464 } else {
2465 /* XXX figure out some good default low power mode for desktop cards */
2466 }
2467
2468default_mode:
2469 /* add the default mode */
2470 rdev->pm.power_state[state_index].num_clock_modes = 1;
2471 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2472 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2473 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2474 rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2475 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2476 if (rdev->asic->get_pcie_lanes)
2477 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2478 else
2479 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2480 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2481 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
2482 rdev->pm.num_power_states = state_index + 1;
2483}
2484
fcec570b
AD		 2485void radeon_external_tmds_setup(struct drm_encoder *encoder)
2486{
2487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2488 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2489
2490 if (!tmds)
2491 return;
2492
2493 switch (tmds->dvo_chip) {
2494 case DVO_SIL164:
2495 /* sil 164 */
5a6f98f5
AD		 2496 radeon_i2c_put_byte(tmds->i2c_bus,
2497 tmds->slave_addr,
2498 0x08, 0x30);
2499 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2500 tmds->slave_addr,
2501 0x09, 0x00);
5a6f98f5
AD		 2502 radeon_i2c_put_byte(tmds->i2c_bus,
2503 tmds->slave_addr,
2504 0x0a, 0x90);
2505 radeon_i2c_put_byte(tmds->i2c_bus,
2506 tmds->slave_addr,
2507 0x0c, 0x89);
2508 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2509 tmds->slave_addr,
2510 0x08, 0x3b);
fcec570b
AD		 2511 break;
2512 case DVO_SIL1178:
2513 /* sil 1178 - untested */
2514 /*
2515 * 0x0f, 0x44
2516 * 0x0f, 0x4c
2517 * 0x0e, 0x01
2518 * 0x0a, 0x80
2519 * 0x09, 0x30
2520 * 0x0c, 0xc9
2521 * 0x0d, 0x70
2522 * 0x08, 0x32
2523 * 0x08, 0x33
2524 */
2525 break;
2526 default:
2527 break;
2528 }
2529
2530}
2531
2532bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2533{
2534 struct drm_device *dev = encoder->dev;
2535 struct radeon_device *rdev = dev->dev_private;
2536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2537 uint16_t offset;
2538 uint8_t blocks, slave_addr, rev;
2539 uint32_t index, id;
2540 uint32_t reg, val, and_mask, or_mask;
2541 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2542
2543 if (rdev->bios == NULL)
2544 return false;
2545
2546 if (!tmds)
2547 return false;
2548
2549 if (rdev->flags & RADEON_IS_IGP) {
2550 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2551 rev = RBIOS8(offset);
2552 if (offset) {
2553 rev = RBIOS8(offset);
2554 if (rev > 1) {
2555 blocks = RBIOS8(offset + 3);
2556 index = offset + 4;
2557 while (blocks > 0) {
2558 id = RBIOS16(index);
2559 index += 2;
2560 switch (id >> 13) {
2561 case 0:
2562 reg = (id & 0x1fff) * 4;
2563 val = RBIOS32(index);
2564 index += 4;
2565 WREG32(reg, val);
2566 break;
2567 case 2:
2568 reg = (id & 0x1fff) * 4;
2569 and_mask = RBIOS32(index);
2570 index += 4;
2571 or_mask = RBIOS32(index);
2572 index += 4;
2573 val = RREG32(reg);
2574 val = (val & and_mask) | or_mask;
2575 WREG32(reg, val);
2576 break;
2577 case 3:
2578 val = RBIOS16(index);
2579 index += 2;
2580 udelay(val);
2581 break;
2582 case 4:
2583 val = RBIOS16(index);
2584 index += 2;
2585 udelay(val * 1000);
2586 break;
2587 case 6:
2588 slave_addr = id & 0xff;
2589 slave_addr >>= 1; /* 7 bit addressing */
2590 index++;
2591 reg = RBIOS8(index);
2592 index++;
2593 val = RBIOS8(index);
2594 index++;
5a6f98f5
AD		 2595 radeon_i2c_put_byte(tmds->i2c_bus,
2596 slave_addr,
2597 reg, val);
fcec570b
AD		 2598 break;
2599 default:
2600 DRM_ERROR("Unknown id %d\n", id >> 13);
2601 break;
2602 }
2603 blocks--;
2604 }
2605 return true;
2606 }
2607 }
2608 } else {
2609 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2610 if (offset) {
2611 index = offset + 10;
2612 id = RBIOS16(index);
2613 while (id != 0xffff) {
2614 index += 2;
2615 switch (id >> 13) {
2616 case 0:
2617 reg = (id & 0x1fff) * 4;
2618 val = RBIOS32(index);
2619 WREG32(reg, val);
2620 break;
2621 case 2:
2622 reg = (id & 0x1fff) * 4;
2623 and_mask = RBIOS32(index);
2624 index += 4;
2625 or_mask = RBIOS32(index);
2626 index += 4;
2627 val = RREG32(reg);
2628 val = (val & and_mask) | or_mask;
2629 WREG32(reg, val);
2630 break;
2631 case 4:
2632 val = RBIOS16(index);
2633 index += 2;
2634 udelay(val);
2635 break;
2636 case 5:
2637 reg = id & 0x1fff;
2638 and_mask = RBIOS32(index);
2639 index += 4;
2640 or_mask = RBIOS32(index);
2641 index += 4;
2642 val = RREG32_PLL(reg);
2643 val = (val & and_mask) | or_mask;
2644 WREG32_PLL(reg, val);
2645 break;
2646 case 6:
2647 reg = id & 0x1fff;
2648 val = RBIOS8(index);
2649 index += 1;
5a6f98f5
AD		 2650 radeon_i2c_put_byte(tmds->i2c_bus,
2651 tmds->slave_addr,
2652 reg, val);
fcec570b
AD		 2653 break;
2654 default:
2655 DRM_ERROR("Unknown id %d\n", id >> 13);
2656 break;
2657 }
2658 id = RBIOS16(index);
2659 }
2660 return true;
2661 }
2662 }
2663 return false;
2664}
2665
771fe6b9
JG		 2666static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2667{
2668 struct radeon_device *rdev = dev->dev_private;
2669
2670 if (offset) {
2671 while (RBIOS16(offset)) {
2672 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2673 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2674 uint32_t val, and_mask, or_mask;
2675 uint32_t tmp;
2676
2677 offset += 2;
2678 switch (cmd) {
2679 case 0:
2680 val = RBIOS32(offset);
2681 offset += 4;
2682 WREG32(addr, val);
2683 break;
2684 case 1:
2685 val = RBIOS32(offset);
2686 offset += 4;
2687 WREG32(addr, val);
2688 break;
2689 case 2:
2690 and_mask = RBIOS32(offset);
2691 offset += 4;
2692 or_mask = RBIOS32(offset);
2693 offset += 4;
2694 tmp = RREG32(addr);
2695 tmp &= and_mask;
2696 tmp |= or_mask;
2697 WREG32(addr, tmp);
2698 break;
2699 case 3:
2700 and_mask = RBIOS32(offset);
2701 offset += 4;
2702 or_mask = RBIOS32(offset);
2703 offset += 4;
2704 tmp = RREG32(addr);
2705 tmp &= and_mask;
2706 tmp |= or_mask;
2707 WREG32(addr, tmp);
2708 break;
2709 case 4:
2710 val = RBIOS16(offset);
2711 offset += 2;
2712 udelay(val);
2713 break;
2714 case 5:
2715 val = RBIOS16(offset);
2716 offset += 2;
2717 switch (addr) {
2718 case 8:
2719 while (val--) {
2720 if (!
2721 (RREG32_PLL
2722 (RADEON_CLK_PWRMGT_CNTL) &
2723 RADEON_MC_BUSY))
2724 break;
2725 }
2726 break;
2727 case 9:
2728 while (val--) {
2729 if ((RREG32(RADEON_MC_STATUS) &
2730 RADEON_MC_IDLE))
2731 break;
2732 }
2733 break;
2734 default:
2735 break;
2736 }
2737 break;
2738 default:
2739 break;
2740 }
2741 }
2742 }
2743}
2744
2745static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2746{
2747 struct radeon_device *rdev = dev->dev_private;
2748
2749 if (offset) {
2750 while (RBIOS8(offset)) {
2751 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2752 uint8_t addr = (RBIOS8(offset) & 0x3f);
2753 uint32_t val, shift, tmp;
2754 uint32_t and_mask, or_mask;
2755
2756 offset++;
2757 switch (cmd) {
2758 case 0:
2759 val = RBIOS32(offset);
2760 offset += 4;
2761 WREG32_PLL(addr, val);
2762 break;
2763 case 1:
2764 shift = RBIOS8(offset) * 8;
2765 offset++;
2766 and_mask = RBIOS8(offset) << shift;
2767 and_mask |= ~(0xff << shift);
2768 offset++;
2769 or_mask = RBIOS8(offset) << shift;
2770 offset++;
2771 tmp = RREG32_PLL(addr);
2772 tmp &= and_mask;
2773 tmp |= or_mask;
2774 WREG32_PLL(addr, tmp);
2775 break;
2776 case 2:
2777 case 3:
2778 tmp = 1000;
2779 switch (addr) {
2780 case 1:
2781 udelay(150);
2782 break;
2783 case 2:
2784 udelay(1000);
2785 break;
2786 case 3:
2787 while (tmp--) {
2788 if (!
2789 (RREG32_PLL
2790 (RADEON_CLK_PWRMGT_CNTL) &
2791 RADEON_MC_BUSY))
2792 break;
2793 }
2794 break;
2795 case 4:
2796 while (tmp--) {
2797 if (RREG32_PLL
2798 (RADEON_CLK_PWRMGT_CNTL) &
2799 RADEON_DLL_READY)
2800 break;
2801 }
2802 break;
2803 case 5:
2804 tmp =
2805 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2806 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2807#if 0
2808 uint32_t mclk_cntl =
2809 RREG32_PLL
2810 (RADEON_MCLK_CNTL);
2811 mclk_cntl &= 0xffff0000;
2812 /*mclk_cntl |= 0x00001111;*//* ??? */
2813 WREG32_PLL(RADEON_MCLK_CNTL,
2814 mclk_cntl);
2815 udelay(10000);
2816#endif
2817 WREG32_PLL
2818 (RADEON_CLK_PWRMGT_CNTL,
2819 tmp &
2820 ~RADEON_CG_NO1_DEBUG_0);
2821 udelay(10000);
2822 }
2823 break;
2824 default:
2825 break;
2826 }
2827 break;
2828 default:
2829 break;
2830 }
2831 }
2832 }
2833}
2834
2835static void combios_parse_ram_reset_table(struct drm_device *dev,
2836 uint16_t offset)
2837{
2838 struct radeon_device *rdev = dev->dev_private;
2839 uint32_t tmp;
2840
2841 if (offset) {
2842 uint8_t val = RBIOS8(offset);
2843 while (val != 0xff) {
2844 offset++;
2845
2846 if (val == 0x0f) {
2847 uint32_t channel_complete_mask;
2848
2849 if (ASIC_IS_R300(rdev))
2850 channel_complete_mask =
2851 R300_MEM_PWRUP_COMPLETE;
2852 else
2853 channel_complete_mask =
2854 RADEON_MEM_PWRUP_COMPLETE;
2855 tmp = 20000;
2856 while (tmp--) {
2857 if ((RREG32(RADEON_MEM_STR_CNTL) &
2858 channel_complete_mask) ==
2859 channel_complete_mask)
2860 break;
2861 }
2862 } else {
2863 uint32_t or_mask = RBIOS16(offset);
2864 offset += 2;
2865
2866 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2867 tmp &= RADEON_SDRAM_MODE_MASK;
2868 tmp |= or_mask;
2869 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2870
2871 or_mask = val << 24;
2872 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2873 tmp &= RADEON_B3MEM_RESET_MASK;
2874 tmp |= or_mask;
2875 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2876 }
2877 val = RBIOS8(offset);
2878 }
2879 }
2880}
2881
2882static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2883 int mem_addr_mapping)
2884{
2885 struct radeon_device *rdev = dev->dev_private;
2886 uint32_t mem_cntl;
2887 uint32_t mem_size;
2888 uint32_t addr = 0;
2889
2890 mem_cntl = RREG32(RADEON_MEM_CNTL);
2891 if (mem_cntl & RV100_HALF_MODE)
2892 ram /= 2;
2893 mem_size = ram;
2894 mem_cntl &= ~(0xff << 8);
2895 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2896 WREG32(RADEON_MEM_CNTL, mem_cntl);
2897 RREG32(RADEON_MEM_CNTL);
2898
2899 /* sdram reset ? */
2900
2901 /* something like this???? */
2902 while (ram--) {
2903 addr = ram * 1024 * 1024;
2904 /* write to each page */
2905 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2906 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2907 /* read back and verify */
2908 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2909 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2910 return 0;
2911 }
2912
2913 return mem_size;
2914}
2915
2916static void combios_write_ram_size(struct drm_device *dev)
2917{
2918 struct radeon_device *rdev = dev->dev_private;
2919 uint8_t rev;
2920 uint16_t offset;
2921 uint32_t mem_size = 0;
2922 uint32_t mem_cntl = 0;
2923
2924 /* should do something smarter here I guess... */
2925 if (rdev->flags & RADEON_IS_IGP)
2926 return;
2927
2928 /* first check detected mem table */
2929 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2930 if (offset) {
2931 rev = RBIOS8(offset);
2932 if (rev < 3) {
2933 mem_cntl = RBIOS32(offset + 1);
2934 mem_size = RBIOS16(offset + 5);
2935 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2936 ((dev->pdev->device != 0x515e)
2937 && (dev->pdev->device != 0x5969)))
2938 WREG32(RADEON_MEM_CNTL, mem_cntl);
2939 }
2940 }
2941
2942 if (!mem_size) {
2943 offset =
2944 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2945 if (offset) {
2946 rev = RBIOS8(offset - 1);
2947 if (rev < 1) {
2948 if (((rdev->flags & RADEON_FAMILY_MASK) <
2949 CHIP_R200)
2950 && ((dev->pdev->device != 0x515e)
2951 && (dev->pdev->device != 0x5969))) {
2952 int ram = 0;
2953 int mem_addr_mapping = 0;
2954
2955 while (RBIOS8(offset)) {
2956 ram = RBIOS8(offset);
2957 mem_addr_mapping =
2958 RBIOS8(offset + 1);
2959 if (mem_addr_mapping != 0x25)
2960 ram *= 2;
2961 mem_size =
2962 combios_detect_ram(dev, ram,
2963 mem_addr_mapping);
2964 if (mem_size)
2965 break;
2966 offset += 2;
2967 }
2968 } else
2969 mem_size = RBIOS8(offset);
2970 } else {
2971 mem_size = RBIOS8(offset);
2972 mem_size *= 2; /* convert to MB */
2973 }
2974 }
2975 }
2976
2977 mem_size *= (1024 * 1024); /* convert to bytes */
2978 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2979}
2980
2981void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2982{
2983 uint16_t dyn_clk_info =
2984 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2985
2986 if (dyn_clk_info)
2987 combios_parse_pll_table(dev, dyn_clk_info);
2988}
2989
2990void radeon_combios_asic_init(struct drm_device *dev)
2991{
2992 struct radeon_device *rdev = dev->dev_private;
2993 uint16_t table;
2994
2995 /* port hardcoded mac stuff from radeonfb */
2996 if (rdev->bios == NULL)
2997 return;
2998
2999 /* ASIC INIT 1 */
3000 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3001 if (table)
3002 combios_parse_mmio_table(dev, table);
3003
3004 /* PLL INIT */
3005 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3006 if (table)
3007 combios_parse_pll_table(dev, table);
3008
3009 /* ASIC INIT 2 */
3010 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3011 if (table)
3012 combios_parse_mmio_table(dev, table);
3013
3014 if (!(rdev->flags & RADEON_IS_IGP)) {
3015 /* ASIC INIT 4 */
3016 table =
3017 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3018 if (table)
3019 combios_parse_mmio_table(dev, table);
3020
3021 /* RAM RESET */
3022 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3023 if (table)
3024 combios_parse_ram_reset_table(dev, table);
3025
3026 /* ASIC INIT 3 */
3027 table =
3028 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3029 if (table)
3030 combios_parse_mmio_table(dev, table);
3031
3032 /* write CONFIG_MEMSIZE */
3033 combios_write_ram_size(dev);
3034 }
3035
3036 /* DYN CLK 1 */
3037 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3038 if (table)
3039 combios_parse_pll_table(dev, table);
3040
3041}
3042
3043void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3044{
3045 struct radeon_device *rdev = dev->dev_private;
3046 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3047
3048 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3049 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3050 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3051
3052 /* let the bios control the backlight */
3053 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3054
3055 /* tell the bios not to handle mode switching */
3056 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3057 RADEON_ACC_MODE_CHANGE);
3058
3059 /* tell the bios a driver is loaded */
3060 bios_7_scratch |= RADEON_DRV_LOADED;
3061
3062 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3063 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3064 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3065}
3066
3067void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3068{
3069 struct drm_device *dev = encoder->dev;
3070 struct radeon_device *rdev = dev->dev_private;
3071 uint32_t bios_6_scratch;
3072
3073 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3074
3075 if (lock)
3076 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3077 else
3078 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3079
3080 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3081}
3082
3083void
3084radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3085 struct drm_encoder *encoder,
3086 bool connected)
3087{
3088 struct drm_device *dev = connector->dev;
3089 struct radeon_device *rdev = dev->dev_private;
3090 struct radeon_connector *radeon_connector =
3091 to_radeon_connector(connector);
3092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3093 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3094 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3095
3096 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3097 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3098 if (connected) {
3099 DRM_DEBUG("TV1 connected\n");
3100 /* fix me */
3101 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3102 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3103 bios_5_scratch |= RADEON_TV1_ON;
3104 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3105 } else {
3106 DRM_DEBUG("TV1 disconnected\n");
3107 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3108 bios_5_scratch &= ~RADEON_TV1_ON;
3109 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3110 }
3111 }
3112 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3113 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3114 if (connected) {
3115 DRM_DEBUG("LCD1 connected\n");
3116 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3117 bios_5_scratch |= RADEON_LCD1_ON;
3118 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3119 } else {
3120 DRM_DEBUG("LCD1 disconnected\n");
3121 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3122 bios_5_scratch &= ~RADEON_LCD1_ON;
3123 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3124 }
3125 }
3126 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3127 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3128 if (connected) {
3129 DRM_DEBUG("CRT1 connected\n");
3130 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3131 bios_5_scratch |= RADEON_CRT1_ON;
3132 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3133 } else {
3134 DRM_DEBUG("CRT1 disconnected\n");
3135 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3136 bios_5_scratch &= ~RADEON_CRT1_ON;
3137 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3138 }
3139 }
3140 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3141 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3142 if (connected) {
3143 DRM_DEBUG("CRT2 connected\n");
3144 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3145 bios_5_scratch |= RADEON_CRT2_ON;
3146 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3147 } else {
3148 DRM_DEBUG("CRT2 disconnected\n");
3149 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3150 bios_5_scratch &= ~RADEON_CRT2_ON;
3151 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3152 }
3153 }
3154 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3155 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3156 if (connected) {
3157 DRM_DEBUG("DFP1 connected\n");
3158 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3159 bios_5_scratch |= RADEON_DFP1_ON;
3160 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3161 } else {
3162 DRM_DEBUG("DFP1 disconnected\n");
3163 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3164 bios_5_scratch &= ~RADEON_DFP1_ON;
3165 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3166 }
3167 }
3168 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3169 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3170 if (connected) {
3171 DRM_DEBUG("DFP2 connected\n");
3172 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3173 bios_5_scratch |= RADEON_DFP2_ON;
3174 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3175 } else {
3176 DRM_DEBUG("DFP2 disconnected\n");
3177 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3178 bios_5_scratch &= ~RADEON_DFP2_ON;
3179 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3180 }
3181 }
3182 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3183 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3184}
3185
3186void
3187radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3188{
3189 struct drm_device *dev = encoder->dev;
3190 struct radeon_device *rdev = dev->dev_private;
3191 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3192 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3193
3194 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3195 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3196 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3197 }
3198 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3199 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3200 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3201 }
3202 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3203 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3204 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3205 }
3206 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3207 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3208 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3209 }
3210 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3211 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3212 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3213 }
3214 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3215 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3216 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3217 }
3218 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3219}
3220
3221void
3222radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3223{
3224 struct drm_device *dev = encoder->dev;
3225 struct radeon_device *rdev = dev->dev_private;
3226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3227 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3228
3229 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3230 if (on)
3231 bios_6_scratch |= RADEON_TV_DPMS_ON;
3232 else
3233 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3234 }
3235 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3236 if (on)
3237 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3238 else
3239 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3240 }
3241 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3242 if (on)
3243 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3244 else
3245 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3246 }
3247 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3248 if (on)
3249 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3250 else
3251 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3252 }
3253 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3254}
Linux kernel - Deliverables
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