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drm/fb: fix CONFIG_DRM=m && CONFIG_FB=n
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
5137ee94
AD		 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
771fe6b9
JG		 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
5137ee94 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
fafcf94e 451 int edid_info, size;
3c537889 452 struct edid *edid;
7466f4cc 453 unsigned char *raw;
3c537889
AD		 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
7466f4cc 458 raw = rdev->bios + edid_info;
fafcf94e
AD		 459 size = EDID_LENGTH * (raw[0x7e] + 1);
460 edid = kmalloc(size, GFP_KERNEL);
3c537889
AD		 461 if (edid == NULL)
462 return false;
463
fafcf94e 464 memcpy((unsigned char *)edid, raw, size);
3c537889
AD		 465
466 if (!drm_edid_is_valid(edid)) {
467 kfree(edid);
468 return false;
469 }
470
471 rdev->mode_info.bios_hardcoded_edid = edid;
fafcf94e 472 rdev->mode_info.bios_hardcoded_edid_size = size;
3c537889
AD		 473 return true;
474}
475
c324acd5 476/* this is used for atom LCDs as well */
3c537889 477struct edid *
c324acd5 478radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
3c537889 479{
fafcf94e
AD		 480 struct edid *edid;
481
482 if (rdev->mode_info.bios_hardcoded_edid) {
483 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
484 if (edid) {
485 memcpy((unsigned char *)edid,
486 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
487 rdev->mode_info.bios_hardcoded_edid_size);
488 return edid;
489 }
490 }
3c537889
AD		 491 return NULL;
492}
493
6a93cb25 494static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
179e8078
AD		 495 enum radeon_combios_ddc ddc,
496 u32 clk_mask,
497 u32 data_mask)
771fe6b9
JG		 498{
499 struct radeon_i2c_bus_rec i2c;
179e8078
AD		 500 int ddc_line = 0;
501
502 /* ddc id = mask reg
503 * DDC_NONE_DETECTED = none
504 * DDC_DVI = RADEON_GPIO_DVI_DDC
505 * DDC_VGA = RADEON_GPIO_VGA_DDC
506 * DDC_LCD = RADEON_GPIOPAD_MASK
507 * DDC_GPIO = RADEON_MDGPIO_MASK
508 * r1xx/r2xx
509 * DDC_MONID = RADEON_GPIO_MONID
510 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
511 * r3xx
512 * DDC_MONID = RADEON_GPIO_MONID
513 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
514 * rs3xx/rs4xx
515 * DDC_MONID = RADEON_GPIOPAD_MASK
516 * DDC_CRT2 = RADEON_GPIO_MONID
517 */
518 switch (ddc) {
519 case DDC_NONE_DETECTED:
520 default:
521 ddc_line = 0;
522 break;
523 case DDC_DVI:
524 ddc_line = RADEON_GPIO_DVI_DDC;
525 break;
526 case DDC_VGA:
527 ddc_line = RADEON_GPIO_VGA_DDC;
528 break;
529 case DDC_LCD:
530 ddc_line = RADEON_GPIOPAD_MASK;
531 break;
532 case DDC_GPIO:
533 ddc_line = RADEON_MDGPIO_MASK;
534 break;
535 case DDC_MONID:
536 if (rdev->family == CHIP_RS300 ||
537 rdev->family == CHIP_RS400 ||
538 rdev->family == CHIP_RS480)
539 ddc_line = RADEON_GPIOPAD_MASK;
540 else
541 ddc_line = RADEON_GPIO_MONID;
542 break;
543 case DDC_CRT2:
544 if (rdev->family == CHIP_RS300 ||
545 rdev->family == CHIP_RS400 ||
546 rdev->family == CHIP_RS480)
547 ddc_line = RADEON_GPIO_MONID;
548 else if (rdev->family >= CHIP_R300) {
549 ddc_line = RADEON_GPIO_DVI_DDC;
550 ddc = DDC_DVI;
551 } else
552 ddc_line = RADEON_GPIO_CRT2_DDC;
553 break;
554 }
771fe6b9 555
6a93cb25
AD		 556 if (ddc_line == RADEON_GPIOPAD_MASK) {
557 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
558 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
559 i2c.a_clk_reg = RADEON_GPIOPAD_A;
560 i2c.a_data_reg = RADEON_GPIOPAD_A;
561 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
562 i2c.en_data_reg = RADEON_GPIOPAD_EN;
563 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
564 i2c.y_data_reg = RADEON_GPIOPAD_Y;
565 } else if (ddc_line == RADEON_MDGPIO_MASK) {
566 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
567 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
568 i2c.a_clk_reg = RADEON_MDGPIO_A;
569 i2c.a_data_reg = RADEON_MDGPIO_A;
570 i2c.en_clk_reg = RADEON_MDGPIO_EN;
571 i2c.en_data_reg = RADEON_MDGPIO_EN;
572 i2c.y_clk_reg = RADEON_MDGPIO_Y;
573 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9
JG		 574 } else {
575 i2c.mask_clk_reg = ddc_line;
576 i2c.mask_data_reg = ddc_line;
577 i2c.a_clk_reg = ddc_line;
578 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 579 i2c.en_clk_reg = ddc_line;
580 i2c.en_data_reg = ddc_line;
581 i2c.y_clk_reg = ddc_line;
582 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 583 }
584
179e8078 585 if (clk_mask && data_mask) {
be663057 586 /* system specific masks */
179e8078
AD		 587 i2c.mask_clk_mask = clk_mask;
588 i2c.mask_data_mask = data_mask;
589 i2c.a_clk_mask = clk_mask;
590 i2c.a_data_mask = data_mask;
591 i2c.en_clk_mask = clk_mask;
592 i2c.en_data_mask = data_mask;
593 i2c.y_clk_mask = clk_mask;
594 i2c.y_data_mask = data_mask;
be663057
AD		 595 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
596 (ddc_line == RADEON_MDGPIO_MASK)) {
597 /* default gpiopad masks */
598 i2c.mask_clk_mask = (0x20 << 8);
599 i2c.mask_data_mask = 0x80;
600 i2c.a_clk_mask = (0x20 << 8);
601 i2c.a_data_mask = 0x80;
602 i2c.en_clk_mask = (0x20 << 8);
603 i2c.en_data_mask = 0x80;
604 i2c.y_clk_mask = (0x20 << 8);
605 i2c.y_data_mask = 0x80;
179e8078 606 } else {
be663057 607 /* default masks for ddc pads */
179e8078
AD		 608 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
609 i2c.mask_data_mask = RADEON_GPIO_EN_0;
610 i2c.a_clk_mask = RADEON_GPIO_A_1;
611 i2c.a_data_mask = RADEON_GPIO_A_0;
612 i2c.en_clk_mask = RADEON_GPIO_EN_1;
613 i2c.en_data_mask = RADEON_GPIO_EN_0;
614 i2c.y_clk_mask = RADEON_GPIO_Y_1;
615 i2c.y_data_mask = RADEON_GPIO_Y_0;
616 }
617
40bacf16
AD		 618 switch (rdev->family) {
619 case CHIP_R100:
620 case CHIP_RV100:
621 case CHIP_RS100:
622 case CHIP_RV200:
623 case CHIP_RS200:
624 case CHIP_RS300:
625 switch (ddc_line) {
626 case RADEON_GPIO_DVI_DDC:
b28ea411 627 i2c.hw_capable = true;
40bacf16
AD		 628 break;
629 default:
630 i2c.hw_capable = false;
631 break;
632 }
633 break;
634 case CHIP_R200:
635 switch (ddc_line) {
636 case RADEON_GPIO_DVI_DDC:
637 case RADEON_GPIO_MONID:
638 i2c.hw_capable = true;
639 break;
640 default:
641 i2c.hw_capable = false;
642 break;
643 }
644 break;
645 case CHIP_RV250:
646 case CHIP_RV280:
647 switch (ddc_line) {
648 case RADEON_GPIO_VGA_DDC:
649 case RADEON_GPIO_DVI_DDC:
650 case RADEON_GPIO_CRT2_DDC:
651 i2c.hw_capable = true;
652 break;
653 default:
654 i2c.hw_capable = false;
655 break;
656 }
657 break;
658 case CHIP_R300:
659 case CHIP_R350:
660 switch (ddc_line) {
661 case RADEON_GPIO_VGA_DDC:
662 case RADEON_GPIO_DVI_DDC:
663 i2c.hw_capable = true;
664 break;
665 default:
666 i2c.hw_capable = false;
667 break;
668 }
669 break;
670 case CHIP_RV350:
671 case CHIP_RV380:
672 case CHIP_RS400:
673 case CHIP_RS480:
6a93cb25
AD		 674 switch (ddc_line) {
675 case RADEON_GPIO_VGA_DDC:
676 case RADEON_GPIO_DVI_DDC:
677 i2c.hw_capable = true;
678 break;
679 case RADEON_GPIO_MONID:
680 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
681 * reliably on some pre-r4xx hardware; not sure why.
682 */
683 i2c.hw_capable = false;
684 break;
685 default:
686 i2c.hw_capable = false;
687 break;
688 }
40bacf16
AD		 689 break;
690 default:
691 i2c.hw_capable = false;
692 break;
6a93cb25
AD		 693 }
694 i2c.mm_i2c = false;
f376b94f 695
179e8078 696 i2c.i2c_id = ddc;
8e36ed00 697 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 698
771fe6b9
JG		 699 if (ddc_line)
700 i2c.valid = true;
701 else
702 i2c.valid = false;
703
704 return i2c;
705}
706
f376b94f
AD		 707void radeon_combios_i2c_init(struct radeon_device *rdev)
708{
709 struct drm_device *dev = rdev->ddev;
710 struct radeon_i2c_bus_rec i2c;
711
f376b94f 712
179e8078
AD		 713 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
714 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
f376b94f 715
179e8078
AD		 716 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
717 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
f376b94f
AD		 718
719 i2c.valid = true;
720 i2c.hw_capable = true;
721 i2c.mm_i2c = true;
179e8078
AD		 722 i2c.i2c_id = 0xa0;
723 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
724
725 if (rdev->family == CHIP_RS300 ||
726 rdev->family == CHIP_RS400 ||
727 rdev->family == CHIP_RS480) {
728 u16 offset;
729 u8 id, blocks, clk, data;
730 int i;
731
732 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
733 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
734
735 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
736 if (offset) {
737 blocks = RBIOS8(offset + 2);
738 for (i = 0; i < blocks; i++) {
739 id = RBIOS8(offset + 3 + (i * 5) + 0);
740 if (id == 136) {
741 clk = RBIOS8(offset + 3 + (i * 5) + 3);
742 data = RBIOS8(offset + 3 + (i * 5) + 4);
743 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
791cfe26 744 (1 << clk), (1 << data));
179e8078
AD		 745 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
746 break;
747 }
748 }
749 }
750
751 } else if (rdev->family >= CHIP_R300) {
752 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
753 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
754 } else {
755 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
756 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
757
758 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
759 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
760 }
f376b94f
AD		 761}
762
771fe6b9
JG		 763bool radeon_combios_get_clock_info(struct drm_device *dev)
764{
765 struct radeon_device *rdev = dev->dev_private;
766 uint16_t pll_info;
767 struct radeon_pll *p1pll = &rdev->clock.p1pll;
768 struct radeon_pll *p2pll = &rdev->clock.p2pll;
769 struct radeon_pll *spll = &rdev->clock.spll;
770 struct radeon_pll *mpll = &rdev->clock.mpll;
771 int8_t rev;
772 uint16_t sclk, mclk;
773
771fe6b9
JG		 774 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
775 if (pll_info) {
776 rev = RBIOS8(pll_info);
777
778 /* pixel clocks */
779 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
780 p1pll->reference_div = RBIOS16(pll_info + 0x10);
781 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
782 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 783 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
784 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 785
786 if (rev > 9) {
787 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
788 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
789 } else {
790 p1pll->pll_in_min = 40;
791 p1pll->pll_in_max = 500;
792 }
793 *p2pll = *p1pll;
794
795 /* system clock */
796 spll->reference_freq = RBIOS16(pll_info + 0x1a);
797 spll->reference_div = RBIOS16(pll_info + 0x1c);
798 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
799 spll->pll_out_max = RBIOS32(pll_info + 0x22);
800
801 if (rev > 10) {
802 spll->pll_in_min = RBIOS32(pll_info + 0x48);
803 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
804 } else {
805 /* ??? */
806 spll->pll_in_min = 40;
807 spll->pll_in_max = 500;
808 }
809
810 /* memory clock */
811 mpll->reference_freq = RBIOS16(pll_info + 0x26);
812 mpll->reference_div = RBIOS16(pll_info + 0x28);
813 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
814 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
815
816 if (rev > 10) {
817 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
818 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
819 } else {
820 /* ??? */
821 mpll->pll_in_min = 40;
822 mpll->pll_in_max = 500;
823 }
824
825 /* default sclk/mclk */
826 sclk = RBIOS16(pll_info + 0xa);
827 mclk = RBIOS16(pll_info + 0x8);
828 if (sclk == 0)
829 sclk = 200 * 100;
830 if (mclk == 0)
831 mclk = 200 * 100;
832
833 rdev->clock.default_sclk = sclk;
834 rdev->clock.default_mclk = mclk;
835
836 return true;
837 }
838 return false;
839}
840
06b6476d
AD		 841bool radeon_combios_sideport_present(struct radeon_device *rdev)
842{
843 struct drm_device *dev = rdev->ddev;
844 u16 igp_info;
845
4c70b2ea
AD		 846 /* sideport is AMD only */
847 if (rdev->family == CHIP_RS400)
848 return false;
849
06b6476d
AD		 850 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
851
852 if (igp_info) {
853 if (RBIOS16(igp_info + 0x4))
854 return true;
855 }
856 return false;
857}
858
246263cc
AD		 859static const uint32_t default_primarydac_adj[CHIP_LAST] = {
860 0x00000808, /* r100 */
861 0x00000808, /* rv100 */
862 0x00000808, /* rs100 */
863 0x00000808, /* rv200 */
864 0x00000808, /* rs200 */
865 0x00000808, /* r200 */
866 0x00000808, /* rv250 */
867 0x00000000, /* rs300 */
868 0x00000808, /* rv280 */
869 0x00000808, /* r300 */
870 0x00000808, /* r350 */
871 0x00000808, /* rv350 */
872 0x00000808, /* rv380 */
873 0x00000808, /* r420 */
874 0x00000808, /* r423 */
875 0x00000808, /* rv410 */
876 0x00000000, /* rs400 */
877 0x00000000, /* rs480 */
878};
879
880static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
881 struct radeon_encoder_primary_dac *p_dac)
882{
883 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
884 return;
885}
886
771fe6b9
JG		 887struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
888 radeon_encoder
889 *encoder)
890{
891 struct drm_device *dev = encoder->base.dev;
892 struct radeon_device *rdev = dev->dev_private;
893 uint16_t dac_info;
894 uint8_t rev, bg, dac;
895 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 896 int found = 0;
771fe6b9 897
246263cc
AD		 898 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
899 GFP_KERNEL);
900
901 if (!p_dac)
771fe6b9
JG		 902 return NULL;
903
904 /* check CRT table */
905 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
906 if (dac_info) {
771fe6b9
JG		 907 rev = RBIOS8(dac_info) & 0x3;
908 if (rev < 2) {
909 bg = RBIOS8(dac_info + 0x2) & 0xf;
910 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
911 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
912 } else {
913 bg = RBIOS8(dac_info + 0x2) & 0xf;
914 dac = RBIOS8(dac_info + 0x3) & 0xf;
915 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
916 }
3a89b4a9
AD		 917 /* if the values are all zeros, use the table */
918 if (p_dac->ps2_pdac_adj)
919 found = 1;
771fe6b9
JG		 920 }
921
246263cc
AD		 922 if (!found) /* fallback to defaults */
923 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
924
771fe6b9
JG		 925 return p_dac;
926}
927
d79766fa
AD		 928enum radeon_tv_std
929radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 930{
d79766fa 931 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 932 uint16_t tv_info;
933 enum radeon_tv_std tv_std = TV_STD_NTSC;
934
935 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
936 if (tv_info) {
937 if (RBIOS8(tv_info + 6) == 'T') {
938 switch (RBIOS8(tv_info + 7) & 0xf) {
939 case 1:
940 tv_std = TV_STD_NTSC;
40f76d81 941 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
771fe6b9
JG		 942 break;
943 case 2:
944 tv_std = TV_STD_PAL;
40f76d81 945 DRM_DEBUG_KMS("Default TV standard: PAL\n");
771fe6b9
JG		 946 break;
947 case 3:
948 tv_std = TV_STD_PAL_M;
40f76d81 949 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
771fe6b9
JG		 950 break;
951 case 4:
952 tv_std = TV_STD_PAL_60;
40f76d81 953 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
771fe6b9
JG		 954 break;
955 case 5:
956 tv_std = TV_STD_NTSC_J;
40f76d81 957 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
771fe6b9
JG		 958 break;
959 case 6:
960 tv_std = TV_STD_SCART_PAL;
40f76d81 961 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
771fe6b9
JG		 962 break;
963 default:
964 tv_std = TV_STD_NTSC;
40f76d81 965 DRM_DEBUG_KMS
771fe6b9
JG		 966 ("Unknown TV standard; defaulting to NTSC\n");
967 break;
968 }
969
970 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
971 case 0:
40f76d81 972 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
771fe6b9
JG		 973 break;
974 case 1:
40f76d81 975 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
771fe6b9
JG		 976 break;
977 case 2:
40f76d81 978 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
771fe6b9
JG		 979 break;
980 case 3:
40f76d81 981 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
771fe6b9
JG		 982 break;
983 default:
984 break;
985 }
986 }
987 }
988 return tv_std;
989}
990
991static const uint32_t default_tvdac_adj[CHIP_LAST] = {
992 0x00000000, /* r100 */
993 0x00280000, /* rv100 */
994 0x00000000, /* rs100 */
995 0x00880000, /* rv200 */
996 0x00000000, /* rs200 */
997 0x00000000, /* r200 */
998 0x00770000, /* rv250 */
999 0x00290000, /* rs300 */
1000 0x00560000, /* rv280 */
1001 0x00780000, /* r300 */
1002 0x00770000, /* r350 */
1003 0x00780000, /* rv350 */
1004 0x00780000, /* rv380 */
1005 0x01080000, /* r420 */
1006 0x01080000, /* r423 */
1007 0x01080000, /* rv410 */
1008 0x00780000, /* rs400 */
1009 0x00780000, /* rs480 */
1010};
1011
6a719e05
DA		 1012static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1013 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 1014{
771fe6b9
JG		 1015 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1016 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1017 tv_dac->ps2_tvdac_adj = 0x00880000;
1018 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1019 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 1020 return;
771fe6b9
JG		 1021}
1022
1023struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1024 radeon_encoder
1025 *encoder)
1026{
1027 struct drm_device *dev = encoder->base.dev;
1028 struct radeon_device *rdev = dev->dev_private;
1029 uint16_t dac_info;
1030 uint8_t rev, bg, dac;
1031 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 1032 int found = 0;
1033
1034 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1035 if (!tv_dac)
1036 return NULL;
771fe6b9 1037
771fe6b9
JG		 1038 /* first check TV table */
1039 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1040 if (dac_info) {
771fe6b9
JG		 1041 rev = RBIOS8(dac_info + 0x3);
1042 if (rev > 4) {
1043 bg = RBIOS8(dac_info + 0xc) & 0xf;
1044 dac = RBIOS8(dac_info + 0xd) & 0xf;
1045 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1046
1047 bg = RBIOS8(dac_info + 0xe) & 0xf;
1048 dac = RBIOS8(dac_info + 0xf) & 0xf;
1049 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1050
1051 bg = RBIOS8(dac_info + 0x10) & 0xf;
1052 dac = RBIOS8(dac_info + 0x11) & 0xf;
1053 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1054 /* if the values are all zeros, use the table */
1055 if (tv_dac->ps2_tvdac_adj)
1056 found = 1;
771fe6b9
JG		 1057 } else if (rev > 1) {
1058 bg = RBIOS8(dac_info + 0xc) & 0xf;
1059 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1060 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1061
1062 bg = RBIOS8(dac_info + 0xd) & 0xf;
1063 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1064 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1065
1066 bg = RBIOS8(dac_info + 0xe) & 0xf;
1067 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1068 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1069 /* if the values are all zeros, use the table */
1070 if (tv_dac->ps2_tvdac_adj)
1071 found = 1;
771fe6b9 1072 }
d79766fa 1073 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 1074 }
1075 if (!found) {
771fe6b9
JG		 1076 /* then check CRT table */
1077 dac_info =
1078 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1079 if (dac_info) {
771fe6b9
JG		 1080 rev = RBIOS8(dac_info) & 0x3;
1081 if (rev < 2) {
1082 bg = RBIOS8(dac_info + 0x3) & 0xf;
1083 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1084 tv_dac->ps2_tvdac_adj =
1085 (bg << 16) | (dac << 20);
1086 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1088 /* if the values are all zeros, use the table */
1089 if (tv_dac->ps2_tvdac_adj)
1090 found = 1;
771fe6b9
JG		 1091 } else {
1092 bg = RBIOS8(dac_info + 0x4) & 0xf;
1093 dac = RBIOS8(dac_info + 0x5) & 0xf;
1094 tv_dac->ps2_tvdac_adj =
1095 (bg << 16) | (dac << 20);
1096 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1097 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1098 /* if the values are all zeros, use the table */
1099 if (tv_dac->ps2_tvdac_adj)
1100 found = 1;
771fe6b9 1101 }
6fe7ac3f
AD		 1102 } else {
1103 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 1104 }
1105 }
1106
6a719e05
DA		 1107 if (!found) /* fallback to defaults */
1108 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1109
771fe6b9
JG		 1110 return tv_dac;
1111}
1112
1113static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1114 radeon_device
1115 *rdev)
1116{
1117 struct radeon_encoder_lvds *lvds = NULL;
1118 uint32_t fp_vert_stretch, fp_horz_stretch;
1119 uint32_t ppll_div_sel, ppll_val;
8b5c7444 1120 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 1121
1122 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1123
1124 if (!lvds)
1125 return NULL;
1126
1127 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1128 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1129
8b5c7444
MD		 1130 /* These should be fail-safe defaults, fingers crossed */
1131 lvds->panel_pwr_delay = 200;
1132 lvds->panel_vcc_delay = 2000;
1133
1134 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1135 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1136 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1137
771fe6b9 1138 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 1139 lvds->native_mode.vdisplay =
771fe6b9
JG		 1140 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1141 RADEON_VERT_PANEL_SHIFT) + 1;
1142 else
de2103e4 1143 lvds->native_mode.vdisplay =
771fe6b9
JG		 1144 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1145
1146 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 1147 lvds->native_mode.hdisplay =
771fe6b9
JG		 1148 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1149 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1150 else
de2103e4 1151 lvds->native_mode.hdisplay =
771fe6b9
JG		 1152 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1153
de2103e4
AD		 1154 if ((lvds->native_mode.hdisplay < 640) ||
1155 (lvds->native_mode.vdisplay < 480)) {
1156 lvds->native_mode.hdisplay = 640;
1157 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1158 }
1159
1160 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1161 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1162 if ((ppll_val & 0x000707ff) == 0x1bb)
1163 lvds->use_bios_dividers = false;
1164 else {
1165 lvds->panel_ref_divider =
1166 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1167 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1168 lvds->panel_fb_divider = ppll_val & 0x7ff;
1169
1170 if ((lvds->panel_ref_divider != 0) &&
1171 (lvds->panel_fb_divider > 3))
1172 lvds->use_bios_dividers = true;
1173 }
1174 lvds->panel_vcc_delay = 200;
1175
1176 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1177 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1178 lvds->native_mode.vdisplay);
771fe6b9
JG		 1179
1180 return lvds;
1181}
1182
1183struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1184 *encoder)
1185{
1186 struct drm_device *dev = encoder->base.dev;
1187 struct radeon_device *rdev = dev->dev_private;
1188 uint16_t lcd_info;
1189 uint32_t panel_setup;
1190 char stmp[30];
1191 int tmp, i;
1192 struct radeon_encoder_lvds *lvds = NULL;
1193
771fe6b9
JG		 1194 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1195
1196 if (lcd_info) {
1197 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1198
1199 if (!lvds)
1200 return NULL;
1201
1202 for (i = 0; i < 24; i++)
1203 stmp[i] = RBIOS8(lcd_info + i + 1);
1204 stmp[24] = 0;
1205
1206 DRM_INFO("Panel ID String: %s\n", stmp);
1207
de2103e4
AD		 1208 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1209 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1210
de2103e4
AD		 1211 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1212 lvds->native_mode.vdisplay);
771fe6b9
JG		 1213
1214 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1215 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1216
1217 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1218 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1219 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1220
1221 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1222 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1223 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1224 if ((lvds->panel_ref_divider != 0) &&
1225 (lvds->panel_fb_divider > 3))
1226 lvds->use_bios_dividers = true;
1227
1228 panel_setup = RBIOS32(lcd_info + 0x39);
1229 lvds->lvds_gen_cntl = 0xff00;
1230 if (panel_setup & 0x1)
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1232
1233 if ((panel_setup >> 4) & 0x1)
1234 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1235
1236 switch ((panel_setup >> 8) & 0x7) {
1237 case 0:
1238 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1239 break;
1240 case 1:
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1242 break;
1243 case 2:
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 if ((panel_setup >> 16) & 0x1)
1251 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1252
1253 if ((panel_setup >> 17) & 0x1)
1254 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1255
1256 if ((panel_setup >> 18) & 0x1)
1257 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1258
1259 if ((panel_setup >> 23) & 0x1)
1260 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1261
1262 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1263
1264 for (i = 0; i < 32; i++) {
1265 tmp = RBIOS16(lcd_info + 64 + i * 2);
1266 if (tmp == 0)
1267 break;
1268
de2103e4 1269 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f
AD		 1270 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1271 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1272 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1273 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1274 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1275 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1276 (RBIOS8(tmp + 23) * 8);
1277
1278 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1279 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1280 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1281 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1282 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1283 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1284
1285 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1286 lvds->native_mode.flags = 0;
de2103e4
AD		 1287 /* set crtc values */
1288 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1289
771fe6b9
JG		 1290 }
1291 }
6fe7ac3f 1292 } else {
771fe6b9 1293 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1294 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1295 }
03047cdf 1296
8dfaa8a7
MD		 1297 if (lvds)
1298 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1299 return lvds;
1300}
1301
1302static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1303 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1304 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1305 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1306 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1307 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1308 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1309 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1310 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1311 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1312 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1313 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1314 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1315 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1316 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1317 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1318 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1319 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1320 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1321};
1322
445282db
DA		 1323bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1324 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1325{
445282db
DA		 1326 struct drm_device *dev = encoder->base.dev;
1327 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1328 int i;
771fe6b9
JG		 1329
1330 for (i = 0; i < 4; i++) {
1331 tmds->tmds_pll[i].value =
445282db 1332 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1333 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1334 }
1335
445282db 1336 return true;
771fe6b9
JG		 1337}
1338
445282db
DA		 1339bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1340 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1341{
1342 struct drm_device *dev = encoder->base.dev;
1343 struct radeon_device *rdev = dev->dev_private;
1344 uint16_t tmds_info;
1345 int i, n;
1346 uint8_t ver;
771fe6b9 1347
771fe6b9
JG		 1348 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1349
1350 if (tmds_info) {
771fe6b9 1351 ver = RBIOS8(tmds_info);
40f76d81 1352 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
771fe6b9
JG		 1353 if (ver == 3) {
1354 n = RBIOS8(tmds_info + 5) + 1;
1355 if (n > 4)
1356 n = 4;
1357 for (i = 0; i < n; i++) {
1358 tmds->tmds_pll[i].value =
1359 RBIOS32(tmds_info + i * 10 + 0x08);
1360 tmds->tmds_pll[i].freq =
1361 RBIOS16(tmds_info + i * 10 + 0x10);
d9fdaafb 1362 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1363 tmds->tmds_pll[i].freq,
1364 tmds->tmds_pll[i].value);
1365 }
1366 } else if (ver == 4) {
1367 int stride = 0;
1368 n = RBIOS8(tmds_info + 5) + 1;
1369 if (n > 4)
1370 n = 4;
1371 for (i = 0; i < n; i++) {
1372 tmds->tmds_pll[i].value =
1373 RBIOS32(tmds_info + stride + 0x08);
1374 tmds->tmds_pll[i].freq =
1375 RBIOS16(tmds_info + stride + 0x10);
1376 if (i == 0)
1377 stride += 10;
1378 else
1379 stride += 6;
d9fdaafb 1380 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1381 tmds->tmds_pll[i].freq,
1382 tmds->tmds_pll[i].value);
1383 }
1384 }
fcec570b 1385 } else {
771fe6b9 1386 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1387 return false;
1388 }
445282db
DA		 1389 return true;
1390}
1391
fcec570b
AD		 1392bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1393 struct radeon_encoder_ext_tmds *tmds)
445282db 1394{
fcec570b
AD		 1395 struct drm_device *dev = encoder->base.dev;
1396 struct radeon_device *rdev = dev->dev_private;
1397 struct radeon_i2c_bus_rec i2c_bus;
445282db 1398
fcec570b 1399 /* default for macs */
179e8078 1400 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
f376b94f 1401 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
445282db 1402
fcec570b
AD		 1403 /* XXX some macs have duallink chips */
1404 switch (rdev->mode_info.connector_table) {
1405 case CT_POWERBOOK_EXTERNAL:
1406 case CT_MINI_EXTERNAL:
1407 default:
1408 tmds->dvo_chip = DVO_SIL164;
1409 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1410 break;
1411 }
445282db 1412
fcec570b 1413 return true;
771fe6b9
JG		 1414}
1415
fcec570b
AD		 1416bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1417 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1418{
1419 struct drm_device *dev = encoder->base.dev;
1420 struct radeon_device *rdev = dev->dev_private;
fcec570b 1421 uint16_t offset;
179e8078 1422 uint8_t ver;
fcec570b
AD		 1423 enum radeon_combios_ddc gpio;
1424 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1425
fcec570b
AD		 1426 tmds->i2c_bus = NULL;
1427 if (rdev->flags & RADEON_IS_IGP) {
179e8078
AD		 1428 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1429 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1430 tmds->dvo_chip = DVO_SIL164;
1431 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
fcec570b
AD		 1432 } else {
1433 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1434 if (offset) {
1435 ver = RBIOS8(offset);
40f76d81 1436 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
fcec570b
AD		 1437 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1438 tmds->slave_addr >>= 1; /* 7 bit addressing */
1439 gpio = RBIOS8(offset + 4 + 3);
179e8078
AD		 1440 if (gpio == DDC_LCD) {
1441 /* MM i2c */
40bacf16
AD		 1442 i2c_bus.valid = true;
1443 i2c_bus.hw_capable = true;
1444 i2c_bus.mm_i2c = true;
179e8078
AD		 1445 i2c_bus.i2c_id = 0xa0;
1446 } else
1447 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1448 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
fcec570b 1449 }
771fe6b9 1450 }
fcec570b
AD		 1451
1452 if (!tmds->i2c_bus) {
1453 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1454 return false;
1455 }
1456
1457 return true;
771fe6b9
JG		 1458}
1459
1460bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1461{
1462 struct radeon_device *rdev = dev->dev_private;
1463 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1464 struct radeon_hpd hpd;
771fe6b9
JG		 1465
1466 rdev->mode_info.connector_table = radeon_connector_table;
1467 if (rdev->mode_info.connector_table == CT_NONE) {
1468#ifdef CONFIG_PPC_PMAC
71a157e8 1469 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1470 /* powerbook with VGA */
1471 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1472 } else if (of_machine_is_compatible("PowerBook3,4") ||
1473 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1474 /* powerbook with internal tmds */
1475 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1476 } else if (of_machine_is_compatible("PowerBook5,1") ||
1477 of_machine_is_compatible("PowerBook5,2") ||
1478 of_machine_is_compatible("PowerBook5,3") ||
1479 of_machine_is_compatible("PowerBook5,4") ||
1480 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1481 /* powerbook with external single link tmds (sil164) */
1482 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1483 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1484 /* powerbook with external dual or single link tmds */
1485 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1486 } else if (of_machine_is_compatible("PowerBook5,7") ||
1487 of_machine_is_compatible("PowerBook5,8") ||
1488 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1489 /* PowerBook6,2 ? */
1490 /* powerbook with external dual link tmds (sil1178?) */
1491 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1492 } else if (of_machine_is_compatible("PowerBook4,1") ||
1493 of_machine_is_compatible("PowerBook4,2") ||
1494 of_machine_is_compatible("PowerBook4,3") ||
1495 of_machine_is_compatible("PowerBook6,3") ||
1496 of_machine_is_compatible("PowerBook6,5") ||
1497 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1498 /* ibook */
1499 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1500 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1501 /* emac */
1502 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1503 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1504 /* mini with internal tmds */
1505 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1506 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1507 /* mini with external tmds */
1508 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1509 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1510 /* PowerMac8,1 ? */
1511 /* imac g5 isight */
1512 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
aa74fbb4
AD		 1513 } else if ((rdev->pdev->device == 0x4a48) &&
1514 (rdev->pdev->subsystem_vendor == 0x1002) &&
1515 (rdev->pdev->subsystem_device == 0x4a48)) {
1516 /* Mac X800 */
1517 rdev->mode_info.connector_table = CT_MAC_X800;
9fad321a
AD		 1518 } else if ((rdev->pdev->device == 0x4150) &&
1519 (rdev->pdev->subsystem_vendor == 0x1002) &&
1520 (rdev->pdev->subsystem_device == 0x4150)) {
1521 /* Mac G5 9600 */
1522 rdev->mode_info.connector_table = CT_MAC_G5_9600;
771fe6b9
JG		 1523 } else
1524#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1525#ifdef CONFIG_PPC64
1526 if (ASIC_IS_RN50(rdev))
1527 rdev->mode_info.connector_table = CT_RN50_POWER;
1528 else
1529#endif
771fe6b9
JG		 1530 rdev->mode_info.connector_table = CT_GENERIC;
1531 }
1532
1533 switch (rdev->mode_info.connector_table) {
1534 case CT_GENERIC:
1535 DRM_INFO("Connector Table: %d (generic)\n",
1536 rdev->mode_info.connector_table);
1537 /* these are the most common settings */
1538 if (rdev->flags & RADEON_SINGLE_CRTC) {
1539 /* VGA - primary dac */
179e8078 1540 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1541 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1542 radeon_add_legacy_encoder(dev,
5137ee94 1543 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1544 ATOM_DEVICE_CRT1_SUPPORT,
1545 1),
1546 ATOM_DEVICE_CRT1_SUPPORT);
1547 radeon_add_legacy_connector(dev, 0,
1548 ATOM_DEVICE_CRT1_SUPPORT,
1549 DRM_MODE_CONNECTOR_VGA,
b75fad06 1550 &ddc_i2c,
eed45b30
AD		 1551 CONNECTOR_OBJECT_ID_VGA,
1552 &hpd);
771fe6b9
JG		 1553 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1554 /* LVDS */
179e8078 1555 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
eed45b30 1556 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1557 radeon_add_legacy_encoder(dev,
5137ee94 1558 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1559 ATOM_DEVICE_LCD1_SUPPORT,
1560 0),
1561 ATOM_DEVICE_LCD1_SUPPORT);
1562 radeon_add_legacy_connector(dev, 0,
1563 ATOM_DEVICE_LCD1_SUPPORT,
1564 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1565 &ddc_i2c,
eed45b30
AD		 1566 CONNECTOR_OBJECT_ID_LVDS,
1567 &hpd);
771fe6b9
JG		 1568
1569 /* VGA - primary dac */
179e8078 1570 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1571 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1572 radeon_add_legacy_encoder(dev,
5137ee94 1573 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1574 ATOM_DEVICE_CRT1_SUPPORT,
1575 1),
1576 ATOM_DEVICE_CRT1_SUPPORT);
1577 radeon_add_legacy_connector(dev, 1,
1578 ATOM_DEVICE_CRT1_SUPPORT,
1579 DRM_MODE_CONNECTOR_VGA,
b75fad06 1580 &ddc_i2c,
eed45b30
AD		 1581 CONNECTOR_OBJECT_ID_VGA,
1582 &hpd);
771fe6b9
JG		 1583 } else {
1584 /* DVI-I - tv dac, int tmds */
179e8078 1585 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1586 hpd.hpd = RADEON_HPD_1;
771fe6b9 1587 radeon_add_legacy_encoder(dev,
5137ee94 1588 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1589 ATOM_DEVICE_DFP1_SUPPORT,
1590 0),
1591 ATOM_DEVICE_DFP1_SUPPORT);
1592 radeon_add_legacy_encoder(dev,
5137ee94 1593 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1594 ATOM_DEVICE_CRT2_SUPPORT,
1595 2),
1596 ATOM_DEVICE_CRT2_SUPPORT);
1597 radeon_add_legacy_connector(dev, 0,
1598 ATOM_DEVICE_DFP1_SUPPORT |
1599 ATOM_DEVICE_CRT2_SUPPORT,
1600 DRM_MODE_CONNECTOR_DVII,
b75fad06 1601 &ddc_i2c,
eed45b30
AD		 1602 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1603 &hpd);
771fe6b9
JG		 1604
1605 /* VGA - primary dac */
179e8078 1606 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1607 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1608 radeon_add_legacy_encoder(dev,
5137ee94 1609 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1610 ATOM_DEVICE_CRT1_SUPPORT,
1611 1),
1612 ATOM_DEVICE_CRT1_SUPPORT);
1613 radeon_add_legacy_connector(dev, 1,
1614 ATOM_DEVICE_CRT1_SUPPORT,
1615 DRM_MODE_CONNECTOR_VGA,
b75fad06 1616 &ddc_i2c,
eed45b30
AD		 1617 CONNECTOR_OBJECT_ID_VGA,
1618 &hpd);
771fe6b9
JG		 1619 }
1620
1621 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1622 /* TV - tv dac */
eed45b30
AD		 1623 ddc_i2c.valid = false;
1624 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1625 radeon_add_legacy_encoder(dev,
5137ee94 1626 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1627 ATOM_DEVICE_TV1_SUPPORT,
1628 2),
1629 ATOM_DEVICE_TV1_SUPPORT);
1630 radeon_add_legacy_connector(dev, 2,
1631 ATOM_DEVICE_TV1_SUPPORT,
1632 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1633 &ddc_i2c,
eed45b30
AD		 1634 CONNECTOR_OBJECT_ID_SVIDEO,
1635 &hpd);
771fe6b9
JG		 1636 }
1637 break;
1638 case CT_IBOOK:
1639 DRM_INFO("Connector Table: %d (ibook)\n",
1640 rdev->mode_info.connector_table);
1641 /* LVDS */
179e8078 1642 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1643 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1644 radeon_add_legacy_encoder(dev,
5137ee94 1645 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1646 ATOM_DEVICE_LCD1_SUPPORT,
1647 0),
1648 ATOM_DEVICE_LCD1_SUPPORT);
1649 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1650 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1651 CONNECTOR_OBJECT_ID_LVDS,
1652 &hpd);
771fe6b9 1653 /* VGA - TV DAC */
179e8078 1654 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1655 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1656 radeon_add_legacy_encoder(dev,
5137ee94 1657 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1658 ATOM_DEVICE_CRT2_SUPPORT,
1659 2),
1660 ATOM_DEVICE_CRT2_SUPPORT);
1661 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1662 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1663 CONNECTOR_OBJECT_ID_VGA,
1664 &hpd);
771fe6b9 1665 /* TV - TV DAC */
eed45b30
AD		 1666 ddc_i2c.valid = false;
1667 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1668 radeon_add_legacy_encoder(dev,
5137ee94 1669 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1670 ATOM_DEVICE_TV1_SUPPORT,
1671 2),
1672 ATOM_DEVICE_TV1_SUPPORT);
1673 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1674 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1675 &ddc_i2c,
eed45b30
AD		 1676 CONNECTOR_OBJECT_ID_SVIDEO,
1677 &hpd);
771fe6b9
JG		 1678 break;
1679 case CT_POWERBOOK_EXTERNAL:
1680 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1681 rdev->mode_info.connector_table);
1682 /* LVDS */
179e8078 1683 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1684 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1685 radeon_add_legacy_encoder(dev,
5137ee94 1686 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1687 ATOM_DEVICE_LCD1_SUPPORT,
1688 0),
1689 ATOM_DEVICE_LCD1_SUPPORT);
1690 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1691 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1692 CONNECTOR_OBJECT_ID_LVDS,
1693 &hpd);
771fe6b9 1694 /* DVI-I - primary dac, ext tmds */
179e8078 1695 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1696 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1697 radeon_add_legacy_encoder(dev,
5137ee94 1698 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1699 ATOM_DEVICE_DFP2_SUPPORT,
1700 0),
1701 ATOM_DEVICE_DFP2_SUPPORT);
1702 radeon_add_legacy_encoder(dev,
5137ee94 1703 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1704 ATOM_DEVICE_CRT1_SUPPORT,
1705 1),
1706 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1707 /* XXX some are SL */
771fe6b9
JG		 1708 radeon_add_legacy_connector(dev, 1,
1709 ATOM_DEVICE_DFP2_SUPPORT |
1710 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1711 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1712 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1713 &hpd);
771fe6b9 1714 /* TV - TV DAC */
eed45b30
AD		 1715 ddc_i2c.valid = false;
1716 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1717 radeon_add_legacy_encoder(dev,
5137ee94 1718 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1719 ATOM_DEVICE_TV1_SUPPORT,
1720 2),
1721 ATOM_DEVICE_TV1_SUPPORT);
1722 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1723 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1724 &ddc_i2c,
eed45b30
AD		 1725 CONNECTOR_OBJECT_ID_SVIDEO,
1726 &hpd);
771fe6b9
JG		 1727 break;
1728 case CT_POWERBOOK_INTERNAL:
1729 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1730 rdev->mode_info.connector_table);
1731 /* LVDS */
179e8078 1732 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1733 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1734 radeon_add_legacy_encoder(dev,
5137ee94 1735 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1736 ATOM_DEVICE_LCD1_SUPPORT,
1737 0),
1738 ATOM_DEVICE_LCD1_SUPPORT);
1739 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1740 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1741 CONNECTOR_OBJECT_ID_LVDS,
1742 &hpd);
771fe6b9 1743 /* DVI-I - primary dac, int tmds */
179e8078 1744 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1745 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1746 radeon_add_legacy_encoder(dev,
5137ee94 1747 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1748 ATOM_DEVICE_DFP1_SUPPORT,
1749 0),
1750 ATOM_DEVICE_DFP1_SUPPORT);
1751 radeon_add_legacy_encoder(dev,
5137ee94 1752 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1753 ATOM_DEVICE_CRT1_SUPPORT,
1754 1),
1755 ATOM_DEVICE_CRT1_SUPPORT);
1756 radeon_add_legacy_connector(dev, 1,
1757 ATOM_DEVICE_DFP1_SUPPORT |
1758 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1759 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1760 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1761 &hpd);
771fe6b9 1762 /* TV - TV DAC */
eed45b30
AD		 1763 ddc_i2c.valid = false;
1764 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1765 radeon_add_legacy_encoder(dev,
5137ee94 1766 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1767 ATOM_DEVICE_TV1_SUPPORT,
1768 2),
1769 ATOM_DEVICE_TV1_SUPPORT);
1770 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1771 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1772 &ddc_i2c,
eed45b30
AD		 1773 CONNECTOR_OBJECT_ID_SVIDEO,
1774 &hpd);
771fe6b9
JG		 1775 break;
1776 case CT_POWERBOOK_VGA:
1777 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1778 rdev->mode_info.connector_table);
1779 /* LVDS */
179e8078 1780 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1781 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1782 radeon_add_legacy_encoder(dev,
5137ee94 1783 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1784 ATOM_DEVICE_LCD1_SUPPORT,
1785 0),
1786 ATOM_DEVICE_LCD1_SUPPORT);
1787 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1788 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1789 CONNECTOR_OBJECT_ID_LVDS,
1790 &hpd);
771fe6b9 1791 /* VGA - primary dac */
179e8078 1792 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1793 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1794 radeon_add_legacy_encoder(dev,
5137ee94 1795 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1796 ATOM_DEVICE_CRT1_SUPPORT,
1797 1),
1798 ATOM_DEVICE_CRT1_SUPPORT);
1799 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1800 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1801 CONNECTOR_OBJECT_ID_VGA,
1802 &hpd);
771fe6b9 1803 /* TV - TV DAC */
eed45b30
AD		 1804 ddc_i2c.valid = false;
1805 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1806 radeon_add_legacy_encoder(dev,
5137ee94 1807 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1808 ATOM_DEVICE_TV1_SUPPORT,
1809 2),
1810 ATOM_DEVICE_TV1_SUPPORT);
1811 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1812 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1813 &ddc_i2c,
eed45b30
AD		 1814 CONNECTOR_OBJECT_ID_SVIDEO,
1815 &hpd);
771fe6b9
JG		 1816 break;
1817 case CT_MINI_EXTERNAL:
1818 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1819 rdev->mode_info.connector_table);
1820 /* DVI-I - tv dac, ext tmds */
179e8078 1821 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1822 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1823 radeon_add_legacy_encoder(dev,
5137ee94 1824 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1825 ATOM_DEVICE_DFP2_SUPPORT,
1826 0),
1827 ATOM_DEVICE_DFP2_SUPPORT);
1828 radeon_add_legacy_encoder(dev,
5137ee94 1829 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1830 ATOM_DEVICE_CRT2_SUPPORT,
1831 2),
1832 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1833 /* XXX are any DL? */
771fe6b9
JG		 1834 radeon_add_legacy_connector(dev, 0,
1835 ATOM_DEVICE_DFP2_SUPPORT |
1836 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1837 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1838 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1839 &hpd);
771fe6b9 1840 /* TV - TV DAC */
eed45b30
AD		 1841 ddc_i2c.valid = false;
1842 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1843 radeon_add_legacy_encoder(dev,
5137ee94 1844 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1845 ATOM_DEVICE_TV1_SUPPORT,
1846 2),
1847 ATOM_DEVICE_TV1_SUPPORT);
1848 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1849 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1850 &ddc_i2c,
eed45b30
AD		 1851 CONNECTOR_OBJECT_ID_SVIDEO,
1852 &hpd);
771fe6b9
JG		 1853 break;
1854 case CT_MINI_INTERNAL:
1855 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1856 rdev->mode_info.connector_table);
1857 /* DVI-I - tv dac, int tmds */
179e8078 1858 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1859 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1860 radeon_add_legacy_encoder(dev,
5137ee94 1861 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1862 ATOM_DEVICE_DFP1_SUPPORT,
1863 0),
1864 ATOM_DEVICE_DFP1_SUPPORT);
1865 radeon_add_legacy_encoder(dev,
5137ee94 1866 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1867 ATOM_DEVICE_CRT2_SUPPORT,
1868 2),
1869 ATOM_DEVICE_CRT2_SUPPORT);
1870 radeon_add_legacy_connector(dev, 0,
1871 ATOM_DEVICE_DFP1_SUPPORT |
1872 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1873 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1874 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1875 &hpd);
771fe6b9 1876 /* TV - TV DAC */
eed45b30
AD		 1877 ddc_i2c.valid = false;
1878 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1879 radeon_add_legacy_encoder(dev,
5137ee94 1880 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1881 ATOM_DEVICE_TV1_SUPPORT,
1882 2),
1883 ATOM_DEVICE_TV1_SUPPORT);
1884 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1885 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1886 &ddc_i2c,
eed45b30
AD		 1887 CONNECTOR_OBJECT_ID_SVIDEO,
1888 &hpd);
771fe6b9
JG		 1889 break;
1890 case CT_IMAC_G5_ISIGHT:
1891 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1892 rdev->mode_info.connector_table);
1893 /* DVI-D - int tmds */
179e8078 1894 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
eed45b30 1895 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1896 radeon_add_legacy_encoder(dev,
5137ee94 1897 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1898 ATOM_DEVICE_DFP1_SUPPORT,
1899 0),
1900 ATOM_DEVICE_DFP1_SUPPORT);
1901 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1902 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1903 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1904 &hpd);
771fe6b9 1905 /* VGA - tv dac */
179e8078 1906 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1907 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1908 radeon_add_legacy_encoder(dev,
5137ee94 1909 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1910 ATOM_DEVICE_CRT2_SUPPORT,
1911 2),
1912 ATOM_DEVICE_CRT2_SUPPORT);
1913 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1914 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1915 CONNECTOR_OBJECT_ID_VGA,
1916 &hpd);
771fe6b9 1917 /* TV - TV DAC */
eed45b30
AD		 1918 ddc_i2c.valid = false;
1919 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1920 radeon_add_legacy_encoder(dev,
5137ee94 1921 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1922 ATOM_DEVICE_TV1_SUPPORT,
1923 2),
1924 ATOM_DEVICE_TV1_SUPPORT);
1925 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1926 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1927 &ddc_i2c,
eed45b30
AD		 1928 CONNECTOR_OBJECT_ID_SVIDEO,
1929 &hpd);
771fe6b9
JG		 1930 break;
1931 case CT_EMAC:
1932 DRM_INFO("Connector Table: %d (emac)\n",
1933 rdev->mode_info.connector_table);
1934 /* VGA - primary dac */
179e8078 1935 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1936 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1937 radeon_add_legacy_encoder(dev,
5137ee94 1938 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1939 ATOM_DEVICE_CRT1_SUPPORT,
1940 1),
1941 ATOM_DEVICE_CRT1_SUPPORT);
1942 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1943 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1944 CONNECTOR_OBJECT_ID_VGA,
1945 &hpd);
771fe6b9 1946 /* VGA - tv dac */
179e8078 1947 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1948 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1949 radeon_add_legacy_encoder(dev,
5137ee94 1950 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1951 ATOM_DEVICE_CRT2_SUPPORT,
1952 2),
1953 ATOM_DEVICE_CRT2_SUPPORT);
1954 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1955 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1956 CONNECTOR_OBJECT_ID_VGA,
1957 &hpd);
771fe6b9 1958 /* TV - TV DAC */
eed45b30
AD		 1959 ddc_i2c.valid = false;
1960 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1961 radeon_add_legacy_encoder(dev,
5137ee94 1962 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1963 ATOM_DEVICE_TV1_SUPPORT,
1964 2),
1965 ATOM_DEVICE_TV1_SUPPORT);
1966 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1967 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1968 &ddc_i2c,
eed45b30
AD		 1969 CONNECTOR_OBJECT_ID_SVIDEO,
1970 &hpd);
771fe6b9 1971 break;
76a7142a
DA		 1972 case CT_RN50_POWER:
1973 DRM_INFO("Connector Table: %d (rn50-power)\n",
1974 rdev->mode_info.connector_table);
1975 /* VGA - primary dac */
179e8078 1976 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
76a7142a
DA		 1977 hpd.hpd = RADEON_HPD_NONE;
1978 radeon_add_legacy_encoder(dev,
5137ee94 1979 radeon_get_encoder_enum(dev,
76a7142a
DA		 1980 ATOM_DEVICE_CRT1_SUPPORT,
1981 1),
1982 ATOM_DEVICE_CRT1_SUPPORT);
1983 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1984 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985 CONNECTOR_OBJECT_ID_VGA,
1986 &hpd);
179e8078 1987 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
76a7142a
DA		 1988 hpd.hpd = RADEON_HPD_NONE;
1989 radeon_add_legacy_encoder(dev,
5137ee94 1990 radeon_get_encoder_enum(dev,
76a7142a
DA		 1991 ATOM_DEVICE_CRT2_SUPPORT,
1992 2),
1993 ATOM_DEVICE_CRT2_SUPPORT);
1994 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1995 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1996 CONNECTOR_OBJECT_ID_VGA,
1997 &hpd);
1998 break;
aa74fbb4
AD		 1999 case CT_MAC_X800:
2000 DRM_INFO("Connector Table: %d (mac x800)\n",
2001 rdev->mode_info.connector_table);
2002 /* DVI - primary dac, internal tmds */
2003 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2004 hpd.hpd = RADEON_HPD_1; /* ??? */
2005 radeon_add_legacy_encoder(dev,
2006 radeon_get_encoder_enum(dev,
2007 ATOM_DEVICE_DFP1_SUPPORT,
2008 0),
2009 ATOM_DEVICE_DFP1_SUPPORT);
2010 radeon_add_legacy_encoder(dev,
2011 radeon_get_encoder_enum(dev,
2012 ATOM_DEVICE_CRT1_SUPPORT,
2013 1),
2014 ATOM_DEVICE_CRT1_SUPPORT);
2015 radeon_add_legacy_connector(dev, 0,
2016 ATOM_DEVICE_DFP1_SUPPORT |
2017 ATOM_DEVICE_CRT1_SUPPORT,
2018 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2019 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2020 &hpd);
2021 /* DVI - tv dac, dvo */
2022 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2023 hpd.hpd = RADEON_HPD_2; /* ??? */
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_enum(dev,
2026 ATOM_DEVICE_DFP2_SUPPORT,
2027 0),
2028 ATOM_DEVICE_DFP2_SUPPORT);
2029 radeon_add_legacy_encoder(dev,
2030 radeon_get_encoder_enum(dev,
2031 ATOM_DEVICE_CRT2_SUPPORT,
2032 2),
2033 ATOM_DEVICE_CRT2_SUPPORT);
2034 radeon_add_legacy_connector(dev, 1,
2035 ATOM_DEVICE_DFP2_SUPPORT |
2036 ATOM_DEVICE_CRT2_SUPPORT,
2037 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2038 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2039 &hpd);
2040 break;
9fad321a
AD		 2041 case CT_MAC_G5_9600:
2042 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2043 rdev->mode_info.connector_table);
2044 /* DVI - tv dac, dvo */
2045 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2046 hpd.hpd = RADEON_HPD_1; /* ??? */
2047 radeon_add_legacy_encoder(dev,
2048 radeon_get_encoder_enum(dev,
2049 ATOM_DEVICE_DFP2_SUPPORT,
2050 0),
2051 ATOM_DEVICE_DFP2_SUPPORT);
2052 radeon_add_legacy_encoder(dev,
2053 radeon_get_encoder_enum(dev,
2054 ATOM_DEVICE_CRT2_SUPPORT,
2055 2),
2056 ATOM_DEVICE_CRT2_SUPPORT);
2057 radeon_add_legacy_connector(dev, 0,
2058 ATOM_DEVICE_DFP2_SUPPORT |
2059 ATOM_DEVICE_CRT2_SUPPORT,
2060 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2061 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2062 &hpd);
2063 /* ADC - primary dac, internal tmds */
2064 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2065 hpd.hpd = RADEON_HPD_2; /* ??? */
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_enum(dev,
2068 ATOM_DEVICE_DFP1_SUPPORT,
2069 0),
2070 ATOM_DEVICE_DFP1_SUPPORT);
2071 radeon_add_legacy_encoder(dev,
2072 radeon_get_encoder_enum(dev,
2073 ATOM_DEVICE_CRT1_SUPPORT,
2074 1),
2075 ATOM_DEVICE_CRT1_SUPPORT);
2076 radeon_add_legacy_connector(dev, 1,
2077 ATOM_DEVICE_DFP1_SUPPORT |
2078 ATOM_DEVICE_CRT1_SUPPORT,
2079 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2080 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2081 &hpd);
beb47274
AD		 2082 /* TV - TV DAC */
2083 ddc_i2c.valid = false;
2084 hpd.hpd = RADEON_HPD_NONE;
2085 radeon_add_legacy_encoder(dev,
2086 radeon_get_encoder_enum(dev,
2087 ATOM_DEVICE_TV1_SUPPORT,
2088 2),
2089 ATOM_DEVICE_TV1_SUPPORT);
2090 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2091 DRM_MODE_CONNECTOR_SVIDEO,
2092 &ddc_i2c,
2093 CONNECTOR_OBJECT_ID_SVIDEO,
2094 &hpd);
9fad321a 2095 break;
771fe6b9
JG		 2096 default:
2097 DRM_INFO("Connector table: %d (invalid)\n",
2098 rdev->mode_info.connector_table);
2099 return false;
2100 }
2101
2102 radeon_link_encoder_connector(dev);
2103
2104 return true;
2105}
2106
2107static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2108 int bios_index,
2109 enum radeon_combios_connector
2110 *legacy_connector,
eed45b30
AD		 2111 struct radeon_i2c_bus_rec *ddc_i2c,
2112 struct radeon_hpd *hpd)
771fe6b9 2113{
fcec570b 2114
771fe6b9
JG		 2115 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2116 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2117 if (dev->pdev->device == 0x515e &&
2118 dev->pdev->subsystem_vendor == 0x1014) {
2119 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2120 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2121 return false;
2122 }
2123
771fe6b9
JG		 2124 /* X300 card with extra non-existent DVI port */
2125 if (dev->pdev->device == 0x5B60 &&
2126 dev->pdev->subsystem_vendor == 0x17af &&
2127 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2128 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2129 return false;
2130 }
2131
2132 return true;
2133}
2134
790cfb34
AD		 2135static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2136{
2137 /* Acer 5102 has non-existent TV port */
2138 if (dev->pdev->device == 0x5975 &&
2139 dev->pdev->subsystem_vendor == 0x1025 &&
2140 dev->pdev->subsystem_device == 0x009f)
2141 return false;
2142
fc7f7119
AD		 2143 /* HP dc5750 has non-existent TV port */
2144 if (dev->pdev->device == 0x5974 &&
2145 dev->pdev->subsystem_vendor == 0x103c &&
2146 dev->pdev->subsystem_device == 0x280a)
2147 return false;
2148
fd874ad0
AD		 2149 /* MSI S270 has non-existent TV port */
2150 if (dev->pdev->device == 0x5955 &&
2151 dev->pdev->subsystem_vendor == 0x1462 &&
2152 dev->pdev->subsystem_device == 0x0131)
2153 return false;
2154
790cfb34
AD		 2155 return true;
2156}
2157
b75fad06
AD		 2158static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2159{
2160 struct radeon_device *rdev = dev->dev_private;
2161 uint32_t ext_tmds_info;
2162
2163 if (rdev->flags & RADEON_IS_IGP) {
2164 if (is_dvi_d)
2165 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2166 else
2167 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2168 }
2169 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2170 if (ext_tmds_info) {
2171 uint8_t rev = RBIOS8(ext_tmds_info);
2172 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2173 if (rev >= 3) {
2174 if (is_dvi_d)
2175 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2176 else
2177 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2178 } else {
2179 if (flags & 1) {
2180 if (is_dvi_d)
2181 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2182 else
2183 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2184 }
2185 }
2186 }
2187 if (is_dvi_d)
2188 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2189 else
2190 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2191}
2192
771fe6b9
JG		 2193bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2194{
2195 struct radeon_device *rdev = dev->dev_private;
2196 uint32_t conn_info, entry, devices;
b75fad06 2197 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2198 enum radeon_combios_ddc ddc_type;
2199 enum radeon_combios_connector connector;
2200 int i = 0;
2201 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2202 struct radeon_hpd hpd;
771fe6b9 2203
771fe6b9
JG		 2204 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2205 if (conn_info) {
2206 for (i = 0; i < 4; i++) {
2207 entry = conn_info + 2 + i * 2;
2208
2209 if (!RBIOS16(entry))
2210 break;
2211
2212 tmp = RBIOS16(entry);
2213
2214 connector = (tmp >> 12) & 0xf;
2215
2216 ddc_type = (tmp >> 8) & 0xf;
179e8078 2217 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9 2218
eed45b30
AD		 2219 switch (connector) {
2220 case CONNECTOR_PROPRIETARY_LEGACY:
2221 case CONNECTOR_DVI_I_LEGACY:
2222 case CONNECTOR_DVI_D_LEGACY:
2223 if ((tmp >> 4) & 0x1)
2224 hpd.hpd = RADEON_HPD_2;
2225 else
2226 hpd.hpd = RADEON_HPD_1;
2227 break;
2228 default:
2229 hpd.hpd = RADEON_HPD_NONE;
2230 break;
2231 }
2232
2d152c6b 2233 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2234 &ddc_i2c, &hpd))
2d152c6b 2235 continue;
771fe6b9
JG		 2236
2237 switch (connector) {
2238 case CONNECTOR_PROPRIETARY_LEGACY:
2239 if ((tmp >> 4) & 0x1)
2240 devices = ATOM_DEVICE_DFP2_SUPPORT;
2241 else
2242 devices = ATOM_DEVICE_DFP1_SUPPORT;
2243 radeon_add_legacy_encoder(dev,
5137ee94 2244 radeon_get_encoder_enum
771fe6b9
JG		 2245 (dev, devices, 0),
2246 devices);
2247 radeon_add_legacy_connector(dev, i, devices,
2248 legacy_connector_convert
2249 [connector],
b75fad06 2250 &ddc_i2c,
eed45b30
AD		 2251 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2252 &hpd);
771fe6b9
JG		 2253 break;
2254 case CONNECTOR_CRT_LEGACY:
2255 if (tmp & 0x1) {
2256 devices = ATOM_DEVICE_CRT2_SUPPORT;
2257 radeon_add_legacy_encoder(dev,
5137ee94 2258 radeon_get_encoder_enum
771fe6b9
JG		 2259 (dev,
2260 ATOM_DEVICE_CRT2_SUPPORT,
2261 2),
2262 ATOM_DEVICE_CRT2_SUPPORT);
2263 } else {
2264 devices = ATOM_DEVICE_CRT1_SUPPORT;
2265 radeon_add_legacy_encoder(dev,
5137ee94 2266 radeon_get_encoder_enum
771fe6b9
JG		 2267 (dev,
2268 ATOM_DEVICE_CRT1_SUPPORT,
2269 1),
2270 ATOM_DEVICE_CRT1_SUPPORT);
2271 }
2272 radeon_add_legacy_connector(dev,
2273 i,
2274 devices,
2275 legacy_connector_convert
2276 [connector],
b75fad06 2277 &ddc_i2c,
eed45b30
AD		 2278 CONNECTOR_OBJECT_ID_VGA,
2279 &hpd);
771fe6b9
JG		 2280 break;
2281 case CONNECTOR_DVI_I_LEGACY:
2282 devices = 0;
2283 if (tmp & 0x1) {
2284 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2285 radeon_add_legacy_encoder(dev,
5137ee94 2286 radeon_get_encoder_enum
771fe6b9
JG		 2287 (dev,
2288 ATOM_DEVICE_CRT2_SUPPORT,
2289 2),
2290 ATOM_DEVICE_CRT2_SUPPORT);
2291 } else {
2292 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2293 radeon_add_legacy_encoder(dev,
5137ee94 2294 radeon_get_encoder_enum
771fe6b9
JG		 2295 (dev,
2296 ATOM_DEVICE_CRT1_SUPPORT,
2297 1),
2298 ATOM_DEVICE_CRT1_SUPPORT);
2299 }
2300 if ((tmp >> 4) & 0x1) {
2301 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2302 radeon_add_legacy_encoder(dev,
5137ee94 2303 radeon_get_encoder_enum
771fe6b9
JG		 2304 (dev,
2305 ATOM_DEVICE_DFP2_SUPPORT,
2306 0),
2307 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2308 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2309 } else {
2310 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2311 radeon_add_legacy_encoder(dev,
5137ee94 2312 radeon_get_encoder_enum
771fe6b9
JG		 2313 (dev,
2314 ATOM_DEVICE_DFP1_SUPPORT,
2315 0),
2316 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2317 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2318 }
2319 radeon_add_legacy_connector(dev,
2320 i,
2321 devices,
2322 legacy_connector_convert
2323 [connector],
b75fad06 2324 &ddc_i2c,
eed45b30
AD		 2325 connector_object_id,
2326 &hpd);
771fe6b9
JG		 2327 break;
2328 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2329 if ((tmp >> 4) & 0x1) {
771fe6b9 2330 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2331 connector_object_id = combios_check_dl_dvi(dev, 1);
2332 } else {
771fe6b9 2333 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2334 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2335 }
771fe6b9 2336 radeon_add_legacy_encoder(dev,
5137ee94 2337 radeon_get_encoder_enum
771fe6b9
JG		 2338 (dev, devices, 0),
2339 devices);
2340 radeon_add_legacy_connector(dev, i, devices,
2341 legacy_connector_convert
2342 [connector],
b75fad06 2343 &ddc_i2c,
eed45b30
AD		 2344 connector_object_id,
2345 &hpd);
771fe6b9
JG		 2346 break;
2347 case CONNECTOR_CTV_LEGACY:
2348 case CONNECTOR_STV_LEGACY:
2349 radeon_add_legacy_encoder(dev,
5137ee94 2350 radeon_get_encoder_enum
771fe6b9
JG		 2351 (dev,
2352 ATOM_DEVICE_TV1_SUPPORT,
2353 2),
2354 ATOM_DEVICE_TV1_SUPPORT);
2355 radeon_add_legacy_connector(dev, i,
2356 ATOM_DEVICE_TV1_SUPPORT,
2357 legacy_connector_convert
2358 [connector],
b75fad06 2359 &ddc_i2c,
eed45b30
AD		 2360 CONNECTOR_OBJECT_ID_SVIDEO,
2361 &hpd);
771fe6b9
JG		 2362 break;
2363 default:
2364 DRM_ERROR("Unknown connector type: %d\n",
2365 connector);
2366 continue;
2367 }
2368
2369 }
2370 } else {
2371 uint16_t tmds_info =
2372 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2373 if (tmds_info) {
d9fdaafb 2374 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
771fe6b9
JG		 2375
2376 radeon_add_legacy_encoder(dev,
5137ee94 2377 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2378 ATOM_DEVICE_CRT1_SUPPORT,
2379 1),
2380 ATOM_DEVICE_CRT1_SUPPORT);
2381 radeon_add_legacy_encoder(dev,
5137ee94 2382 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2383 ATOM_DEVICE_DFP1_SUPPORT,
2384 0),
2385 ATOM_DEVICE_DFP1_SUPPORT);
2386
179e8078 2387 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
8e36ed00 2388 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2389 radeon_add_legacy_connector(dev,
2390 0,
2391 ATOM_DEVICE_CRT1_SUPPORT |
2392 ATOM_DEVICE_DFP1_SUPPORT,
2393 DRM_MODE_CONNECTOR_DVII,
b75fad06 2394 &ddc_i2c,
eed45b30
AD		 2395 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2396 &hpd);
771fe6b9 2397 } else {
d0c403e9
AD		 2398 uint16_t crt_info =
2399 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
d9fdaafb 2400 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
d0c403e9
AD		 2401 if (crt_info) {
2402 radeon_add_legacy_encoder(dev,
5137ee94 2403 radeon_get_encoder_enum(dev,
d0c403e9
AD		 2404 ATOM_DEVICE_CRT1_SUPPORT,
2405 1),
2406 ATOM_DEVICE_CRT1_SUPPORT);
179e8078 2407 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 2408 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2409 radeon_add_legacy_connector(dev,
2410 0,
2411 ATOM_DEVICE_CRT1_SUPPORT,
2412 DRM_MODE_CONNECTOR_VGA,
b75fad06 2413 &ddc_i2c,
eed45b30
AD		 2414 CONNECTOR_OBJECT_ID_VGA,
2415 &hpd);
d0c403e9 2416 } else {
d9fdaafb 2417 DRM_DEBUG_KMS("No connector info found\n");
d0c403e9
AD		 2418 return false;
2419 }
771fe6b9
JG		 2420 }
2421 }
2422
2423 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2424 uint16_t lcd_info =
2425 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2426 if (lcd_info) {
2427 uint16_t lcd_ddc_info =
2428 combios_get_table_offset(dev,
2429 COMBIOS_LCD_DDC_INFO_TABLE);
2430
2431 radeon_add_legacy_encoder(dev,
5137ee94 2432 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2433 ATOM_DEVICE_LCD1_SUPPORT,
2434 0),
2435 ATOM_DEVICE_LCD1_SUPPORT);
2436
2437 if (lcd_ddc_info) {
2438 ddc_type = RBIOS8(lcd_ddc_info + 2);
2439 switch (ddc_type) {
771fe6b9
JG		 2440 case DDC_LCD:
2441 ddc_i2c =
179e8078
AD		 2442 combios_setup_i2c_bus(rdev,
2443 DDC_LCD,
2444 RBIOS32(lcd_ddc_info + 3),
2445 RBIOS32(lcd_ddc_info + 7));
f376b94f 2446 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2447 break;
2448 case DDC_GPIO:
2449 ddc_i2c =
179e8078
AD		 2450 combios_setup_i2c_bus(rdev,
2451 DDC_GPIO,
2452 RBIOS32(lcd_ddc_info + 3),
2453 RBIOS32(lcd_ddc_info + 7));
f376b94f 2454 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2455 break;
2456 default:
179e8078
AD		 2457 ddc_i2c =
2458 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9
JG		 2459 break;
2460 }
d9fdaafb 2461 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
771fe6b9
JG		 2462 } else
2463 ddc_i2c.valid = false;
2464
eed45b30 2465 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2466 radeon_add_legacy_connector(dev,
2467 5,
2468 ATOM_DEVICE_LCD1_SUPPORT,
2469 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2470 &ddc_i2c,
eed45b30
AD		 2471 CONNECTOR_OBJECT_ID_LVDS,
2472 &hpd);
771fe6b9
JG		 2473 }
2474 }
2475
2476 /* check TV table */
2477 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2478 uint32_t tv_info =
2479 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2480 if (tv_info) {
2481 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2482 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2483 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2484 ddc_i2c.valid = false;
790cfb34 2485 radeon_add_legacy_encoder(dev,
5137ee94 2486 radeon_get_encoder_enum
790cfb34
AD		 2487 (dev,
2488 ATOM_DEVICE_TV1_SUPPORT,
2489 2),
2490 ATOM_DEVICE_TV1_SUPPORT);
2491 radeon_add_legacy_connector(dev, 6,
2492 ATOM_DEVICE_TV1_SUPPORT,
2493 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2494 &ddc_i2c,
eed45b30
AD		 2495 CONNECTOR_OBJECT_ID_SVIDEO,
2496 &hpd);
790cfb34 2497 }
771fe6b9
JG		 2498 }
2499 }
2500 }
2501
2502 radeon_link_encoder_connector(dev);
2503
2504 return true;
2505}
2506
56278a8e
AD		 2507void radeon_combios_get_power_modes(struct radeon_device *rdev)
2508{
2509 struct drm_device *dev = rdev->ddev;
2510 u16 offset, misc, misc2 = 0;
2511 u8 rev, blocks, tmp;
2512 int state_index = 0;
2513
a48b9b4e 2514 rdev->pm.default_power_state_index = -1;
56278a8e 2515
0975b162
AD		 2516 /* allocate 2 power states */
2517 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2518 if (!rdev->pm.power_state) {
2519 rdev->pm.default_power_state_index = state_index;
2520 rdev->pm.num_power_states = 0;
2521
2522 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2523 rdev->pm.current_clock_mode_index = 0;
2524 return;
2525 }
2526
56278a8e
AD		 2527 if (rdev->flags & RADEON_IS_MOBILITY) {
2528 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2529 if (offset) {
2530 rev = RBIOS8(offset);
2531 blocks = RBIOS8(offset + 0x2);
2532 /* power mode 0 tends to be the only valid one */
2533 rdev->pm.power_state[state_index].num_clock_modes = 1;
2534 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2535 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2536 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2537 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2538 goto default_mode;
0ec0e74f
AD		 2539 rdev->pm.power_state[state_index].type =
2540 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2541 misc = RBIOS16(offset + 0x5 + 0x0);
2542 if (rev > 4)
2543 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2544 rdev->pm.power_state[state_index].misc = misc;
2545 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2546 if (misc & 0x4) {
2547 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2548 if (misc & 0x8)
2549 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2550 true;
2551 else
2552 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2553 false;
2554 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2555 if (rev < 6) {
2556 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2557 RBIOS16(offset + 0x5 + 0xb) * 4;
2558 tmp = RBIOS8(offset + 0x5 + 0xd);
2559 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2560 } else {
2561 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2562 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2563 if (entries && voltage_table_offset) {
2564 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2565 RBIOS16(voltage_table_offset) * 4;
2566 tmp = RBIOS8(voltage_table_offset + 0x2);
2567 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2568 } else
2569 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2570 }
2571 switch ((misc2 & 0x700) >> 8) {
2572 case 0:
2573 default:
2574 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2575 break;
2576 case 1:
2577 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2578 break;
2579 case 2:
2580 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2581 break;
2582 case 3:
2583 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2584 break;
2585 case 4:
2586 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2587 break;
2588 }
2589 } else
2590 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2591 if (rev > 6)
79daedc9 2592 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2593 RBIOS8(offset + 0x5 + 0x10);
d7311171 2594 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2595 state_index++;
2596 } else {
2597 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2598 }
2599 } else {
2600 /* XXX figure out some good default low power mode for desktop cards */
2601 }
2602
2603default_mode:
2604 /* add the default mode */
0ec0e74f
AD		 2605 rdev->pm.power_state[state_index].type =
2606 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2607 rdev->pm.power_state[state_index].num_clock_modes = 1;
2608 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2609 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2610 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2611 if ((state_index > 0) &&
8de016e2 2612 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2613 rdev->pm.power_state[state_index].clock_info[0].voltage =
2614 rdev->pm.power_state[0].clock_info[0].voltage;
2615 else
2616 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2617 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2618 rdev->pm.power_state[state_index].flags = 0;
2619 rdev->pm.default_power_state_index = state_index;
56278a8e 2620 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2621
a48b9b4e
AD		 2622 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2623 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2624}
2625
fcec570b
AD		 2626void radeon_external_tmds_setup(struct drm_encoder *encoder)
2627{
2628 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2629 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2630
2631 if (!tmds)
2632 return;
2633
2634 switch (tmds->dvo_chip) {
2635 case DVO_SIL164:
2636 /* sil 164 */
5a6f98f5
AD		 2637 radeon_i2c_put_byte(tmds->i2c_bus,
2638 tmds->slave_addr,
2639 0x08, 0x30);
2640 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2641 tmds->slave_addr,
2642 0x09, 0x00);
5a6f98f5
AD		 2643 radeon_i2c_put_byte(tmds->i2c_bus,
2644 tmds->slave_addr,
2645 0x0a, 0x90);
2646 radeon_i2c_put_byte(tmds->i2c_bus,
2647 tmds->slave_addr,
2648 0x0c, 0x89);
2649 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2650 tmds->slave_addr,
2651 0x08, 0x3b);
fcec570b
AD		 2652 break;
2653 case DVO_SIL1178:
2654 /* sil 1178 - untested */
2655 /*
2656 * 0x0f, 0x44
2657 * 0x0f, 0x4c
2658 * 0x0e, 0x01
2659 * 0x0a, 0x80
2660 * 0x09, 0x30
2661 * 0x0c, 0xc9
2662 * 0x0d, 0x70
2663 * 0x08, 0x32
2664 * 0x08, 0x33
2665 */
2666 break;
2667 default:
2668 break;
2669 }
2670
2671}
2672
2673bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2674{
2675 struct drm_device *dev = encoder->dev;
2676 struct radeon_device *rdev = dev->dev_private;
2677 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2678 uint16_t offset;
2679 uint8_t blocks, slave_addr, rev;
2680 uint32_t index, id;
2681 uint32_t reg, val, and_mask, or_mask;
2682 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2683
fcec570b
AD		 2684 if (!tmds)
2685 return false;
2686
2687 if (rdev->flags & RADEON_IS_IGP) {
2688 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2689 rev = RBIOS8(offset);
2690 if (offset) {
2691 rev = RBIOS8(offset);
2692 if (rev > 1) {
2693 blocks = RBIOS8(offset + 3);
2694 index = offset + 4;
2695 while (blocks > 0) {
2696 id = RBIOS16(index);
2697 index += 2;
2698 switch (id >> 13) {
2699 case 0:
2700 reg = (id & 0x1fff) * 4;
2701 val = RBIOS32(index);
2702 index += 4;
2703 WREG32(reg, val);
2704 break;
2705 case 2:
2706 reg = (id & 0x1fff) * 4;
2707 and_mask = RBIOS32(index);
2708 index += 4;
2709 or_mask = RBIOS32(index);
2710 index += 4;
2711 val = RREG32(reg);
2712 val = (val & and_mask) | or_mask;
2713 WREG32(reg, val);
2714 break;
2715 case 3:
2716 val = RBIOS16(index);
2717 index += 2;
2718 udelay(val);
2719 break;
2720 case 4:
2721 val = RBIOS16(index);
2722 index += 2;
2723 udelay(val * 1000);
2724 break;
2725 case 6:
2726 slave_addr = id & 0xff;
2727 slave_addr >>= 1; /* 7 bit addressing */
2728 index++;
2729 reg = RBIOS8(index);
2730 index++;
2731 val = RBIOS8(index);
2732 index++;
5a6f98f5
AD		 2733 radeon_i2c_put_byte(tmds->i2c_bus,
2734 slave_addr,
2735 reg, val);
fcec570b
AD		 2736 break;
2737 default:
2738 DRM_ERROR("Unknown id %d\n", id >> 13);
2739 break;
2740 }
2741 blocks--;
2742 }
2743 return true;
2744 }
2745 }
2746 } else {
2747 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2748 if (offset) {
2749 index = offset + 10;
2750 id = RBIOS16(index);
2751 while (id != 0xffff) {
2752 index += 2;
2753 switch (id >> 13) {
2754 case 0:
2755 reg = (id & 0x1fff) * 4;
2756 val = RBIOS32(index);
2757 WREG32(reg, val);
2758 break;
2759 case 2:
2760 reg = (id & 0x1fff) * 4;
2761 and_mask = RBIOS32(index);
2762 index += 4;
2763 or_mask = RBIOS32(index);
2764 index += 4;
2765 val = RREG32(reg);
2766 val = (val & and_mask) | or_mask;
2767 WREG32(reg, val);
2768 break;
2769 case 4:
2770 val = RBIOS16(index);
2771 index += 2;
2772 udelay(val);
2773 break;
2774 case 5:
2775 reg = id & 0x1fff;
2776 and_mask = RBIOS32(index);
2777 index += 4;
2778 or_mask = RBIOS32(index);
2779 index += 4;
2780 val = RREG32_PLL(reg);
2781 val = (val & and_mask) | or_mask;
2782 WREG32_PLL(reg, val);
2783 break;
2784 case 6:
2785 reg = id & 0x1fff;
2786 val = RBIOS8(index);
2787 index += 1;
5a6f98f5
AD		 2788 radeon_i2c_put_byte(tmds->i2c_bus,
2789 tmds->slave_addr,
2790 reg, val);
fcec570b
AD		 2791 break;
2792 default:
2793 DRM_ERROR("Unknown id %d\n", id >> 13);
2794 break;
2795 }
2796 id = RBIOS16(index);
2797 }
2798 return true;
2799 }
2800 }
2801 return false;
2802}
2803
771fe6b9
JG		 2804static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2805{
2806 struct radeon_device *rdev = dev->dev_private;
2807
2808 if (offset) {
2809 while (RBIOS16(offset)) {
2810 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2811 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2812 uint32_t val, and_mask, or_mask;
2813 uint32_t tmp;
2814
2815 offset += 2;
2816 switch (cmd) {
2817 case 0:
2818 val = RBIOS32(offset);
2819 offset += 4;
2820 WREG32(addr, val);
2821 break;
2822 case 1:
2823 val = RBIOS32(offset);
2824 offset += 4;
2825 WREG32(addr, val);
2826 break;
2827 case 2:
2828 and_mask = RBIOS32(offset);
2829 offset += 4;
2830 or_mask = RBIOS32(offset);
2831 offset += 4;
2832 tmp = RREG32(addr);
2833 tmp &= and_mask;
2834 tmp |= or_mask;
2835 WREG32(addr, tmp);
2836 break;
2837 case 3:
2838 and_mask = RBIOS32(offset);
2839 offset += 4;
2840 or_mask = RBIOS32(offset);
2841 offset += 4;
2842 tmp = RREG32(addr);
2843 tmp &= and_mask;
2844 tmp |= or_mask;
2845 WREG32(addr, tmp);
2846 break;
2847 case 4:
2848 val = RBIOS16(offset);
2849 offset += 2;
2850 udelay(val);
2851 break;
2852 case 5:
2853 val = RBIOS16(offset);
2854 offset += 2;
2855 switch (addr) {
2856 case 8:
2857 while (val--) {
2858 if (!
2859 (RREG32_PLL
2860 (RADEON_CLK_PWRMGT_CNTL) &
2861 RADEON_MC_BUSY))
2862 break;
2863 }
2864 break;
2865 case 9:
2866 while (val--) {
2867 if ((RREG32(RADEON_MC_STATUS) &
2868 RADEON_MC_IDLE))
2869 break;
2870 }
2871 break;
2872 default:
2873 break;
2874 }
2875 break;
2876 default:
2877 break;
2878 }
2879 }
2880 }
2881}
2882
2883static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2884{
2885 struct radeon_device *rdev = dev->dev_private;
2886
2887 if (offset) {
2888 while (RBIOS8(offset)) {
2889 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2890 uint8_t addr = (RBIOS8(offset) & 0x3f);
2891 uint32_t val, shift, tmp;
2892 uint32_t and_mask, or_mask;
2893
2894 offset++;
2895 switch (cmd) {
2896 case 0:
2897 val = RBIOS32(offset);
2898 offset += 4;
2899 WREG32_PLL(addr, val);
2900 break;
2901 case 1:
2902 shift = RBIOS8(offset) * 8;
2903 offset++;
2904 and_mask = RBIOS8(offset) << shift;
2905 and_mask |= ~(0xff << shift);
2906 offset++;
2907 or_mask = RBIOS8(offset) << shift;
2908 offset++;
2909 tmp = RREG32_PLL(addr);
2910 tmp &= and_mask;
2911 tmp |= or_mask;
2912 WREG32_PLL(addr, tmp);
2913 break;
2914 case 2:
2915 case 3:
2916 tmp = 1000;
2917 switch (addr) {
2918 case 1:
2919 udelay(150);
2920 break;
2921 case 2:
2922 udelay(1000);
2923 break;
2924 case 3:
2925 while (tmp--) {
2926 if (!
2927 (RREG32_PLL
2928 (RADEON_CLK_PWRMGT_CNTL) &
2929 RADEON_MC_BUSY))
2930 break;
2931 }
2932 break;
2933 case 4:
2934 while (tmp--) {
2935 if (RREG32_PLL
2936 (RADEON_CLK_PWRMGT_CNTL) &
2937 RADEON_DLL_READY)
2938 break;
2939 }
2940 break;
2941 case 5:
2942 tmp =
2943 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2944 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2945#if 0
2946 uint32_t mclk_cntl =
2947 RREG32_PLL
2948 (RADEON_MCLK_CNTL);
2949 mclk_cntl &= 0xffff0000;
2950 /*mclk_cntl |= 0x00001111;*//* ??? */
2951 WREG32_PLL(RADEON_MCLK_CNTL,
2952 mclk_cntl);
2953 udelay(10000);
2954#endif
2955 WREG32_PLL
2956 (RADEON_CLK_PWRMGT_CNTL,
2957 tmp &
2958 ~RADEON_CG_NO1_DEBUG_0);
2959 udelay(10000);
2960 }
2961 break;
2962 default:
2963 break;
2964 }
2965 break;
2966 default:
2967 break;
2968 }
2969 }
2970 }
2971}
2972
2973static void combios_parse_ram_reset_table(struct drm_device *dev,
2974 uint16_t offset)
2975{
2976 struct radeon_device *rdev = dev->dev_private;
2977 uint32_t tmp;
2978
2979 if (offset) {
2980 uint8_t val = RBIOS8(offset);
2981 while (val != 0xff) {
2982 offset++;
2983
2984 if (val == 0x0f) {
2985 uint32_t channel_complete_mask;
2986
2987 if (ASIC_IS_R300(rdev))
2988 channel_complete_mask =
2989 R300_MEM_PWRUP_COMPLETE;
2990 else
2991 channel_complete_mask =
2992 RADEON_MEM_PWRUP_COMPLETE;
2993 tmp = 20000;
2994 while (tmp--) {
2995 if ((RREG32(RADEON_MEM_STR_CNTL) &
2996 channel_complete_mask) ==
2997 channel_complete_mask)
2998 break;
2999 }
3000 } else {
3001 uint32_t or_mask = RBIOS16(offset);
3002 offset += 2;
3003
3004 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3005 tmp &= RADEON_SDRAM_MODE_MASK;
3006 tmp |= or_mask;
3007 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3008
3009 or_mask = val << 24;
3010 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3011 tmp &= RADEON_B3MEM_RESET_MASK;
3012 tmp |= or_mask;
3013 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3014 }
3015 val = RBIOS8(offset);
3016 }
3017 }
3018}
3019
3020static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3021 int mem_addr_mapping)
3022{
3023 struct radeon_device *rdev = dev->dev_private;
3024 uint32_t mem_cntl;
3025 uint32_t mem_size;
3026 uint32_t addr = 0;
3027
3028 mem_cntl = RREG32(RADEON_MEM_CNTL);
3029 if (mem_cntl & RV100_HALF_MODE)
3030 ram /= 2;
3031 mem_size = ram;
3032 mem_cntl &= ~(0xff << 8);
3033 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3034 WREG32(RADEON_MEM_CNTL, mem_cntl);
3035 RREG32(RADEON_MEM_CNTL);
3036
3037 /* sdram reset ? */
3038
3039 /* something like this???? */
3040 while (ram--) {
3041 addr = ram * 1024 * 1024;
3042 /* write to each page */
3043 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3044 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3045 /* read back and verify */
3046 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3047 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3048 return 0;
3049 }
3050
3051 return mem_size;
3052}
3053
3054static void combios_write_ram_size(struct drm_device *dev)
3055{
3056 struct radeon_device *rdev = dev->dev_private;
3057 uint8_t rev;
3058 uint16_t offset;
3059 uint32_t mem_size = 0;
3060 uint32_t mem_cntl = 0;
3061
3062 /* should do something smarter here I guess... */
3063 if (rdev->flags & RADEON_IS_IGP)
3064 return;
3065
3066 /* first check detected mem table */
3067 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3068 if (offset) {
3069 rev = RBIOS8(offset);
3070 if (rev < 3) {
3071 mem_cntl = RBIOS32(offset + 1);
3072 mem_size = RBIOS16(offset + 5);
4ce9198e
AD		 3073 if ((rdev->family < CHIP_R200) &&
3074 !ASIC_IS_RN50(rdev))
771fe6b9
JG		 3075 WREG32(RADEON_MEM_CNTL, mem_cntl);
3076 }
3077 }
3078
3079 if (!mem_size) {
3080 offset =
3081 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3082 if (offset) {
3083 rev = RBIOS8(offset - 1);
3084 if (rev < 1) {
4ce9198e
AD		 3085 if ((rdev->family < CHIP_R200)
3086 && !ASIC_IS_RN50(rdev)) {
771fe6b9
JG		 3087 int ram = 0;
3088 int mem_addr_mapping = 0;
3089
3090 while (RBIOS8(offset)) {
3091 ram = RBIOS8(offset);
3092 mem_addr_mapping =
3093 RBIOS8(offset + 1);
3094 if (mem_addr_mapping != 0x25)
3095 ram *= 2;
3096 mem_size =
3097 combios_detect_ram(dev, ram,
3098 mem_addr_mapping);
3099 if (mem_size)
3100 break;
3101 offset += 2;
3102 }
3103 } else
3104 mem_size = RBIOS8(offset);
3105 } else {
3106 mem_size = RBIOS8(offset);
3107 mem_size *= 2; /* convert to MB */
3108 }
3109 }
3110 }
3111
3112 mem_size *= (1024 * 1024); /* convert to bytes */
3113 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3114}
3115
3116void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3117{
3118 uint16_t dyn_clk_info =
3119 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3120
3121 if (dyn_clk_info)
3122 combios_parse_pll_table(dev, dyn_clk_info);
3123}
3124
3125void radeon_combios_asic_init(struct drm_device *dev)
3126{
3127 struct radeon_device *rdev = dev->dev_private;
3128 uint16_t table;
3129
3130 /* port hardcoded mac stuff from radeonfb */
3131 if (rdev->bios == NULL)
3132 return;
3133
3134 /* ASIC INIT 1 */
3135 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3136 if (table)
3137 combios_parse_mmio_table(dev, table);
3138
3139 /* PLL INIT */
3140 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3141 if (table)
3142 combios_parse_pll_table(dev, table);
3143
3144 /* ASIC INIT 2 */
3145 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3146 if (table)
3147 combios_parse_mmio_table(dev, table);
3148
3149 if (!(rdev->flags & RADEON_IS_IGP)) {
3150 /* ASIC INIT 4 */
3151 table =
3152 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3153 if (table)
3154 combios_parse_mmio_table(dev, table);
3155
3156 /* RAM RESET */
3157 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3158 if (table)
3159 combios_parse_ram_reset_table(dev, table);
3160
3161 /* ASIC INIT 3 */
3162 table =
3163 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3164 if (table)
3165 combios_parse_mmio_table(dev, table);
3166
3167 /* write CONFIG_MEMSIZE */
3168 combios_write_ram_size(dev);
3169 }
3170
580b4fff
DA		 3171 /* quirk for rs4xx HP nx6125 laptop to make it resume
3172 * - it hangs on resume inside the dynclk 1 table.
3173 */
3174 if (rdev->family == CHIP_RS480 &&
3175 rdev->pdev->subsystem_vendor == 0x103c &&
3176 rdev->pdev->subsystem_device == 0x308b)
3177 return;
3178
52fa2bbc
AD		 3179 /* quirk for rs4xx HP dv5000 laptop to make it resume
3180 * - it hangs on resume inside the dynclk 1 table.
3181 */
3182 if (rdev->family == CHIP_RS480 &&
3183 rdev->pdev->subsystem_vendor == 0x103c &&
3184 rdev->pdev->subsystem_device == 0x30a4)
3185 return;
3186
771fe6b9
JG		 3187 /* DYN CLK 1 */
3188 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3189 if (table)
3190 combios_parse_pll_table(dev, table);
3191
3192}
3193
3194void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3195{
3196 struct radeon_device *rdev = dev->dev_private;
3197 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3198
3199 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3200 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3201 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3202
3203 /* let the bios control the backlight */
3204 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3205
3206 /* tell the bios not to handle mode switching */
3207 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3208 RADEON_ACC_MODE_CHANGE);
3209
3210 /* tell the bios a driver is loaded */
3211 bios_7_scratch |= RADEON_DRV_LOADED;
3212
3213 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3214 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3215 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3216}
3217
3218void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3219{
3220 struct drm_device *dev = encoder->dev;
3221 struct radeon_device *rdev = dev->dev_private;
3222 uint32_t bios_6_scratch;
3223
3224 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3225
3226 if (lock)
3227 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3228 else
3229 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3230
3231 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3232}
3233
3234void
3235radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3236 struct drm_encoder *encoder,
3237 bool connected)
3238{
3239 struct drm_device *dev = connector->dev;
3240 struct radeon_device *rdev = dev->dev_private;
3241 struct radeon_connector *radeon_connector =
3242 to_radeon_connector(connector);
3243 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3244 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3245 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3246
3247 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3248 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3249 if (connected) {
d9fdaafb 3250 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3251 /* fix me */
3252 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3253 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3254 bios_5_scratch |= RADEON_TV1_ON;
3255 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3256 } else {
d9fdaafb 3257 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3258 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3259 bios_5_scratch &= ~RADEON_TV1_ON;
3260 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3261 }
3262 }
3263 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3264 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3265 if (connected) {
d9fdaafb 3266 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3267 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3268 bios_5_scratch |= RADEON_LCD1_ON;
3269 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3270 } else {
d9fdaafb 3271 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3272 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3273 bios_5_scratch &= ~RADEON_LCD1_ON;
3274 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3275 }
3276 }
3277 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3278 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3279 if (connected) {
d9fdaafb 3280 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3281 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3282 bios_5_scratch |= RADEON_CRT1_ON;
3283 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3284 } else {
d9fdaafb 3285 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3286 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3287 bios_5_scratch &= ~RADEON_CRT1_ON;
3288 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3289 }
3290 }
3291 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3292 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3293 if (connected) {
d9fdaafb 3294 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3295 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3296 bios_5_scratch |= RADEON_CRT2_ON;
3297 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3298 } else {
d9fdaafb 3299 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3300 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3301 bios_5_scratch &= ~RADEON_CRT2_ON;
3302 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3303 }
3304 }
3305 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3306 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3307 if (connected) {
d9fdaafb 3308 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3309 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3310 bios_5_scratch |= RADEON_DFP1_ON;
3311 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3312 } else {
d9fdaafb 3313 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3314 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3315 bios_5_scratch &= ~RADEON_DFP1_ON;
3316 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3317 }
3318 }
3319 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3320 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3321 if (connected) {
d9fdaafb 3322 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3323 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3324 bios_5_scratch |= RADEON_DFP2_ON;
3325 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3326 } else {
d9fdaafb 3327 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3328 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3329 bios_5_scratch &= ~RADEON_DFP2_ON;
3330 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3331 }
3332 }
3333 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3334 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3335}
3336
3337void
3338radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3339{
3340 struct drm_device *dev = encoder->dev;
3341 struct radeon_device *rdev = dev->dev_private;
3342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3343 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3344
3345 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3346 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3347 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3348 }
3349 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3350 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3351 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3352 }
3353 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3354 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3355 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3356 }
3357 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3358 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3359 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3360 }
3361 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3362 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3363 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3364 }
3365 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3366 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3367 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3368 }
3369 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3370}
3371
3372void
3373radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3374{
3375 struct drm_device *dev = encoder->dev;
3376 struct radeon_device *rdev = dev->dev_private;
3377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3378 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3379
3380 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3381 if (on)
3382 bios_6_scratch |= RADEON_TV_DPMS_ON;
3383 else
3384 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3385 }
3386 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3387 if (on)
3388 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3389 else
3390 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3391 }
3392 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3393 if (on)
3394 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3395 else
3396 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3397 }
3398 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3399 if (on)
3400 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3401 else
3402 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3403 }
3404 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3405}
Linux kernel - Deliverables
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