projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
vga_switcheroo: Remove unbalanced pci_enable_device
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
5137ee94
AD		 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
771fe6b9
JG		 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
5137ee94 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
fafcf94e 451 int edid_info, size;
3c537889 452 struct edid *edid;
7466f4cc 453 unsigned char *raw;
3c537889
AD		 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
7466f4cc 458 raw = rdev->bios + edid_info;
fafcf94e
AD		 459 size = EDID_LENGTH * (raw[0x7e] + 1);
460 edid = kmalloc(size, GFP_KERNEL);
3c537889
AD		 461 if (edid == NULL)
462 return false;
463
fafcf94e 464 memcpy((unsigned char *)edid, raw, size);
3c537889
AD		 465
466 if (!drm_edid_is_valid(edid)) {
467 kfree(edid);
468 return false;
469 }
470
471 rdev->mode_info.bios_hardcoded_edid = edid;
fafcf94e 472 rdev->mode_info.bios_hardcoded_edid_size = size;
3c537889
AD		 473 return true;
474}
475
c324acd5 476/* this is used for atom LCDs as well */
3c537889 477struct edid *
c324acd5 478radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
3c537889 479{
fafcf94e
AD		 480 struct edid *edid;
481
482 if (rdev->mode_info.bios_hardcoded_edid) {
483 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
484 if (edid) {
485 memcpy((unsigned char *)edid,
486 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
487 rdev->mode_info.bios_hardcoded_edid_size);
488 return edid;
489 }
490 }
3c537889
AD		 491 return NULL;
492}
493
6a93cb25 494static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
179e8078
AD		 495 enum radeon_combios_ddc ddc,
496 u32 clk_mask,
497 u32 data_mask)
771fe6b9
JG		 498{
499 struct radeon_i2c_bus_rec i2c;
179e8078
AD		 500 int ddc_line = 0;
501
502 /* ddc id = mask reg
503 * DDC_NONE_DETECTED = none
504 * DDC_DVI = RADEON_GPIO_DVI_DDC
505 * DDC_VGA = RADEON_GPIO_VGA_DDC
506 * DDC_LCD = RADEON_GPIOPAD_MASK
507 * DDC_GPIO = RADEON_MDGPIO_MASK
508c8d60 508 * r1xx
179e8078
AD		 509 * DDC_MONID = RADEON_GPIO_MONID
510 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
508c8d60 511 * r200
179e8078
AD		 512 * DDC_MONID = RADEON_GPIO_MONID
513 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
508c8d60
AD		 514 * r300/r350
515 * DDC_MONID = RADEON_GPIO_DVI_DDC
516 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
517 * rv2xx/rv3xx
518 * DDC_MONID = RADEON_GPIO_MONID
519 * DDC_CRT2 = RADEON_GPIO_MONID
179e8078
AD		 520 * rs3xx/rs4xx
521 * DDC_MONID = RADEON_GPIOPAD_MASK
522 * DDC_CRT2 = RADEON_GPIO_MONID
523 */
524 switch (ddc) {
525 case DDC_NONE_DETECTED:
526 default:
527 ddc_line = 0;
528 break;
529 case DDC_DVI:
530 ddc_line = RADEON_GPIO_DVI_DDC;
531 break;
532 case DDC_VGA:
533 ddc_line = RADEON_GPIO_VGA_DDC;
534 break;
535 case DDC_LCD:
536 ddc_line = RADEON_GPIOPAD_MASK;
537 break;
538 case DDC_GPIO:
539 ddc_line = RADEON_MDGPIO_MASK;
540 break;
541 case DDC_MONID:
542 if (rdev->family == CHIP_RS300 ||
543 rdev->family == CHIP_RS400 ||
544 rdev->family == CHIP_RS480)
545 ddc_line = RADEON_GPIOPAD_MASK;
508c8d60
AD		 546 else if (rdev->family == CHIP_R300 ||
547 rdev->family == CHIP_R350)
548 ddc_line = RADEON_GPIO_DVI_DDC;
179e8078
AD		 549 else
550 ddc_line = RADEON_GPIO_MONID;
551 break;
552 case DDC_CRT2:
508c8d60
AD		 553 if (rdev->family == CHIP_R200 ||
554 rdev->family == CHIP_R300 ||
555 rdev->family == CHIP_R350)
179e8078 556 ddc_line = RADEON_GPIO_DVI_DDC;
508c8d60
AD		 557 else if (rdev->family == CHIP_RS300 ||
558 rdev->family >= CHIP_RV350)
559 ddc_line = RADEON_GPIO_MONID;
560 else
179e8078
AD		 561 ddc_line = RADEON_GPIO_CRT2_DDC;
562 break;
563 }
771fe6b9 564
6a93cb25
AD		 565 if (ddc_line == RADEON_GPIOPAD_MASK) {
566 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
567 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
568 i2c.a_clk_reg = RADEON_GPIOPAD_A;
569 i2c.a_data_reg = RADEON_GPIOPAD_A;
570 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
571 i2c.en_data_reg = RADEON_GPIOPAD_EN;
572 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
573 i2c.y_data_reg = RADEON_GPIOPAD_Y;
574 } else if (ddc_line == RADEON_MDGPIO_MASK) {
575 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
576 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
577 i2c.a_clk_reg = RADEON_MDGPIO_A;
578 i2c.a_data_reg = RADEON_MDGPIO_A;
579 i2c.en_clk_reg = RADEON_MDGPIO_EN;
580 i2c.en_data_reg = RADEON_MDGPIO_EN;
581 i2c.y_clk_reg = RADEON_MDGPIO_Y;
582 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9
JG		 583 } else {
584 i2c.mask_clk_reg = ddc_line;
585 i2c.mask_data_reg = ddc_line;
586 i2c.a_clk_reg = ddc_line;
587 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 588 i2c.en_clk_reg = ddc_line;
589 i2c.en_data_reg = ddc_line;
590 i2c.y_clk_reg = ddc_line;
591 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 592 }
593
179e8078 594 if (clk_mask && data_mask) {
be663057 595 /* system specific masks */
179e8078
AD		 596 i2c.mask_clk_mask = clk_mask;
597 i2c.mask_data_mask = data_mask;
598 i2c.a_clk_mask = clk_mask;
599 i2c.a_data_mask = data_mask;
600 i2c.en_clk_mask = clk_mask;
601 i2c.en_data_mask = data_mask;
602 i2c.y_clk_mask = clk_mask;
603 i2c.y_data_mask = data_mask;
be663057
AD		 604 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
605 (ddc_line == RADEON_MDGPIO_MASK)) {
606 /* default gpiopad masks */
607 i2c.mask_clk_mask = (0x20 << 8);
608 i2c.mask_data_mask = 0x80;
609 i2c.a_clk_mask = (0x20 << 8);
610 i2c.a_data_mask = 0x80;
611 i2c.en_clk_mask = (0x20 << 8);
612 i2c.en_data_mask = 0x80;
613 i2c.y_clk_mask = (0x20 << 8);
614 i2c.y_data_mask = 0x80;
179e8078 615 } else {
be663057 616 /* default masks for ddc pads */
179e8078
AD		 617 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
618 i2c.mask_data_mask = RADEON_GPIO_EN_0;
619 i2c.a_clk_mask = RADEON_GPIO_A_1;
620 i2c.a_data_mask = RADEON_GPIO_A_0;
621 i2c.en_clk_mask = RADEON_GPIO_EN_1;
622 i2c.en_data_mask = RADEON_GPIO_EN_0;
623 i2c.y_clk_mask = RADEON_GPIO_Y_1;
624 i2c.y_data_mask = RADEON_GPIO_Y_0;
625 }
626
40bacf16
AD		 627 switch (rdev->family) {
628 case CHIP_R100:
629 case CHIP_RV100:
630 case CHIP_RS100:
631 case CHIP_RV200:
632 case CHIP_RS200:
633 case CHIP_RS300:
634 switch (ddc_line) {
635 case RADEON_GPIO_DVI_DDC:
b28ea411 636 i2c.hw_capable = true;
40bacf16
AD		 637 break;
638 default:
639 i2c.hw_capable = false;
640 break;
641 }
642 break;
643 case CHIP_R200:
644 switch (ddc_line) {
645 case RADEON_GPIO_DVI_DDC:
646 case RADEON_GPIO_MONID:
647 i2c.hw_capable = true;
648 break;
649 default:
650 i2c.hw_capable = false;
651 break;
652 }
653 break;
654 case CHIP_RV250:
655 case CHIP_RV280:
656 switch (ddc_line) {
657 case RADEON_GPIO_VGA_DDC:
658 case RADEON_GPIO_DVI_DDC:
659 case RADEON_GPIO_CRT2_DDC:
660 i2c.hw_capable = true;
661 break;
662 default:
663 i2c.hw_capable = false;
664 break;
665 }
666 break;
667 case CHIP_R300:
668 case CHIP_R350:
669 switch (ddc_line) {
670 case RADEON_GPIO_VGA_DDC:
671 case RADEON_GPIO_DVI_DDC:
672 i2c.hw_capable = true;
673 break;
674 default:
675 i2c.hw_capable = false;
676 break;
677 }
678 break;
679 case CHIP_RV350:
680 case CHIP_RV380:
681 case CHIP_RS400:
682 case CHIP_RS480:
6a93cb25
AD		 683 switch (ddc_line) {
684 case RADEON_GPIO_VGA_DDC:
685 case RADEON_GPIO_DVI_DDC:
686 i2c.hw_capable = true;
687 break;
688 case RADEON_GPIO_MONID:
689 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
690 * reliably on some pre-r4xx hardware; not sure why.
691 */
692 i2c.hw_capable = false;
693 break;
694 default:
695 i2c.hw_capable = false;
696 break;
697 }
40bacf16
AD		 698 break;
699 default:
700 i2c.hw_capable = false;
701 break;
6a93cb25
AD		 702 }
703 i2c.mm_i2c = false;
f376b94f 704
179e8078 705 i2c.i2c_id = ddc;
8e36ed00 706 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 707
771fe6b9
JG		 708 if (ddc_line)
709 i2c.valid = true;
710 else
711 i2c.valid = false;
712
713 return i2c;
714}
715
f376b94f
AD		 716void radeon_combios_i2c_init(struct radeon_device *rdev)
717{
718 struct drm_device *dev = rdev->ddev;
719 struct radeon_i2c_bus_rec i2c;
720
508c8d60
AD		 721 /* actual hw pads
722 * r1xx/rs2xx/rs3xx
723 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
724 * r200
725 * 0x60, 0x64, 0x68, mm
726 * r300/r350
727 * 0x60, 0x64, mm
728 * rv2xx/rv3xx/rs4xx
729 * 0x60, 0x64, 0x68, gpiopads, mm
730 */
f376b94f 731
508c8d60 732 /* 0x60 */
179e8078
AD		 733 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
734 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
508c8d60 735 /* 0x64 */
179e8078
AD		 736 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
737 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
f376b94f 738
508c8d60 739 /* mm i2c */
f376b94f
AD		 740 i2c.valid = true;
741 i2c.hw_capable = true;
742 i2c.mm_i2c = true;
179e8078
AD		 743 i2c.i2c_id = 0xa0;
744 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
745
508c8d60
AD		 746 if (rdev->family == CHIP_R300 ||
747 rdev->family == CHIP_R350) {
748 /* only 2 sw i2c pads */
749 } else if (rdev->family == CHIP_RS300 ||
750 rdev->family == CHIP_RS400 ||
751 rdev->family == CHIP_RS480) {
179e8078
AD		 752 u16 offset;
753 u8 id, blocks, clk, data;
754 int i;
755
508c8d60 756 /* 0x68 */
179e8078
AD		 757 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
758 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
759
760 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
761 if (offset) {
762 blocks = RBIOS8(offset + 2);
763 for (i = 0; i < blocks; i++) {
764 id = RBIOS8(offset + 3 + (i * 5) + 0);
765 if (id == 136) {
766 clk = RBIOS8(offset + 3 + (i * 5) + 3);
767 data = RBIOS8(offset + 3 + (i * 5) + 4);
508c8d60 768 /* gpiopad */
179e8078 769 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
791cfe26 770 (1 << clk), (1 << data));
179e8078
AD		 771 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
772 break;
773 }
774 }
775 }
508c8d60
AD		 776 } else if (rdev->family >= CHIP_R200) {
777 /* 0x68 */
179e8078
AD		 778 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
779 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
780 } else {
508c8d60 781 /* 0x68 */
179e8078
AD		 782 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
783 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
508c8d60 784 /* 0x6c */
179e8078
AD		 785 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
786 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
787 }
f376b94f
AD		 788}
789
771fe6b9
JG		 790bool radeon_combios_get_clock_info(struct drm_device *dev)
791{
792 struct radeon_device *rdev = dev->dev_private;
793 uint16_t pll_info;
794 struct radeon_pll *p1pll = &rdev->clock.p1pll;
795 struct radeon_pll *p2pll = &rdev->clock.p2pll;
796 struct radeon_pll *spll = &rdev->clock.spll;
797 struct radeon_pll *mpll = &rdev->clock.mpll;
798 int8_t rev;
799 uint16_t sclk, mclk;
800
771fe6b9
JG		 801 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
802 if (pll_info) {
803 rev = RBIOS8(pll_info);
804
805 /* pixel clocks */
806 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
807 p1pll->reference_div = RBIOS16(pll_info + 0x10);
808 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
809 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 810 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
811 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 812
813 if (rev > 9) {
814 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
815 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
816 } else {
817 p1pll->pll_in_min = 40;
818 p1pll->pll_in_max = 500;
819 }
820 *p2pll = *p1pll;
821
822 /* system clock */
823 spll->reference_freq = RBIOS16(pll_info + 0x1a);
824 spll->reference_div = RBIOS16(pll_info + 0x1c);
825 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
826 spll->pll_out_max = RBIOS32(pll_info + 0x22);
827
828 if (rev > 10) {
829 spll->pll_in_min = RBIOS32(pll_info + 0x48);
830 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
831 } else {
832 /* ??? */
833 spll->pll_in_min = 40;
834 spll->pll_in_max = 500;
835 }
836
837 /* memory clock */
838 mpll->reference_freq = RBIOS16(pll_info + 0x26);
839 mpll->reference_div = RBIOS16(pll_info + 0x28);
840 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
841 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
842
843 if (rev > 10) {
844 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
845 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
846 } else {
847 /* ??? */
848 mpll->pll_in_min = 40;
849 mpll->pll_in_max = 500;
850 }
851
852 /* default sclk/mclk */
853 sclk = RBIOS16(pll_info + 0xa);
854 mclk = RBIOS16(pll_info + 0x8);
855 if (sclk == 0)
856 sclk = 200 * 100;
857 if (mclk == 0)
858 mclk = 200 * 100;
859
860 rdev->clock.default_sclk = sclk;
861 rdev->clock.default_mclk = mclk;
862
863 return true;
864 }
865 return false;
866}
867
06b6476d
AD		 868bool radeon_combios_sideport_present(struct radeon_device *rdev)
869{
870 struct drm_device *dev = rdev->ddev;
871 u16 igp_info;
872
4c70b2ea
AD		 873 /* sideport is AMD only */
874 if (rdev->family == CHIP_RS400)
875 return false;
876
06b6476d
AD		 877 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
878
879 if (igp_info) {
880 if (RBIOS16(igp_info + 0x4))
881 return true;
882 }
883 return false;
884}
885
246263cc
AD		 886static const uint32_t default_primarydac_adj[CHIP_LAST] = {
887 0x00000808, /* r100 */
888 0x00000808, /* rv100 */
889 0x00000808, /* rs100 */
890 0x00000808, /* rv200 */
891 0x00000808, /* rs200 */
892 0x00000808, /* r200 */
893 0x00000808, /* rv250 */
894 0x00000000, /* rs300 */
895 0x00000808, /* rv280 */
896 0x00000808, /* r300 */
897 0x00000808, /* r350 */
898 0x00000808, /* rv350 */
899 0x00000808, /* rv380 */
900 0x00000808, /* r420 */
901 0x00000808, /* r423 */
902 0x00000808, /* rv410 */
903 0x00000000, /* rs400 */
904 0x00000000, /* rs480 */
905};
906
907static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
908 struct radeon_encoder_primary_dac *p_dac)
909{
910 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
911 return;
912}
913
771fe6b9
JG		 914struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
915 radeon_encoder
916 *encoder)
917{
918 struct drm_device *dev = encoder->base.dev;
919 struct radeon_device *rdev = dev->dev_private;
920 uint16_t dac_info;
921 uint8_t rev, bg, dac;
922 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 923 int found = 0;
771fe6b9 924
246263cc
AD		 925 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
926 GFP_KERNEL);
927
928 if (!p_dac)
771fe6b9
JG		 929 return NULL;
930
931 /* check CRT table */
932 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
933 if (dac_info) {
771fe6b9
JG		 934 rev = RBIOS8(dac_info) & 0x3;
935 if (rev < 2) {
936 bg = RBIOS8(dac_info + 0x2) & 0xf;
937 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
938 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
939 } else {
940 bg = RBIOS8(dac_info + 0x2) & 0xf;
941 dac = RBIOS8(dac_info + 0x3) & 0xf;
942 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
943 }
3a89b4a9
AD		 944 /* if the values are all zeros, use the table */
945 if (p_dac->ps2_pdac_adj)
946 found = 1;
771fe6b9
JG		 947 }
948
246263cc
AD		 949 if (!found) /* fallback to defaults */
950 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
951
771fe6b9
JG		 952 return p_dac;
953}
954
d79766fa
AD		 955enum radeon_tv_std
956radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 957{
d79766fa 958 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 959 uint16_t tv_info;
960 enum radeon_tv_std tv_std = TV_STD_NTSC;
961
962 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
963 if (tv_info) {
964 if (RBIOS8(tv_info + 6) == 'T') {
965 switch (RBIOS8(tv_info + 7) & 0xf) {
966 case 1:
967 tv_std = TV_STD_NTSC;
40f76d81 968 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
771fe6b9
JG		 969 break;
970 case 2:
971 tv_std = TV_STD_PAL;
40f76d81 972 DRM_DEBUG_KMS("Default TV standard: PAL\n");
771fe6b9
JG		 973 break;
974 case 3:
975 tv_std = TV_STD_PAL_M;
40f76d81 976 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
771fe6b9
JG		 977 break;
978 case 4:
979 tv_std = TV_STD_PAL_60;
40f76d81 980 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
771fe6b9
JG		 981 break;
982 case 5:
983 tv_std = TV_STD_NTSC_J;
40f76d81 984 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
771fe6b9
JG		 985 break;
986 case 6:
987 tv_std = TV_STD_SCART_PAL;
40f76d81 988 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
771fe6b9
JG		 989 break;
990 default:
991 tv_std = TV_STD_NTSC;
40f76d81 992 DRM_DEBUG_KMS
771fe6b9
JG		 993 ("Unknown TV standard; defaulting to NTSC\n");
994 break;
995 }
996
997 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
998 case 0:
40f76d81 999 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
771fe6b9
JG		 1000 break;
1001 case 1:
40f76d81 1002 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
771fe6b9
JG		 1003 break;
1004 case 2:
40f76d81 1005 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
771fe6b9
JG		 1006 break;
1007 case 3:
40f76d81 1008 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
771fe6b9
JG		 1009 break;
1010 default:
1011 break;
1012 }
1013 }
1014 }
1015 return tv_std;
1016}
1017
1018static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1019 0x00000000, /* r100 */
1020 0x00280000, /* rv100 */
1021 0x00000000, /* rs100 */
1022 0x00880000, /* rv200 */
1023 0x00000000, /* rs200 */
1024 0x00000000, /* r200 */
1025 0x00770000, /* rv250 */
1026 0x00290000, /* rs300 */
1027 0x00560000, /* rv280 */
1028 0x00780000, /* r300 */
1029 0x00770000, /* r350 */
1030 0x00780000, /* rv350 */
1031 0x00780000, /* rv380 */
1032 0x01080000, /* r420 */
1033 0x01080000, /* r423 */
1034 0x01080000, /* rv410 */
1035 0x00780000, /* rs400 */
1036 0x00780000, /* rs480 */
1037};
1038
6a719e05
DA		 1039static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1040 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 1041{
771fe6b9
JG		 1042 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1043 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1044 tv_dac->ps2_tvdac_adj = 0x00880000;
1045 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1046 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 1047 return;
771fe6b9
JG		 1048}
1049
1050struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1051 radeon_encoder
1052 *encoder)
1053{
1054 struct drm_device *dev = encoder->base.dev;
1055 struct radeon_device *rdev = dev->dev_private;
1056 uint16_t dac_info;
1057 uint8_t rev, bg, dac;
1058 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 1059 int found = 0;
1060
1061 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1062 if (!tv_dac)
1063 return NULL;
771fe6b9 1064
771fe6b9
JG		 1065 /* first check TV table */
1066 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1067 if (dac_info) {
771fe6b9
JG		 1068 rev = RBIOS8(dac_info + 0x3);
1069 if (rev > 4) {
1070 bg = RBIOS8(dac_info + 0xc) & 0xf;
1071 dac = RBIOS8(dac_info + 0xd) & 0xf;
1072 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1073
1074 bg = RBIOS8(dac_info + 0xe) & 0xf;
1075 dac = RBIOS8(dac_info + 0xf) & 0xf;
1076 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1077
1078 bg = RBIOS8(dac_info + 0x10) & 0xf;
1079 dac = RBIOS8(dac_info + 0x11) & 0xf;
1080 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1081 /* if the values are all zeros, use the table */
1082 if (tv_dac->ps2_tvdac_adj)
1083 found = 1;
771fe6b9
JG		 1084 } else if (rev > 1) {
1085 bg = RBIOS8(dac_info + 0xc) & 0xf;
1086 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1087 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1088
1089 bg = RBIOS8(dac_info + 0xd) & 0xf;
1090 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1091 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1092
1093 bg = RBIOS8(dac_info + 0xe) & 0xf;
1094 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1095 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1096 /* if the values are all zeros, use the table */
1097 if (tv_dac->ps2_tvdac_adj)
1098 found = 1;
771fe6b9 1099 }
d79766fa 1100 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 1101 }
1102 if (!found) {
771fe6b9
JG		 1103 /* then check CRT table */
1104 dac_info =
1105 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1106 if (dac_info) {
771fe6b9
JG		 1107 rev = RBIOS8(dac_info) & 0x3;
1108 if (rev < 2) {
1109 bg = RBIOS8(dac_info + 0x3) & 0xf;
1110 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1111 tv_dac->ps2_tvdac_adj =
1112 (bg << 16) | (dac << 20);
1113 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1114 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1115 /* if the values are all zeros, use the table */
1116 if (tv_dac->ps2_tvdac_adj)
1117 found = 1;
771fe6b9
JG		 1118 } else {
1119 bg = RBIOS8(dac_info + 0x4) & 0xf;
1120 dac = RBIOS8(dac_info + 0x5) & 0xf;
1121 tv_dac->ps2_tvdac_adj =
1122 (bg << 16) | (dac << 20);
1123 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1124 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1125 /* if the values are all zeros, use the table */
1126 if (tv_dac->ps2_tvdac_adj)
1127 found = 1;
771fe6b9 1128 }
6fe7ac3f
AD		 1129 } else {
1130 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 1131 }
1132 }
1133
6a719e05
DA		 1134 if (!found) /* fallback to defaults */
1135 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1136
771fe6b9
JG		 1137 return tv_dac;
1138}
1139
1140static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1141 radeon_device
1142 *rdev)
1143{
1144 struct radeon_encoder_lvds *lvds = NULL;
1145 uint32_t fp_vert_stretch, fp_horz_stretch;
1146 uint32_t ppll_div_sel, ppll_val;
8b5c7444 1147 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 1148
1149 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1150
1151 if (!lvds)
1152 return NULL;
1153
1154 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1155 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1156
8b5c7444
MD		 1157 /* These should be fail-safe defaults, fingers crossed */
1158 lvds->panel_pwr_delay = 200;
1159 lvds->panel_vcc_delay = 2000;
1160
1161 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1162 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1163 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1164
771fe6b9 1165 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 1166 lvds->native_mode.vdisplay =
771fe6b9
JG		 1167 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1168 RADEON_VERT_PANEL_SHIFT) + 1;
1169 else
de2103e4 1170 lvds->native_mode.vdisplay =
771fe6b9
JG		 1171 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1172
1173 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 1174 lvds->native_mode.hdisplay =
771fe6b9
JG		 1175 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1176 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1177 else
de2103e4 1178 lvds->native_mode.hdisplay =
771fe6b9
JG		 1179 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1180
de2103e4
AD		 1181 if ((lvds->native_mode.hdisplay < 640) ||
1182 (lvds->native_mode.vdisplay < 480)) {
1183 lvds->native_mode.hdisplay = 640;
1184 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1185 }
1186
1187 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1188 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1189 if ((ppll_val & 0x000707ff) == 0x1bb)
1190 lvds->use_bios_dividers = false;
1191 else {
1192 lvds->panel_ref_divider =
1193 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1194 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1195 lvds->panel_fb_divider = ppll_val & 0x7ff;
1196
1197 if ((lvds->panel_ref_divider != 0) &&
1198 (lvds->panel_fb_divider > 3))
1199 lvds->use_bios_dividers = true;
1200 }
1201 lvds->panel_vcc_delay = 200;
1202
1203 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1204 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1205 lvds->native_mode.vdisplay);
771fe6b9
JG		 1206
1207 return lvds;
1208}
1209
1210struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1211 *encoder)
1212{
1213 struct drm_device *dev = encoder->base.dev;
1214 struct radeon_device *rdev = dev->dev_private;
1215 uint16_t lcd_info;
1216 uint32_t panel_setup;
1217 char stmp[30];
1218 int tmp, i;
1219 struct radeon_encoder_lvds *lvds = NULL;
1220
771fe6b9
JG		 1221 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1222
1223 if (lcd_info) {
1224 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1225
1226 if (!lvds)
1227 return NULL;
1228
1229 for (i = 0; i < 24; i++)
1230 stmp[i] = RBIOS8(lcd_info + i + 1);
1231 stmp[24] = 0;
1232
1233 DRM_INFO("Panel ID String: %s\n", stmp);
1234
de2103e4
AD		 1235 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1236 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1237
de2103e4
AD		 1238 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1239 lvds->native_mode.vdisplay);
771fe6b9
JG		 1240
1241 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1242 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1243
1244 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1245 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1246 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1247
1248 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1249 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1250 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1251 if ((lvds->panel_ref_divider != 0) &&
1252 (lvds->panel_fb_divider > 3))
1253 lvds->use_bios_dividers = true;
1254
1255 panel_setup = RBIOS32(lcd_info + 0x39);
1256 lvds->lvds_gen_cntl = 0xff00;
1257 if (panel_setup & 0x1)
1258 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1259
1260 if ((panel_setup >> 4) & 0x1)
1261 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1262
1263 switch ((panel_setup >> 8) & 0x7) {
1264 case 0:
1265 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1266 break;
1267 case 1:
1268 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1269 break;
1270 case 2:
1271 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1272 break;
1273 default:
1274 break;
1275 }
1276
1277 if ((panel_setup >> 16) & 0x1)
1278 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1279
1280 if ((panel_setup >> 17) & 0x1)
1281 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1282
1283 if ((panel_setup >> 18) & 0x1)
1284 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1285
1286 if ((panel_setup >> 23) & 0x1)
1287 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1288
1289 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1290
1291 for (i = 0; i < 32; i++) {
1292 tmp = RBIOS16(lcd_info + 64 + i * 2);
1293 if (tmp == 0)
1294 break;
1295
de2103e4 1296 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f
AD		 1297 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1298 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1299 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1300 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1301 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1302 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1303 (RBIOS8(tmp + 23) * 8);
1304
1305 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1306 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1307 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1308 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1309 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1310 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1311
1312 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1313 lvds->native_mode.flags = 0;
de2103e4
AD		 1314 /* set crtc values */
1315 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1316
771fe6b9
JG		 1317 }
1318 }
6fe7ac3f 1319 } else {
771fe6b9 1320 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1321 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1322 }
03047cdf 1323
8dfaa8a7
MD		 1324 if (lvds)
1325 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1326 return lvds;
1327}
1328
1329static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1330 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1331 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1332 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1333 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1334 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1335 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1336 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1337 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1338 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1339 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1340 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1341 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1342 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1343 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1344 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1345 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1346 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1347 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1348};
1349
445282db
DA		 1350bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1351 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1352{
445282db
DA		 1353 struct drm_device *dev = encoder->base.dev;
1354 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1355 int i;
771fe6b9
JG		 1356
1357 for (i = 0; i < 4; i++) {
1358 tmds->tmds_pll[i].value =
445282db 1359 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1360 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1361 }
1362
445282db 1363 return true;
771fe6b9
JG		 1364}
1365
445282db
DA		 1366bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1367 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1368{
1369 struct drm_device *dev = encoder->base.dev;
1370 struct radeon_device *rdev = dev->dev_private;
1371 uint16_t tmds_info;
1372 int i, n;
1373 uint8_t ver;
771fe6b9 1374
771fe6b9
JG		 1375 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1376
1377 if (tmds_info) {
771fe6b9 1378 ver = RBIOS8(tmds_info);
40f76d81 1379 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
771fe6b9
JG		 1380 if (ver == 3) {
1381 n = RBIOS8(tmds_info + 5) + 1;
1382 if (n > 4)
1383 n = 4;
1384 for (i = 0; i < n; i++) {
1385 tmds->tmds_pll[i].value =
1386 RBIOS32(tmds_info + i * 10 + 0x08);
1387 tmds->tmds_pll[i].freq =
1388 RBIOS16(tmds_info + i * 10 + 0x10);
d9fdaafb 1389 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1390 tmds->tmds_pll[i].freq,
1391 tmds->tmds_pll[i].value);
1392 }
1393 } else if (ver == 4) {
1394 int stride = 0;
1395 n = RBIOS8(tmds_info + 5) + 1;
1396 if (n > 4)
1397 n = 4;
1398 for (i = 0; i < n; i++) {
1399 tmds->tmds_pll[i].value =
1400 RBIOS32(tmds_info + stride + 0x08);
1401 tmds->tmds_pll[i].freq =
1402 RBIOS16(tmds_info + stride + 0x10);
1403 if (i == 0)
1404 stride += 10;
1405 else
1406 stride += 6;
d9fdaafb 1407 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1408 tmds->tmds_pll[i].freq,
1409 tmds->tmds_pll[i].value);
1410 }
1411 }
fcec570b 1412 } else {
771fe6b9 1413 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1414 return false;
1415 }
445282db
DA		 1416 return true;
1417}
1418
fcec570b
AD		 1419bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1420 struct radeon_encoder_ext_tmds *tmds)
445282db 1421{
fcec570b
AD		 1422 struct drm_device *dev = encoder->base.dev;
1423 struct radeon_device *rdev = dev->dev_private;
1424 struct radeon_i2c_bus_rec i2c_bus;
445282db 1425
fcec570b 1426 /* default for macs */
179e8078 1427 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
f376b94f 1428 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
445282db 1429
fcec570b
AD		 1430 /* XXX some macs have duallink chips */
1431 switch (rdev->mode_info.connector_table) {
1432 case CT_POWERBOOK_EXTERNAL:
1433 case CT_MINI_EXTERNAL:
1434 default:
1435 tmds->dvo_chip = DVO_SIL164;
1436 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1437 break;
1438 }
445282db 1439
fcec570b 1440 return true;
771fe6b9
JG		 1441}
1442
fcec570b
AD		 1443bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1444 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1445{
1446 struct drm_device *dev = encoder->base.dev;
1447 struct radeon_device *rdev = dev->dev_private;
fcec570b 1448 uint16_t offset;
179e8078 1449 uint8_t ver;
fcec570b
AD		 1450 enum radeon_combios_ddc gpio;
1451 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1452
fcec570b
AD		 1453 tmds->i2c_bus = NULL;
1454 if (rdev->flags & RADEON_IS_IGP) {
179e8078
AD		 1455 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1456 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1457 tmds->dvo_chip = DVO_SIL164;
1458 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
fcec570b
AD		 1459 } else {
1460 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1461 if (offset) {
1462 ver = RBIOS8(offset);
40f76d81 1463 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
fcec570b
AD		 1464 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1465 tmds->slave_addr >>= 1; /* 7 bit addressing */
1466 gpio = RBIOS8(offset + 4 + 3);
179e8078
AD		 1467 if (gpio == DDC_LCD) {
1468 /* MM i2c */
40bacf16
AD		 1469 i2c_bus.valid = true;
1470 i2c_bus.hw_capable = true;
1471 i2c_bus.mm_i2c = true;
179e8078
AD		 1472 i2c_bus.i2c_id = 0xa0;
1473 } else
1474 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1475 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
fcec570b 1476 }
771fe6b9 1477 }
fcec570b
AD		 1478
1479 if (!tmds->i2c_bus) {
1480 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1481 return false;
1482 }
1483
1484 return true;
771fe6b9
JG		 1485}
1486
1487bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1488{
1489 struct radeon_device *rdev = dev->dev_private;
1490 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1491 struct radeon_hpd hpd;
771fe6b9
JG		 1492
1493 rdev->mode_info.connector_table = radeon_connector_table;
1494 if (rdev->mode_info.connector_table == CT_NONE) {
1495#ifdef CONFIG_PPC_PMAC
71a157e8 1496 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1497 /* powerbook with VGA */
1498 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1499 } else if (of_machine_is_compatible("PowerBook3,4") ||
1500 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1501 /* powerbook with internal tmds */
1502 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1503 } else if (of_machine_is_compatible("PowerBook5,1") ||
1504 of_machine_is_compatible("PowerBook5,2") ||
1505 of_machine_is_compatible("PowerBook5,3") ||
1506 of_machine_is_compatible("PowerBook5,4") ||
1507 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1508 /* powerbook with external single link tmds (sil164) */
1509 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1510 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1511 /* powerbook with external dual or single link tmds */
1512 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1513 } else if (of_machine_is_compatible("PowerBook5,7") ||
1514 of_machine_is_compatible("PowerBook5,8") ||
1515 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1516 /* PowerBook6,2 ? */
1517 /* powerbook with external dual link tmds (sil1178?) */
1518 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1519 } else if (of_machine_is_compatible("PowerBook4,1") ||
1520 of_machine_is_compatible("PowerBook4,2") ||
1521 of_machine_is_compatible("PowerBook4,3") ||
1522 of_machine_is_compatible("PowerBook6,3") ||
1523 of_machine_is_compatible("PowerBook6,5") ||
1524 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1525 /* ibook */
1526 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1527 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1528 /* emac */
1529 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1530 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1531 /* mini with internal tmds */
1532 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1533 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1534 /* mini with external tmds */
1535 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1536 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1537 /* PowerMac8,1 ? */
1538 /* imac g5 isight */
1539 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
aa74fbb4
AD		 1540 } else if ((rdev->pdev->device == 0x4a48) &&
1541 (rdev->pdev->subsystem_vendor == 0x1002) &&
1542 (rdev->pdev->subsystem_device == 0x4a48)) {
1543 /* Mac X800 */
1544 rdev->mode_info.connector_table = CT_MAC_X800;
9fad321a
AD		 1545 } else if ((rdev->pdev->device == 0x4150) &&
1546 (rdev->pdev->subsystem_vendor == 0x1002) &&
1547 (rdev->pdev->subsystem_device == 0x4150)) {
1548 /* Mac G5 9600 */
1549 rdev->mode_info.connector_table = CT_MAC_G5_9600;
771fe6b9
JG		 1550 } else
1551#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1552#ifdef CONFIG_PPC64
1553 if (ASIC_IS_RN50(rdev))
1554 rdev->mode_info.connector_table = CT_RN50_POWER;
1555 else
1556#endif
771fe6b9
JG		 1557 rdev->mode_info.connector_table = CT_GENERIC;
1558 }
1559
1560 switch (rdev->mode_info.connector_table) {
1561 case CT_GENERIC:
1562 DRM_INFO("Connector Table: %d (generic)\n",
1563 rdev->mode_info.connector_table);
1564 /* these are the most common settings */
1565 if (rdev->flags & RADEON_SINGLE_CRTC) {
1566 /* VGA - primary dac */
179e8078 1567 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1568 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1569 radeon_add_legacy_encoder(dev,
5137ee94 1570 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1571 ATOM_DEVICE_CRT1_SUPPORT,
1572 1),
1573 ATOM_DEVICE_CRT1_SUPPORT);
1574 radeon_add_legacy_connector(dev, 0,
1575 ATOM_DEVICE_CRT1_SUPPORT,
1576 DRM_MODE_CONNECTOR_VGA,
b75fad06 1577 &ddc_i2c,
eed45b30
AD		 1578 CONNECTOR_OBJECT_ID_VGA,
1579 &hpd);
771fe6b9
JG		 1580 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1581 /* LVDS */
179e8078 1582 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
eed45b30 1583 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1584 radeon_add_legacy_encoder(dev,
5137ee94 1585 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1586 ATOM_DEVICE_LCD1_SUPPORT,
1587 0),
1588 ATOM_DEVICE_LCD1_SUPPORT);
1589 radeon_add_legacy_connector(dev, 0,
1590 ATOM_DEVICE_LCD1_SUPPORT,
1591 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1592 &ddc_i2c,
eed45b30
AD		 1593 CONNECTOR_OBJECT_ID_LVDS,
1594 &hpd);
771fe6b9
JG		 1595
1596 /* VGA - primary dac */
179e8078 1597 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1598 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1599 radeon_add_legacy_encoder(dev,
5137ee94 1600 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1601 ATOM_DEVICE_CRT1_SUPPORT,
1602 1),
1603 ATOM_DEVICE_CRT1_SUPPORT);
1604 radeon_add_legacy_connector(dev, 1,
1605 ATOM_DEVICE_CRT1_SUPPORT,
1606 DRM_MODE_CONNECTOR_VGA,
b75fad06 1607 &ddc_i2c,
eed45b30
AD		 1608 CONNECTOR_OBJECT_ID_VGA,
1609 &hpd);
771fe6b9
JG		 1610 } else {
1611 /* DVI-I - tv dac, int tmds */
179e8078 1612 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1613 hpd.hpd = RADEON_HPD_1;
771fe6b9 1614 radeon_add_legacy_encoder(dev,
5137ee94 1615 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1616 ATOM_DEVICE_DFP1_SUPPORT,
1617 0),
1618 ATOM_DEVICE_DFP1_SUPPORT);
1619 radeon_add_legacy_encoder(dev,
5137ee94 1620 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1621 ATOM_DEVICE_CRT2_SUPPORT,
1622 2),
1623 ATOM_DEVICE_CRT2_SUPPORT);
1624 radeon_add_legacy_connector(dev, 0,
1625 ATOM_DEVICE_DFP1_SUPPORT |
1626 ATOM_DEVICE_CRT2_SUPPORT,
1627 DRM_MODE_CONNECTOR_DVII,
b75fad06 1628 &ddc_i2c,
eed45b30
AD		 1629 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1630 &hpd);
771fe6b9
JG		 1631
1632 /* VGA - primary dac */
179e8078 1633 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1634 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1635 radeon_add_legacy_encoder(dev,
5137ee94 1636 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1637 ATOM_DEVICE_CRT1_SUPPORT,
1638 1),
1639 ATOM_DEVICE_CRT1_SUPPORT);
1640 radeon_add_legacy_connector(dev, 1,
1641 ATOM_DEVICE_CRT1_SUPPORT,
1642 DRM_MODE_CONNECTOR_VGA,
b75fad06 1643 &ddc_i2c,
eed45b30
AD		 1644 CONNECTOR_OBJECT_ID_VGA,
1645 &hpd);
771fe6b9
JG		 1646 }
1647
1648 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1649 /* TV - tv dac */
eed45b30
AD		 1650 ddc_i2c.valid = false;
1651 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1652 radeon_add_legacy_encoder(dev,
5137ee94 1653 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1654 ATOM_DEVICE_TV1_SUPPORT,
1655 2),
1656 ATOM_DEVICE_TV1_SUPPORT);
1657 radeon_add_legacy_connector(dev, 2,
1658 ATOM_DEVICE_TV1_SUPPORT,
1659 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1660 &ddc_i2c,
eed45b30
AD		 1661 CONNECTOR_OBJECT_ID_SVIDEO,
1662 &hpd);
771fe6b9
JG		 1663 }
1664 break;
1665 case CT_IBOOK:
1666 DRM_INFO("Connector Table: %d (ibook)\n",
1667 rdev->mode_info.connector_table);
1668 /* LVDS */
179e8078 1669 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1670 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1671 radeon_add_legacy_encoder(dev,
5137ee94 1672 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1673 ATOM_DEVICE_LCD1_SUPPORT,
1674 0),
1675 ATOM_DEVICE_LCD1_SUPPORT);
1676 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1677 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1678 CONNECTOR_OBJECT_ID_LVDS,
1679 &hpd);
771fe6b9 1680 /* VGA - TV DAC */
179e8078 1681 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1682 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1683 radeon_add_legacy_encoder(dev,
5137ee94 1684 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1685 ATOM_DEVICE_CRT2_SUPPORT,
1686 2),
1687 ATOM_DEVICE_CRT2_SUPPORT);
1688 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1689 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1690 CONNECTOR_OBJECT_ID_VGA,
1691 &hpd);
771fe6b9 1692 /* TV - TV DAC */
eed45b30
AD		 1693 ddc_i2c.valid = false;
1694 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1695 radeon_add_legacy_encoder(dev,
5137ee94 1696 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1697 ATOM_DEVICE_TV1_SUPPORT,
1698 2),
1699 ATOM_DEVICE_TV1_SUPPORT);
1700 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1701 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1702 &ddc_i2c,
eed45b30
AD		 1703 CONNECTOR_OBJECT_ID_SVIDEO,
1704 &hpd);
771fe6b9
JG		 1705 break;
1706 case CT_POWERBOOK_EXTERNAL:
1707 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1708 rdev->mode_info.connector_table);
1709 /* LVDS */
179e8078 1710 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1711 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1712 radeon_add_legacy_encoder(dev,
5137ee94 1713 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1714 ATOM_DEVICE_LCD1_SUPPORT,
1715 0),
1716 ATOM_DEVICE_LCD1_SUPPORT);
1717 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1718 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1719 CONNECTOR_OBJECT_ID_LVDS,
1720 &hpd);
771fe6b9 1721 /* DVI-I - primary dac, ext tmds */
179e8078 1722 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1723 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1724 radeon_add_legacy_encoder(dev,
5137ee94 1725 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1726 ATOM_DEVICE_DFP2_SUPPORT,
1727 0),
1728 ATOM_DEVICE_DFP2_SUPPORT);
1729 radeon_add_legacy_encoder(dev,
5137ee94 1730 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1731 ATOM_DEVICE_CRT1_SUPPORT,
1732 1),
1733 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1734 /* XXX some are SL */
771fe6b9
JG		 1735 radeon_add_legacy_connector(dev, 1,
1736 ATOM_DEVICE_DFP2_SUPPORT |
1737 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1738 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1739 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1740 &hpd);
771fe6b9 1741 /* TV - TV DAC */
eed45b30
AD		 1742 ddc_i2c.valid = false;
1743 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1744 radeon_add_legacy_encoder(dev,
5137ee94 1745 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1746 ATOM_DEVICE_TV1_SUPPORT,
1747 2),
1748 ATOM_DEVICE_TV1_SUPPORT);
1749 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1750 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1751 &ddc_i2c,
eed45b30
AD		 1752 CONNECTOR_OBJECT_ID_SVIDEO,
1753 &hpd);
771fe6b9
JG		 1754 break;
1755 case CT_POWERBOOK_INTERNAL:
1756 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1757 rdev->mode_info.connector_table);
1758 /* LVDS */
179e8078 1759 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1760 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1761 radeon_add_legacy_encoder(dev,
5137ee94 1762 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1763 ATOM_DEVICE_LCD1_SUPPORT,
1764 0),
1765 ATOM_DEVICE_LCD1_SUPPORT);
1766 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1767 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1768 CONNECTOR_OBJECT_ID_LVDS,
1769 &hpd);
771fe6b9 1770 /* DVI-I - primary dac, int tmds */
179e8078 1771 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1772 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1773 radeon_add_legacy_encoder(dev,
5137ee94 1774 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1775 ATOM_DEVICE_DFP1_SUPPORT,
1776 0),
1777 ATOM_DEVICE_DFP1_SUPPORT);
1778 radeon_add_legacy_encoder(dev,
5137ee94 1779 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1780 ATOM_DEVICE_CRT1_SUPPORT,
1781 1),
1782 ATOM_DEVICE_CRT1_SUPPORT);
1783 radeon_add_legacy_connector(dev, 1,
1784 ATOM_DEVICE_DFP1_SUPPORT |
1785 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1786 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1787 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1788 &hpd);
771fe6b9 1789 /* TV - TV DAC */
eed45b30
AD		 1790 ddc_i2c.valid = false;
1791 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1792 radeon_add_legacy_encoder(dev,
5137ee94 1793 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1794 ATOM_DEVICE_TV1_SUPPORT,
1795 2),
1796 ATOM_DEVICE_TV1_SUPPORT);
1797 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1798 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1799 &ddc_i2c,
eed45b30
AD		 1800 CONNECTOR_OBJECT_ID_SVIDEO,
1801 &hpd);
771fe6b9
JG		 1802 break;
1803 case CT_POWERBOOK_VGA:
1804 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1805 rdev->mode_info.connector_table);
1806 /* LVDS */
179e8078 1807 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1808 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1809 radeon_add_legacy_encoder(dev,
5137ee94 1810 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1811 ATOM_DEVICE_LCD1_SUPPORT,
1812 0),
1813 ATOM_DEVICE_LCD1_SUPPORT);
1814 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1815 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1816 CONNECTOR_OBJECT_ID_LVDS,
1817 &hpd);
771fe6b9 1818 /* VGA - primary dac */
179e8078 1819 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1820 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1821 radeon_add_legacy_encoder(dev,
5137ee94 1822 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1823 ATOM_DEVICE_CRT1_SUPPORT,
1824 1),
1825 ATOM_DEVICE_CRT1_SUPPORT);
1826 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1827 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1828 CONNECTOR_OBJECT_ID_VGA,
1829 &hpd);
771fe6b9 1830 /* TV - TV DAC */
eed45b30
AD		 1831 ddc_i2c.valid = false;
1832 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1833 radeon_add_legacy_encoder(dev,
5137ee94 1834 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1835 ATOM_DEVICE_TV1_SUPPORT,
1836 2),
1837 ATOM_DEVICE_TV1_SUPPORT);
1838 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1839 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1840 &ddc_i2c,
eed45b30
AD		 1841 CONNECTOR_OBJECT_ID_SVIDEO,
1842 &hpd);
771fe6b9
JG		 1843 break;
1844 case CT_MINI_EXTERNAL:
1845 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1846 rdev->mode_info.connector_table);
1847 /* DVI-I - tv dac, ext tmds */
179e8078 1848 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1849 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1850 radeon_add_legacy_encoder(dev,
5137ee94 1851 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1852 ATOM_DEVICE_DFP2_SUPPORT,
1853 0),
1854 ATOM_DEVICE_DFP2_SUPPORT);
1855 radeon_add_legacy_encoder(dev,
5137ee94 1856 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1857 ATOM_DEVICE_CRT2_SUPPORT,
1858 2),
1859 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1860 /* XXX are any DL? */
771fe6b9
JG		 1861 radeon_add_legacy_connector(dev, 0,
1862 ATOM_DEVICE_DFP2_SUPPORT |
1863 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1864 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1865 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1866 &hpd);
771fe6b9 1867 /* TV - TV DAC */
eed45b30
AD		 1868 ddc_i2c.valid = false;
1869 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1870 radeon_add_legacy_encoder(dev,
5137ee94 1871 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1872 ATOM_DEVICE_TV1_SUPPORT,
1873 2),
1874 ATOM_DEVICE_TV1_SUPPORT);
1875 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1876 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1877 &ddc_i2c,
eed45b30
AD		 1878 CONNECTOR_OBJECT_ID_SVIDEO,
1879 &hpd);
771fe6b9
JG		 1880 break;
1881 case CT_MINI_INTERNAL:
1882 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1883 rdev->mode_info.connector_table);
1884 /* DVI-I - tv dac, int tmds */
179e8078 1885 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1886 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1887 radeon_add_legacy_encoder(dev,
5137ee94 1888 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1889 ATOM_DEVICE_DFP1_SUPPORT,
1890 0),
1891 ATOM_DEVICE_DFP1_SUPPORT);
1892 radeon_add_legacy_encoder(dev,
5137ee94 1893 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1894 ATOM_DEVICE_CRT2_SUPPORT,
1895 2),
1896 ATOM_DEVICE_CRT2_SUPPORT);
1897 radeon_add_legacy_connector(dev, 0,
1898 ATOM_DEVICE_DFP1_SUPPORT |
1899 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1900 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1901 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1902 &hpd);
771fe6b9 1903 /* TV - TV DAC */
eed45b30
AD		 1904 ddc_i2c.valid = false;
1905 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1906 radeon_add_legacy_encoder(dev,
5137ee94 1907 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1908 ATOM_DEVICE_TV1_SUPPORT,
1909 2),
1910 ATOM_DEVICE_TV1_SUPPORT);
1911 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1912 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1913 &ddc_i2c,
eed45b30
AD		 1914 CONNECTOR_OBJECT_ID_SVIDEO,
1915 &hpd);
771fe6b9
JG		 1916 break;
1917 case CT_IMAC_G5_ISIGHT:
1918 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1919 rdev->mode_info.connector_table);
1920 /* DVI-D - int tmds */
179e8078 1921 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
eed45b30 1922 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1923 radeon_add_legacy_encoder(dev,
5137ee94 1924 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1925 ATOM_DEVICE_DFP1_SUPPORT,
1926 0),
1927 ATOM_DEVICE_DFP1_SUPPORT);
1928 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1929 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1930 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1931 &hpd);
771fe6b9 1932 /* VGA - tv dac */
179e8078 1933 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1934 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1935 radeon_add_legacy_encoder(dev,
5137ee94 1936 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1937 ATOM_DEVICE_CRT2_SUPPORT,
1938 2),
1939 ATOM_DEVICE_CRT2_SUPPORT);
1940 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1941 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1942 CONNECTOR_OBJECT_ID_VGA,
1943 &hpd);
771fe6b9 1944 /* TV - TV DAC */
eed45b30
AD		 1945 ddc_i2c.valid = false;
1946 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1947 radeon_add_legacy_encoder(dev,
5137ee94 1948 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1949 ATOM_DEVICE_TV1_SUPPORT,
1950 2),
1951 ATOM_DEVICE_TV1_SUPPORT);
1952 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1953 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1954 &ddc_i2c,
eed45b30
AD		 1955 CONNECTOR_OBJECT_ID_SVIDEO,
1956 &hpd);
771fe6b9
JG		 1957 break;
1958 case CT_EMAC:
1959 DRM_INFO("Connector Table: %d (emac)\n",
1960 rdev->mode_info.connector_table);
1961 /* VGA - primary dac */
179e8078 1962 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1963 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1964 radeon_add_legacy_encoder(dev,
5137ee94 1965 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1966 ATOM_DEVICE_CRT1_SUPPORT,
1967 1),
1968 ATOM_DEVICE_CRT1_SUPPORT);
1969 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1970 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1971 CONNECTOR_OBJECT_ID_VGA,
1972 &hpd);
771fe6b9 1973 /* VGA - tv dac */
179e8078 1974 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1975 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1976 radeon_add_legacy_encoder(dev,
5137ee94 1977 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1978 ATOM_DEVICE_CRT2_SUPPORT,
1979 2),
1980 ATOM_DEVICE_CRT2_SUPPORT);
1981 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1982 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1983 CONNECTOR_OBJECT_ID_VGA,
1984 &hpd);
771fe6b9 1985 /* TV - TV DAC */
eed45b30
AD		 1986 ddc_i2c.valid = false;
1987 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1988 radeon_add_legacy_encoder(dev,
5137ee94 1989 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1990 ATOM_DEVICE_TV1_SUPPORT,
1991 2),
1992 ATOM_DEVICE_TV1_SUPPORT);
1993 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1994 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1995 &ddc_i2c,
eed45b30
AD		 1996 CONNECTOR_OBJECT_ID_SVIDEO,
1997 &hpd);
771fe6b9 1998 break;
76a7142a
DA		 1999 case CT_RN50_POWER:
2000 DRM_INFO("Connector Table: %d (rn50-power)\n",
2001 rdev->mode_info.connector_table);
2002 /* VGA - primary dac */
179e8078 2003 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
76a7142a
DA		 2004 hpd.hpd = RADEON_HPD_NONE;
2005 radeon_add_legacy_encoder(dev,
5137ee94 2006 radeon_get_encoder_enum(dev,
76a7142a
DA		 2007 ATOM_DEVICE_CRT1_SUPPORT,
2008 1),
2009 ATOM_DEVICE_CRT1_SUPPORT);
2010 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2011 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2012 CONNECTOR_OBJECT_ID_VGA,
2013 &hpd);
179e8078 2014 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
76a7142a
DA		 2015 hpd.hpd = RADEON_HPD_NONE;
2016 radeon_add_legacy_encoder(dev,
5137ee94 2017 radeon_get_encoder_enum(dev,
76a7142a
DA		 2018 ATOM_DEVICE_CRT2_SUPPORT,
2019 2),
2020 ATOM_DEVICE_CRT2_SUPPORT);
2021 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2022 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2023 CONNECTOR_OBJECT_ID_VGA,
2024 &hpd);
2025 break;
aa74fbb4
AD		 2026 case CT_MAC_X800:
2027 DRM_INFO("Connector Table: %d (mac x800)\n",
2028 rdev->mode_info.connector_table);
2029 /* DVI - primary dac, internal tmds */
2030 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2031 hpd.hpd = RADEON_HPD_1; /* ??? */
2032 radeon_add_legacy_encoder(dev,
2033 radeon_get_encoder_enum(dev,
2034 ATOM_DEVICE_DFP1_SUPPORT,
2035 0),
2036 ATOM_DEVICE_DFP1_SUPPORT);
2037 radeon_add_legacy_encoder(dev,
2038 radeon_get_encoder_enum(dev,
2039 ATOM_DEVICE_CRT1_SUPPORT,
2040 1),
2041 ATOM_DEVICE_CRT1_SUPPORT);
2042 radeon_add_legacy_connector(dev, 0,
2043 ATOM_DEVICE_DFP1_SUPPORT |
2044 ATOM_DEVICE_CRT1_SUPPORT,
2045 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2046 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2047 &hpd);
2048 /* DVI - tv dac, dvo */
2049 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2050 hpd.hpd = RADEON_HPD_2; /* ??? */
2051 radeon_add_legacy_encoder(dev,
2052 radeon_get_encoder_enum(dev,
2053 ATOM_DEVICE_DFP2_SUPPORT,
2054 0),
2055 ATOM_DEVICE_DFP2_SUPPORT);
2056 radeon_add_legacy_encoder(dev,
2057 radeon_get_encoder_enum(dev,
2058 ATOM_DEVICE_CRT2_SUPPORT,
2059 2),
2060 ATOM_DEVICE_CRT2_SUPPORT);
2061 radeon_add_legacy_connector(dev, 1,
2062 ATOM_DEVICE_DFP2_SUPPORT |
2063 ATOM_DEVICE_CRT2_SUPPORT,
2064 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2065 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2066 &hpd);
2067 break;
9fad321a
AD		 2068 case CT_MAC_G5_9600:
2069 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2070 rdev->mode_info.connector_table);
2071 /* DVI - tv dac, dvo */
2072 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2073 hpd.hpd = RADEON_HPD_1; /* ??? */
2074 radeon_add_legacy_encoder(dev,
2075 radeon_get_encoder_enum(dev,
2076 ATOM_DEVICE_DFP2_SUPPORT,
2077 0),
2078 ATOM_DEVICE_DFP2_SUPPORT);
2079 radeon_add_legacy_encoder(dev,
2080 radeon_get_encoder_enum(dev,
2081 ATOM_DEVICE_CRT2_SUPPORT,
2082 2),
2083 ATOM_DEVICE_CRT2_SUPPORT);
2084 radeon_add_legacy_connector(dev, 0,
2085 ATOM_DEVICE_DFP2_SUPPORT |
2086 ATOM_DEVICE_CRT2_SUPPORT,
2087 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2088 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2089 &hpd);
2090 /* ADC - primary dac, internal tmds */
2091 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2092 hpd.hpd = RADEON_HPD_2; /* ??? */
2093 radeon_add_legacy_encoder(dev,
2094 radeon_get_encoder_enum(dev,
2095 ATOM_DEVICE_DFP1_SUPPORT,
2096 0),
2097 ATOM_DEVICE_DFP1_SUPPORT);
2098 radeon_add_legacy_encoder(dev,
2099 radeon_get_encoder_enum(dev,
2100 ATOM_DEVICE_CRT1_SUPPORT,
2101 1),
2102 ATOM_DEVICE_CRT1_SUPPORT);
2103 radeon_add_legacy_connector(dev, 1,
2104 ATOM_DEVICE_DFP1_SUPPORT |
2105 ATOM_DEVICE_CRT1_SUPPORT,
2106 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2107 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2108 &hpd);
beb47274
AD		 2109 /* TV - TV DAC */
2110 ddc_i2c.valid = false;
2111 hpd.hpd = RADEON_HPD_NONE;
2112 radeon_add_legacy_encoder(dev,
2113 radeon_get_encoder_enum(dev,
2114 ATOM_DEVICE_TV1_SUPPORT,
2115 2),
2116 ATOM_DEVICE_TV1_SUPPORT);
2117 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2118 DRM_MODE_CONNECTOR_SVIDEO,
2119 &ddc_i2c,
2120 CONNECTOR_OBJECT_ID_SVIDEO,
2121 &hpd);
9fad321a 2122 break;
771fe6b9
JG		 2123 default:
2124 DRM_INFO("Connector table: %d (invalid)\n",
2125 rdev->mode_info.connector_table);
2126 return false;
2127 }
2128
2129 radeon_link_encoder_connector(dev);
2130
2131 return true;
2132}
2133
2134static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2135 int bios_index,
2136 enum radeon_combios_connector
2137 *legacy_connector,
eed45b30
AD		 2138 struct radeon_i2c_bus_rec *ddc_i2c,
2139 struct radeon_hpd *hpd)
771fe6b9 2140{
fcec570b 2141
771fe6b9
JG		 2142 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2143 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2144 if (dev->pdev->device == 0x515e &&
2145 dev->pdev->subsystem_vendor == 0x1014) {
2146 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2147 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2148 return false;
2149 }
2150
771fe6b9
JG		 2151 /* X300 card with extra non-existent DVI port */
2152 if (dev->pdev->device == 0x5B60 &&
2153 dev->pdev->subsystem_vendor == 0x17af &&
2154 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2155 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2156 return false;
2157 }
2158
2159 return true;
2160}
2161
790cfb34
AD		 2162static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2163{
2164 /* Acer 5102 has non-existent TV port */
2165 if (dev->pdev->device == 0x5975 &&
2166 dev->pdev->subsystem_vendor == 0x1025 &&
2167 dev->pdev->subsystem_device == 0x009f)
2168 return false;
2169
fc7f7119
AD		 2170 /* HP dc5750 has non-existent TV port */
2171 if (dev->pdev->device == 0x5974 &&
2172 dev->pdev->subsystem_vendor == 0x103c &&
2173 dev->pdev->subsystem_device == 0x280a)
2174 return false;
2175
fd874ad0
AD		 2176 /* MSI S270 has non-existent TV port */
2177 if (dev->pdev->device == 0x5955 &&
2178 dev->pdev->subsystem_vendor == 0x1462 &&
2179 dev->pdev->subsystem_device == 0x0131)
2180 return false;
2181
790cfb34
AD		 2182 return true;
2183}
2184
b75fad06
AD		 2185static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2186{
2187 struct radeon_device *rdev = dev->dev_private;
2188 uint32_t ext_tmds_info;
2189
2190 if (rdev->flags & RADEON_IS_IGP) {
2191 if (is_dvi_d)
2192 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2193 else
2194 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2195 }
2196 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2197 if (ext_tmds_info) {
2198 uint8_t rev = RBIOS8(ext_tmds_info);
2199 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2200 if (rev >= 3) {
2201 if (is_dvi_d)
2202 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2203 else
2204 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2205 } else {
2206 if (flags & 1) {
2207 if (is_dvi_d)
2208 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2209 else
2210 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2211 }
2212 }
2213 }
2214 if (is_dvi_d)
2215 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2216 else
2217 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2218}
2219
771fe6b9
JG		 2220bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2221{
2222 struct radeon_device *rdev = dev->dev_private;
2223 uint32_t conn_info, entry, devices;
b75fad06 2224 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2225 enum radeon_combios_ddc ddc_type;
2226 enum radeon_combios_connector connector;
2227 int i = 0;
2228 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2229 struct radeon_hpd hpd;
771fe6b9 2230
771fe6b9
JG		 2231 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2232 if (conn_info) {
2233 for (i = 0; i < 4; i++) {
2234 entry = conn_info + 2 + i * 2;
2235
2236 if (!RBIOS16(entry))
2237 break;
2238
2239 tmp = RBIOS16(entry);
2240
2241 connector = (tmp >> 12) & 0xf;
2242
2243 ddc_type = (tmp >> 8) & 0xf;
179e8078 2244 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9 2245
eed45b30
AD		 2246 switch (connector) {
2247 case CONNECTOR_PROPRIETARY_LEGACY:
2248 case CONNECTOR_DVI_I_LEGACY:
2249 case CONNECTOR_DVI_D_LEGACY:
2250 if ((tmp >> 4) & 0x1)
2251 hpd.hpd = RADEON_HPD_2;
2252 else
2253 hpd.hpd = RADEON_HPD_1;
2254 break;
2255 default:
2256 hpd.hpd = RADEON_HPD_NONE;
2257 break;
2258 }
2259
2d152c6b 2260 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2261 &ddc_i2c, &hpd))
2d152c6b 2262 continue;
771fe6b9
JG		 2263
2264 switch (connector) {
2265 case CONNECTOR_PROPRIETARY_LEGACY:
2266 if ((tmp >> 4) & 0x1)
2267 devices = ATOM_DEVICE_DFP2_SUPPORT;
2268 else
2269 devices = ATOM_DEVICE_DFP1_SUPPORT;
2270 radeon_add_legacy_encoder(dev,
5137ee94 2271 radeon_get_encoder_enum
771fe6b9
JG		 2272 (dev, devices, 0),
2273 devices);
2274 radeon_add_legacy_connector(dev, i, devices,
2275 legacy_connector_convert
2276 [connector],
b75fad06 2277 &ddc_i2c,
eed45b30
AD		 2278 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2279 &hpd);
771fe6b9
JG		 2280 break;
2281 case CONNECTOR_CRT_LEGACY:
2282 if (tmp & 0x1) {
2283 devices = ATOM_DEVICE_CRT2_SUPPORT;
2284 radeon_add_legacy_encoder(dev,
5137ee94 2285 radeon_get_encoder_enum
771fe6b9
JG		 2286 (dev,
2287 ATOM_DEVICE_CRT2_SUPPORT,
2288 2),
2289 ATOM_DEVICE_CRT2_SUPPORT);
2290 } else {
2291 devices = ATOM_DEVICE_CRT1_SUPPORT;
2292 radeon_add_legacy_encoder(dev,
5137ee94 2293 radeon_get_encoder_enum
771fe6b9
JG		 2294 (dev,
2295 ATOM_DEVICE_CRT1_SUPPORT,
2296 1),
2297 ATOM_DEVICE_CRT1_SUPPORT);
2298 }
2299 radeon_add_legacy_connector(dev,
2300 i,
2301 devices,
2302 legacy_connector_convert
2303 [connector],
b75fad06 2304 &ddc_i2c,
eed45b30
AD		 2305 CONNECTOR_OBJECT_ID_VGA,
2306 &hpd);
771fe6b9
JG		 2307 break;
2308 case CONNECTOR_DVI_I_LEGACY:
2309 devices = 0;
2310 if (tmp & 0x1) {
2311 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2312 radeon_add_legacy_encoder(dev,
5137ee94 2313 radeon_get_encoder_enum
771fe6b9
JG		 2314 (dev,
2315 ATOM_DEVICE_CRT2_SUPPORT,
2316 2),
2317 ATOM_DEVICE_CRT2_SUPPORT);
2318 } else {
2319 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2320 radeon_add_legacy_encoder(dev,
5137ee94 2321 radeon_get_encoder_enum
771fe6b9
JG		 2322 (dev,
2323 ATOM_DEVICE_CRT1_SUPPORT,
2324 1),
2325 ATOM_DEVICE_CRT1_SUPPORT);
2326 }
2327 if ((tmp >> 4) & 0x1) {
2328 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2329 radeon_add_legacy_encoder(dev,
5137ee94 2330 radeon_get_encoder_enum
771fe6b9
JG		 2331 (dev,
2332 ATOM_DEVICE_DFP2_SUPPORT,
2333 0),
2334 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2335 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2336 } else {
2337 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2338 radeon_add_legacy_encoder(dev,
5137ee94 2339 radeon_get_encoder_enum
771fe6b9
JG		 2340 (dev,
2341 ATOM_DEVICE_DFP1_SUPPORT,
2342 0),
2343 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2344 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2345 }
2346 radeon_add_legacy_connector(dev,
2347 i,
2348 devices,
2349 legacy_connector_convert
2350 [connector],
b75fad06 2351 &ddc_i2c,
eed45b30
AD		 2352 connector_object_id,
2353 &hpd);
771fe6b9
JG		 2354 break;
2355 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2356 if ((tmp >> 4) & 0x1) {
771fe6b9 2357 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2358 connector_object_id = combios_check_dl_dvi(dev, 1);
2359 } else {
771fe6b9 2360 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2361 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2362 }
771fe6b9 2363 radeon_add_legacy_encoder(dev,
5137ee94 2364 radeon_get_encoder_enum
771fe6b9
JG		 2365 (dev, devices, 0),
2366 devices);
2367 radeon_add_legacy_connector(dev, i, devices,
2368 legacy_connector_convert
2369 [connector],
b75fad06 2370 &ddc_i2c,
eed45b30
AD		 2371 connector_object_id,
2372 &hpd);
771fe6b9
JG		 2373 break;
2374 case CONNECTOR_CTV_LEGACY:
2375 case CONNECTOR_STV_LEGACY:
2376 radeon_add_legacy_encoder(dev,
5137ee94 2377 radeon_get_encoder_enum
771fe6b9
JG		 2378 (dev,
2379 ATOM_DEVICE_TV1_SUPPORT,
2380 2),
2381 ATOM_DEVICE_TV1_SUPPORT);
2382 radeon_add_legacy_connector(dev, i,
2383 ATOM_DEVICE_TV1_SUPPORT,
2384 legacy_connector_convert
2385 [connector],
b75fad06 2386 &ddc_i2c,
eed45b30
AD		 2387 CONNECTOR_OBJECT_ID_SVIDEO,
2388 &hpd);
771fe6b9
JG		 2389 break;
2390 default:
2391 DRM_ERROR("Unknown connector type: %d\n",
2392 connector);
2393 continue;
2394 }
2395
2396 }
2397 } else {
2398 uint16_t tmds_info =
2399 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2400 if (tmds_info) {
d9fdaafb 2401 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
771fe6b9
JG		 2402
2403 radeon_add_legacy_encoder(dev,
5137ee94 2404 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2405 ATOM_DEVICE_CRT1_SUPPORT,
2406 1),
2407 ATOM_DEVICE_CRT1_SUPPORT);
2408 radeon_add_legacy_encoder(dev,
5137ee94 2409 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2410 ATOM_DEVICE_DFP1_SUPPORT,
2411 0),
2412 ATOM_DEVICE_DFP1_SUPPORT);
2413
179e8078 2414 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
8e36ed00 2415 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2416 radeon_add_legacy_connector(dev,
2417 0,
2418 ATOM_DEVICE_CRT1_SUPPORT |
2419 ATOM_DEVICE_DFP1_SUPPORT,
2420 DRM_MODE_CONNECTOR_DVII,
b75fad06 2421 &ddc_i2c,
eed45b30
AD		 2422 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2423 &hpd);
771fe6b9 2424 } else {
d0c403e9
AD		 2425 uint16_t crt_info =
2426 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
d9fdaafb 2427 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
d0c403e9
AD		 2428 if (crt_info) {
2429 radeon_add_legacy_encoder(dev,
5137ee94 2430 radeon_get_encoder_enum(dev,
d0c403e9
AD		 2431 ATOM_DEVICE_CRT1_SUPPORT,
2432 1),
2433 ATOM_DEVICE_CRT1_SUPPORT);
179e8078 2434 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 2435 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2436 radeon_add_legacy_connector(dev,
2437 0,
2438 ATOM_DEVICE_CRT1_SUPPORT,
2439 DRM_MODE_CONNECTOR_VGA,
b75fad06 2440 &ddc_i2c,
eed45b30
AD		 2441 CONNECTOR_OBJECT_ID_VGA,
2442 &hpd);
d0c403e9 2443 } else {
d9fdaafb 2444 DRM_DEBUG_KMS("No connector info found\n");
d0c403e9
AD		 2445 return false;
2446 }
771fe6b9
JG		 2447 }
2448 }
2449
2450 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2451 uint16_t lcd_info =
2452 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2453 if (lcd_info) {
2454 uint16_t lcd_ddc_info =
2455 combios_get_table_offset(dev,
2456 COMBIOS_LCD_DDC_INFO_TABLE);
2457
2458 radeon_add_legacy_encoder(dev,
5137ee94 2459 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2460 ATOM_DEVICE_LCD1_SUPPORT,
2461 0),
2462 ATOM_DEVICE_LCD1_SUPPORT);
2463
2464 if (lcd_ddc_info) {
2465 ddc_type = RBIOS8(lcd_ddc_info + 2);
2466 switch (ddc_type) {
771fe6b9
JG		 2467 case DDC_LCD:
2468 ddc_i2c =
179e8078
AD		 2469 combios_setup_i2c_bus(rdev,
2470 DDC_LCD,
2471 RBIOS32(lcd_ddc_info + 3),
2472 RBIOS32(lcd_ddc_info + 7));
f376b94f 2473 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2474 break;
2475 case DDC_GPIO:
2476 ddc_i2c =
179e8078
AD		 2477 combios_setup_i2c_bus(rdev,
2478 DDC_GPIO,
2479 RBIOS32(lcd_ddc_info + 3),
2480 RBIOS32(lcd_ddc_info + 7));
f376b94f 2481 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2482 break;
2483 default:
179e8078
AD		 2484 ddc_i2c =
2485 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9
JG		 2486 break;
2487 }
d9fdaafb 2488 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
771fe6b9
JG		 2489 } else
2490 ddc_i2c.valid = false;
2491
eed45b30 2492 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2493 radeon_add_legacy_connector(dev,
2494 5,
2495 ATOM_DEVICE_LCD1_SUPPORT,
2496 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2497 &ddc_i2c,
eed45b30
AD		 2498 CONNECTOR_OBJECT_ID_LVDS,
2499 &hpd);
771fe6b9
JG		 2500 }
2501 }
2502
2503 /* check TV table */
2504 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2505 uint32_t tv_info =
2506 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2507 if (tv_info) {
2508 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2509 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2510 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2511 ddc_i2c.valid = false;
790cfb34 2512 radeon_add_legacy_encoder(dev,
5137ee94 2513 radeon_get_encoder_enum
790cfb34
AD		 2514 (dev,
2515 ATOM_DEVICE_TV1_SUPPORT,
2516 2),
2517 ATOM_DEVICE_TV1_SUPPORT);
2518 radeon_add_legacy_connector(dev, 6,
2519 ATOM_DEVICE_TV1_SUPPORT,
2520 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2521 &ddc_i2c,
eed45b30
AD		 2522 CONNECTOR_OBJECT_ID_SVIDEO,
2523 &hpd);
790cfb34 2524 }
771fe6b9
JG		 2525 }
2526 }
2527 }
2528
2529 radeon_link_encoder_connector(dev);
2530
2531 return true;
2532}
2533
63f7d982
AD		 2534static const char *thermal_controller_names[] = {
2535 "NONE",
2536 "lm63",
2537 "adm1032",
2538};
2539
56278a8e
AD		 2540void radeon_combios_get_power_modes(struct radeon_device *rdev)
2541{
2542 struct drm_device *dev = rdev->ddev;
2543 u16 offset, misc, misc2 = 0;
2544 u8 rev, blocks, tmp;
2545 int state_index = 0;
2546
a48b9b4e 2547 rdev->pm.default_power_state_index = -1;
56278a8e 2548
0975b162
AD		 2549 /* allocate 2 power states */
2550 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2551 if (!rdev->pm.power_state) {
2552 rdev->pm.default_power_state_index = state_index;
2553 rdev->pm.num_power_states = 0;
2554
2555 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2556 rdev->pm.current_clock_mode_index = 0;
2557 return;
2558 }
2559
63f7d982
AD		 2560 /* check for a thermal chip */
2561 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2562 if (offset) {
2563 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2564 struct radeon_i2c_bus_rec i2c_bus;
2565
2566 rev = RBIOS8(offset);
2567
2568 if (rev == 0) {
2569 thermal_controller = RBIOS8(offset + 3);
2570 gpio = RBIOS8(offset + 4) & 0x3f;
2571 i2c_addr = RBIOS8(offset + 5);
2572 } else if (rev == 1) {
2573 thermal_controller = RBIOS8(offset + 4);
2574 gpio = RBIOS8(offset + 5) & 0x3f;
2575 i2c_addr = RBIOS8(offset + 6);
2576 } else if (rev == 2) {
2577 thermal_controller = RBIOS8(offset + 4);
2578 gpio = RBIOS8(offset + 5) & 0x3f;
2579 i2c_addr = RBIOS8(offset + 6);
2580 clk_bit = RBIOS8(offset + 0xa);
2581 data_bit = RBIOS8(offset + 0xb);
2582 }
2583 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2584 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2585 thermal_controller_names[thermal_controller],
2586 i2c_addr >> 1);
2587 if (gpio == DDC_LCD) {
2588 /* MM i2c */
2589 i2c_bus.valid = true;
2590 i2c_bus.hw_capable = true;
2591 i2c_bus.mm_i2c = true;
2592 i2c_bus.i2c_id = 0xa0;
2593 } else if (gpio == DDC_GPIO)
2594 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2595 else
2596 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2597 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2598 if (rdev->pm.i2c_bus) {
2599 struct i2c_board_info info = { };
2600 const char *name = thermal_controller_names[thermal_controller];
2601 info.addr = i2c_addr >> 1;
2602 strlcpy(info.type, name, sizeof(info.type));
2603 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2604 }
2605 }
2606 }
2607
56278a8e
AD		 2608 if (rdev->flags & RADEON_IS_MOBILITY) {
2609 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2610 if (offset) {
2611 rev = RBIOS8(offset);
2612 blocks = RBIOS8(offset + 0x2);
2613 /* power mode 0 tends to be the only valid one */
2614 rdev->pm.power_state[state_index].num_clock_modes = 1;
2615 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2616 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2617 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2618 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2619 goto default_mode;
0ec0e74f
AD		 2620 rdev->pm.power_state[state_index].type =
2621 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2622 misc = RBIOS16(offset + 0x5 + 0x0);
2623 if (rev > 4)
2624 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2625 rdev->pm.power_state[state_index].misc = misc;
2626 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2627 if (misc & 0x4) {
2628 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2629 if (misc & 0x8)
2630 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2631 true;
2632 else
2633 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2634 false;
2635 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2636 if (rev < 6) {
2637 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2638 RBIOS16(offset + 0x5 + 0xb) * 4;
2639 tmp = RBIOS8(offset + 0x5 + 0xd);
2640 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2641 } else {
2642 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2643 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2644 if (entries && voltage_table_offset) {
2645 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2646 RBIOS16(voltage_table_offset) * 4;
2647 tmp = RBIOS8(voltage_table_offset + 0x2);
2648 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2649 } else
2650 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2651 }
2652 switch ((misc2 & 0x700) >> 8) {
2653 case 0:
2654 default:
2655 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2656 break;
2657 case 1:
2658 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2659 break;
2660 case 2:
2661 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2662 break;
2663 case 3:
2664 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2665 break;
2666 case 4:
2667 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2668 break;
2669 }
2670 } else
2671 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2672 if (rev > 6)
79daedc9 2673 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2674 RBIOS8(offset + 0x5 + 0x10);
d7311171 2675 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2676 state_index++;
2677 } else {
2678 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2679 }
2680 } else {
2681 /* XXX figure out some good default low power mode for desktop cards */
2682 }
2683
2684default_mode:
2685 /* add the default mode */
0ec0e74f
AD		 2686 rdev->pm.power_state[state_index].type =
2687 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2688 rdev->pm.power_state[state_index].num_clock_modes = 1;
2689 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2690 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2691 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2692 if ((state_index > 0) &&
8de016e2 2693 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2694 rdev->pm.power_state[state_index].clock_info[0].voltage =
2695 rdev->pm.power_state[0].clock_info[0].voltage;
2696 else
2697 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2698 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2699 rdev->pm.power_state[state_index].flags = 0;
2700 rdev->pm.default_power_state_index = state_index;
56278a8e 2701 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2702
a48b9b4e
AD		 2703 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2704 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2705}
2706
fcec570b
AD		 2707void radeon_external_tmds_setup(struct drm_encoder *encoder)
2708{
2709 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2710 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2711
2712 if (!tmds)
2713 return;
2714
2715 switch (tmds->dvo_chip) {
2716 case DVO_SIL164:
2717 /* sil 164 */
5a6f98f5
AD		 2718 radeon_i2c_put_byte(tmds->i2c_bus,
2719 tmds->slave_addr,
2720 0x08, 0x30);
2721 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2722 tmds->slave_addr,
2723 0x09, 0x00);
5a6f98f5
AD		 2724 radeon_i2c_put_byte(tmds->i2c_bus,
2725 tmds->slave_addr,
2726 0x0a, 0x90);
2727 radeon_i2c_put_byte(tmds->i2c_bus,
2728 tmds->slave_addr,
2729 0x0c, 0x89);
2730 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2731 tmds->slave_addr,
2732 0x08, 0x3b);
fcec570b
AD		 2733 break;
2734 case DVO_SIL1178:
2735 /* sil 1178 - untested */
2736 /*
2737 * 0x0f, 0x44
2738 * 0x0f, 0x4c
2739 * 0x0e, 0x01
2740 * 0x0a, 0x80
2741 * 0x09, 0x30
2742 * 0x0c, 0xc9
2743 * 0x0d, 0x70
2744 * 0x08, 0x32
2745 * 0x08, 0x33
2746 */
2747 break;
2748 default:
2749 break;
2750 }
2751
2752}
2753
2754bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2755{
2756 struct drm_device *dev = encoder->dev;
2757 struct radeon_device *rdev = dev->dev_private;
2758 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2759 uint16_t offset;
2760 uint8_t blocks, slave_addr, rev;
2761 uint32_t index, id;
2762 uint32_t reg, val, and_mask, or_mask;
2763 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2764
fcec570b
AD		 2765 if (!tmds)
2766 return false;
2767
2768 if (rdev->flags & RADEON_IS_IGP) {
2769 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2770 rev = RBIOS8(offset);
2771 if (offset) {
2772 rev = RBIOS8(offset);
2773 if (rev > 1) {
2774 blocks = RBIOS8(offset + 3);
2775 index = offset + 4;
2776 while (blocks > 0) {
2777 id = RBIOS16(index);
2778 index += 2;
2779 switch (id >> 13) {
2780 case 0:
2781 reg = (id & 0x1fff) * 4;
2782 val = RBIOS32(index);
2783 index += 4;
2784 WREG32(reg, val);
2785 break;
2786 case 2:
2787 reg = (id & 0x1fff) * 4;
2788 and_mask = RBIOS32(index);
2789 index += 4;
2790 or_mask = RBIOS32(index);
2791 index += 4;
2792 val = RREG32(reg);
2793 val = (val & and_mask) | or_mask;
2794 WREG32(reg, val);
2795 break;
2796 case 3:
2797 val = RBIOS16(index);
2798 index += 2;
2799 udelay(val);
2800 break;
2801 case 4:
2802 val = RBIOS16(index);
2803 index += 2;
2804 udelay(val * 1000);
2805 break;
2806 case 6:
2807 slave_addr = id & 0xff;
2808 slave_addr >>= 1; /* 7 bit addressing */
2809 index++;
2810 reg = RBIOS8(index);
2811 index++;
2812 val = RBIOS8(index);
2813 index++;
5a6f98f5
AD		 2814 radeon_i2c_put_byte(tmds->i2c_bus,
2815 slave_addr,
2816 reg, val);
fcec570b
AD		 2817 break;
2818 default:
2819 DRM_ERROR("Unknown id %d\n", id >> 13);
2820 break;
2821 }
2822 blocks--;
2823 }
2824 return true;
2825 }
2826 }
2827 } else {
2828 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2829 if (offset) {
2830 index = offset + 10;
2831 id = RBIOS16(index);
2832 while (id != 0xffff) {
2833 index += 2;
2834 switch (id >> 13) {
2835 case 0:
2836 reg = (id & 0x1fff) * 4;
2837 val = RBIOS32(index);
2838 WREG32(reg, val);
2839 break;
2840 case 2:
2841 reg = (id & 0x1fff) * 4;
2842 and_mask = RBIOS32(index);
2843 index += 4;
2844 or_mask = RBIOS32(index);
2845 index += 4;
2846 val = RREG32(reg);
2847 val = (val & and_mask) | or_mask;
2848 WREG32(reg, val);
2849 break;
2850 case 4:
2851 val = RBIOS16(index);
2852 index += 2;
2853 udelay(val);
2854 break;
2855 case 5:
2856 reg = id & 0x1fff;
2857 and_mask = RBIOS32(index);
2858 index += 4;
2859 or_mask = RBIOS32(index);
2860 index += 4;
2861 val = RREG32_PLL(reg);
2862 val = (val & and_mask) | or_mask;
2863 WREG32_PLL(reg, val);
2864 break;
2865 case 6:
2866 reg = id & 0x1fff;
2867 val = RBIOS8(index);
2868 index += 1;
5a6f98f5
AD		 2869 radeon_i2c_put_byte(tmds->i2c_bus,
2870 tmds->slave_addr,
2871 reg, val);
fcec570b
AD		 2872 break;
2873 default:
2874 DRM_ERROR("Unknown id %d\n", id >> 13);
2875 break;
2876 }
2877 id = RBIOS16(index);
2878 }
2879 return true;
2880 }
2881 }
2882 return false;
2883}
2884
771fe6b9
JG		 2885static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2886{
2887 struct radeon_device *rdev = dev->dev_private;
2888
2889 if (offset) {
2890 while (RBIOS16(offset)) {
2891 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2892 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2893 uint32_t val, and_mask, or_mask;
2894 uint32_t tmp;
2895
2896 offset += 2;
2897 switch (cmd) {
2898 case 0:
2899 val = RBIOS32(offset);
2900 offset += 4;
2901 WREG32(addr, val);
2902 break;
2903 case 1:
2904 val = RBIOS32(offset);
2905 offset += 4;
2906 WREG32(addr, val);
2907 break;
2908 case 2:
2909 and_mask = RBIOS32(offset);
2910 offset += 4;
2911 or_mask = RBIOS32(offset);
2912 offset += 4;
2913 tmp = RREG32(addr);
2914 tmp &= and_mask;
2915 tmp |= or_mask;
2916 WREG32(addr, tmp);
2917 break;
2918 case 3:
2919 and_mask = RBIOS32(offset);
2920 offset += 4;
2921 or_mask = RBIOS32(offset);
2922 offset += 4;
2923 tmp = RREG32(addr);
2924 tmp &= and_mask;
2925 tmp |= or_mask;
2926 WREG32(addr, tmp);
2927 break;
2928 case 4:
2929 val = RBIOS16(offset);
2930 offset += 2;
2931 udelay(val);
2932 break;
2933 case 5:
2934 val = RBIOS16(offset);
2935 offset += 2;
2936 switch (addr) {
2937 case 8:
2938 while (val--) {
2939 if (!
2940 (RREG32_PLL
2941 (RADEON_CLK_PWRMGT_CNTL) &
2942 RADEON_MC_BUSY))
2943 break;
2944 }
2945 break;
2946 case 9:
2947 while (val--) {
2948 if ((RREG32(RADEON_MC_STATUS) &
2949 RADEON_MC_IDLE))
2950 break;
2951 }
2952 break;
2953 default:
2954 break;
2955 }
2956 break;
2957 default:
2958 break;
2959 }
2960 }
2961 }
2962}
2963
2964static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2965{
2966 struct radeon_device *rdev = dev->dev_private;
2967
2968 if (offset) {
2969 while (RBIOS8(offset)) {
2970 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2971 uint8_t addr = (RBIOS8(offset) & 0x3f);
2972 uint32_t val, shift, tmp;
2973 uint32_t and_mask, or_mask;
2974
2975 offset++;
2976 switch (cmd) {
2977 case 0:
2978 val = RBIOS32(offset);
2979 offset += 4;
2980 WREG32_PLL(addr, val);
2981 break;
2982 case 1:
2983 shift = RBIOS8(offset) * 8;
2984 offset++;
2985 and_mask = RBIOS8(offset) << shift;
2986 and_mask |= ~(0xff << shift);
2987 offset++;
2988 or_mask = RBIOS8(offset) << shift;
2989 offset++;
2990 tmp = RREG32_PLL(addr);
2991 tmp &= and_mask;
2992 tmp |= or_mask;
2993 WREG32_PLL(addr, tmp);
2994 break;
2995 case 2:
2996 case 3:
2997 tmp = 1000;
2998 switch (addr) {
2999 case 1:
3000 udelay(150);
3001 break;
3002 case 2:
3003 udelay(1000);
3004 break;
3005 case 3:
3006 while (tmp--) {
3007 if (!
3008 (RREG32_PLL
3009 (RADEON_CLK_PWRMGT_CNTL) &
3010 RADEON_MC_BUSY))
3011 break;
3012 }
3013 break;
3014 case 4:
3015 while (tmp--) {
3016 if (RREG32_PLL
3017 (RADEON_CLK_PWRMGT_CNTL) &
3018 RADEON_DLL_READY)
3019 break;
3020 }
3021 break;
3022 case 5:
3023 tmp =
3024 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3025 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3026#if 0
3027 uint32_t mclk_cntl =
3028 RREG32_PLL
3029 (RADEON_MCLK_CNTL);
3030 mclk_cntl &= 0xffff0000;
3031 /*mclk_cntl |= 0x00001111;*//* ??? */
3032 WREG32_PLL(RADEON_MCLK_CNTL,
3033 mclk_cntl);
3034 udelay(10000);
3035#endif
3036 WREG32_PLL
3037 (RADEON_CLK_PWRMGT_CNTL,
3038 tmp &
3039 ~RADEON_CG_NO1_DEBUG_0);
3040 udelay(10000);
3041 }
3042 break;
3043 default:
3044 break;
3045 }
3046 break;
3047 default:
3048 break;
3049 }
3050 }
3051 }
3052}
3053
3054static void combios_parse_ram_reset_table(struct drm_device *dev,
3055 uint16_t offset)
3056{
3057 struct radeon_device *rdev = dev->dev_private;
3058 uint32_t tmp;
3059
3060 if (offset) {
3061 uint8_t val = RBIOS8(offset);
3062 while (val != 0xff) {
3063 offset++;
3064
3065 if (val == 0x0f) {
3066 uint32_t channel_complete_mask;
3067
3068 if (ASIC_IS_R300(rdev))
3069 channel_complete_mask =
3070 R300_MEM_PWRUP_COMPLETE;
3071 else
3072 channel_complete_mask =
3073 RADEON_MEM_PWRUP_COMPLETE;
3074 tmp = 20000;
3075 while (tmp--) {
3076 if ((RREG32(RADEON_MEM_STR_CNTL) &
3077 channel_complete_mask) ==
3078 channel_complete_mask)
3079 break;
3080 }
3081 } else {
3082 uint32_t or_mask = RBIOS16(offset);
3083 offset += 2;
3084
3085 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3086 tmp &= RADEON_SDRAM_MODE_MASK;
3087 tmp |= or_mask;
3088 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3089
3090 or_mask = val << 24;
3091 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3092 tmp &= RADEON_B3MEM_RESET_MASK;
3093 tmp |= or_mask;
3094 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3095 }
3096 val = RBIOS8(offset);
3097 }
3098 }
3099}
3100
3101static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3102 int mem_addr_mapping)
3103{
3104 struct radeon_device *rdev = dev->dev_private;
3105 uint32_t mem_cntl;
3106 uint32_t mem_size;
3107 uint32_t addr = 0;
3108
3109 mem_cntl = RREG32(RADEON_MEM_CNTL);
3110 if (mem_cntl & RV100_HALF_MODE)
3111 ram /= 2;
3112 mem_size = ram;
3113 mem_cntl &= ~(0xff << 8);
3114 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3115 WREG32(RADEON_MEM_CNTL, mem_cntl);
3116 RREG32(RADEON_MEM_CNTL);
3117
3118 /* sdram reset ? */
3119
3120 /* something like this???? */
3121 while (ram--) {
3122 addr = ram * 1024 * 1024;
3123 /* write to each page */
3124 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3125 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3126 /* read back and verify */
3127 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3128 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3129 return 0;
3130 }
3131
3132 return mem_size;
3133}
3134
3135static void combios_write_ram_size(struct drm_device *dev)
3136{
3137 struct radeon_device *rdev = dev->dev_private;
3138 uint8_t rev;
3139 uint16_t offset;
3140 uint32_t mem_size = 0;
3141 uint32_t mem_cntl = 0;
3142
3143 /* should do something smarter here I guess... */
3144 if (rdev->flags & RADEON_IS_IGP)
3145 return;
3146
3147 /* first check detected mem table */
3148 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3149 if (offset) {
3150 rev = RBIOS8(offset);
3151 if (rev < 3) {
3152 mem_cntl = RBIOS32(offset + 1);
3153 mem_size = RBIOS16(offset + 5);
4ce9198e
AD		 3154 if ((rdev->family < CHIP_R200) &&
3155 !ASIC_IS_RN50(rdev))
771fe6b9
JG		 3156 WREG32(RADEON_MEM_CNTL, mem_cntl);
3157 }
3158 }
3159
3160 if (!mem_size) {
3161 offset =
3162 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3163 if (offset) {
3164 rev = RBIOS8(offset - 1);
3165 if (rev < 1) {
4ce9198e
AD		 3166 if ((rdev->family < CHIP_R200)
3167 && !ASIC_IS_RN50(rdev)) {
771fe6b9
JG		 3168 int ram = 0;
3169 int mem_addr_mapping = 0;
3170
3171 while (RBIOS8(offset)) {
3172 ram = RBIOS8(offset);
3173 mem_addr_mapping =
3174 RBIOS8(offset + 1);
3175 if (mem_addr_mapping != 0x25)
3176 ram *= 2;
3177 mem_size =
3178 combios_detect_ram(dev, ram,
3179 mem_addr_mapping);
3180 if (mem_size)
3181 break;
3182 offset += 2;
3183 }
3184 } else
3185 mem_size = RBIOS8(offset);
3186 } else {
3187 mem_size = RBIOS8(offset);
3188 mem_size *= 2; /* convert to MB */
3189 }
3190 }
3191 }
3192
3193 mem_size *= (1024 * 1024); /* convert to bytes */
3194 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3195}
3196
3197void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3198{
3199 uint16_t dyn_clk_info =
3200 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3201
3202 if (dyn_clk_info)
3203 combios_parse_pll_table(dev, dyn_clk_info);
3204}
3205
3206void radeon_combios_asic_init(struct drm_device *dev)
3207{
3208 struct radeon_device *rdev = dev->dev_private;
3209 uint16_t table;
3210
3211 /* port hardcoded mac stuff from radeonfb */
3212 if (rdev->bios == NULL)
3213 return;
3214
3215 /* ASIC INIT 1 */
3216 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3217 if (table)
3218 combios_parse_mmio_table(dev, table);
3219
3220 /* PLL INIT */
3221 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3222 if (table)
3223 combios_parse_pll_table(dev, table);
3224
3225 /* ASIC INIT 2 */
3226 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3227 if (table)
3228 combios_parse_mmio_table(dev, table);
3229
3230 if (!(rdev->flags & RADEON_IS_IGP)) {
3231 /* ASIC INIT 4 */
3232 table =
3233 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3234 if (table)
3235 combios_parse_mmio_table(dev, table);
3236
3237 /* RAM RESET */
3238 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3239 if (table)
3240 combios_parse_ram_reset_table(dev, table);
3241
3242 /* ASIC INIT 3 */
3243 table =
3244 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3245 if (table)
3246 combios_parse_mmio_table(dev, table);
3247
3248 /* write CONFIG_MEMSIZE */
3249 combios_write_ram_size(dev);
3250 }
3251
580b4fff
DA		 3252 /* quirk for rs4xx HP nx6125 laptop to make it resume
3253 * - it hangs on resume inside the dynclk 1 table.
3254 */
3255 if (rdev->family == CHIP_RS480 &&
3256 rdev->pdev->subsystem_vendor == 0x103c &&
3257 rdev->pdev->subsystem_device == 0x308b)
3258 return;
3259
52fa2bbc
AD		 3260 /* quirk for rs4xx HP dv5000 laptop to make it resume
3261 * - it hangs on resume inside the dynclk 1 table.
3262 */
3263 if (rdev->family == CHIP_RS480 &&
3264 rdev->pdev->subsystem_vendor == 0x103c &&
3265 rdev->pdev->subsystem_device == 0x30a4)
3266 return;
3267
771fe6b9
JG		 3268 /* DYN CLK 1 */
3269 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3270 if (table)
3271 combios_parse_pll_table(dev, table);
3272
3273}
3274
3275void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3276{
3277 struct radeon_device *rdev = dev->dev_private;
3278 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3279
3280 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3281 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3282 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3283
3284 /* let the bios control the backlight */
3285 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3286
3287 /* tell the bios not to handle mode switching */
3288 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3289 RADEON_ACC_MODE_CHANGE);
3290
3291 /* tell the bios a driver is loaded */
3292 bios_7_scratch |= RADEON_DRV_LOADED;
3293
3294 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3295 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3296 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3297}
3298
3299void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3300{
3301 struct drm_device *dev = encoder->dev;
3302 struct radeon_device *rdev = dev->dev_private;
3303 uint32_t bios_6_scratch;
3304
3305 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3306
3307 if (lock)
3308 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3309 else
3310 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3311
3312 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3313}
3314
3315void
3316radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3317 struct drm_encoder *encoder,
3318 bool connected)
3319{
3320 struct drm_device *dev = connector->dev;
3321 struct radeon_device *rdev = dev->dev_private;
3322 struct radeon_connector *radeon_connector =
3323 to_radeon_connector(connector);
3324 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3325 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3326 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3327
3328 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3329 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3330 if (connected) {
d9fdaafb 3331 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3332 /* fix me */
3333 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3334 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3335 bios_5_scratch |= RADEON_TV1_ON;
3336 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3337 } else {
d9fdaafb 3338 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3339 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3340 bios_5_scratch &= ~RADEON_TV1_ON;
3341 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3342 }
3343 }
3344 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3345 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3346 if (connected) {
d9fdaafb 3347 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3348 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3349 bios_5_scratch |= RADEON_LCD1_ON;
3350 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3351 } else {
d9fdaafb 3352 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3353 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3354 bios_5_scratch &= ~RADEON_LCD1_ON;
3355 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3356 }
3357 }
3358 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3359 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3360 if (connected) {
d9fdaafb 3361 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3362 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3363 bios_5_scratch |= RADEON_CRT1_ON;
3364 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3365 } else {
d9fdaafb 3366 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3367 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3368 bios_5_scratch &= ~RADEON_CRT1_ON;
3369 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3370 }
3371 }
3372 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3373 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3374 if (connected) {
d9fdaafb 3375 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3376 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3377 bios_5_scratch |= RADEON_CRT2_ON;
3378 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3379 } else {
d9fdaafb 3380 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3381 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3382 bios_5_scratch &= ~RADEON_CRT2_ON;
3383 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3384 }
3385 }
3386 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3387 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3388 if (connected) {
d9fdaafb 3389 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3390 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3391 bios_5_scratch |= RADEON_DFP1_ON;
3392 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3393 } else {
d9fdaafb 3394 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3395 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3396 bios_5_scratch &= ~RADEON_DFP1_ON;
3397 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3398 }
3399 }
3400 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3401 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3402 if (connected) {
d9fdaafb 3403 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3404 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3405 bios_5_scratch |= RADEON_DFP2_ON;
3406 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3407 } else {
d9fdaafb 3408 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3409 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3410 bios_5_scratch &= ~RADEON_DFP2_ON;
3411 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3412 }
3413 }
3414 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3415 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3416}
3417
3418void
3419radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3420{
3421 struct drm_device *dev = encoder->dev;
3422 struct radeon_device *rdev = dev->dev_private;
3423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3424 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3425
3426 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3427 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3428 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3429 }
3430 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3431 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3432 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3433 }
3434 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3435 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3436 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3437 }
3438 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3439 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3440 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3441 }
3442 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3443 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3444 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3445 }
3446 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3447 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3448 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3449 }
3450 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3451}
3452
3453void
3454radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3455{
3456 struct drm_device *dev = encoder->dev;
3457 struct radeon_device *rdev = dev->dev_private;
3458 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3459 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3460
3461 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3462 if (on)
3463 bios_6_scratch |= RADEON_TV_DPMS_ON;
3464 else
3465 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3466 }
3467 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3468 if (on)
3469 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3470 else
3471 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3472 }
3473 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3474 if (on)
3475 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3476 else
3477 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3478 }
3479 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3480 if (on)
3481 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3482 else
3483 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3484 }
3485 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3486}
Linux kernel - Deliverables
This page took 0.340768 seconds and 5 git commands to generate.