Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | |
31 | ||
1109ca09 | 32 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
771fe6b9 JG |
33 | { |
34 | struct drm_device *ddev = p->rdev->ddev; | |
35 | struct radeon_cs_chunk *chunk; | |
36 | unsigned i, j; | |
37 | bool duplicate; | |
38 | ||
39 | if (p->chunk_relocs_idx == -1) { | |
40 | return 0; | |
41 | } | |
42 | chunk = &p->chunks[p->chunk_relocs_idx]; | |
cf4ccd01 | 43 | p->dma_reloc_idx = 0; |
771fe6b9 JG |
44 | /* FIXME: we assume that each relocs use 4 dwords */ |
45 | p->nrelocs = chunk->length_dw / 4; | |
46 | p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); | |
47 | if (p->relocs_ptr == NULL) { | |
48 | return -ENOMEM; | |
49 | } | |
50 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); | |
51 | if (p->relocs == NULL) { | |
52 | return -ENOMEM; | |
53 | } | |
54 | for (i = 0; i < p->nrelocs; i++) { | |
55 | struct drm_radeon_cs_reloc *r; | |
56 | ||
57 | duplicate = false; | |
58 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; | |
16557f1e | 59 | for (j = 0; j < i; j++) { |
771fe6b9 JG |
60 | if (r->handle == p->relocs[j].handle) { |
61 | p->relocs_ptr[i] = &p->relocs[j]; | |
62 | duplicate = true; | |
63 | break; | |
64 | } | |
65 | } | |
4474f3a9 | 66 | if (duplicate) { |
16557f1e | 67 | p->relocs[i].handle = 0; |
4474f3a9 CK |
68 | continue; |
69 | } | |
70 | ||
71 | p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, | |
72 | r->handle); | |
73 | if (p->relocs[i].gobj == NULL) { | |
74 | DRM_ERROR("gem object lookup failed 0x%x\n", | |
75 | r->handle); | |
76 | return -ENOENT; | |
77 | } | |
78 | p->relocs_ptr[i] = &p->relocs[i]; | |
79 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); | |
80 | p->relocs[i].lobj.bo = p->relocs[i].robj; | |
81 | p->relocs[i].lobj.written = !!r->write_domain; | |
82 | ||
f2ba57b5 CK |
83 | /* the first reloc of an UVD job is the |
84 | msg and that must be in VRAM */ | |
85 | if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) { | |
86 | /* TODO: is this still needed for NI+ ? */ | |
87 | p->relocs[i].lobj.domain = | |
88 | RADEON_GEM_DOMAIN_VRAM; | |
89 | ||
90 | p->relocs[i].lobj.alt_domain = | |
91 | RADEON_GEM_DOMAIN_VRAM; | |
92 | ||
93 | } else { | |
94 | uint32_t domain = r->write_domain ? | |
95 | r->write_domain : r->read_domains; | |
96 | ||
97 | p->relocs[i].lobj.domain = domain; | |
98 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
99 | domain |= RADEON_GEM_DOMAIN_GTT; | |
100 | p->relocs[i].lobj.alt_domain = domain; | |
101 | } | |
4474f3a9 CK |
102 | |
103 | p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; | |
104 | p->relocs[i].handle = r->handle; | |
105 | ||
106 | radeon_bo_list_add_object(&p->relocs[i].lobj, | |
107 | &p->validated); | |
771fe6b9 | 108 | } |
f2ba57b5 | 109 | return radeon_bo_list_validate(&p->validated, p->ring); |
771fe6b9 JG |
110 | } |
111 | ||
721604a1 JG |
112 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
113 | { | |
114 | p->priority = priority; | |
115 | ||
116 | switch (ring) { | |
117 | default: | |
118 | DRM_ERROR("unknown ring id: %d\n", ring); | |
119 | return -EINVAL; | |
120 | case RADEON_CS_RING_GFX: | |
121 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
122 | break; | |
123 | case RADEON_CS_RING_COMPUTE: | |
8d5ef7b1 AD |
124 | if (p->rdev->family >= CHIP_TAHITI) { |
125 | if (p->priority > 0) | |
126 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; | |
127 | else | |
128 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; | |
129 | } else | |
130 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
721604a1 | 131 | break; |
278a334c AD |
132 | case RADEON_CS_RING_DMA: |
133 | if (p->rdev->family >= CHIP_CAYMAN) { | |
134 | if (p->priority > 0) | |
135 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
136 | else | |
137 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; | |
138 | } else if (p->rdev->family >= CHIP_R600) { | |
139 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
140 | } else { | |
141 | return -EINVAL; | |
142 | } | |
143 | break; | |
f2ba57b5 CK |
144 | case RADEON_CS_RING_UVD: |
145 | p->ring = R600_RING_TYPE_UVD_INDEX; | |
146 | break; | |
721604a1 JG |
147 | } |
148 | return 0; | |
149 | } | |
150 | ||
220907d9 | 151 | static void radeon_cs_sync_rings(struct radeon_cs_parser *p) |
93504fce | 152 | { |
220907d9 | 153 | int i; |
93504fce | 154 | |
cdac5504 | 155 | for (i = 0; i < p->nrelocs; i++) { |
f82cbddd | 156 | if (!p->relocs[i].robj) |
cdac5504 CK |
157 | continue; |
158 | ||
43f1214a | 159 | radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj); |
8f676c4c | 160 | } |
93504fce CK |
161 | } |
162 | ||
9b00147d | 163 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
771fe6b9 JG |
164 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
165 | { | |
166 | struct drm_radeon_cs *cs = data; | |
167 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
168 | unsigned size, i; |
169 | u32 ring = RADEON_CS_RING_GFX; | |
170 | s32 priority = 0; | |
771fe6b9 JG |
171 | |
172 | if (!cs->num_chunks) { | |
173 | return 0; | |
174 | } | |
175 | /* get chunks */ | |
176 | INIT_LIST_HEAD(&p->validated); | |
177 | p->idx = 0; | |
f2e39221 JG |
178 | p->ib.sa_bo = NULL; |
179 | p->ib.semaphore = NULL; | |
180 | p->const_ib.sa_bo = NULL; | |
181 | p->const_ib.semaphore = NULL; | |
771fe6b9 JG |
182 | p->chunk_ib_idx = -1; |
183 | p->chunk_relocs_idx = -1; | |
721604a1 | 184 | p->chunk_flags_idx = -1; |
dfcf5f36 | 185 | p->chunk_const_ib_idx = -1; |
771fe6b9 JG |
186 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
187 | if (p->chunks_array == NULL) { | |
188 | return -ENOMEM; | |
189 | } | |
190 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
191 | if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, | |
192 | sizeof(uint64_t)*cs->num_chunks)) { | |
193 | return -EFAULT; | |
194 | } | |
721604a1 | 195 | p->cs_flags = 0; |
771fe6b9 JG |
196 | p->nchunks = cs->num_chunks; |
197 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
198 | if (p->chunks == NULL) { | |
199 | return -ENOMEM; | |
200 | } | |
201 | for (i = 0; i < p->nchunks; i++) { | |
202 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
203 | struct drm_radeon_cs_chunk user_chunk; | |
204 | uint32_t __user *cdata; | |
205 | ||
206 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
207 | if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, | |
208 | sizeof(struct drm_radeon_cs_chunk))) { | |
209 | return -EFAULT; | |
210 | } | |
5176fdc4 DA |
211 | p->chunks[i].length_dw = user_chunk.length_dw; |
212 | p->chunks[i].kdata = NULL; | |
771fe6b9 | 213 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
580f8398 | 214 | p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; |
771fe6b9 JG |
215 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { |
216 | p->chunk_relocs_idx = i; | |
217 | } | |
218 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
219 | p->chunk_ib_idx = i; | |
5176fdc4 DA |
220 | /* zero length IB isn't useful */ |
221 | if (p->chunks[i].length_dw == 0) | |
222 | return -EINVAL; | |
771fe6b9 | 223 | } |
dfcf5f36 AD |
224 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
225 | p->chunk_const_ib_idx = i; | |
226 | /* zero length CONST IB isn't useful */ | |
227 | if (p->chunks[i].length_dw == 0) | |
228 | return -EINVAL; | |
229 | } | |
721604a1 JG |
230 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
231 | p->chunk_flags_idx = i; | |
232 | /* zero length flags aren't useful */ | |
233 | if (p->chunks[i].length_dw == 0) | |
234 | return -EINVAL; | |
e70f224c | 235 | } |
5176fdc4 | 236 | |
513bcb46 | 237 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
721604a1 JG |
238 | if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || |
239 | (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { | |
513bcb46 DA |
240 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
241 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); | |
242 | if (p->chunks[i].kdata == NULL) { | |
243 | return -ENOMEM; | |
244 | } | |
245 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, | |
246 | p->chunks[i].user_ptr, size)) { | |
247 | return -EFAULT; | |
248 | } | |
e70f224c | 249 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
721604a1 JG |
250 | p->cs_flags = p->chunks[i].kdata[0]; |
251 | if (p->chunks[i].length_dw > 1) | |
252 | ring = p->chunks[i].kdata[1]; | |
253 | if (p->chunks[i].length_dw > 2) | |
254 | priority = (s32)p->chunks[i].kdata[2]; | |
e70f224c | 255 | } |
771fe6b9 JG |
256 | } |
257 | } | |
721604a1 | 258 | |
9b00147d AD |
259 | /* these are KMS only */ |
260 | if (p->rdev) { | |
261 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
262 | !p->rdev->vm_manager.enabled) { | |
263 | DRM_ERROR("VM not active on asic!\n"); | |
264 | return -EINVAL; | |
265 | } | |
1b5475db | 266 | |
57449040 | 267 | if (radeon_cs_get_ring(p, ring, priority)) |
9b00147d | 268 | return -EINVAL; |
721604a1 | 269 | |
57449040 CK |
270 | /* we only support VM on some SI+ rings */ |
271 | if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) && | |
272 | ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { | |
273 | DRM_ERROR("Ring %d requires VM!\n", p->ring); | |
9b00147d | 274 | return -EINVAL; |
57449040 | 275 | } |
9b00147d | 276 | } |
721604a1 JG |
277 | |
278 | /* deal with non-vm */ | |
279 | if ((p->chunk_ib_idx != -1) && | |
280 | ((p->cs_flags & RADEON_CS_USE_VM) == 0) && | |
281 | (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { | |
282 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { | |
283 | DRM_ERROR("cs IB too big: %d\n", | |
284 | p->chunks[p->chunk_ib_idx].length_dw); | |
285 | return -EINVAL; | |
286 | } | |
ff4bd082 | 287 | if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { |
6a7068b4 DA |
288 | p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); |
289 | p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
290 | if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || | |
291 | p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { | |
25d89997 IH |
292 | kfree(p->chunks[p->chunk_ib_idx].kpage[0]); |
293 | kfree(p->chunks[p->chunk_ib_idx].kpage[1]); | |
1da80cfa IH |
294 | p->chunks[p->chunk_ib_idx].kpage[0] = NULL; |
295 | p->chunks[p->chunk_ib_idx].kpage[1] = NULL; | |
6a7068b4 DA |
296 | return -ENOMEM; |
297 | } | |
298 | } | |
721604a1 JG |
299 | p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; |
300 | p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; | |
301 | p->chunks[p->chunk_ib_idx].last_copied_page = -1; | |
302 | p->chunks[p->chunk_ib_idx].last_page_index = | |
303 | ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; | |
304 | } | |
305 | ||
771fe6b9 JG |
306 | return 0; |
307 | } | |
308 | ||
309 | /** | |
310 | * cs_parser_fini() - clean parser states | |
311 | * @parser: parser structure holding parsing context. | |
312 | * @error: error number | |
313 | * | |
314 | * If error is set than unvalidate buffer, otherwise just free memory | |
315 | * used by parsing context. | |
316 | **/ | |
317 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |
318 | { | |
319 | unsigned i; | |
320 | ||
e43b5ec0 | 321 | if (!error) { |
147666fb | 322 | ttm_eu_fence_buffer_objects(&parser->validated, |
f2e39221 | 323 | parser->ib.fence); |
e43b5ec0 | 324 | } else { |
147666fb | 325 | ttm_eu_backoff_reservation(&parser->validated); |
e43b5ec0 | 326 | } |
147666fb | 327 | |
fcbc451b PN |
328 | if (parser->relocs != NULL) { |
329 | for (i = 0; i < parser->nrelocs; i++) { | |
330 | if (parser->relocs[i].gobj) | |
331 | drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); | |
332 | } | |
771fe6b9 | 333 | } |
48e113e5 | 334 | kfree(parser->track); |
771fe6b9 JG |
335 | kfree(parser->relocs); |
336 | kfree(parser->relocs_ptr); | |
337 | for (i = 0; i < parser->nchunks; i++) { | |
338 | kfree(parser->chunks[i].kdata); | |
6a7068b4 DA |
339 | if ((parser->rdev->flags & RADEON_IS_AGP)) { |
340 | kfree(parser->chunks[i].kpage[0]); | |
341 | kfree(parser->chunks[i].kpage[1]); | |
342 | } | |
771fe6b9 JG |
343 | } |
344 | kfree(parser->chunks); | |
345 | kfree(parser->chunks_array); | |
346 | radeon_ib_free(parser->rdev, &parser->ib); | |
f2e39221 | 347 | radeon_ib_free(parser->rdev, &parser->const_ib); |
771fe6b9 JG |
348 | } |
349 | ||
721604a1 JG |
350 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
351 | struct radeon_cs_parser *parser) | |
352 | { | |
353 | struct radeon_cs_chunk *ib_chunk; | |
354 | int r; | |
355 | ||
356 | if (parser->chunk_ib_idx == -1) | |
357 | return 0; | |
358 | ||
359 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
360 | return 0; | |
361 | ||
362 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
363 | /* Copy the packet into the IB, the parser will read from the | |
364 | * input memory (cached) and write to the IB (which can be | |
365 | * uncached). | |
366 | */ | |
367 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 368 | NULL, ib_chunk->length_dw * 4); |
721604a1 JG |
369 | if (r) { |
370 | DRM_ERROR("Failed to get ib !\n"); | |
371 | return r; | |
372 | } | |
f2e39221 | 373 | parser->ib.length_dw = ib_chunk->length_dw; |
eb0c19c5 | 374 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
375 | if (r || parser->parser_error) { |
376 | DRM_ERROR("Invalid command stream !\n"); | |
377 | return r; | |
378 | } | |
379 | r = radeon_cs_finish_pages(parser); | |
380 | if (r) { | |
381 | DRM_ERROR("Invalid command stream !\n"); | |
382 | return r; | |
383 | } | |
220907d9 | 384 | radeon_cs_sync_rings(parser); |
4ef72566 | 385 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); |
721604a1 JG |
386 | if (r) { |
387 | DRM_ERROR("Failed to schedule IB !\n"); | |
388 | } | |
93bf888c | 389 | return r; |
721604a1 JG |
390 | } |
391 | ||
392 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, | |
393 | struct radeon_vm *vm) | |
394 | { | |
3e8970f9 | 395 | struct radeon_device *rdev = parser->rdev; |
721604a1 JG |
396 | struct radeon_bo_list *lobj; |
397 | struct radeon_bo *bo; | |
398 | int r; | |
399 | ||
3e8970f9 JG |
400 | r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); |
401 | if (r) { | |
402 | return r; | |
403 | } | |
721604a1 JG |
404 | list_for_each_entry(lobj, &parser->validated, tv.head) { |
405 | bo = lobj->bo; | |
406 | r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); | |
407 | if (r) { | |
408 | return r; | |
409 | } | |
410 | } | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
415 | struct radeon_cs_parser *parser) | |
416 | { | |
417 | struct radeon_cs_chunk *ib_chunk; | |
418 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
419 | struct radeon_vm *vm = &fpriv->vm; | |
420 | int r; | |
421 | ||
422 | if (parser->chunk_ib_idx == -1) | |
423 | return 0; | |
721604a1 JG |
424 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
425 | return 0; | |
426 | ||
dfcf5f36 AD |
427 | if ((rdev->family >= CHIP_TAHITI) && |
428 | (parser->chunk_const_ib_idx != -1)) { | |
429 | ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; | |
430 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
431 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); | |
432 | return -EINVAL; | |
433 | } | |
434 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, | |
4bf3dd92 | 435 | vm, ib_chunk->length_dw * 4); |
dfcf5f36 AD |
436 | if (r) { |
437 | DRM_ERROR("Failed to get const ib !\n"); | |
438 | return r; | |
439 | } | |
f2e39221 JG |
440 | parser->const_ib.is_const_ib = true; |
441 | parser->const_ib.length_dw = ib_chunk->length_dw; | |
dfcf5f36 | 442 | /* Copy the packet into the IB */ |
f2e39221 | 443 | if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, |
dfcf5f36 AD |
444 | ib_chunk->length_dw * 4)) { |
445 | return -EFAULT; | |
446 | } | |
f2e39221 | 447 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
dfcf5f36 AD |
448 | if (r) { |
449 | return r; | |
450 | } | |
451 | } | |
452 | ||
721604a1 JG |
453 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; |
454 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
455 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
456 | return -EINVAL; | |
457 | } | |
458 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 459 | vm, ib_chunk->length_dw * 4); |
721604a1 JG |
460 | if (r) { |
461 | DRM_ERROR("Failed to get ib !\n"); | |
462 | return r; | |
463 | } | |
f2e39221 | 464 | parser->ib.length_dw = ib_chunk->length_dw; |
721604a1 | 465 | /* Copy the packet into the IB */ |
f2e39221 | 466 | if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, |
721604a1 JG |
467 | ib_chunk->length_dw * 4)) { |
468 | return -EFAULT; | |
469 | } | |
f2e39221 | 470 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
721604a1 JG |
471 | if (r) { |
472 | return r; | |
473 | } | |
474 | ||
36ff39c4 | 475 | mutex_lock(&rdev->vm_manager.lock); |
721604a1 | 476 | mutex_lock(&vm->mutex); |
ddf03f5c | 477 | r = radeon_vm_alloc_pt(rdev, vm); |
721604a1 JG |
478 | if (r) { |
479 | goto out; | |
480 | } | |
481 | r = radeon_bo_vm_update_pte(parser, vm); | |
482 | if (r) { | |
483 | goto out; | |
484 | } | |
220907d9 | 485 | radeon_cs_sync_rings(parser); |
43f1214a AD |
486 | radeon_ib_sync_to(&parser->ib, vm->fence); |
487 | radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id( | |
488 | rdev, vm, parser->ring)); | |
4ef72566 | 489 | |
dfcf5f36 AD |
490 | if ((rdev->family >= CHIP_TAHITI) && |
491 | (parser->chunk_const_ib_idx != -1)) { | |
4ef72566 CK |
492 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); |
493 | } else { | |
494 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | |
dfcf5f36 AD |
495 | } |
496 | ||
721604a1 | 497 | if (!r) { |
ee60e29f | 498 | radeon_vm_fence(rdev, vm, parser->ib.fence); |
721604a1 | 499 | } |
ee60e29f CK |
500 | |
501 | out: | |
13e55c38 | 502 | radeon_vm_add_to_lru(rdev, vm); |
36ff39c4 CK |
503 | mutex_unlock(&vm->mutex); |
504 | mutex_unlock(&rdev->vm_manager.lock); | |
721604a1 JG |
505 | return r; |
506 | } | |
507 | ||
6c6f4783 CK |
508 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
509 | { | |
510 | if (r == -EDEADLK) { | |
511 | r = radeon_gpu_reset(rdev); | |
512 | if (!r) | |
513 | r = -EAGAIN; | |
514 | } | |
515 | return r; | |
516 | } | |
517 | ||
771fe6b9 JG |
518 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
519 | { | |
520 | struct radeon_device *rdev = dev->dev_private; | |
521 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
522 | int r; |
523 | ||
dee53e7f | 524 | down_read(&rdev->exclusive_lock); |
6b7746e8 | 525 | if (!rdev->accel_working) { |
dee53e7f | 526 | up_read(&rdev->exclusive_lock); |
6b7746e8 JG |
527 | return -EBUSY; |
528 | } | |
771fe6b9 JG |
529 | /* initialize parser */ |
530 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
531 | parser.filp = filp; | |
532 | parser.rdev = rdev; | |
c8c15ff1 | 533 | parser.dev = rdev->dev; |
428c6e36 | 534 | parser.family = rdev->family; |
771fe6b9 JG |
535 | r = radeon_cs_parser_init(&parser, data); |
536 | if (r) { | |
537 | DRM_ERROR("Failed to initialize parser !\n"); | |
538 | radeon_cs_parser_fini(&parser, r); | |
dee53e7f | 539 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 540 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
541 | return r; |
542 | } | |
771fe6b9 JG |
543 | r = radeon_cs_parser_relocs(&parser); |
544 | if (r) { | |
97f23b3d DA |
545 | if (r != -ERESTARTSYS) |
546 | DRM_ERROR("Failed to parse relocation %d!\n", r); | |
771fe6b9 | 547 | radeon_cs_parser_fini(&parser, r); |
dee53e7f | 548 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 549 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
550 | return r; |
551 | } | |
721604a1 | 552 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 553 | if (r) { |
721604a1 | 554 | goto out; |
771fe6b9 | 555 | } |
721604a1 | 556 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 557 | if (r) { |
721604a1 | 558 | goto out; |
771fe6b9 | 559 | } |
721604a1 | 560 | out: |
771fe6b9 | 561 | radeon_cs_parser_fini(&parser, r); |
dee53e7f | 562 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 563 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
564 | return r; |
565 | } | |
513bcb46 DA |
566 | |
567 | int radeon_cs_finish_pages(struct radeon_cs_parser *p) | |
568 | { | |
569 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
570 | int i; | |
571 | int size = PAGE_SIZE; | |
572 | ||
573 | for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { | |
574 | if (i == ibc->last_page_index) { | |
575 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
576 | if (size == 0) | |
577 | size = PAGE_SIZE; | |
578 | } | |
579 | ||
f2e39221 | 580 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
581 | ibc->user_ptr + (i * PAGE_SIZE), |
582 | size)) | |
583 | return -EFAULT; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | ||
c4c7f314 | 588 | static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) |
513bcb46 DA |
589 | { |
590 | int new_page; | |
513bcb46 DA |
591 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
592 | int i; | |
593 | int size = PAGE_SIZE; | |
ff4bd082 IH |
594 | bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? |
595 | false : true; | |
513bcb46 | 596 | |
c5e617e2 | 597 | for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { |
f2e39221 | 598 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
599 | ibc->user_ptr + (i * PAGE_SIZE), |
600 | PAGE_SIZE)) { | |
601 | p->parser_error = -EFAULT; | |
602 | return 0; | |
603 | } | |
604 | } | |
605 | ||
513bcb46 DA |
606 | if (pg_idx == ibc->last_page_index) { |
607 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
6a7068b4 DA |
608 | if (size == 0) |
609 | size = PAGE_SIZE; | |
513bcb46 DA |
610 | } |
611 | ||
6a7068b4 DA |
612 | new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; |
613 | if (copy1) | |
f2e39221 | 614 | ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); |
6a7068b4 | 615 | |
513bcb46 DA |
616 | if (DRM_COPY_FROM_USER(ibc->kpage[new_page], |
617 | ibc->user_ptr + (pg_idx * PAGE_SIZE), | |
618 | size)) { | |
619 | p->parser_error = -EFAULT; | |
620 | return 0; | |
621 | } | |
622 | ||
6a7068b4 DA |
623 | /* copy to IB for non single case */ |
624 | if (!copy1) | |
f2e39221 | 625 | memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); |
513bcb46 DA |
626 | |
627 | ibc->last_copied_page = pg_idx; | |
628 | ibc->kpage_idx[new_page] = pg_idx; | |
629 | ||
630 | return new_page; | |
631 | } | |
c4c7f314 DA |
632 | |
633 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
634 | { | |
635 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
636 | u32 pg_idx, pg_offset; | |
637 | u32 idx_value = 0; | |
638 | int new_page; | |
639 | ||
640 | pg_idx = (idx * 4) / PAGE_SIZE; | |
641 | pg_offset = (idx * 4) % PAGE_SIZE; | |
642 | ||
643 | if (ibc->kpage_idx[0] == pg_idx) | |
644 | return ibc->kpage[0][pg_offset/4]; | |
645 | if (ibc->kpage_idx[1] == pg_idx) | |
646 | return ibc->kpage[1][pg_offset/4]; | |
647 | ||
648 | new_page = radeon_cs_update_pages(p, pg_idx); | |
649 | if (new_page < 0) { | |
650 | p->parser_error = new_page; | |
651 | return 0; | |
652 | } | |
653 | ||
654 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
655 | return idx_value; | |
656 | } | |
4db01311 IH |
657 | |
658 | /** | |
659 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet | |
660 | * @parser: parser structure holding parsing context. | |
661 | * @pkt: where to store packet information | |
662 | * | |
663 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
664 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
665 | **/ | |
666 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, | |
667 | struct radeon_cs_packet *pkt, | |
668 | unsigned idx) | |
669 | { | |
670 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
671 | struct radeon_device *rdev = p->rdev; | |
672 | uint32_t header; | |
673 | ||
674 | if (idx >= ib_chunk->length_dw) { | |
675 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
676 | idx, ib_chunk->length_dw); | |
677 | return -EINVAL; | |
678 | } | |
679 | header = radeon_get_ib_value(p, idx); | |
680 | pkt->idx = idx; | |
681 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); | |
682 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); | |
683 | pkt->one_reg_wr = 0; | |
684 | switch (pkt->type) { | |
685 | case RADEON_PACKET_TYPE0: | |
686 | if (rdev->family < CHIP_R600) { | |
687 | pkt->reg = R100_CP_PACKET0_GET_REG(header); | |
688 | pkt->one_reg_wr = | |
689 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); | |
690 | } else | |
691 | pkt->reg = R600_CP_PACKET0_GET_REG(header); | |
692 | break; | |
693 | case RADEON_PACKET_TYPE3: | |
694 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); | |
695 | break; | |
696 | case RADEON_PACKET_TYPE2: | |
697 | pkt->count = -1; | |
698 | break; | |
699 | default: | |
700 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
701 | return -EINVAL; | |
702 | } | |
703 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
704 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
705 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
706 | return -EINVAL; | |
707 | } | |
708 | return 0; | |
709 | } | |
9ffb7a6d IH |
710 | |
711 | /** | |
712 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP | |
713 | * @p: structure holding the parser context. | |
714 | * | |
715 | * Check if the next packet is NOP relocation packet3. | |
716 | **/ | |
717 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | |
718 | { | |
719 | struct radeon_cs_packet p3reloc; | |
720 | int r; | |
721 | ||
722 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
723 | if (r) | |
724 | return false; | |
725 | if (p3reloc.type != RADEON_PACKET_TYPE3) | |
726 | return false; | |
727 | if (p3reloc.opcode != RADEON_PACKET3_NOP) | |
728 | return false; | |
729 | return true; | |
730 | } | |
c3ad63af IH |
731 | |
732 | /** | |
733 | * radeon_cs_dump_packet() - dump raw packet context | |
734 | * @p: structure holding the parser context. | |
735 | * @pkt: structure holding the packet. | |
736 | * | |
737 | * Used mostly for debugging and error reporting. | |
738 | **/ | |
739 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, | |
740 | struct radeon_cs_packet *pkt) | |
741 | { | |
742 | volatile uint32_t *ib; | |
743 | unsigned i; | |
744 | unsigned idx; | |
745 | ||
746 | ib = p->ib.ptr; | |
747 | idx = pkt->idx; | |
748 | for (i = 0; i <= (pkt->count + 1); i++, idx++) | |
749 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
750 | } | |
751 | ||
e9716993 IH |
752 | /** |
753 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet | |
754 | * @parser: parser structure holding parsing context. | |
755 | * @data: pointer to relocation data | |
756 | * @offset_start: starting offset | |
757 | * @offset_mask: offset mask (to align start offset on) | |
758 | * @reloc: reloc informations | |
759 | * | |
760 | * Check if next packet is relocation packet3, do bo validation and compute | |
761 | * GPU offset using the provided start. | |
762 | **/ | |
763 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
764 | struct radeon_cs_reloc **cs_reloc, | |
765 | int nomm) | |
766 | { | |
767 | struct radeon_cs_chunk *relocs_chunk; | |
768 | struct radeon_cs_packet p3reloc; | |
769 | unsigned idx; | |
770 | int r; | |
771 | ||
772 | if (p->chunk_relocs_idx == -1) { | |
773 | DRM_ERROR("No relocation chunk !\n"); | |
774 | return -EINVAL; | |
775 | } | |
776 | *cs_reloc = NULL; | |
777 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | |
778 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
779 | if (r) | |
780 | return r; | |
781 | p->idx += p3reloc.count + 2; | |
782 | if (p3reloc.type != RADEON_PACKET_TYPE3 || | |
783 | p3reloc.opcode != RADEON_PACKET3_NOP) { | |
784 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
785 | p3reloc.idx); | |
786 | radeon_cs_dump_packet(p, &p3reloc); | |
787 | return -EINVAL; | |
788 | } | |
789 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | |
790 | if (idx >= relocs_chunk->length_dw) { | |
791 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
792 | idx, relocs_chunk->length_dw); | |
793 | radeon_cs_dump_packet(p, &p3reloc); | |
794 | return -EINVAL; | |
795 | } | |
796 | /* FIXME: we assume reloc size is 4 dwords */ | |
797 | if (nomm) { | |
798 | *cs_reloc = p->relocs; | |
799 | (*cs_reloc)->lobj.gpu_offset = | |
800 | (u64)relocs_chunk->kdata[idx + 3] << 32; | |
801 | (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; | |
802 | } else | |
803 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
804 | return 0; | |
805 | } |