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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | |
860024e5 | 31 | #include "radeon_trace.h" |
771fe6b9 | 32 | |
1109ca09 | 33 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
771fe6b9 JG |
34 | { |
35 | struct drm_device *ddev = p->rdev->ddev; | |
36 | struct radeon_cs_chunk *chunk; | |
37 | unsigned i, j; | |
38 | bool duplicate; | |
39 | ||
40 | if (p->chunk_relocs_idx == -1) { | |
41 | return 0; | |
42 | } | |
43 | chunk = &p->chunks[p->chunk_relocs_idx]; | |
cf4ccd01 | 44 | p->dma_reloc_idx = 0; |
771fe6b9 JG |
45 | /* FIXME: we assume that each relocs use 4 dwords */ |
46 | p->nrelocs = chunk->length_dw / 4; | |
47 | p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); | |
48 | if (p->relocs_ptr == NULL) { | |
49 | return -ENOMEM; | |
50 | } | |
51 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); | |
52 | if (p->relocs == NULL) { | |
53 | return -ENOMEM; | |
54 | } | |
55 | for (i = 0; i < p->nrelocs; i++) { | |
56 | struct drm_radeon_cs_reloc *r; | |
57 | ||
58 | duplicate = false; | |
59 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; | |
16557f1e | 60 | for (j = 0; j < i; j++) { |
771fe6b9 JG |
61 | if (r->handle == p->relocs[j].handle) { |
62 | p->relocs_ptr[i] = &p->relocs[j]; | |
63 | duplicate = true; | |
64 | break; | |
65 | } | |
66 | } | |
4474f3a9 | 67 | if (duplicate) { |
16557f1e | 68 | p->relocs[i].handle = 0; |
4474f3a9 CK |
69 | continue; |
70 | } | |
71 | ||
72 | p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, | |
73 | r->handle); | |
74 | if (p->relocs[i].gobj == NULL) { | |
75 | DRM_ERROR("gem object lookup failed 0x%x\n", | |
76 | r->handle); | |
77 | return -ENOENT; | |
78 | } | |
79 | p->relocs_ptr[i] = &p->relocs[i]; | |
80 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); | |
81 | p->relocs[i].lobj.bo = p->relocs[i].robj; | |
82 | p->relocs[i].lobj.written = !!r->write_domain; | |
83 | ||
4f66c599 CK |
84 | /* the first reloc of an UVD job is the msg and that must be in |
85 | VRAM, also but everything into VRAM on AGP cards to avoid | |
86 | image corruptions */ | |
87 | if (p->ring == R600_RING_TYPE_UVD_INDEX && | |
4b40e592 | 88 | p->rdev->family < CHIP_PALM && |
4ca5a6cb | 89 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { |
4b40e592 | 90 | |
f2ba57b5 CK |
91 | p->relocs[i].lobj.domain = |
92 | RADEON_GEM_DOMAIN_VRAM; | |
93 | ||
94 | p->relocs[i].lobj.alt_domain = | |
95 | RADEON_GEM_DOMAIN_VRAM; | |
96 | ||
97 | } else { | |
98 | uint32_t domain = r->write_domain ? | |
99 | r->write_domain : r->read_domains; | |
100 | ||
101 | p->relocs[i].lobj.domain = domain; | |
102 | if (domain == RADEON_GEM_DOMAIN_VRAM) | |
103 | domain |= RADEON_GEM_DOMAIN_GTT; | |
104 | p->relocs[i].lobj.alt_domain = domain; | |
105 | } | |
4474f3a9 CK |
106 | |
107 | p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; | |
108 | p->relocs[i].handle = r->handle; | |
109 | ||
110 | radeon_bo_list_add_object(&p->relocs[i].lobj, | |
111 | &p->validated); | |
771fe6b9 | 112 | } |
ecff665f | 113 | return radeon_bo_list_validate(&p->ticket, &p->validated, p->ring); |
771fe6b9 JG |
114 | } |
115 | ||
721604a1 JG |
116 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
117 | { | |
118 | p->priority = priority; | |
119 | ||
120 | switch (ring) { | |
121 | default: | |
122 | DRM_ERROR("unknown ring id: %d\n", ring); | |
123 | return -EINVAL; | |
124 | case RADEON_CS_RING_GFX: | |
125 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
126 | break; | |
127 | case RADEON_CS_RING_COMPUTE: | |
963e81f9 | 128 | if (p->rdev->family >= CHIP_TAHITI) { |
8d5ef7b1 AD |
129 | if (p->priority > 0) |
130 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; | |
131 | else | |
132 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; | |
133 | } else | |
134 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
721604a1 | 135 | break; |
278a334c AD |
136 | case RADEON_CS_RING_DMA: |
137 | if (p->rdev->family >= CHIP_CAYMAN) { | |
138 | if (p->priority > 0) | |
139 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
140 | else | |
141 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; | |
142 | } else if (p->rdev->family >= CHIP_R600) { | |
143 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
144 | } else { | |
145 | return -EINVAL; | |
146 | } | |
147 | break; | |
f2ba57b5 CK |
148 | case RADEON_CS_RING_UVD: |
149 | p->ring = R600_RING_TYPE_UVD_INDEX; | |
150 | break; | |
721604a1 JG |
151 | } |
152 | return 0; | |
153 | } | |
154 | ||
220907d9 | 155 | static void radeon_cs_sync_rings(struct radeon_cs_parser *p) |
93504fce | 156 | { |
220907d9 | 157 | int i; |
93504fce | 158 | |
cdac5504 | 159 | for (i = 0; i < p->nrelocs; i++) { |
f82cbddd | 160 | if (!p->relocs[i].robj) |
cdac5504 CK |
161 | continue; |
162 | ||
43f1214a | 163 | radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj); |
8f676c4c | 164 | } |
93504fce CK |
165 | } |
166 | ||
9b00147d | 167 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
771fe6b9 JG |
168 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
169 | { | |
170 | struct drm_radeon_cs *cs = data; | |
171 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
172 | unsigned size, i; |
173 | u32 ring = RADEON_CS_RING_GFX; | |
174 | s32 priority = 0; | |
771fe6b9 JG |
175 | |
176 | if (!cs->num_chunks) { | |
177 | return 0; | |
178 | } | |
179 | /* get chunks */ | |
180 | INIT_LIST_HEAD(&p->validated); | |
181 | p->idx = 0; | |
f2e39221 JG |
182 | p->ib.sa_bo = NULL; |
183 | p->ib.semaphore = NULL; | |
184 | p->const_ib.sa_bo = NULL; | |
185 | p->const_ib.semaphore = NULL; | |
771fe6b9 JG |
186 | p->chunk_ib_idx = -1; |
187 | p->chunk_relocs_idx = -1; | |
721604a1 | 188 | p->chunk_flags_idx = -1; |
dfcf5f36 | 189 | p->chunk_const_ib_idx = -1; |
771fe6b9 JG |
190 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
191 | if (p->chunks_array == NULL) { | |
192 | return -ENOMEM; | |
193 | } | |
194 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
195 | if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, | |
196 | sizeof(uint64_t)*cs->num_chunks)) { | |
197 | return -EFAULT; | |
198 | } | |
721604a1 | 199 | p->cs_flags = 0; |
771fe6b9 JG |
200 | p->nchunks = cs->num_chunks; |
201 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
202 | if (p->chunks == NULL) { | |
203 | return -ENOMEM; | |
204 | } | |
205 | for (i = 0; i < p->nchunks; i++) { | |
206 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
207 | struct drm_radeon_cs_chunk user_chunk; | |
208 | uint32_t __user *cdata; | |
209 | ||
210 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
211 | if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, | |
212 | sizeof(struct drm_radeon_cs_chunk))) { | |
213 | return -EFAULT; | |
214 | } | |
5176fdc4 DA |
215 | p->chunks[i].length_dw = user_chunk.length_dw; |
216 | p->chunks[i].kdata = NULL; | |
771fe6b9 | 217 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
580f8398 | 218 | p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; |
771fe6b9 JG |
219 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { |
220 | p->chunk_relocs_idx = i; | |
221 | } | |
222 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
223 | p->chunk_ib_idx = i; | |
5176fdc4 DA |
224 | /* zero length IB isn't useful */ |
225 | if (p->chunks[i].length_dw == 0) | |
226 | return -EINVAL; | |
771fe6b9 | 227 | } |
dfcf5f36 AD |
228 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
229 | p->chunk_const_ib_idx = i; | |
230 | /* zero length CONST IB isn't useful */ | |
231 | if (p->chunks[i].length_dw == 0) | |
232 | return -EINVAL; | |
233 | } | |
721604a1 JG |
234 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
235 | p->chunk_flags_idx = i; | |
236 | /* zero length flags aren't useful */ | |
237 | if (p->chunks[i].length_dw == 0) | |
238 | return -EINVAL; | |
e70f224c | 239 | } |
5176fdc4 | 240 | |
513bcb46 | 241 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
721604a1 JG |
242 | if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || |
243 | (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { | |
513bcb46 DA |
244 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
245 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); | |
246 | if (p->chunks[i].kdata == NULL) { | |
247 | return -ENOMEM; | |
248 | } | |
249 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, | |
250 | p->chunks[i].user_ptr, size)) { | |
251 | return -EFAULT; | |
252 | } | |
e70f224c | 253 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
721604a1 JG |
254 | p->cs_flags = p->chunks[i].kdata[0]; |
255 | if (p->chunks[i].length_dw > 1) | |
256 | ring = p->chunks[i].kdata[1]; | |
257 | if (p->chunks[i].length_dw > 2) | |
258 | priority = (s32)p->chunks[i].kdata[2]; | |
e70f224c | 259 | } |
771fe6b9 JG |
260 | } |
261 | } | |
721604a1 | 262 | |
9b00147d AD |
263 | /* these are KMS only */ |
264 | if (p->rdev) { | |
265 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
266 | !p->rdev->vm_manager.enabled) { | |
267 | DRM_ERROR("VM not active on asic!\n"); | |
268 | return -EINVAL; | |
269 | } | |
1b5475db | 270 | |
57449040 | 271 | if (radeon_cs_get_ring(p, ring, priority)) |
9b00147d | 272 | return -EINVAL; |
721604a1 | 273 | |
57449040 | 274 | /* we only support VM on some SI+ rings */ |
76a0df85 | 275 | if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) && |
57449040 CK |
276 | ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { |
277 | DRM_ERROR("Ring %d requires VM!\n", p->ring); | |
9b00147d | 278 | return -EINVAL; |
57449040 | 279 | } |
9b00147d | 280 | } |
721604a1 JG |
281 | |
282 | /* deal with non-vm */ | |
283 | if ((p->chunk_ib_idx != -1) && | |
284 | ((p->cs_flags & RADEON_CS_USE_VM) == 0) && | |
285 | (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { | |
286 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { | |
287 | DRM_ERROR("cs IB too big: %d\n", | |
288 | p->chunks[p->chunk_ib_idx].length_dw); | |
289 | return -EINVAL; | |
290 | } | |
ff4bd082 | 291 | if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { |
6a7068b4 DA |
292 | p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); |
293 | p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
294 | if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || | |
295 | p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { | |
25d89997 IH |
296 | kfree(p->chunks[p->chunk_ib_idx].kpage[0]); |
297 | kfree(p->chunks[p->chunk_ib_idx].kpage[1]); | |
1da80cfa IH |
298 | p->chunks[p->chunk_ib_idx].kpage[0] = NULL; |
299 | p->chunks[p->chunk_ib_idx].kpage[1] = NULL; | |
6a7068b4 DA |
300 | return -ENOMEM; |
301 | } | |
302 | } | |
721604a1 JG |
303 | p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; |
304 | p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; | |
305 | p->chunks[p->chunk_ib_idx].last_copied_page = -1; | |
306 | p->chunks[p->chunk_ib_idx].last_page_index = | |
307 | ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; | |
308 | } | |
309 | ||
771fe6b9 JG |
310 | return 0; |
311 | } | |
312 | ||
313 | /** | |
314 | * cs_parser_fini() - clean parser states | |
315 | * @parser: parser structure holding parsing context. | |
316 | * @error: error number | |
317 | * | |
318 | * If error is set than unvalidate buffer, otherwise just free memory | |
319 | * used by parsing context. | |
320 | **/ | |
ecff665f | 321 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) |
771fe6b9 JG |
322 | { |
323 | unsigned i; | |
324 | ||
e43b5ec0 | 325 | if (!error) { |
ecff665f ML |
326 | ttm_eu_fence_buffer_objects(&parser->ticket, |
327 | &parser->validated, | |
f2e39221 | 328 | parser->ib.fence); |
ecff665f ML |
329 | } else if (backoff) { |
330 | ttm_eu_backoff_reservation(&parser->ticket, | |
331 | &parser->validated); | |
e43b5ec0 | 332 | } |
147666fb | 333 | |
fcbc451b PN |
334 | if (parser->relocs != NULL) { |
335 | for (i = 0; i < parser->nrelocs; i++) { | |
336 | if (parser->relocs[i].gobj) | |
337 | drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); | |
338 | } | |
771fe6b9 | 339 | } |
48e113e5 | 340 | kfree(parser->track); |
771fe6b9 JG |
341 | kfree(parser->relocs); |
342 | kfree(parser->relocs_ptr); | |
343 | for (i = 0; i < parser->nchunks; i++) { | |
344 | kfree(parser->chunks[i].kdata); | |
6a7068b4 DA |
345 | if ((parser->rdev->flags & RADEON_IS_AGP)) { |
346 | kfree(parser->chunks[i].kpage[0]); | |
347 | kfree(parser->chunks[i].kpage[1]); | |
348 | } | |
771fe6b9 JG |
349 | } |
350 | kfree(parser->chunks); | |
351 | kfree(parser->chunks_array); | |
352 | radeon_ib_free(parser->rdev, &parser->ib); | |
f2e39221 | 353 | radeon_ib_free(parser->rdev, &parser->const_ib); |
771fe6b9 JG |
354 | } |
355 | ||
721604a1 JG |
356 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
357 | struct radeon_cs_parser *parser) | |
358 | { | |
359 | struct radeon_cs_chunk *ib_chunk; | |
360 | int r; | |
361 | ||
362 | if (parser->chunk_ib_idx == -1) | |
363 | return 0; | |
364 | ||
365 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
366 | return 0; | |
367 | ||
368 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
369 | /* Copy the packet into the IB, the parser will read from the | |
370 | * input memory (cached) and write to the IB (which can be | |
371 | * uncached). | |
372 | */ | |
373 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 374 | NULL, ib_chunk->length_dw * 4); |
721604a1 JG |
375 | if (r) { |
376 | DRM_ERROR("Failed to get ib !\n"); | |
377 | return r; | |
378 | } | |
f2e39221 | 379 | parser->ib.length_dw = ib_chunk->length_dw; |
eb0c19c5 | 380 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
381 | if (r || parser->parser_error) { |
382 | DRM_ERROR("Invalid command stream !\n"); | |
383 | return r; | |
384 | } | |
385 | r = radeon_cs_finish_pages(parser); | |
386 | if (r) { | |
387 | DRM_ERROR("Invalid command stream !\n"); | |
388 | return r; | |
389 | } | |
ce3537d5 AD |
390 | |
391 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) | |
392 | radeon_uvd_note_usage(rdev); | |
393 | ||
220907d9 | 394 | radeon_cs_sync_rings(parser); |
4ef72566 | 395 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); |
721604a1 JG |
396 | if (r) { |
397 | DRM_ERROR("Failed to schedule IB !\n"); | |
398 | } | |
93bf888c | 399 | return r; |
721604a1 JG |
400 | } |
401 | ||
402 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, | |
403 | struct radeon_vm *vm) | |
404 | { | |
3e8970f9 | 405 | struct radeon_device *rdev = parser->rdev; |
721604a1 JG |
406 | struct radeon_bo_list *lobj; |
407 | struct radeon_bo *bo; | |
408 | int r; | |
409 | ||
3e8970f9 JG |
410 | r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); |
411 | if (r) { | |
412 | return r; | |
413 | } | |
721604a1 JG |
414 | list_for_each_entry(lobj, &parser->validated, tv.head) { |
415 | bo = lobj->bo; | |
416 | r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); | |
417 | if (r) { | |
418 | return r; | |
419 | } | |
420 | } | |
421 | return 0; | |
422 | } | |
423 | ||
424 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
425 | struct radeon_cs_parser *parser) | |
426 | { | |
427 | struct radeon_cs_chunk *ib_chunk; | |
428 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
429 | struct radeon_vm *vm = &fpriv->vm; | |
430 | int r; | |
431 | ||
432 | if (parser->chunk_ib_idx == -1) | |
433 | return 0; | |
721604a1 JG |
434 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
435 | return 0; | |
436 | ||
dfcf5f36 AD |
437 | if ((rdev->family >= CHIP_TAHITI) && |
438 | (parser->chunk_const_ib_idx != -1)) { | |
439 | ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; | |
440 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
441 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); | |
442 | return -EINVAL; | |
443 | } | |
444 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, | |
4bf3dd92 | 445 | vm, ib_chunk->length_dw * 4); |
dfcf5f36 AD |
446 | if (r) { |
447 | DRM_ERROR("Failed to get const ib !\n"); | |
448 | return r; | |
449 | } | |
f2e39221 JG |
450 | parser->const_ib.is_const_ib = true; |
451 | parser->const_ib.length_dw = ib_chunk->length_dw; | |
dfcf5f36 | 452 | /* Copy the packet into the IB */ |
f2e39221 | 453 | if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, |
dfcf5f36 AD |
454 | ib_chunk->length_dw * 4)) { |
455 | return -EFAULT; | |
456 | } | |
f2e39221 | 457 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
dfcf5f36 AD |
458 | if (r) { |
459 | return r; | |
460 | } | |
461 | } | |
462 | ||
721604a1 JG |
463 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; |
464 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
465 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
466 | return -EINVAL; | |
467 | } | |
468 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 469 | vm, ib_chunk->length_dw * 4); |
721604a1 JG |
470 | if (r) { |
471 | DRM_ERROR("Failed to get ib !\n"); | |
472 | return r; | |
473 | } | |
f2e39221 | 474 | parser->ib.length_dw = ib_chunk->length_dw; |
721604a1 | 475 | /* Copy the packet into the IB */ |
f2e39221 | 476 | if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, |
721604a1 JG |
477 | ib_chunk->length_dw * 4)) { |
478 | return -EFAULT; | |
479 | } | |
f2e39221 | 480 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
721604a1 JG |
481 | if (r) { |
482 | return r; | |
483 | } | |
484 | ||
ce3537d5 AD |
485 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
486 | radeon_uvd_note_usage(rdev); | |
487 | ||
36ff39c4 | 488 | mutex_lock(&rdev->vm_manager.lock); |
721604a1 | 489 | mutex_lock(&vm->mutex); |
ddf03f5c | 490 | r = radeon_vm_alloc_pt(rdev, vm); |
721604a1 JG |
491 | if (r) { |
492 | goto out; | |
493 | } | |
494 | r = radeon_bo_vm_update_pte(parser, vm); | |
495 | if (r) { | |
496 | goto out; | |
497 | } | |
220907d9 | 498 | radeon_cs_sync_rings(parser); |
43f1214a AD |
499 | radeon_ib_sync_to(&parser->ib, vm->fence); |
500 | radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id( | |
501 | rdev, vm, parser->ring)); | |
4ef72566 | 502 | |
dfcf5f36 AD |
503 | if ((rdev->family >= CHIP_TAHITI) && |
504 | (parser->chunk_const_ib_idx != -1)) { | |
4ef72566 CK |
505 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); |
506 | } else { | |
507 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | |
dfcf5f36 AD |
508 | } |
509 | ||
721604a1 | 510 | if (!r) { |
ee60e29f | 511 | radeon_vm_fence(rdev, vm, parser->ib.fence); |
721604a1 | 512 | } |
ee60e29f CK |
513 | |
514 | out: | |
13e55c38 | 515 | radeon_vm_add_to_lru(rdev, vm); |
36ff39c4 CK |
516 | mutex_unlock(&vm->mutex); |
517 | mutex_unlock(&rdev->vm_manager.lock); | |
721604a1 JG |
518 | return r; |
519 | } | |
520 | ||
6c6f4783 CK |
521 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
522 | { | |
523 | if (r == -EDEADLK) { | |
524 | r = radeon_gpu_reset(rdev); | |
525 | if (!r) | |
526 | r = -EAGAIN; | |
527 | } | |
528 | return r; | |
529 | } | |
530 | ||
771fe6b9 JG |
531 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
532 | { | |
533 | struct radeon_device *rdev = dev->dev_private; | |
534 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
535 | int r; |
536 | ||
dee53e7f | 537 | down_read(&rdev->exclusive_lock); |
6b7746e8 | 538 | if (!rdev->accel_working) { |
dee53e7f | 539 | up_read(&rdev->exclusive_lock); |
6b7746e8 JG |
540 | return -EBUSY; |
541 | } | |
771fe6b9 JG |
542 | /* initialize parser */ |
543 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
544 | parser.filp = filp; | |
545 | parser.rdev = rdev; | |
c8c15ff1 | 546 | parser.dev = rdev->dev; |
428c6e36 | 547 | parser.family = rdev->family; |
771fe6b9 JG |
548 | r = radeon_cs_parser_init(&parser, data); |
549 | if (r) { | |
550 | DRM_ERROR("Failed to initialize parser !\n"); | |
ecff665f | 551 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 552 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 553 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
554 | return r; |
555 | } | |
771fe6b9 JG |
556 | r = radeon_cs_parser_relocs(&parser); |
557 | if (r) { | |
97f23b3d DA |
558 | if (r != -ERESTARTSYS) |
559 | DRM_ERROR("Failed to parse relocation %d!\n", r); | |
ecff665f | 560 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 561 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 562 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
563 | return r; |
564 | } | |
55b51c88 | 565 | |
860024e5 CK |
566 | trace_radeon_cs(&parser); |
567 | ||
721604a1 | 568 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 569 | if (r) { |
721604a1 | 570 | goto out; |
771fe6b9 | 571 | } |
721604a1 | 572 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 573 | if (r) { |
721604a1 | 574 | goto out; |
771fe6b9 | 575 | } |
721604a1 | 576 | out: |
ecff665f | 577 | radeon_cs_parser_fini(&parser, r, true); |
dee53e7f | 578 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 579 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
580 | return r; |
581 | } | |
513bcb46 DA |
582 | |
583 | int radeon_cs_finish_pages(struct radeon_cs_parser *p) | |
584 | { | |
585 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
586 | int i; | |
587 | int size = PAGE_SIZE; | |
588 | ||
589 | for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { | |
590 | if (i == ibc->last_page_index) { | |
591 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
592 | if (size == 0) | |
593 | size = PAGE_SIZE; | |
594 | } | |
595 | ||
f2e39221 | 596 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
597 | ibc->user_ptr + (i * PAGE_SIZE), |
598 | size)) | |
599 | return -EFAULT; | |
600 | } | |
601 | return 0; | |
602 | } | |
603 | ||
c4c7f314 | 604 | static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) |
513bcb46 DA |
605 | { |
606 | int new_page; | |
513bcb46 DA |
607 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
608 | int i; | |
609 | int size = PAGE_SIZE; | |
ff4bd082 IH |
610 | bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? |
611 | false : true; | |
513bcb46 | 612 | |
c5e617e2 | 613 | for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { |
f2e39221 | 614 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
615 | ibc->user_ptr + (i * PAGE_SIZE), |
616 | PAGE_SIZE)) { | |
617 | p->parser_error = -EFAULT; | |
618 | return 0; | |
619 | } | |
620 | } | |
621 | ||
513bcb46 DA |
622 | if (pg_idx == ibc->last_page_index) { |
623 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
6a7068b4 DA |
624 | if (size == 0) |
625 | size = PAGE_SIZE; | |
513bcb46 DA |
626 | } |
627 | ||
6a7068b4 DA |
628 | new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; |
629 | if (copy1) | |
f2e39221 | 630 | ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); |
6a7068b4 | 631 | |
513bcb46 DA |
632 | if (DRM_COPY_FROM_USER(ibc->kpage[new_page], |
633 | ibc->user_ptr + (pg_idx * PAGE_SIZE), | |
634 | size)) { | |
635 | p->parser_error = -EFAULT; | |
636 | return 0; | |
637 | } | |
638 | ||
6a7068b4 DA |
639 | /* copy to IB for non single case */ |
640 | if (!copy1) | |
f2e39221 | 641 | memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); |
513bcb46 DA |
642 | |
643 | ibc->last_copied_page = pg_idx; | |
644 | ibc->kpage_idx[new_page] = pg_idx; | |
645 | ||
646 | return new_page; | |
647 | } | |
c4c7f314 DA |
648 | |
649 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
650 | { | |
651 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
652 | u32 pg_idx, pg_offset; | |
653 | u32 idx_value = 0; | |
654 | int new_page; | |
655 | ||
656 | pg_idx = (idx * 4) / PAGE_SIZE; | |
657 | pg_offset = (idx * 4) % PAGE_SIZE; | |
658 | ||
659 | if (ibc->kpage_idx[0] == pg_idx) | |
660 | return ibc->kpage[0][pg_offset/4]; | |
661 | if (ibc->kpage_idx[1] == pg_idx) | |
662 | return ibc->kpage[1][pg_offset/4]; | |
663 | ||
664 | new_page = radeon_cs_update_pages(p, pg_idx); | |
665 | if (new_page < 0) { | |
666 | p->parser_error = new_page; | |
667 | return 0; | |
668 | } | |
669 | ||
670 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
671 | return idx_value; | |
672 | } | |
4db01311 IH |
673 | |
674 | /** | |
675 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet | |
676 | * @parser: parser structure holding parsing context. | |
677 | * @pkt: where to store packet information | |
678 | * | |
679 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
680 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
681 | **/ | |
682 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, | |
683 | struct radeon_cs_packet *pkt, | |
684 | unsigned idx) | |
685 | { | |
686 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
687 | struct radeon_device *rdev = p->rdev; | |
688 | uint32_t header; | |
689 | ||
690 | if (idx >= ib_chunk->length_dw) { | |
691 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
692 | idx, ib_chunk->length_dw); | |
693 | return -EINVAL; | |
694 | } | |
695 | header = radeon_get_ib_value(p, idx); | |
696 | pkt->idx = idx; | |
697 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); | |
698 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); | |
699 | pkt->one_reg_wr = 0; | |
700 | switch (pkt->type) { | |
701 | case RADEON_PACKET_TYPE0: | |
702 | if (rdev->family < CHIP_R600) { | |
703 | pkt->reg = R100_CP_PACKET0_GET_REG(header); | |
704 | pkt->one_reg_wr = | |
705 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); | |
706 | } else | |
707 | pkt->reg = R600_CP_PACKET0_GET_REG(header); | |
708 | break; | |
709 | case RADEON_PACKET_TYPE3: | |
710 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); | |
711 | break; | |
712 | case RADEON_PACKET_TYPE2: | |
713 | pkt->count = -1; | |
714 | break; | |
715 | default: | |
716 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
717 | return -EINVAL; | |
718 | } | |
719 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
720 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
721 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
722 | return -EINVAL; | |
723 | } | |
724 | return 0; | |
725 | } | |
9ffb7a6d IH |
726 | |
727 | /** | |
728 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP | |
729 | * @p: structure holding the parser context. | |
730 | * | |
731 | * Check if the next packet is NOP relocation packet3. | |
732 | **/ | |
733 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | |
734 | { | |
735 | struct radeon_cs_packet p3reloc; | |
736 | int r; | |
737 | ||
738 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
739 | if (r) | |
740 | return false; | |
741 | if (p3reloc.type != RADEON_PACKET_TYPE3) | |
742 | return false; | |
743 | if (p3reloc.opcode != RADEON_PACKET3_NOP) | |
744 | return false; | |
745 | return true; | |
746 | } | |
c3ad63af IH |
747 | |
748 | /** | |
749 | * radeon_cs_dump_packet() - dump raw packet context | |
750 | * @p: structure holding the parser context. | |
751 | * @pkt: structure holding the packet. | |
752 | * | |
753 | * Used mostly for debugging and error reporting. | |
754 | **/ | |
755 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, | |
756 | struct radeon_cs_packet *pkt) | |
757 | { | |
758 | volatile uint32_t *ib; | |
759 | unsigned i; | |
760 | unsigned idx; | |
761 | ||
762 | ib = p->ib.ptr; | |
763 | idx = pkt->idx; | |
764 | for (i = 0; i <= (pkt->count + 1); i++, idx++) | |
765 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
766 | } | |
767 | ||
e9716993 IH |
768 | /** |
769 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet | |
770 | * @parser: parser structure holding parsing context. | |
771 | * @data: pointer to relocation data | |
772 | * @offset_start: starting offset | |
773 | * @offset_mask: offset mask (to align start offset on) | |
774 | * @reloc: reloc informations | |
775 | * | |
776 | * Check if next packet is relocation packet3, do bo validation and compute | |
777 | * GPU offset using the provided start. | |
778 | **/ | |
779 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
780 | struct radeon_cs_reloc **cs_reloc, | |
781 | int nomm) | |
782 | { | |
783 | struct radeon_cs_chunk *relocs_chunk; | |
784 | struct radeon_cs_packet p3reloc; | |
785 | unsigned idx; | |
786 | int r; | |
787 | ||
788 | if (p->chunk_relocs_idx == -1) { | |
789 | DRM_ERROR("No relocation chunk !\n"); | |
790 | return -EINVAL; | |
791 | } | |
792 | *cs_reloc = NULL; | |
793 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | |
794 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
795 | if (r) | |
796 | return r; | |
797 | p->idx += p3reloc.count + 2; | |
798 | if (p3reloc.type != RADEON_PACKET_TYPE3 || | |
799 | p3reloc.opcode != RADEON_PACKET3_NOP) { | |
800 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
801 | p3reloc.idx); | |
802 | radeon_cs_dump_packet(p, &p3reloc); | |
803 | return -EINVAL; | |
804 | } | |
805 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | |
806 | if (idx >= relocs_chunk->length_dw) { | |
807 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
808 | idx, relocs_chunk->length_dw); | |
809 | radeon_cs_dump_packet(p, &p3reloc); | |
810 | return -EINVAL; | |
811 | } | |
812 | /* FIXME: we assume reloc size is 4 dwords */ | |
813 | if (nomm) { | |
814 | *cs_reloc = p->relocs; | |
815 | (*cs_reloc)->lobj.gpu_offset = | |
816 | (u64)relocs_chunk->kdata[idx + 3] << 32; | |
817 | (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; | |
818 | } else | |
819 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
820 | return 0; | |
821 | } |