[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);
		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		/* for now */
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	    (p->rdev->family < CHIP_CAYMAN)) {
		DRM_ERROR("VM not supported on asic!\n");
		if (p->chunk_relocs_idx != -1)
			kfree(p->chunks[p->chunk_relocs_idx].kdata);
		if (p->chunk_flags_idx != -1)
			kfree(p->chunks[p->chunk_flags_idx].kdata);
		return -EINVAL;
	}

	if (radeon_cs_get_ring(p, ring, priority)) {
		if (p->chunk_relocs_idx != -1)
			kfree(p->chunks[p->chunk_relocs_idx].kdata);
		if (p->chunk_flags_idx != -1)
			kfree(p->chunks[p->chunk_flags_idx].kdata);
		return -EINVAL;
	}


	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
		p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
		if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
		    p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
			kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
			kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
			return -ENOMEM;
		}
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;


	if (!error && parser->ib)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib->fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		kfree(parser->chunks[i].kpage[0]);
		kfree(parser->chunks[i].kpage[1]);
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	parser->ib->vm_id = 0;
	r = radeon_ib_schedule(rdev, parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return 0;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	parser->ib->vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
	r = radeon_ib_schedule(rdev, parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib->fence);
	}
	mutex_unlock(&fpriv->vm.mutex);
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	radeon_mutex_lock(&rdev->cs_mutex);
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	radeon_mutex_unlock(&rdev->cs_mutex);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
	}

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB here */
	memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
16557f1e CK	87	} else
16557f1e CK	88	p->relocs[i].handle = 0;
771fe6b9	89	}
94429bb6	90	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	91	}
771fe6b9 JG	92
721604a1 JG	93	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	94	{
	95	p->priority = priority;
	96
	97	switch (ring) {
	98	default:
	99	DRM_ERROR("unknown ring id: %d\n", ring);
	100	return -EINVAL;
	101	case RADEON_CS_RING_GFX:
	102	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	103	break;
	104	case RADEON_CS_RING_COMPUTE:
	105	/* for now */
	106	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	107	break;
	108	}
	109	return 0;
	110	}
	111
771fe6b9 JG	112	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	113	{
	114	struct drm_radeon_cs *cs = data;
	115	uint64_t *chunk_array_ptr;
721604a1 JG	116	unsigned size, i;
	117	u32 ring = RADEON_CS_RING_GFX;
	118	s32 priority = 0;
771fe6b9 JG	119
	120	if (!cs->num_chunks) {
	121	return 0;
	122	}
	123	/* get chunks */
	124	INIT_LIST_HEAD(&p->validated);
	125	p->idx = 0;
	126	p->chunk_ib_idx = -1;
	127	p->chunk_relocs_idx = -1;
721604a1	128	p->chunk_flags_idx = -1;
771fe6b9 JG	129	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	130	if (p->chunks_array == NULL) {
	131	return -ENOMEM;
	132	}
	133	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	134	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	135	sizeof(uint64_t)*cs->num_chunks)) {
	136	return -EFAULT;
	137	}
721604a1	138	p->cs_flags = 0;
771fe6b9 JG	139	p->nchunks = cs->num_chunks;
	140	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	141	if (p->chunks == NULL) {
	142	return -ENOMEM;
	143	}
	144	for (i = 0; i < p->nchunks; i++) {
	145	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	146	struct drm_radeon_cs_chunk user_chunk;
	147	uint32_t __user *cdata;
	148
	149	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	150	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	151	sizeof(struct drm_radeon_cs_chunk))) {
	152	return -EFAULT;
	153	}
5176fdc4 DA	154	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	155	p->chunks[i].kdata = NULL;
771fe6b9	156	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	157
771fe6b9 JG	158	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	159	p->chunk_relocs_idx = i;
	160	}
	161	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	162	p->chunk_ib_idx = i;
5176fdc4 DA	163	/* zero length IB isn't useful */
	164	if (p->chunks[i].length_dw == 0)
	165	return -EINVAL;
771fe6b9	166	}
721604a1 JG	167	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	168	p->chunk_flags_idx = i;
	169	/* zero length flags aren't useful */
	170	if (p->chunks[i].length_dw == 0)
	171	return -EINVAL;
e70f224c	172	}
5176fdc4	173
771fe6b9	174	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	175	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	176
513bcb46	177	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	178	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	179	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	180	size = p->chunks[i].length_dw * sizeof(uint32_t);
	181	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	182	if (p->chunks[i].kdata == NULL) {
	183	return -ENOMEM;
	184	}
	185	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	186	p->chunks[i].user_ptr, size)) {
	187	return -EFAULT;
	188	}
e70f224c	189	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	190	p->cs_flags = p->chunks[i].kdata[0];
	191	if (p->chunks[i].length_dw > 1)
	192	ring = p->chunks[i].kdata[1];
	193	if (p->chunks[i].length_dw > 2)
	194	priority = (s32)p->chunks[i].kdata[2];
e70f224c	195	}
771fe6b9 JG	196	}
771fe6b9 JG	197	}
721604a1 JG	198
	199	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	200	(p->rdev->family < CHIP_CAYMAN)) {
	201	DRM_ERROR("VM not supported on asic!\n");
	202	if (p->chunk_relocs_idx != -1)
	203	kfree(p->chunks[p->chunk_relocs_idx].kdata);
	204	if (p->chunk_flags_idx != -1)
	205	kfree(p->chunks[p->chunk_flags_idx].kdata);
771fe6b9 JG	206	return -EINVAL;
771fe6b9 JG	207	}
e70f224c	208
721604a1 JG	209	if (radeon_cs_get_ring(p, ring, priority)) {
	210	if (p->chunk_relocs_idx != -1)
	211	kfree(p->chunks[p->chunk_relocs_idx].kdata);
	212	if (p->chunk_flags_idx != -1)
	213	kfree(p->chunks[p->chunk_flags_idx].kdata);
	214	return -EINVAL;
	215	}
	216
	217
	218	/* deal with non-vm */
	219	if ((p->chunk_ib_idx != -1) &&
	220	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	221	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	222	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	223	DRM_ERROR("cs IB too big: %d\n",
	224	p->chunks[p->chunk_ib_idx].length_dw);
	225	return -EINVAL;
	226	}
	227	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	228	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	229	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
	230	p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
	231	kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
	232	kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
	233	return -ENOMEM;
	234	}
	235	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	236	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	237	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	238	p->chunks[p->chunk_ib_idx].last_page_index =
	239	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	240	}
	241
771fe6b9 JG	242	return 0;
	243	}
	244
	245	/**
	246	* cs_parser_fini() - clean parser states
	247	* @parser: parser structure holding parsing context.
	248	* @error: error number
	249	*
	250	* If error is set than unvalidate buffer, otherwise just free memory
	251	* used by parsing context.
	252	**/
	253	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	254	{
	255	unsigned i;
	256
147666fb TH	257
	258	if (!error && parser->ib)
	259	ttm_eu_fence_buffer_objects(&parser->validated,
	260	parser->ib->fence);
	261	else
	262	ttm_eu_backoff_reservation(&parser->validated);
	263
fcbc451b PN	264	if (parser->relocs != NULL) {
	265	for (i = 0; i < parser->nrelocs; i++) {
	266	if (parser->relocs[i].gobj)
	267	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	268	}
771fe6b9	269	}
48e113e5	270	kfree(parser->track);
771fe6b9 JG	271	kfree(parser->relocs);
	272	kfree(parser->relocs_ptr);
	273	for (i = 0; i < parser->nchunks; i++) {
	274	kfree(parser->chunks[i].kdata);
513bcb46 DA	275	kfree(parser->chunks[i].kpage[0]);
513bcb46 DA	276	kfree(parser->chunks[i].kpage[1]);
771fe6b9 JG	277	}
	278	kfree(parser->chunks);
	279	kfree(parser->chunks_array);
	280	radeon_ib_free(parser->rdev, &parser->ib);
	281	}
	282
721604a1 JG	283	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	284	struct radeon_cs_parser *parser)
	285	{
	286	struct radeon_cs_chunk *ib_chunk;
	287	int r;
	288
	289	if (parser->chunk_ib_idx == -1)
	290	return 0;
	291
	292	if (parser->cs_flags & RADEON_CS_USE_VM)
	293	return 0;
	294
	295	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	296	/* Copy the packet into the IB, the parser will read from the
	297	* input memory (cached) and write to the IB (which can be
	298	* uncached).
	299	*/
	300	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	301	ib_chunk->length_dw * 4);
	302	if (r) {
	303	DRM_ERROR("Failed to get ib !\n");
	304	return r;
	305	}
	306	parser->ib->length_dw = ib_chunk->length_dw;
	307	r = radeon_cs_parse(parser);
	308	if (r \|\| parser->parser_error) {
	309	DRM_ERROR("Invalid command stream !\n");
	310	return r;
	311	}
	312	r = radeon_cs_finish_pages(parser);
	313	if (r) {
	314	DRM_ERROR("Invalid command stream !\n");
	315	return r;
	316	}
	317	parser->ib->vm_id = 0;
	318	r = radeon_ib_schedule(rdev, parser->ib);
	319	if (r) {
	320	DRM_ERROR("Failed to schedule IB !\n");
	321	}
	322	return 0;
	323	}
	324
	325	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	326	struct radeon_vm *vm)
	327	{
	328	struct radeon_bo_list *lobj;
	329	struct radeon_bo *bo;
	330	int r;
	331
	332	list_for_each_entry(lobj, &parser->validated, tv.head) {
	333	bo = lobj->bo;
	334	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	335	if (r) {
	336	return r;
	337	}
	338	}
	339	return 0;
	340	}
	341
	342	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	343	struct radeon_cs_parser *parser)
	344	{
	345	struct radeon_cs_chunk *ib_chunk;
	346	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
347	struct radeon_vm *vm = &fpriv->vm;
348	int r;
349
350	if (parser->chunk_ib_idx == -1)
351	return 0;
352
353	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
354	return 0;
355
356	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
357	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
358	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
359	return -EINVAL;
360	}
361	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
362	ib_chunk->length_dw * 4);
363	if (r) {
364	DRM_ERROR("Failed to get ib !\n");
365	return r;
366	}
367	parser->ib->length_dw = ib_chunk->length_dw;
368	/* Copy the packet into the IB */
369	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
370	ib_chunk->length_dw * 4)) {
371	return -EFAULT;
372	}
373	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
374	if (r) {
375	return r;
376	}
377
378	mutex_lock(&vm->mutex);
379	r = radeon_vm_bind(rdev, vm);
380	if (r) {
381	goto out;
382	}
383	r = radeon_bo_vm_update_pte(parser, vm);
384	if (r) {
385	goto out;
386	}
387	parser->ib->vm_id = vm->id;
388	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
389	* offset inside the pool bo
390	*/
391	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
392	r = radeon_ib_schedule(rdev, parser->ib);
393	out:
394	if (!r) {
395	if (vm->fence) {
396	radeon_fence_unref(&vm->fence);
397	}
398	vm->fence = radeon_fence_ref(parser->ib->fence);
399	}
400	mutex_unlock(&fpriv->vm.mutex);
401	return r;
402	}
403
771fe6b9 JG	404	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	405	{
	406	struct radeon_device *rdev = dev->dev_private;
	407	struct radeon_cs_parser parser;
771fe6b9 JG	408	int r;
771fe6b9 JG	409
7a1619b9	410	radeon_mutex_lock(&rdev->cs_mutex);
771fe6b9 JG	411	/* initialize parser */
	412	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	413	parser.filp = filp;
	414	parser.rdev = rdev;
c8c15ff1	415	parser.dev = rdev->dev;
428c6e36	416	parser.family = rdev->family;
771fe6b9 JG	417	r = radeon_cs_parser_init(&parser, data);
	418	if (r) {
	419	DRM_ERROR("Failed to initialize parser !\n");
	420	radeon_cs_parser_fini(&parser, r);
7a1619b9	421	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	422	return r;
771fe6b9 JG	423	}
771fe6b9 JG	424	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	425	if (r) {
97f23b3d DA	426	if (r != -ERESTARTSYS)
97f23b3d DA	427	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	428	radeon_cs_parser_fini(&parser, r);
7a1619b9	429	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	430	return r;
771fe6b9 JG	431	}
721604a1	432	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	433	if (r) {
721604a1	434	goto out;
771fe6b9	435	}
721604a1	436	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	437	if (r) {
721604a1	438	goto out;
771fe6b9	439	}
721604a1	440	out:
771fe6b9	441	radeon_cs_parser_fini(&parser, r);
7a1619b9	442	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	443	return r;
771fe6b9 JG	444	}
513bcb46 DA	445
	446	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	447	{
	448	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	449	int i;
	450	int size = PAGE_SIZE;
	451
	452	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	453	if (i == ibc->last_page_index) {
	454	size = (ibc->length_dw * 4) % PAGE_SIZE;
	455	if (size == 0)
	456	size = PAGE_SIZE;
	457	}
	458
	459	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	460	ibc->user_ptr + (i * PAGE_SIZE),
	461	size))
	462	return -EFAULT;
	463	}
	464	return 0;
	465	}
	466
	467	int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
	468	{
	469	int new_page;
513bcb46 DA	470	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	471	int i;
	472	int size = PAGE_SIZE;
	473
c5e617e2	474	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
513bcb46 DA	475	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	476	ibc->user_ptr + (i * PAGE_SIZE),
	477	PAGE_SIZE)) {
	478	p->parser_error = -EFAULT;
	479	return 0;
	480	}
	481	}
	482
	483	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	484
	485	if (pg_idx == ibc->last_page_index) {
	486	size = (ibc->length_dw * 4) % PAGE_SIZE;
	487	if (size == 0)
	488	size = PAGE_SIZE;
	489	}
	490
	491	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	492	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	493	size)) {
	494	p->parser_error = -EFAULT;
	495	return 0;
	496	}
	497
	498	/* copy to IB here */
	499	memcpy((void )(p->ib->ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
	500
	501	ibc->last_copied_page = pg_idx;
	502	ibc->kpage_idx[new_page] = pg_idx;
	503
	504	return new_page;
	505	}