Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
4330441a | 27 | #include <linux/list_sort.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
30 | #include "radeon_reg.h" |
31 | #include "radeon.h" | |
860024e5 | 32 | #include "radeon_trace.h" |
771fe6b9 | 33 | |
c9b76548 MO |
34 | #define RADEON_CS_MAX_PRIORITY 32u |
35 | #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1) | |
36 | ||
37 | /* This is based on the bucket sort with O(n) time complexity. | |
38 | * An item with priority "i" is added to bucket[i]. The lists are then | |
39 | * concatenated in descending order. | |
40 | */ | |
41 | struct radeon_cs_buckets { | |
42 | struct list_head bucket[RADEON_CS_NUM_BUCKETS]; | |
43 | }; | |
44 | ||
45 | static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) | |
46 | { | |
47 | unsigned i; | |
48 | ||
49 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) | |
50 | INIT_LIST_HEAD(&b->bucket[i]); | |
51 | } | |
52 | ||
53 | static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, | |
54 | struct list_head *item, unsigned priority) | |
55 | { | |
56 | /* Since buffers which appear sooner in the relocation list are | |
57 | * likely to be used more often than buffers which appear later | |
58 | * in the list, the sort mustn't change the ordering of buffers | |
59 | * with the same priority, i.e. it must be stable. | |
60 | */ | |
61 | list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]); | |
62 | } | |
63 | ||
64 | static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, | |
65 | struct list_head *out_list) | |
66 | { | |
67 | unsigned i; | |
68 | ||
69 | /* Connect the sorted buckets in the output list. */ | |
70 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) { | |
71 | list_splice(&b->bucket[i], out_list); | |
72 | } | |
73 | } | |
74 | ||
1109ca09 | 75 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
771fe6b9 JG |
76 | { |
77 | struct drm_device *ddev = p->rdev->ddev; | |
78 | struct radeon_cs_chunk *chunk; | |
c9b76548 | 79 | struct radeon_cs_buckets buckets; |
771fe6b9 | 80 | unsigned i, j; |
f72a113a CK |
81 | bool duplicate, need_mmap_lock = false; |
82 | int r; | |
771fe6b9 JG |
83 | |
84 | if (p->chunk_relocs_idx == -1) { | |
85 | return 0; | |
86 | } | |
87 | chunk = &p->chunks[p->chunk_relocs_idx]; | |
cf4ccd01 | 88 | p->dma_reloc_idx = 0; |
771fe6b9 JG |
89 | /* FIXME: we assume that each relocs use 4 dwords */ |
90 | p->nrelocs = chunk->length_dw / 4; | |
91 | p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); | |
92 | if (p->relocs_ptr == NULL) { | |
93 | return -ENOMEM; | |
94 | } | |
95 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); | |
96 | if (p->relocs == NULL) { | |
97 | return -ENOMEM; | |
98 | } | |
c9b76548 MO |
99 | |
100 | radeon_cs_buckets_init(&buckets); | |
101 | ||
771fe6b9 JG |
102 | for (i = 0; i < p->nrelocs; i++) { |
103 | struct drm_radeon_cs_reloc *r; | |
c9b76548 | 104 | unsigned priority; |
771fe6b9 JG |
105 | |
106 | duplicate = false; | |
107 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; | |
16557f1e | 108 | for (j = 0; j < i; j++) { |
771fe6b9 JG |
109 | if (r->handle == p->relocs[j].handle) { |
110 | p->relocs_ptr[i] = &p->relocs[j]; | |
111 | duplicate = true; | |
112 | break; | |
113 | } | |
114 | } | |
4474f3a9 | 115 | if (duplicate) { |
16557f1e | 116 | p->relocs[i].handle = 0; |
4474f3a9 CK |
117 | continue; |
118 | } | |
119 | ||
120 | p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, | |
121 | r->handle); | |
122 | if (p->relocs[i].gobj == NULL) { | |
123 | DRM_ERROR("gem object lookup failed 0x%x\n", | |
124 | r->handle); | |
125 | return -ENOENT; | |
126 | } | |
127 | p->relocs_ptr[i] = &p->relocs[i]; | |
128 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); | |
c9b76548 MO |
129 | |
130 | /* The userspace buffer priorities are from 0 to 15. A higher | |
131 | * number means the buffer is more important. | |
132 | * Also, the buffers used for write have a higher priority than | |
133 | * the buffers used for read only, which doubles the range | |
134 | * to 0 to 31. 32 is reserved for the kernel driver. | |
135 | */ | |
136 | priority = (r->flags & 0xf) * 2 + !!r->write_domain; | |
4474f3a9 | 137 | |
4f66c599 CK |
138 | /* the first reloc of an UVD job is the msg and that must be in |
139 | VRAM, also but everything into VRAM on AGP cards to avoid | |
140 | image corruptions */ | |
141 | if (p->ring == R600_RING_TYPE_UVD_INDEX && | |
4ca5a6cb | 142 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { |
bcf6f1e9 | 143 | /* TODO: is this still needed for NI+ ? */ |
ce6758c8 | 144 | p->relocs[i].prefered_domains = |
f2ba57b5 CK |
145 | RADEON_GEM_DOMAIN_VRAM; |
146 | ||
ce6758c8 | 147 | p->relocs[i].allowed_domains = |
f2ba57b5 CK |
148 | RADEON_GEM_DOMAIN_VRAM; |
149 | ||
c9b76548 MO |
150 | /* prioritize this over any other relocation */ |
151 | priority = RADEON_CS_MAX_PRIORITY; | |
f2ba57b5 CK |
152 | } else { |
153 | uint32_t domain = r->write_domain ? | |
154 | r->write_domain : r->read_domains; | |
155 | ||
ec65da38 MO |
156 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
157 | DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid " | |
158 | "for command submission\n"); | |
159 | return -EINVAL; | |
160 | } | |
161 | ||
ce6758c8 | 162 | p->relocs[i].prefered_domains = domain; |
f2ba57b5 CK |
163 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
164 | domain |= RADEON_GEM_DOMAIN_GTT; | |
ce6758c8 | 165 | p->relocs[i].allowed_domains = domain; |
f2ba57b5 | 166 | } |
4474f3a9 | 167 | |
f72a113a CK |
168 | if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) { |
169 | uint32_t domain = p->relocs[i].prefered_domains; | |
170 | if (!(domain & RADEON_GEM_DOMAIN_GTT)) { | |
171 | DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is " | |
172 | "allowed for userptr BOs\n"); | |
173 | return -EINVAL; | |
174 | } | |
175 | need_mmap_lock = true; | |
176 | domain = RADEON_GEM_DOMAIN_GTT; | |
177 | p->relocs[i].prefered_domains = domain; | |
178 | p->relocs[i].allowed_domains = domain; | |
179 | } | |
180 | ||
df0af440 | 181 | p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; |
4474f3a9 CK |
182 | p->relocs[i].handle = r->handle; |
183 | ||
df0af440 | 184 | radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, |
c9b76548 | 185 | priority); |
771fe6b9 | 186 | } |
c9b76548 MO |
187 | |
188 | radeon_cs_buckets_get_list(&buckets, &p->validated); | |
189 | ||
6d2f2944 CK |
190 | if (p->cs_flags & RADEON_CS_USE_VM) |
191 | p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, | |
192 | &p->validated); | |
f72a113a CK |
193 | if (need_mmap_lock) |
194 | down_read(¤t->mm->mmap_sem); | |
195 | ||
196 | r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); | |
197 | ||
198 | if (need_mmap_lock) | |
199 | up_read(¤t->mm->mmap_sem); | |
6d2f2944 | 200 | |
f72a113a | 201 | return r; |
771fe6b9 JG |
202 | } |
203 | ||
721604a1 JG |
204 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
205 | { | |
206 | p->priority = priority; | |
207 | ||
208 | switch (ring) { | |
209 | default: | |
210 | DRM_ERROR("unknown ring id: %d\n", ring); | |
211 | return -EINVAL; | |
212 | case RADEON_CS_RING_GFX: | |
213 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
214 | break; | |
215 | case RADEON_CS_RING_COMPUTE: | |
963e81f9 | 216 | if (p->rdev->family >= CHIP_TAHITI) { |
8d5ef7b1 AD |
217 | if (p->priority > 0) |
218 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; | |
219 | else | |
220 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; | |
221 | } else | |
222 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
721604a1 | 223 | break; |
278a334c AD |
224 | case RADEON_CS_RING_DMA: |
225 | if (p->rdev->family >= CHIP_CAYMAN) { | |
226 | if (p->priority > 0) | |
227 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
228 | else | |
229 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; | |
b9ace36f | 230 | } else if (p->rdev->family >= CHIP_RV770) { |
278a334c AD |
231 | p->ring = R600_RING_TYPE_DMA_INDEX; |
232 | } else { | |
233 | return -EINVAL; | |
234 | } | |
235 | break; | |
f2ba57b5 CK |
236 | case RADEON_CS_RING_UVD: |
237 | p->ring = R600_RING_TYPE_UVD_INDEX; | |
238 | break; | |
d93f7937 CK |
239 | case RADEON_CS_RING_VCE: |
240 | /* TODO: only use the low priority ring for now */ | |
241 | p->ring = TN_RING_TYPE_VCE1_INDEX; | |
242 | break; | |
721604a1 JG |
243 | } |
244 | return 0; | |
245 | } | |
246 | ||
220907d9 | 247 | static void radeon_cs_sync_rings(struct radeon_cs_parser *p) |
93504fce | 248 | { |
220907d9 | 249 | int i; |
93504fce | 250 | |
cdac5504 | 251 | for (i = 0; i < p->nrelocs; i++) { |
f82cbddd | 252 | if (!p->relocs[i].robj) |
cdac5504 CK |
253 | continue; |
254 | ||
1654b817 CK |
255 | radeon_semaphore_sync_to(p->ib.semaphore, |
256 | p->relocs[i].robj->tbo.sync_obj); | |
8f676c4c | 257 | } |
93504fce CK |
258 | } |
259 | ||
9b00147d | 260 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
771fe6b9 JG |
261 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
262 | { | |
263 | struct drm_radeon_cs *cs = data; | |
264 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
265 | unsigned size, i; |
266 | u32 ring = RADEON_CS_RING_GFX; | |
267 | s32 priority = 0; | |
771fe6b9 JG |
268 | |
269 | if (!cs->num_chunks) { | |
270 | return 0; | |
271 | } | |
272 | /* get chunks */ | |
273 | INIT_LIST_HEAD(&p->validated); | |
274 | p->idx = 0; | |
f2e39221 JG |
275 | p->ib.sa_bo = NULL; |
276 | p->ib.semaphore = NULL; | |
277 | p->const_ib.sa_bo = NULL; | |
278 | p->const_ib.semaphore = NULL; | |
771fe6b9 JG |
279 | p->chunk_ib_idx = -1; |
280 | p->chunk_relocs_idx = -1; | |
721604a1 | 281 | p->chunk_flags_idx = -1; |
dfcf5f36 | 282 | p->chunk_const_ib_idx = -1; |
771fe6b9 JG |
283 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
284 | if (p->chunks_array == NULL) { | |
285 | return -ENOMEM; | |
286 | } | |
287 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
1d6ac185 | 288 | if (copy_from_user(p->chunks_array, chunk_array_ptr, |
771fe6b9 JG |
289 | sizeof(uint64_t)*cs->num_chunks)) { |
290 | return -EFAULT; | |
291 | } | |
721604a1 | 292 | p->cs_flags = 0; |
771fe6b9 JG |
293 | p->nchunks = cs->num_chunks; |
294 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
295 | if (p->chunks == NULL) { | |
296 | return -ENOMEM; | |
297 | } | |
298 | for (i = 0; i < p->nchunks; i++) { | |
299 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
300 | struct drm_radeon_cs_chunk user_chunk; | |
301 | uint32_t __user *cdata; | |
302 | ||
303 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
1d6ac185 | 304 | if (copy_from_user(&user_chunk, chunk_ptr, |
771fe6b9 JG |
305 | sizeof(struct drm_radeon_cs_chunk))) { |
306 | return -EFAULT; | |
307 | } | |
5176fdc4 | 308 | p->chunks[i].length_dw = user_chunk.length_dw; |
771fe6b9 JG |
309 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
310 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { | |
311 | p->chunk_relocs_idx = i; | |
312 | } | |
313 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
314 | p->chunk_ib_idx = i; | |
5176fdc4 DA |
315 | /* zero length IB isn't useful */ |
316 | if (p->chunks[i].length_dw == 0) | |
317 | return -EINVAL; | |
771fe6b9 | 318 | } |
dfcf5f36 AD |
319 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
320 | p->chunk_const_ib_idx = i; | |
321 | /* zero length CONST IB isn't useful */ | |
322 | if (p->chunks[i].length_dw == 0) | |
323 | return -EINVAL; | |
324 | } | |
721604a1 JG |
325 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
326 | p->chunk_flags_idx = i; | |
327 | /* zero length flags aren't useful */ | |
328 | if (p->chunks[i].length_dw == 0) | |
329 | return -EINVAL; | |
e70f224c | 330 | } |
5176fdc4 | 331 | |
28a326c5 ML |
332 | size = p->chunks[i].length_dw; |
333 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; | |
334 | p->chunks[i].user_ptr = cdata; | |
335 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) | |
336 | continue; | |
337 | ||
338 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
339 | if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) | |
340 | continue; | |
341 | } | |
342 | ||
343 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
344 | size *= sizeof(uint32_t); | |
345 | if (p->chunks[i].kdata == NULL) { | |
346 | return -ENOMEM; | |
347 | } | |
1d6ac185 | 348 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { |
28a326c5 ML |
349 | return -EFAULT; |
350 | } | |
351 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { | |
352 | p->cs_flags = p->chunks[i].kdata[0]; | |
353 | if (p->chunks[i].length_dw > 1) | |
354 | ring = p->chunks[i].kdata[1]; | |
355 | if (p->chunks[i].length_dw > 2) | |
356 | priority = (s32)p->chunks[i].kdata[2]; | |
771fe6b9 JG |
357 | } |
358 | } | |
721604a1 | 359 | |
9b00147d AD |
360 | /* these are KMS only */ |
361 | if (p->rdev) { | |
362 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
363 | !p->rdev->vm_manager.enabled) { | |
364 | DRM_ERROR("VM not active on asic!\n"); | |
365 | return -EINVAL; | |
366 | } | |
1b5475db | 367 | |
57449040 | 368 | if (radeon_cs_get_ring(p, ring, priority)) |
9b00147d | 369 | return -EINVAL; |
721604a1 | 370 | |
57449040 | 371 | /* we only support VM on some SI+ rings */ |
60a44540 CK |
372 | if ((p->cs_flags & RADEON_CS_USE_VM) == 0) { |
373 | if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) { | |
374 | DRM_ERROR("Ring %d requires VM!\n", p->ring); | |
375 | return -EINVAL; | |
376 | } | |
377 | } else { | |
378 | if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) { | |
379 | DRM_ERROR("VM not supported on ring %d!\n", | |
380 | p->ring); | |
381 | return -EINVAL; | |
382 | } | |
57449040 | 383 | } |
9b00147d | 384 | } |
721604a1 | 385 | |
771fe6b9 JG |
386 | return 0; |
387 | } | |
388 | ||
4330441a MO |
389 | static int cmp_size_smaller_first(void *priv, struct list_head *a, |
390 | struct list_head *b) | |
391 | { | |
df0af440 CK |
392 | struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head); |
393 | struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head); | |
4330441a MO |
394 | |
395 | /* Sort A before B if A is smaller. */ | |
df0af440 | 396 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; |
4330441a MO |
397 | } |
398 | ||
771fe6b9 JG |
399 | /** |
400 | * cs_parser_fini() - clean parser states | |
401 | * @parser: parser structure holding parsing context. | |
402 | * @error: error number | |
403 | * | |
404 | * If error is set than unvalidate buffer, otherwise just free memory | |
405 | * used by parsing context. | |
406 | **/ | |
ecff665f | 407 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) |
771fe6b9 JG |
408 | { |
409 | unsigned i; | |
410 | ||
e43b5ec0 | 411 | if (!error) { |
4330441a MO |
412 | /* Sort the buffer list from the smallest to largest buffer, |
413 | * which affects the order of buffers in the LRU list. | |
414 | * This assures that the smallest buffers are added first | |
415 | * to the LRU list, so they are likely to be later evicted | |
416 | * first, instead of large buffers whose eviction is more | |
417 | * expensive. | |
418 | * | |
419 | * This slightly lowers the number of bytes moved by TTM | |
420 | * per frame under memory pressure. | |
421 | */ | |
422 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
423 | ||
ecff665f ML |
424 | ttm_eu_fence_buffer_objects(&parser->ticket, |
425 | &parser->validated, | |
f2e39221 | 426 | parser->ib.fence); |
ecff665f ML |
427 | } else if (backoff) { |
428 | ttm_eu_backoff_reservation(&parser->ticket, | |
429 | &parser->validated); | |
e43b5ec0 | 430 | } |
147666fb | 431 | |
fcbc451b PN |
432 | if (parser->relocs != NULL) { |
433 | for (i = 0; i < parser->nrelocs; i++) { | |
434 | if (parser->relocs[i].gobj) | |
435 | drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); | |
436 | } | |
771fe6b9 | 437 | } |
48e113e5 | 438 | kfree(parser->track); |
771fe6b9 JG |
439 | kfree(parser->relocs); |
440 | kfree(parser->relocs_ptr); | |
6d2f2944 | 441 | kfree(parser->vm_bos); |
28a326c5 ML |
442 | for (i = 0; i < parser->nchunks; i++) |
443 | drm_free_large(parser->chunks[i].kdata); | |
771fe6b9 JG |
444 | kfree(parser->chunks); |
445 | kfree(parser->chunks_array); | |
446 | radeon_ib_free(parser->rdev, &parser->ib); | |
f2e39221 | 447 | radeon_ib_free(parser->rdev, &parser->const_ib); |
771fe6b9 JG |
448 | } |
449 | ||
721604a1 JG |
450 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
451 | struct radeon_cs_parser *parser) | |
452 | { | |
721604a1 JG |
453 | int r; |
454 | ||
455 | if (parser->chunk_ib_idx == -1) | |
456 | return 0; | |
457 | ||
458 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
459 | return 0; | |
460 | ||
eb0c19c5 | 461 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
462 | if (r || parser->parser_error) { |
463 | DRM_ERROR("Invalid command stream !\n"); | |
464 | return r; | |
465 | } | |
ce3537d5 AD |
466 | |
467 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) | |
468 | radeon_uvd_note_usage(rdev); | |
03afe6f6 AD |
469 | else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || |
470 | (parser->ring == TN_RING_TYPE_VCE2_INDEX)) | |
471 | radeon_vce_note_usage(rdev); | |
ce3537d5 | 472 | |
220907d9 | 473 | radeon_cs_sync_rings(parser); |
4ef72566 | 474 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); |
721604a1 JG |
475 | if (r) { |
476 | DRM_ERROR("Failed to schedule IB !\n"); | |
477 | } | |
93bf888c | 478 | return r; |
721604a1 JG |
479 | } |
480 | ||
6d2f2944 | 481 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, |
721604a1 JG |
482 | struct radeon_vm *vm) |
483 | { | |
6d2f2944 | 484 | struct radeon_device *rdev = p->rdev; |
036bf46a | 485 | struct radeon_bo_va *bo_va; |
6d2f2944 | 486 | int i, r; |
721604a1 | 487 | |
6d2f2944 CK |
488 | r = radeon_vm_update_page_directory(rdev, vm); |
489 | if (r) | |
3e8970f9 | 490 | return r; |
6d2f2944 | 491 | |
036bf46a CK |
492 | r = radeon_vm_clear_freed(rdev, vm); |
493 | if (r) | |
494 | return r; | |
495 | ||
cc9e67e3 | 496 | if (vm->ib_bo_va == NULL) { |
036bf46a CK |
497 | DRM_ERROR("Tmp BO not in VM!\n"); |
498 | return -EINVAL; | |
499 | } | |
500 | ||
cc9e67e3 CK |
501 | r = radeon_vm_bo_update(rdev, vm->ib_bo_va, |
502 | &rdev->ring_tmp_bo.bo->tbo.mem); | |
6d2f2944 CK |
503 | if (r) |
504 | return r; | |
505 | ||
506 | for (i = 0; i < p->nrelocs; i++) { | |
507 | struct radeon_bo *bo; | |
508 | ||
509 | /* ignore duplicates */ | |
510 | if (p->relocs_ptr[i] != &p->relocs[i]) | |
511 | continue; | |
512 | ||
513 | bo = p->relocs[i].robj; | |
036bf46a CK |
514 | bo_va = radeon_vm_bo_find(vm, bo); |
515 | if (bo_va == NULL) { | |
516 | dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); | |
6d2f2944 | 521 | if (r) |
721604a1 | 522 | return r; |
721604a1 | 523 | } |
e31ad969 CK |
524 | |
525 | return radeon_vm_clear_invalids(rdev, vm); | |
721604a1 JG |
526 | } |
527 | ||
528 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
529 | struct radeon_cs_parser *parser) | |
530 | { | |
721604a1 JG |
531 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
532 | struct radeon_vm *vm = &fpriv->vm; | |
533 | int r; | |
534 | ||
535 | if (parser->chunk_ib_idx == -1) | |
536 | return 0; | |
721604a1 JG |
537 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
538 | return 0; | |
539 | ||
28a326c5 | 540 | if (parser->const_ib.length_dw) { |
f2e39221 | 541 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
dfcf5f36 AD |
542 | if (r) { |
543 | return r; | |
544 | } | |
545 | } | |
546 | ||
f2e39221 | 547 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
721604a1 JG |
548 | if (r) { |
549 | return r; | |
550 | } | |
551 | ||
ce3537d5 AD |
552 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
553 | radeon_uvd_note_usage(rdev); | |
554 | ||
721604a1 | 555 | mutex_lock(&vm->mutex); |
721604a1 JG |
556 | r = radeon_bo_vm_update_pte(parser, vm); |
557 | if (r) { | |
558 | goto out; | |
559 | } | |
220907d9 | 560 | radeon_cs_sync_rings(parser); |
1654b817 | 561 | radeon_semaphore_sync_to(parser->ib.semaphore, vm->fence); |
4ef72566 | 562 | |
dfcf5f36 AD |
563 | if ((rdev->family >= CHIP_TAHITI) && |
564 | (parser->chunk_const_ib_idx != -1)) { | |
4ef72566 CK |
565 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); |
566 | } else { | |
567 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | |
dfcf5f36 AD |
568 | } |
569 | ||
ee60e29f | 570 | out: |
36ff39c4 | 571 | mutex_unlock(&vm->mutex); |
721604a1 JG |
572 | return r; |
573 | } | |
574 | ||
6c6f4783 CK |
575 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
576 | { | |
577 | if (r == -EDEADLK) { | |
578 | r = radeon_gpu_reset(rdev); | |
579 | if (!r) | |
580 | r = -EAGAIN; | |
581 | } | |
582 | return r; | |
583 | } | |
584 | ||
28a326c5 ML |
585 | static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) |
586 | { | |
587 | struct radeon_cs_chunk *ib_chunk; | |
588 | struct radeon_vm *vm = NULL; | |
589 | int r; | |
590 | ||
591 | if (parser->chunk_ib_idx == -1) | |
592 | return 0; | |
593 | ||
594 | if (parser->cs_flags & RADEON_CS_USE_VM) { | |
595 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
596 | vm = &fpriv->vm; | |
597 | ||
598 | if ((rdev->family >= CHIP_TAHITI) && | |
599 | (parser->chunk_const_ib_idx != -1)) { | |
600 | ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; | |
601 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
602 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); | |
603 | return -EINVAL; | |
604 | } | |
605 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, | |
606 | vm, ib_chunk->length_dw * 4); | |
607 | if (r) { | |
608 | DRM_ERROR("Failed to get const ib !\n"); | |
609 | return r; | |
610 | } | |
611 | parser->const_ib.is_const_ib = true; | |
612 | parser->const_ib.length_dw = ib_chunk->length_dw; | |
1d6ac185 | 613 | if (copy_from_user(parser->const_ib.ptr, |
28a326c5 ML |
614 | ib_chunk->user_ptr, |
615 | ib_chunk->length_dw * 4)) | |
616 | return -EFAULT; | |
617 | } | |
618 | ||
619 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
620 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
621 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
622 | return -EINVAL; | |
623 | } | |
624 | } | |
625 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
626 | ||
627 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
628 | vm, ib_chunk->length_dw * 4); | |
629 | if (r) { | |
630 | DRM_ERROR("Failed to get ib !\n"); | |
631 | return r; | |
632 | } | |
633 | parser->ib.length_dw = ib_chunk->length_dw; | |
634 | if (ib_chunk->kdata) | |
635 | memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); | |
1d6ac185 | 636 | else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) |
28a326c5 ML |
637 | return -EFAULT; |
638 | return 0; | |
639 | } | |
640 | ||
771fe6b9 JG |
641 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
642 | { | |
643 | struct radeon_device *rdev = dev->dev_private; | |
644 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
645 | int r; |
646 | ||
dee53e7f | 647 | down_read(&rdev->exclusive_lock); |
6b7746e8 | 648 | if (!rdev->accel_working) { |
dee53e7f | 649 | up_read(&rdev->exclusive_lock); |
6b7746e8 JG |
650 | return -EBUSY; |
651 | } | |
771fe6b9 JG |
652 | /* initialize parser */ |
653 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
654 | parser.filp = filp; | |
655 | parser.rdev = rdev; | |
c8c15ff1 | 656 | parser.dev = rdev->dev; |
428c6e36 | 657 | parser.family = rdev->family; |
771fe6b9 JG |
658 | r = radeon_cs_parser_init(&parser, data); |
659 | if (r) { | |
660 | DRM_ERROR("Failed to initialize parser !\n"); | |
ecff665f | 661 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 662 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 663 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
664 | return r; |
665 | } | |
28a326c5 ML |
666 | |
667 | r = radeon_cs_ib_fill(rdev, &parser); | |
668 | if (!r) { | |
669 | r = radeon_cs_parser_relocs(&parser); | |
670 | if (r && r != -ERESTARTSYS) | |
97f23b3d | 671 | DRM_ERROR("Failed to parse relocation %d!\n", r); |
28a326c5 ML |
672 | } |
673 | ||
674 | if (r) { | |
ecff665f | 675 | radeon_cs_parser_fini(&parser, r, false); |
dee53e7f | 676 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 677 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
678 | return r; |
679 | } | |
55b51c88 | 680 | |
860024e5 CK |
681 | trace_radeon_cs(&parser); |
682 | ||
721604a1 | 683 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 684 | if (r) { |
721604a1 | 685 | goto out; |
771fe6b9 | 686 | } |
721604a1 | 687 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 688 | if (r) { |
721604a1 | 689 | goto out; |
771fe6b9 | 690 | } |
721604a1 | 691 | out: |
ecff665f | 692 | radeon_cs_parser_fini(&parser, r, true); |
dee53e7f | 693 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 694 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
695 | return r; |
696 | } | |
513bcb46 | 697 | |
4db01311 IH |
698 | /** |
699 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet | |
700 | * @parser: parser structure holding parsing context. | |
701 | * @pkt: where to store packet information | |
702 | * | |
703 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
704 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
705 | **/ | |
706 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, | |
707 | struct radeon_cs_packet *pkt, | |
708 | unsigned idx) | |
709 | { | |
710 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
711 | struct radeon_device *rdev = p->rdev; | |
712 | uint32_t header; | |
713 | ||
714 | if (idx >= ib_chunk->length_dw) { | |
715 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
716 | idx, ib_chunk->length_dw); | |
717 | return -EINVAL; | |
718 | } | |
719 | header = radeon_get_ib_value(p, idx); | |
720 | pkt->idx = idx; | |
721 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); | |
722 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); | |
723 | pkt->one_reg_wr = 0; | |
724 | switch (pkt->type) { | |
725 | case RADEON_PACKET_TYPE0: | |
726 | if (rdev->family < CHIP_R600) { | |
727 | pkt->reg = R100_CP_PACKET0_GET_REG(header); | |
728 | pkt->one_reg_wr = | |
729 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); | |
730 | } else | |
731 | pkt->reg = R600_CP_PACKET0_GET_REG(header); | |
732 | break; | |
733 | case RADEON_PACKET_TYPE3: | |
734 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); | |
735 | break; | |
736 | case RADEON_PACKET_TYPE2: | |
737 | pkt->count = -1; | |
738 | break; | |
739 | default: | |
740 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
741 | return -EINVAL; | |
742 | } | |
743 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
744 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
745 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
746 | return -EINVAL; | |
747 | } | |
748 | return 0; | |
749 | } | |
9ffb7a6d IH |
750 | |
751 | /** | |
752 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP | |
753 | * @p: structure holding the parser context. | |
754 | * | |
755 | * Check if the next packet is NOP relocation packet3. | |
756 | **/ | |
757 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | |
758 | { | |
759 | struct radeon_cs_packet p3reloc; | |
760 | int r; | |
761 | ||
762 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
763 | if (r) | |
764 | return false; | |
765 | if (p3reloc.type != RADEON_PACKET_TYPE3) | |
766 | return false; | |
767 | if (p3reloc.opcode != RADEON_PACKET3_NOP) | |
768 | return false; | |
769 | return true; | |
770 | } | |
c3ad63af IH |
771 | |
772 | /** | |
773 | * radeon_cs_dump_packet() - dump raw packet context | |
774 | * @p: structure holding the parser context. | |
775 | * @pkt: structure holding the packet. | |
776 | * | |
777 | * Used mostly for debugging and error reporting. | |
778 | **/ | |
779 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, | |
780 | struct radeon_cs_packet *pkt) | |
781 | { | |
782 | volatile uint32_t *ib; | |
783 | unsigned i; | |
784 | unsigned idx; | |
785 | ||
786 | ib = p->ib.ptr; | |
787 | idx = pkt->idx; | |
788 | for (i = 0; i <= (pkt->count + 1); i++, idx++) | |
789 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
790 | } | |
791 | ||
e9716993 IH |
792 | /** |
793 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet | |
794 | * @parser: parser structure holding parsing context. | |
795 | * @data: pointer to relocation data | |
796 | * @offset_start: starting offset | |
797 | * @offset_mask: offset mask (to align start offset on) | |
798 | * @reloc: reloc informations | |
799 | * | |
800 | * Check if next packet is relocation packet3, do bo validation and compute | |
801 | * GPU offset using the provided start. | |
802 | **/ | |
803 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
804 | struct radeon_cs_reloc **cs_reloc, | |
805 | int nomm) | |
806 | { | |
807 | struct radeon_cs_chunk *relocs_chunk; | |
808 | struct radeon_cs_packet p3reloc; | |
809 | unsigned idx; | |
810 | int r; | |
811 | ||
812 | if (p->chunk_relocs_idx == -1) { | |
813 | DRM_ERROR("No relocation chunk !\n"); | |
814 | return -EINVAL; | |
815 | } | |
816 | *cs_reloc = NULL; | |
817 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | |
818 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
819 | if (r) | |
820 | return r; | |
821 | p->idx += p3reloc.count + 2; | |
822 | if (p3reloc.type != RADEON_PACKET_TYPE3 || | |
823 | p3reloc.opcode != RADEON_PACKET3_NOP) { | |
824 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
825 | p3reloc.idx); | |
826 | radeon_cs_dump_packet(p, &p3reloc); | |
827 | return -EINVAL; | |
828 | } | |
829 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | |
830 | if (idx >= relocs_chunk->length_dw) { | |
831 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
832 | idx, relocs_chunk->length_dw); | |
833 | radeon_cs_dump_packet(p, &p3reloc); | |
834 | return -EINVAL; | |
835 | } | |
836 | /* FIXME: we assume reloc size is 4 dwords */ | |
837 | if (nomm) { | |
838 | *cs_reloc = p->relocs; | |
df0af440 | 839 | (*cs_reloc)->gpu_offset = |
e9716993 | 840 | (u64)relocs_chunk->kdata[idx + 3] << 32; |
df0af440 | 841 | (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; |
e9716993 IH |
842 | } else |
843 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
844 | return 0; | |
845 | } |