[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_cursor.c

/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64

static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
{
	struct radeon_device *rdev = crtc->dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	uint32_t cur_lock;

	if (ASIC_IS_DCE4(rdev)) {
		cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
		if (lock)
			cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
		else
			cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
		WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
	} else if (ASIC_IS_AVIVO(rdev)) {
		cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
		if (lock)
			cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
		else
			cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
		WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
	} else {
		cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
		if (lock)
			cur_lock |= RADEON_CUR_LOCK;
		else
			cur_lock &= ~RADEON_CUR_LOCK;
		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
	}
}

static void radeon_hide_cursor(struct drm_crtc *crtc)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_device *rdev = crtc->dev->dev_private;

	if (ASIC_IS_DCE4(rdev)) {
		WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
			   EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
			   EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
	} else if (ASIC_IS_AVIVO(rdev)) {
		WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
			   (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
	} else {
		u32 reg;
		switch (radeon_crtc->crtc_id) {
		case 0:
			reg = RADEON_CRTC_GEN_CNTL;
			break;
		case 1:
			reg = RADEON_CRTC2_GEN_CNTL;
			break;
		default:
			return;
		}
		WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
	}
}

static void radeon_show_cursor(struct drm_crtc *crtc)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_device *rdev = crtc->dev->dev_private;

	if (ASIC_IS_DCE4(rdev)) {
		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
		       EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
		       EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
	} else if (ASIC_IS_AVIVO(rdev)) {
		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
		WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
		       (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
	} else {
		switch (radeon_crtc->crtc_id) {
		case 0:
			WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
			break;
		case 1:
			WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
			break;
		default:
			return;
		}

		WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
					  (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
			 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
	}
}

static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
			      uint64_t gpu_addr)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_device *rdev = crtc->dev->dev_private;

	if (ASIC_IS_DCE4(rdev)) {
		WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
		       upper_32_bits(gpu_addr));
		WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		       gpu_addr & 0xffffffff);
	} else if (ASIC_IS_AVIVO(rdev)) {
		if (rdev->family >= CHIP_RV770) {
			if (radeon_crtc->crtc_id)
				WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
			else
				WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
		}
		WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		       gpu_addr & 0xffffffff);
	} else {
		radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
		/* offset is from DISP(2)_BASE_ADDRESS */
		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
	}
}

int radeon_crtc_cursor_set(struct drm_crtc *crtc,
			   struct drm_file *file_priv,
			   uint32_t handle,
			   uint32_t width,
			   uint32_t height)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_device *rdev = crtc->dev->dev_private;
	struct drm_gem_object *obj;
	struct radeon_bo *robj;
	uint64_t gpu_addr;
	int ret;

	if (!handle) {
		/* turn off cursor */
		radeon_hide_cursor(crtc);
		obj = NULL;
		goto unpin;
	}

	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
		return -EINVAL;
	}

	obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
	if (!obj) {
		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
		return -ENOENT;
	}

	robj = gem_to_radeon_bo(obj);
	ret = radeon_bo_reserve(robj, false);
	if (unlikely(ret != 0))
		goto fail;
	/* Only 27 bit offset for legacy cursor */
	ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
				       ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
				       &gpu_addr);
	radeon_bo_unreserve(robj);
	if (ret)
		goto fail;

	radeon_crtc->cursor_width = width;
	radeon_crtc->cursor_height = height;

	radeon_lock_cursor(crtc, true);
	radeon_set_cursor(crtc, obj, gpu_addr);
	radeon_show_cursor(crtc);
	radeon_lock_cursor(crtc, false);

unpin:
	if (radeon_crtc->cursor_bo) {
		robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
		ret = radeon_bo_reserve(robj, false);
		if (likely(ret == 0)) {
			radeon_bo_unpin(robj);
			radeon_bo_unreserve(robj);
		}
		drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
	}

	radeon_crtc->cursor_bo = obj;
	return 0;
fail:
	drm_gem_object_unreference_unlocked(obj);

	return ret;
}

int radeon_crtc_cursor_move(struct drm_crtc *crtc,
			    int x, int y)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_device *rdev = crtc->dev->dev_private;
	int xorigin = 0, yorigin = 0;
	int w = radeon_crtc->cursor_width;

	if (ASIC_IS_AVIVO(rdev)) {
		/* avivo cursor are offset into the total surface */
		x += crtc->x;
		y += crtc->y;
	}
	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);

	if (x < 0) {
		xorigin = min(-x, CURSOR_WIDTH - 1);
		x = 0;
	}
	if (y < 0) {
		yorigin = min(-y, CURSOR_HEIGHT - 1);
		y = 0;
	}

	/* fixed on DCE6 and newer */
	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
		int i = 0;
		struct drm_crtc *crtc_p;

		/*
		 * avivo cursor image can't end on 128 pixel boundary or
		 * go past the end of the frame if both crtcs are enabled
		 *
		 * NOTE: It is safe to access crtc->enabled of other crtcs
		 * without holding either the mode_config lock or the other
		 * crtc's lock as long as write access to this flag _always_
		 * grabs all locks.
		 */
		list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
			if (crtc_p->enabled)
				i++;
		}
		if (i > 1) {
			int cursor_end, frame_end;

			cursor_end = x - xorigin + w;
			frame_end = crtc->x + crtc->mode.crtc_hdisplay;
			if (cursor_end >= frame_end) {
				w = w - (cursor_end - frame_end);
				if (!(frame_end & 0x7f))
					w--;
			} else {
				if (!(cursor_end & 0x7f))
					w--;
			}
			if (w <= 0) {
				w = 1;
				cursor_end = x - xorigin + w;
				if (!(cursor_end & 0x7f)) {
					x--;
					WARN_ON_ONCE(x < 0);
				}
			}
		}
	}

	radeon_lock_cursor(crtc, true);
	if (ASIC_IS_DCE4(rdev)) {
		WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
		WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
		WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
		       ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
	} else if (ASIC_IS_AVIVO(rdev)) {
		WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
		WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
		WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
		       ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
	} else {
		if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
			y *= 2;

		WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
		       (RADEON_CUR_LOCK
			| (xorigin << 16)
			| yorigin));
		WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
		       (RADEON_CUR_LOCK
			| (x << 16)
			| y));
		/* offset is from DISP(2)_BASE_ADDRESS */
		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
								      (yorigin * 256)));
	}
	radeon_lock_cursor(crtc, false);

	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2007-8 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors: Dave Airlie
	24	* Alex Deucher
	25	*/
760285e7 DH	26	#include <drm/drmP.h>
760285e7 DH	27	#include <drm/radeon_drm.h>
771fe6b9 JG	28	#include "radeon.h"
	29
	30	#define CURSOR_WIDTH 64
	31	#define CURSOR_HEIGHT 64
	32
	33	static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
	34	{
	35	struct radeon_device *rdev = crtc->dev->dev_private;
	36	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	37	uint32_t cur_lock;
	38
bcc1c2a1 AD	39	if (ASIC_IS_DCE4(rdev)) {
	40	cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
	41	if (lock)
	42	cur_lock \|= EVERGREEN_CURSOR_UPDATE_LOCK;
	43	else
	44	cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
	45	WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
	46	} else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9 JG	47	cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
	48	if (lock)
	49	cur_lock \|= AVIVO_D1CURSOR_UPDATE_LOCK;
	50	else
	51	cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
	52	WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
	53	} else {
	54	cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
	55	if (lock)
	56	cur_lock \|= RADEON_CUR_LOCK;
	57	else
	58	cur_lock &= ~RADEON_CUR_LOCK;
	59	WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
	60	}
	61	}
	62
	63	static void radeon_hide_cursor(struct drm_crtc *crtc)
	64	{
	65	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	66	struct radeon_device *rdev = crtc->dev->dev_private;
	67
bcc1c2a1	68	if (ASIC_IS_DCE4(rdev)) {
2ef9bdfe DV	69	WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
	70	EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) \|
	71	EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
bcc1c2a1	72	} else if (ASIC_IS_AVIVO(rdev)) {
2ef9bdfe DV	73	WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
2ef9bdfe DV	74	(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
771fe6b9	75	} else {
2ef9bdfe	76	u32 reg;
771fe6b9 JG	77	switch (radeon_crtc->crtc_id) {
771fe6b9 JG	78	case 0:
2ef9bdfe	79	reg = RADEON_CRTC_GEN_CNTL;
771fe6b9 JG	80	break;
771fe6b9 JG	81	case 1:
2ef9bdfe	82	reg = RADEON_CRTC2_GEN_CNTL;
771fe6b9 JG	83	break;
	84	default:
	85	return;
	86	}
2ef9bdfe	87	WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
771fe6b9 JG	88	}
	89	}
	90
	91	static void radeon_show_cursor(struct drm_crtc *crtc)
	92	{
	93	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	94	struct radeon_device *rdev = crtc->dev->dev_private;
	95
bcc1c2a1 AD	96	if (ASIC_IS_DCE4(rdev)) {
	97	WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
	98	WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN \|
f4254a2b AD	99	EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) \|
f4254a2b AD	100	EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
bcc1c2a1	101	} else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9 JG	102	WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
771fe6b9 JG	103	WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN \|
bcc1c2a1	104	(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
771fe6b9 JG	105	} else {
	106	switch (radeon_crtc->crtc_id) {
	107	case 0:
	108	WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
	109	break;
	110	case 1:
	111	WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
	112	break;
	113	default:
	114	return;
	115	}
	116
	117	WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN \|
	118	(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
	119	~(RADEON_CRTC_CUR_EN \| RADEON_CRTC_CUR_MODE_MASK));
	120	}
	121	}
	122
	123	static void radeon_set_cursor(struct drm_crtc crtc, struct drm_gem_object obj,
f981d463	124	uint64_t gpu_addr)
771fe6b9 JG	125	{
	126	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	127	struct radeon_device *rdev = crtc->dev->dev_private;
	128
bcc1c2a1	129	if (ASIC_IS_DCE4(rdev)) {
f981d463 AD	130	WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
	131	upper_32_bits(gpu_addr));
	132	WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	133	gpu_addr & 0xffffffff);
bcc1c2a1	134	} else if (ASIC_IS_AVIVO(rdev)) {
c290dadf AD	135	if (rdev->family >= CHIP_RV770) {
c290dadf AD	136	if (radeon_crtc->crtc_id)
f981d463	137	WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
c290dadf	138	else
f981d463	139	WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
c290dadf	140	}
f981d463 AD	141	WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
f981d463 AD	142	gpu_addr & 0xffffffff);
c290dadf	143	} else {
c836e862	144	radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
771fe6b9	145	/* offset is from DISP(2)_BASE_ADDRESS */
c836e862 AD	146	WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
c836e862 AD	147	}
771fe6b9 JG	148	}
	149
	150	int radeon_crtc_cursor_set(struct drm_crtc *crtc,
	151	struct drm_file *file_priv,
	152	uint32_t handle,
	153	uint32_t width,
	154	uint32_t height)
	155	{
	156	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
c4353016	157	struct radeon_device *rdev = crtc->dev->dev_private;
771fe6b9	158	struct drm_gem_object *obj;
c4353016	159	struct radeon_bo *robj;
771fe6b9 JG	160	uint64_t gpu_addr;
	161	int ret;
	162
	163	if (!handle) {
	164	/* turn off cursor */
	165	radeon_hide_cursor(crtc);
	166	obj = NULL;
	167	goto unpin;
	168	}
	169
	170	if ((width > CURSOR_WIDTH) \|\| (height > CURSOR_HEIGHT)) {
	171	DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
	172	return -EINVAL;
	173	}
	174
771fe6b9 JG	175	obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
	176	if (!obj) {
	177	DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
bf79cb91	178	return -ENOENT;
771fe6b9 JG	179	}
771fe6b9 JG	180
c4353016 MD	181	robj = gem_to_radeon_bo(obj);
	182	ret = radeon_bo_reserve(robj, false);
	183	if (unlikely(ret != 0))
	184	goto fail;
	185	/* Only 27 bit offset for legacy cursor */
	186	ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
	187	ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
	188	&gpu_addr);
	189	radeon_bo_unreserve(robj);
771fe6b9 JG	190	if (ret)
	191	goto fail;
	192
45e5f6a2 IH	193	radeon_crtc->cursor_width = width;
	194	radeon_crtc->cursor_height = height;
	195
771fe6b9	196	radeon_lock_cursor(crtc, true);
771fe6b9 JG	197	radeon_set_cursor(crtc, obj, gpu_addr);
	198	radeon_show_cursor(crtc);
	199	radeon_lock_cursor(crtc, false);
	200
	201	unpin:
	202	if (radeon_crtc->cursor_bo) {
654c59cf MD	203	robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
	204	ret = radeon_bo_reserve(robj, false);
	205	if (likely(ret == 0)) {
	206	radeon_bo_unpin(robj);
	207	radeon_bo_unreserve(robj);
	208	}
bc9025bd	209	drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
771fe6b9 JG	210	}
	211
	212	radeon_crtc->cursor_bo = obj;
	213	return 0;
	214	fail:
bc9025bd	215	drm_gem_object_unreference_unlocked(obj);
771fe6b9	216
4cdb82b9	217	return ret;
771fe6b9 JG	218	}
	219
	220	int radeon_crtc_cursor_move(struct drm_crtc *crtc,
	221	int x, int y)
	222	{
	223	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	224	struct radeon_device *rdev = crtc->dev->dev_private;
	225	int xorigin = 0, yorigin = 0;
6a2a11db	226	int w = radeon_crtc->cursor_width;
771fe6b9	227
b8aee294 MD	228	if (ASIC_IS_AVIVO(rdev)) {
	229	/* avivo cursor are offset into the total surface */
	230	x += crtc->x;
	231	y += crtc->y;
	232	}
	233	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
	234
02e6859e	235	if (x < 0) {
7d309529	236	xorigin = min(-x, CURSOR_WIDTH - 1);
02e6859e MD	237	x = 0;
	238	}
	239	if (y < 0) {
7d309529	240	yorigin = min(-y, CURSOR_HEIGHT - 1);
02e6859e MD	241	y = 0;
02e6859e MD	242	}
771fe6b9	243
e521a290 JG	244	/* fixed on DCE6 and newer */
e521a290 JG	245	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
771fe6b9 JG	246	int i = 0;
	247	struct drm_crtc *crtc_p;
	248
dac35663 DV	249	/*
dac35663 DV	250	* avivo cursor image can't end on 128 pixel boundary or
771fe6b9	251	* go past the end of the frame if both crtcs are enabled
dac35663 DV	252	*
	253	* NOTE: It is safe to access crtc->enabled of other crtcs
	254	* without holding either the mode_config lock or the other
	255	* crtc's lock as long as write access to this flag _always_
	256	* grabs all locks.
771fe6b9 JG	257	*/
	258	list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
	259	if (crtc_p->enabled)
	260	i++;
	261	}
	262	if (i > 1) {
	263	int cursor_end, frame_end;
	264
	265	cursor_end = x - xorigin + w;
	266	frame_end = crtc->x + crtc->mode.crtc_hdisplay;
	267	if (cursor_end >= frame_end) {
	268	w = w - (cursor_end - frame_end);
	269	if (!(frame_end & 0x7f))
	270	w--;
	271	} else {
	272	if (!(cursor_end & 0x7f))
	273	w--;
	274	}
f60ec4c7	275	if (w <= 0) {
771fe6b9	276	w = 1;
f60ec4c7 MD	277	cursor_end = x - xorigin + w;
	278	if (!(cursor_end & 0x7f)) {
	279	x--;
	280	WARN_ON_ONCE(x < 0);
	281	}
	282	}
771fe6b9	283	}
6a2a11db	284	}
771fe6b9	285
6a2a11db AD	286	radeon_lock_cursor(crtc, true);
6a2a11db AD	287	if (ASIC_IS_DCE4(rdev)) {
02e6859e	288	WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) \| y);
6a2a11db AD	289	WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) \| yorigin);
	290	WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
	291	((w - 1) << 16) \| (radeon_crtc->cursor_height - 1));
	292	} else if (ASIC_IS_AVIVO(rdev)) {
02e6859e	293	WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) \| y);
771fe6b9 JG	294	WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) \| yorigin);
	295	WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
	296	((w - 1) << 16) \| (radeon_crtc->cursor_height - 1));
	297	} else {
	298	if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
	299	y *= 2;
	300
	301	WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
	302	(RADEON_CUR_LOCK
	303	\| (xorigin << 16)
	304	\| yorigin));
	305	WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
	306	(RADEON_CUR_LOCK
02e6859e MD	307	\| (x << 16)
02e6859e MD	308	\| y));
c836e862 AD	309	/* offset is from DISP(2)_BASE_ADDRESS */
	310	WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
	311	(yorigin * 256)));
771fe6b9 JG	312	}
	313	radeon_lock_cursor(crtc, false);
	314
	315	return 0;
	316	}