projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: evergreen.c updates for fusion
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
28d52043 33#include <linux/vgaarb.h>
6a9ee8af 34#include <linux/vga_switcheroo.h>
771fe6b9
JG		 35#include "radeon_reg.h"
36#include "radeon.h"
771fe6b9
JG		 37#include "atom.h"
38
1b5331d9
JG		 39static const char radeon_family_name[][16] = {
40 "R100",
41 "RV100",
42 "RS100",
43 "RV200",
44 "RS200",
45 "R200",
46 "RV250",
47 "RS300",
48 "RV280",
49 "R300",
50 "R350",
51 "RV350",
52 "RV380",
53 "R420",
54 "R423",
55 "RV410",
56 "RS400",
57 "RS480",
58 "RS600",
59 "RS690",
60 "RS740",
61 "RV515",
62 "R520",
63 "RV530",
64 "RV560",
65 "RV570",
66 "R580",
67 "R600",
68 "RV610",
69 "RV630",
70 "RV670",
71 "RV620",
72 "RV635",
73 "RS780",
74 "RS880",
75 "RV770",
76 "RV730",
77 "RV710",
78 "RV740",
79 "CEDAR",
80 "REDWOOD",
81 "JUNIPER",
82 "CYPRESS",
83 "HEMLOCK",
84 "LAST",
85};
86
b1e3a6d1
MD		 87/*
88 * Clear GPU surface registers.
89 */
3ce0a23d 90void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 91{
92 /* FIXME: check this out */
93 if (rdev->family < CHIP_R600) {
94 int i;
95
550e2d92
DA		 96 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
97 if (rdev->surface_regs[i].bo)
98 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
99 else
100 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 101 }
e024e110
DA		 102 /* enable surfaces */
103 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 104 }
105}
106
771fe6b9
JG		 107/*
108 * GPU scratch registers helpers function.
109 */
3ce0a23d 110void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 111{
112 int i;
113
114 /* FIXME: check this out */
115 if (rdev->family < CHIP_R300) {
116 rdev->scratch.num_reg = 5;
117 } else {
118 rdev->scratch.num_reg = 7;
119 }
724c80e1 120 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
771fe6b9
JG		 121 for (i = 0; i < rdev->scratch.num_reg; i++) {
122 rdev->scratch.free[i] = true;
724c80e1 123 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
771fe6b9
JG		 124 }
125}
126
127int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
128{
129 int i;
130
131 for (i = 0; i < rdev->scratch.num_reg; i++) {
132 if (rdev->scratch.free[i]) {
133 rdev->scratch.free[i] = false;
134 *reg = rdev->scratch.reg[i];
135 return 0;
136 }
137 }
138 return -EINVAL;
139}
140
141void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
142{
143 int i;
144
145 for (i = 0; i < rdev->scratch.num_reg; i++) {
146 if (rdev->scratch.reg[i] == reg) {
147 rdev->scratch.free[i] = true;
148 return;
149 }
150 }
151}
152
724c80e1
AD		 153void radeon_wb_disable(struct radeon_device *rdev)
154{
155 int r;
156
157 if (rdev->wb.wb_obj) {
158 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
159 if (unlikely(r != 0))
160 return;
161 radeon_bo_kunmap(rdev->wb.wb_obj);
162 radeon_bo_unpin(rdev->wb.wb_obj);
163 radeon_bo_unreserve(rdev->wb.wb_obj);
164 }
165 rdev->wb.enabled = false;
166}
167
168void radeon_wb_fini(struct radeon_device *rdev)
169{
170 radeon_wb_disable(rdev);
171 if (rdev->wb.wb_obj) {
172 radeon_bo_unref(&rdev->wb.wb_obj);
173 rdev->wb.wb = NULL;
174 rdev->wb.wb_obj = NULL;
175 }
176}
177
178int radeon_wb_init(struct radeon_device *rdev)
179{
180 int r;
181
182 if (rdev->wb.wb_obj == NULL) {
268b2510 183 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
724c80e1
AD		 184 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
185 if (r) {
186 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
187 return r;
188 }
189 }
190 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
191 if (unlikely(r != 0)) {
192 radeon_wb_fini(rdev);
193 return r;
194 }
195 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
196 &rdev->wb.gpu_addr);
197 if (r) {
198 radeon_bo_unreserve(rdev->wb.wb_obj);
199 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
200 radeon_wb_fini(rdev);
201 return r;
202 }
203 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
204 radeon_bo_unreserve(rdev->wb.wb_obj);
205 if (r) {
206 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
207 radeon_wb_fini(rdev);
208 return r;
209 }
210
d0f8a854
AD		 211 /* disable event_write fences */
212 rdev->wb.use_event = false;
724c80e1
AD		 213 /* disabled via module param */
214 if (radeon_no_wb == 1)
215 rdev->wb.enabled = false;
216 else {
217 /* often unreliable on AGP */
218 if (rdev->flags & RADEON_IS_AGP) {
219 rdev->wb.enabled = false;
d0f8a854 220 } else {
724c80e1 221 rdev->wb.enabled = true;
d0f8a854
AD		 222 /* event_write fences are only available on r600+ */
223 if (rdev->family >= CHIP_R600)
224 rdev->wb.use_event = true;
225 }
724c80e1
AD		 226 }
227
228 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
229
230 return 0;
231}
232
d594e46a
JG		 233/**
234 * radeon_vram_location - try to find VRAM location
235 * @rdev: radeon device structure holding all necessary informations
236 * @mc: memory controller structure holding memory informations
237 * @base: base address at which to put VRAM
238 *
239 * Function will place try to place VRAM at base address provided
240 * as parameter (which is so far either PCI aperture address or
241 * for IGP TOM base address).
242 *
243 * If there is not enough space to fit the unvisible VRAM in the 32bits
244 * address space then we limit the VRAM size to the aperture.
245 *
246 * If we are using AGP and if the AGP aperture doesn't allow us to have
247 * room for all the VRAM than we restrict the VRAM to the PCI aperture
248 * size and print a warning.
249 *
250 * This function will never fails, worst case are limiting VRAM.
251 *
252 * Note: GTT start, end, size should be initialized before calling this
253 * function on AGP platform.
254 *
255 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
256 * this shouldn't be a problem as we are using the PCI aperture as a reference.
257 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
258 * not IGP.
259 *
260 * Note: we use mc_vram_size as on some board we need to program the mc to
261 * cover the whole aperture even if VRAM size is inferior to aperture size
262 * Novell bug 204882 + along with lots of ubuntu ones
263 *
264 * Note: when limiting vram it's safe to overwritte real_vram_size because
265 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
266 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
267 * ones)
268 *
269 * Note: IGP TOM addr should be the same as the aperture addr, we don't
270 * explicitly check for that thought.
271 *
272 * FIXME: when reducing VRAM size align new size on power of 2.
771fe6b9 273 */
d594e46a 274void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
771fe6b9 275{
d594e46a
JG		 276 mc->vram_start = base;
277 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
278 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
279 mc->real_vram_size = mc->aper_size;
280 mc->mc_vram_size = mc->aper_size;
281 }
282 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2cbeb4ef 283 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
d594e46a
JG		 284 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
285 mc->real_vram_size = mc->aper_size;
286 mc->mc_vram_size = mc->aper_size;
287 }
288 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
289 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
290 mc->mc_vram_size >> 20, mc->vram_start,
291 mc->vram_end, mc->real_vram_size >> 20);
292}
771fe6b9 293
d594e46a
JG		 294/**
295 * radeon_gtt_location - try to find GTT location
296 * @rdev: radeon device structure holding all necessary informations
297 * @mc: memory controller structure holding memory informations
298 *
299 * Function will place try to place GTT before or after VRAM.
300 *
301 * If GTT size is bigger than space left then we ajust GTT size.
302 * Thus function will never fails.
303 *
304 * FIXME: when reducing GTT size align new size on power of 2.
305 */
306void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
307{
308 u64 size_af, size_bf;
309
8d369bb1
AD		 310 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
311 size_bf = mc->vram_start & ~mc->gtt_base_align;
d594e46a
JG		 312 if (size_bf > size_af) {
313 if (mc->gtt_size > size_bf) {
314 dev_warn(rdev->dev, "limiting GTT\n");
315 mc->gtt_size = size_bf;
771fe6b9 316 }
8d369bb1 317 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
771fe6b9 318 } else {
d594e46a
JG		 319 if (mc->gtt_size > size_af) {
320 dev_warn(rdev->dev, "limiting GTT\n");
321 mc->gtt_size = size_af;
322 }
8d369bb1 323 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
771fe6b9 324 }
d594e46a
JG		 325 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
326 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
327 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
771fe6b9
JG		 328}
329
771fe6b9
JG		 330/*
331 * GPU helpers function.
332 */
9f022ddf 333bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 334{
335 uint32_t reg;
336
337 /* first check CRTCs */
18007401
AD		 338 if (ASIC_IS_DCE41(rdev)) {
339 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
340 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
341 if (reg & EVERGREEN_CRTC_MASTER_EN)
342 return true;
343 } else if (ASIC_IS_DCE4(rdev)) {
bcc1c2a1
AD		 344 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
345 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
346 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
347 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
348 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
349 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
350 if (reg & EVERGREEN_CRTC_MASTER_EN)
351 return true;
352 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 353 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
354 RREG32(AVIVO_D2CRTC_CONTROL);
355 if (reg & AVIVO_CRTC_EN) {
356 return true;
357 }
358 } else {
359 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
360 RREG32(RADEON_CRTC2_GEN_CNTL);
361 if (reg & RADEON_CRTC_EN) {
362 return true;
363 }
364 }
365
366 /* then check MEM_SIZE, in case the crtcs are off */
367 if (rdev->family >= CHIP_R600)
368 reg = RREG32(R600_CONFIG_MEMSIZE);
369 else
370 reg = RREG32(RADEON_CONFIG_MEMSIZE);
371
372 if (reg)
373 return true;
374
375 return false;
376
377}
378
f47299c5
AD		 379void radeon_update_bandwidth_info(struct radeon_device *rdev)
380{
381 fixed20_12 a;
8807286e
AD		 382 u32 sclk = rdev->pm.current_sclk;
383 u32 mclk = rdev->pm.current_mclk;
f47299c5 384
8807286e
AD		 385 /* sclk/mclk in Mhz */
386 a.full = dfixed_const(100);
387 rdev->pm.sclk.full = dfixed_const(sclk);
388 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
389 rdev->pm.mclk.full = dfixed_const(mclk);
390 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
f47299c5 391
8807286e 392 if (rdev->flags & RADEON_IS_IGP) {
68adac5e 393 a.full = dfixed_const(16);
f47299c5 394 /* core_bandwidth = sclk(Mhz) * 16 */
68adac5e 395 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
f47299c5
AD		 396 }
397}
398
72542d77
DA		 399bool radeon_boot_test_post_card(struct radeon_device *rdev)
400{
401 if (radeon_card_posted(rdev))
402 return true;
403
404 if (rdev->bios) {
405 DRM_INFO("GPU not posted. posting now...\n");
406 if (rdev->is_atom_bios)
407 atom_asic_init(rdev->mode_info.atom_context);
408 else
409 radeon_combios_asic_init(rdev->ddev);
410 return true;
411 } else {
412 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
413 return false;
414 }
415}
416
3ce0a23d
JG		 417int radeon_dummy_page_init(struct radeon_device *rdev)
418{
82568565
DA		 419 if (rdev->dummy_page.page)
420 return 0;
3ce0a23d
JG		 421 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
422 if (rdev->dummy_page.page == NULL)
423 return -ENOMEM;
424 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
425 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
a30f6fb7
BH		 426 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
427 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
3ce0a23d
JG		 428 __free_page(rdev->dummy_page.page);
429 rdev->dummy_page.page = NULL;
430 return -ENOMEM;
431 }
432 return 0;
433}
434
435void radeon_dummy_page_fini(struct radeon_device *rdev)
436{
437 if (rdev->dummy_page.page == NULL)
438 return;
439 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
440 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
441 __free_page(rdev->dummy_page.page);
442 rdev->dummy_page.page = NULL;
443}
444
771fe6b9 445
771fe6b9
JG		 446/* ATOM accessor methods */
447static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
448{
449 struct radeon_device *rdev = info->dev->dev_private;
450 uint32_t r;
451
452 r = rdev->pll_rreg(rdev, reg);
453 return r;
454}
455
456static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
457{
458 struct radeon_device *rdev = info->dev->dev_private;
459
460 rdev->pll_wreg(rdev, reg, val);
461}
462
463static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
464{
465 struct radeon_device *rdev = info->dev->dev_private;
466 uint32_t r;
467
468 r = rdev->mc_rreg(rdev, reg);
469 return r;
470}
471
472static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
473{
474 struct radeon_device *rdev = info->dev->dev_private;
475
476 rdev->mc_wreg(rdev, reg, val);
477}
478
479static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
480{
481 struct radeon_device *rdev = info->dev->dev_private;
482
483 WREG32(reg*4, val);
484}
485
486static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
487{
488 struct radeon_device *rdev = info->dev->dev_private;
489 uint32_t r;
490
491 r = RREG32(reg*4);
492 return r;
493}
494
351a52a2
AD		 495static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
496{
497 struct radeon_device *rdev = info->dev->dev_private;
498
499 WREG32_IO(reg*4, val);
500}
501
502static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
503{
504 struct radeon_device *rdev = info->dev->dev_private;
505 uint32_t r;
506
507 r = RREG32_IO(reg*4);
508 return r;
509}
510
771fe6b9
JG		 511int radeon_atombios_init(struct radeon_device *rdev)
512{
61c4b24b
MF		 513 struct card_info *atom_card_info =
514 kzalloc(sizeof(struct card_info), GFP_KERNEL);
515
516 if (!atom_card_info)
517 return -ENOMEM;
518
519 rdev->mode_info.atom_card_info = atom_card_info;
520 atom_card_info->dev = rdev->ddev;
521 atom_card_info->reg_read = cail_reg_read;
522 atom_card_info->reg_write = cail_reg_write;
351a52a2
AD		 523 /* needed for iio ops */
524 if (rdev->rio_mem) {
525 atom_card_info->ioreg_read = cail_ioreg_read;
526 atom_card_info->ioreg_write = cail_ioreg_write;
527 } else {
528 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
529 atom_card_info->ioreg_read = cail_reg_read;
530 atom_card_info->ioreg_write = cail_reg_write;
531 }
61c4b24b
MF		 532 atom_card_info->mc_read = cail_mc_read;
533 atom_card_info->mc_write = cail_mc_write;
534 atom_card_info->pll_read = cail_pll_read;
535 atom_card_info->pll_write = cail_pll_write;
536
537 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 538 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 539 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 540 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 541 return 0;
542}
543
544void radeon_atombios_fini(struct radeon_device *rdev)
545{
4a04a844
JG		 546 if (rdev->mode_info.atom_context) {
547 kfree(rdev->mode_info.atom_context->scratch);
548 kfree(rdev->mode_info.atom_context);
549 }
61c4b24b 550 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 551}
552
553int radeon_combios_init(struct radeon_device *rdev)
554{
555 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
556 return 0;
557}
558
559void radeon_combios_fini(struct radeon_device *rdev)
560{
561}
562
28d52043
DA		 563/* if we get transitioned to only one device, tak VGA back */
564static unsigned int radeon_vga_set_decode(void *cookie, bool state)
565{
566 struct radeon_device *rdev = cookie;
28d52043
DA		 567 radeon_vga_set_state(rdev, state);
568 if (state)
569 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
570 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
571 else
572 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
573}
c1176d6f 574
36421338
JG		 575void radeon_check_arguments(struct radeon_device *rdev)
576{
577 /* vramlimit must be a power of two */
578 switch (radeon_vram_limit) {
579 case 0:
580 case 4:
581 case 8:
582 case 16:
583 case 32:
584 case 64:
585 case 128:
586 case 256:
587 case 512:
588 case 1024:
589 case 2048:
590 case 4096:
591 break;
592 default:
593 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
594 radeon_vram_limit);
595 radeon_vram_limit = 0;
596 break;
597 }
598 radeon_vram_limit = radeon_vram_limit << 20;
599 /* gtt size must be power of two and greater or equal to 32M */
600 switch (radeon_gart_size) {
601 case 4:
602 case 8:
603 case 16:
604 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
605 radeon_gart_size);
606 radeon_gart_size = 512;
607 break;
608 case 32:
609 case 64:
610 case 128:
611 case 256:
612 case 512:
613 case 1024:
614 case 2048:
615 case 4096:
616 break;
617 default:
618 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
619 radeon_gart_size);
620 radeon_gart_size = 512;
621 break;
622 }
623 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
624 /* AGP mode can only be -1, 1, 2, 4, 8 */
625 switch (radeon_agpmode) {
626 case -1:
627 case 0:
628 case 1:
629 case 2:
630 case 4:
631 case 8:
632 break;
633 default:
634 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
635 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
636 radeon_agpmode = 0;
637 break;
638 }
639}
640
6a9ee8af
DA		 641static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
642{
643 struct drm_device *dev = pci_get_drvdata(pdev);
644 struct radeon_device *rdev = dev->dev_private;
645 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
646 if (state == VGA_SWITCHEROO_ON) {
647 printk(KERN_INFO "radeon: switched on\n");
648 /* don't suspend or resume card normally */
649 rdev->powered_down = false;
650 radeon_resume_kms(dev);
fbf81762 651 drm_kms_helper_poll_enable(dev);
6a9ee8af
DA		 652 } else {
653 printk(KERN_INFO "radeon: switched off\n");
fbf81762 654 drm_kms_helper_poll_disable(dev);
6a9ee8af
DA		 655 radeon_suspend_kms(dev, pmm);
656 /* don't suspend or resume card normally */
657 rdev->powered_down = true;
658 }
659}
660
661static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
662{
663 struct drm_device *dev = pci_get_drvdata(pdev);
664 bool can_switch;
665
666 spin_lock(&dev->count_lock);
667 can_switch = (dev->open_count == 0);
668 spin_unlock(&dev->count_lock);
669 return can_switch;
670}
671
672
771fe6b9
JG		 673int radeon_device_init(struct radeon_device *rdev,
674 struct drm_device *ddev,
675 struct pci_dev *pdev,
676 uint32_t flags)
677{
351a52a2 678 int r, i;
ad49f501 679 int dma_bits;
771fe6b9 680
771fe6b9 681 rdev->shutdown = false;
9f022ddf 682 rdev->dev = &pdev->dev;
771fe6b9
JG		 683 rdev->ddev = ddev;
684 rdev->pdev = pdev;
685 rdev->flags = flags;
686 rdev->family = flags & RADEON_FAMILY_MASK;
687 rdev->is_atom_bios = false;
688 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
689 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
690 rdev->gpu_lockup = false;
733289c2 691 rdev->accel_working = false;
1b5331d9
JG		 692
693 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
694 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
695
771fe6b9
JG		 696 /* mutex initialization are all done here so we
697 * can recall function without having locking issues */
698 mutex_init(&rdev->cs_mutex);
699 mutex_init(&rdev->ib_pool.mutex);
700 mutex_init(&rdev->cp.mutex);
40bacf16 701 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 702 if (rdev->family >= CHIP_R600)
703 spin_lock_init(&rdev->ih.lock);
4c788679 704 mutex_init(&rdev->gem.mutex);
c913e23a 705 mutex_init(&rdev->pm.mutex);
5876dd24 706 mutex_init(&rdev->vram_mutex);
771fe6b9 707 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 708 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 709 init_waitqueue_head(&rdev->irq.vblank_queue);
2031f77c 710 init_waitqueue_head(&rdev->irq.idle_queue);
771fe6b9 711
d4877cf2
AD		 712 /* setup workqueue */
713 rdev->wq = create_workqueue("radeon");
714 if (rdev->wq == NULL)
715 return -ENOMEM;
716
4aac0473
JG		 717 /* Set asic functions */
718 r = radeon_asic_init(rdev);
36421338 719 if (r)
4aac0473 720 return r;
36421338 721 radeon_check_arguments(rdev);
4aac0473 722
f95df9ca
AD		 723 /* all of the newer IGP chips have an internal gart
724 * However some rs4xx report as AGP, so remove that here.
725 */
726 if ((rdev->family >= CHIP_RS400) &&
727 (rdev->flags & RADEON_IS_IGP)) {
728 rdev->flags &= ~RADEON_IS_AGP;
729 }
730
30256a3f 731 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 732 radeon_agp_disable(rdev);
771fe6b9
JG		 733 }
734
ad49f501
DA		 735 /* set DMA mask + need_dma32 flags.
736 * PCIE - can handle 40-bits.
737 * IGP - can handle 40-bits (in theory)
738 * AGP - generally dma32 is safest
739 * PCI - only dma32
740 */
741 rdev->need_dma32 = false;
742 if (rdev->flags & RADEON_IS_AGP)
743 rdev->need_dma32 = true;
744 if (rdev->flags & RADEON_IS_PCI)
745 rdev->need_dma32 = true;
746
747 dma_bits = rdev->need_dma32 ? 32 : 40;
748 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 749 if (r) {
750 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
751 }
752
753 /* Registers mapping */
754 /* TODO: block userspace mapping of io register */
01d73a69
JC		 755 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
756 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
771fe6b9
JG		 757 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
758 if (rdev->rmmio == NULL) {
759 return -ENOMEM;
760 }
761 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
762 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
763
351a52a2
AD		 764 /* io port mapping */
765 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
766 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
767 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
768 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
769 break;
770 }
771 }
772 if (rdev->rio_mem == NULL)
773 DRM_ERROR("Unable to find PCI I/O BAR\n");
774
28d52043 775 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 776 /* this will fail for cards that aren't VGA class devices, just
777 * ignore it */
778 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
6a9ee8af
DA		 779 vga_switcheroo_register_client(rdev->pdev,
780 radeon_switcheroo_set_state,
781 radeon_switcheroo_can_switch);
28d52043 782
3ce0a23d 783 r = radeon_init(rdev);
b574f251 784 if (r)
3ce0a23d 785 return r;
3ce0a23d 786
b574f251
JG		 787 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
788 /* Acceleration not working on AGP card try again
789 * with fallback to PCI or PCIE GART
790 */
a2d07b74 791 radeon_asic_reset(rdev);
b574f251
JG		 792 radeon_fini(rdev);
793 radeon_agp_disable(rdev);
794 r = radeon_init(rdev);
4aac0473
JG		 795 if (r)
796 return r;
771fe6b9 797 }
ecc0b326
MD		 798 if (radeon_testing) {
799 radeon_test_moves(rdev);
800 }
771fe6b9
JG		 801 if (radeon_benchmarking) {
802 radeon_benchmark(rdev);
803 }
6cf8a3f5 804 return 0;
771fe6b9
JG		 805}
806
807void radeon_device_fini(struct radeon_device *rdev)
808{
771fe6b9
JG		 809 DRM_INFO("radeon: finishing device.\n");
810 rdev->shutdown = true;
90aca4d2
JG		 811 /* evict vram memory */
812 radeon_bo_evict_vram(rdev);
62a8ea3f 813 radeon_fini(rdev);
d4877cf2 814 destroy_workqueue(rdev->wq);
6a9ee8af 815 vga_switcheroo_unregister_client(rdev->pdev);
c1176d6f 816 vga_client_register(rdev->pdev, NULL, NULL, NULL);
e0a2ca73
AD		 817 if (rdev->rio_mem)
818 pci_iounmap(rdev->pdev, rdev->rio_mem);
351a52a2 819 rdev->rio_mem = NULL;
771fe6b9
JG		 820 iounmap(rdev->rmmio);
821 rdev->rmmio = NULL;
822}
823
824
825/*
826 * Suspend & resume.
827 */
828int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
829{
875c1866 830 struct radeon_device *rdev;
771fe6b9 831 struct drm_crtc *crtc;
d8dcaa1d 832 struct drm_connector *connector;
4c788679 833 int r;
771fe6b9 834
875c1866 835 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 836 return -ENODEV;
837 }
838 if (state.event == PM_EVENT_PRETHAW) {
839 return 0;
840 }
875c1866
DJ		 841 rdev = dev->dev_private;
842
6a9ee8af
DA		 843 if (rdev->powered_down)
844 return 0;
d8dcaa1d
AD		 845
846 /* turn off display hw */
847 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
848 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
849 }
850
771fe6b9
JG		 851 /* unpin the front buffers */
852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
853 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 854 struct radeon_bo *robj;
771fe6b9
JG		 855
856 if (rfb == NULL || rfb->obj == NULL) {
857 continue;
858 }
859 robj = rfb->obj->driver_private;
38651674
DA		 860 /* don't unpin kernel fb objects */
861 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
4c788679 862 r = radeon_bo_reserve(robj, false);
38651674 863 if (r == 0) {
4c788679
JG		 864 radeon_bo_unpin(robj);
865 radeon_bo_unreserve(robj);
866 }
771fe6b9
JG		 867 }
868 }
869 /* evict vram memory */
4c788679 870 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 871 /* wait for gpu to finish processing current batch */
872 radeon_fence_wait_last(rdev);
873
f657c2a7
YZ		 874 radeon_save_bios_scratch_regs(rdev);
875
ce8f5370 876 radeon_pm_suspend(rdev);
62a8ea3f 877 radeon_suspend(rdev);
d4877cf2 878 radeon_hpd_fini(rdev);
771fe6b9 879 /* evict remaining vram memory */
4c788679 880 radeon_bo_evict_vram(rdev);
771fe6b9 881
10b06122
JG		 882 radeon_agp_suspend(rdev);
883
771fe6b9
JG		 884 pci_save_state(dev->pdev);
885 if (state.event == PM_EVENT_SUSPEND) {
886 /* Shut down the device */
887 pci_disable_device(dev->pdev);
888 pci_set_power_state(dev->pdev, PCI_D3hot);
889 }
890 acquire_console_sem();
38651674 891 radeon_fbdev_set_suspend(rdev, 1);
771fe6b9
JG		 892 release_console_sem();
893 return 0;
894}
895
896int radeon_resume_kms(struct drm_device *dev)
897{
09bdf591 898 struct drm_connector *connector;
771fe6b9 899 struct radeon_device *rdev = dev->dev_private;
771fe6b9 900
6a9ee8af
DA		 901 if (rdev->powered_down)
902 return 0;
903
771fe6b9
JG		 904 acquire_console_sem();
905 pci_set_power_state(dev->pdev, PCI_D0);
906 pci_restore_state(dev->pdev);
907 if (pci_enable_device(dev->pdev)) {
908 release_console_sem();
909 return -1;
910 }
911 pci_set_master(dev->pdev);
0ebf1717
DA		 912 /* resume AGP if in use */
913 radeon_agp_resume(rdev);
62a8ea3f 914 radeon_resume(rdev);
ce8f5370 915 radeon_pm_resume(rdev);
f657c2a7 916 radeon_restore_bios_scratch_regs(rdev);
09bdf591
CG		 917
918 /* turn on display hw */
919 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
920 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
921 }
922
38651674 923 radeon_fbdev_set_suspend(rdev, 0);
771fe6b9
JG		 924 release_console_sem();
925
d4877cf2
AD		 926 /* reset hpd state */
927 radeon_hpd_init(rdev);
771fe6b9
JG		 928 /* blat the mode back in */
929 drm_helper_resume_force_mode(dev);
930 return 0;
931}
932
90aca4d2
JG		 933int radeon_gpu_reset(struct radeon_device *rdev)
934{
935 int r;
936
937 radeon_save_bios_scratch_regs(rdev);
938 radeon_suspend(rdev);
939
940 r = radeon_asic_reset(rdev);
941 if (!r) {
942 dev_info(rdev->dev, "GPU reset succeed\n");
943 radeon_resume(rdev);
944 radeon_restore_bios_scratch_regs(rdev);
945 drm_helper_resume_force_mode(rdev->ddev);
946 return 0;
947 }
948 /* bad news, how to tell it to userspace ? */
949 dev_info(rdev->dev, "GPU reset failed\n");
950 return r;
951}
952
771fe6b9
JG		 953
954/*
955 * Debugfs
956 */
957struct radeon_debugfs {
958 struct drm_info_list *files;
959 unsigned num_files;
960};
961static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
962static unsigned _radeon_debugfs_count = 0;
963
964int radeon_debugfs_add_files(struct radeon_device *rdev,
965 struct drm_info_list *files,
966 unsigned nfiles)
967{
968 unsigned i;
969
970 for (i = 0; i < _radeon_debugfs_count; i++) {
971 if (_radeon_debugfs[i].files == files) {
972 /* Already registered */
973 return 0;
974 }
975 }
976 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
977 DRM_ERROR("Reached maximum number of debugfs files.\n");
978 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
979 return -EINVAL;
980 }
981 _radeon_debugfs[_radeon_debugfs_count].files = files;
982 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
983 _radeon_debugfs_count++;
984#if defined(CONFIG_DEBUG_FS)
985 drm_debugfs_create_files(files, nfiles,
986 rdev->ddev->control->debugfs_root,
987 rdev->ddev->control);
988 drm_debugfs_create_files(files, nfiles,
989 rdev->ddev->primary->debugfs_root,
990 rdev->ddev->primary);
991#endif
992 return 0;
993}
994
995#if defined(CONFIG_DEBUG_FS)
996int radeon_debugfs_init(struct drm_minor *minor)
997{
998 return 0;
999}
1000
1001void radeon_debugfs_cleanup(struct drm_minor *minor)
1002{
1003 unsigned i;
1004
1005 for (i = 0; i < _radeon_debugfs_count; i++) {
1006 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1007 _radeon_debugfs[i].num_files, minor);
1008 }
1009}
1010#endif
Linux kernel - Deliverables
This page took 0.156915 seconds and 5 git commands to generate.