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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_crtc_helper.h> | |
31 | #include <drm/radeon_drm.h> | |
32 | #include "radeon_reg.h" | |
33 | #include "radeon.h" | |
34 | #include "radeon_asic.h" | |
35 | #include "atom.h" | |
36 | ||
b1e3a6d1 MD |
37 | /* |
38 | * Clear GPU surface registers. | |
39 | */ | |
40 | static void radeon_surface_init(struct radeon_device *rdev) | |
41 | { | |
42 | /* FIXME: check this out */ | |
43 | if (rdev->family < CHIP_R600) { | |
44 | int i; | |
45 | ||
46 | for (i = 0; i < 8; i++) { | |
47 | WREG32(RADEON_SURFACE0_INFO + | |
48 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), | |
49 | 0); | |
50 | } | |
51 | } | |
52 | } | |
53 | ||
771fe6b9 JG |
54 | /* |
55 | * GPU scratch registers helpers function. | |
56 | */ | |
57 | static void radeon_scratch_init(struct radeon_device *rdev) | |
58 | { | |
59 | int i; | |
60 | ||
61 | /* FIXME: check this out */ | |
62 | if (rdev->family < CHIP_R300) { | |
63 | rdev->scratch.num_reg = 5; | |
64 | } else { | |
65 | rdev->scratch.num_reg = 7; | |
66 | } | |
67 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
68 | rdev->scratch.free[i] = true; | |
69 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); | |
70 | } | |
71 | } | |
72 | ||
73 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) | |
74 | { | |
75 | int i; | |
76 | ||
77 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
78 | if (rdev->scratch.free[i]) { | |
79 | rdev->scratch.free[i] = false; | |
80 | *reg = rdev->scratch.reg[i]; | |
81 | return 0; | |
82 | } | |
83 | } | |
84 | return -EINVAL; | |
85 | } | |
86 | ||
87 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) | |
88 | { | |
89 | int i; | |
90 | ||
91 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
92 | if (rdev->scratch.reg[i] == reg) { | |
93 | rdev->scratch.free[i] = true; | |
94 | return; | |
95 | } | |
96 | } | |
97 | } | |
98 | ||
99 | /* | |
100 | * MC common functions | |
101 | */ | |
102 | int radeon_mc_setup(struct radeon_device *rdev) | |
103 | { | |
104 | uint32_t tmp; | |
105 | ||
106 | /* Some chips have an "issue" with the memory controller, the | |
107 | * location must be aligned to the size. We just align it down, | |
108 | * too bad if we walk over the top of system memory, we don't | |
109 | * use DMA without a remapped anyway. | |
110 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP | |
111 | */ | |
112 | /* FGLRX seems to setup like this, VRAM a 0, then GART. | |
113 | */ | |
114 | /* | |
115 | * Note: from R6xx the address space is 40bits but here we only | |
116 | * use 32bits (still have to see a card which would exhaust 4G | |
117 | * address space). | |
118 | */ | |
119 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { | |
120 | /* vram location was already setup try to put gtt after | |
121 | * if it fits */ | |
122 | tmp = rdev->mc.vram_location + rdev->mc.vram_size; | |
123 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); | |
124 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { | |
125 | rdev->mc.gtt_location = tmp; | |
126 | } else { | |
127 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { | |
128 | printk(KERN_ERR "[drm] GTT too big to fit " | |
129 | "before or after vram location.\n"); | |
130 | return -EINVAL; | |
131 | } | |
132 | rdev->mc.gtt_location = 0; | |
133 | } | |
134 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { | |
135 | /* gtt location was already setup try to put vram before | |
136 | * if it fits */ | |
137 | if (rdev->mc.vram_size < rdev->mc.gtt_location) { | |
138 | rdev->mc.vram_location = 0; | |
139 | } else { | |
140 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; | |
141 | tmp += (rdev->mc.vram_size - 1); | |
142 | tmp &= ~(rdev->mc.vram_size - 1); | |
143 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { | |
144 | rdev->mc.vram_location = tmp; | |
145 | } else { | |
146 | printk(KERN_ERR "[drm] vram too big to fit " | |
147 | "before or after GTT location.\n"); | |
148 | return -EINVAL; | |
149 | } | |
150 | } | |
151 | } else { | |
152 | rdev->mc.vram_location = 0; | |
153 | rdev->mc.gtt_location = rdev->mc.vram_size; | |
154 | } | |
155 | DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); | |
156 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", | |
157 | rdev->mc.vram_location, | |
158 | rdev->mc.vram_location + rdev->mc.vram_size - 1); | |
159 | DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); | |
160 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", | |
161 | rdev->mc.gtt_location, | |
162 | rdev->mc.gtt_location + rdev->mc.gtt_size - 1); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | ||
167 | /* | |
168 | * GPU helpers function. | |
169 | */ | |
170 | static bool radeon_card_posted(struct radeon_device *rdev) | |
171 | { | |
172 | uint32_t reg; | |
173 | ||
174 | /* first check CRTCs */ | |
175 | if (ASIC_IS_AVIVO(rdev)) { | |
176 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | | |
177 | RREG32(AVIVO_D2CRTC_CONTROL); | |
178 | if (reg & AVIVO_CRTC_EN) { | |
179 | return true; | |
180 | } | |
181 | } else { | |
182 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
183 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
184 | if (reg & RADEON_CRTC_EN) { | |
185 | return true; | |
186 | } | |
187 | } | |
188 | ||
189 | /* then check MEM_SIZE, in case the crtcs are off */ | |
190 | if (rdev->family >= CHIP_R600) | |
191 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
192 | else | |
193 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
194 | ||
195 | if (reg) | |
196 | return true; | |
197 | ||
198 | return false; | |
199 | ||
200 | } | |
201 | ||
202 | ||
203 | /* | |
204 | * Registers accessors functions. | |
205 | */ | |
206 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | |
207 | { | |
208 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
209 | BUG_ON(1); | |
210 | return 0; | |
211 | } | |
212 | ||
213 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
214 | { | |
215 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
216 | reg, v); | |
217 | BUG_ON(1); | |
218 | } | |
219 | ||
220 | void radeon_register_accessor_init(struct radeon_device *rdev) | |
221 | { | |
222 | rdev->mm_rreg = &r100_mm_rreg; | |
223 | rdev->mm_wreg = &r100_mm_wreg; | |
224 | rdev->mc_rreg = &radeon_invalid_rreg; | |
225 | rdev->mc_wreg = &radeon_invalid_wreg; | |
226 | rdev->pll_rreg = &radeon_invalid_rreg; | |
227 | rdev->pll_wreg = &radeon_invalid_wreg; | |
228 | rdev->pcie_rreg = &radeon_invalid_rreg; | |
229 | rdev->pcie_wreg = &radeon_invalid_wreg; | |
230 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
231 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
232 | ||
233 | /* Don't change order as we are overridding accessor. */ | |
234 | if (rdev->family < CHIP_RV515) { | |
235 | rdev->pcie_rreg = &rv370_pcie_rreg; | |
236 | rdev->pcie_wreg = &rv370_pcie_wreg; | |
237 | } | |
238 | if (rdev->family >= CHIP_RV515) { | |
239 | rdev->pcie_rreg = &rv515_pcie_rreg; | |
240 | rdev->pcie_wreg = &rv515_pcie_wreg; | |
241 | } | |
242 | /* FIXME: not sure here */ | |
243 | if (rdev->family <= CHIP_R580) { | |
244 | rdev->pll_rreg = &r100_pll_rreg; | |
245 | rdev->pll_wreg = &r100_pll_wreg; | |
246 | } | |
247 | if (rdev->family >= CHIP_RV515) { | |
248 | rdev->mc_rreg = &rv515_mc_rreg; | |
249 | rdev->mc_wreg = &rv515_mc_wreg; | |
250 | } | |
251 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
252 | rdev->mc_rreg = &rs400_mc_rreg; | |
253 | rdev->mc_wreg = &rs400_mc_wreg; | |
254 | } | |
255 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
256 | rdev->mc_rreg = &rs690_mc_rreg; | |
257 | rdev->mc_wreg = &rs690_mc_wreg; | |
258 | } | |
259 | if (rdev->family == CHIP_RS600) { | |
260 | rdev->mc_rreg = &rs600_mc_rreg; | |
261 | rdev->mc_wreg = &rs600_mc_wreg; | |
262 | } | |
263 | if (rdev->family >= CHIP_R600) { | |
264 | rdev->pciep_rreg = &r600_pciep_rreg; | |
265 | rdev->pciep_wreg = &r600_pciep_wreg; | |
266 | } | |
267 | } | |
268 | ||
269 | ||
270 | /* | |
271 | * ASIC | |
272 | */ | |
273 | int radeon_asic_init(struct radeon_device *rdev) | |
274 | { | |
275 | radeon_register_accessor_init(rdev); | |
276 | switch (rdev->family) { | |
277 | case CHIP_R100: | |
278 | case CHIP_RV100: | |
279 | case CHIP_RS100: | |
280 | case CHIP_RV200: | |
281 | case CHIP_RS200: | |
282 | case CHIP_R200: | |
283 | case CHIP_RV250: | |
284 | case CHIP_RS300: | |
285 | case CHIP_RV280: | |
286 | rdev->asic = &r100_asic; | |
287 | break; | |
288 | case CHIP_R300: | |
289 | case CHIP_R350: | |
290 | case CHIP_RV350: | |
291 | case CHIP_RV380: | |
292 | rdev->asic = &r300_asic; | |
293 | break; | |
294 | case CHIP_R420: | |
295 | case CHIP_R423: | |
296 | case CHIP_RV410: | |
297 | rdev->asic = &r420_asic; | |
298 | break; | |
299 | case CHIP_RS400: | |
300 | case CHIP_RS480: | |
301 | rdev->asic = &rs400_asic; | |
302 | break; | |
303 | case CHIP_RS600: | |
304 | rdev->asic = &rs600_asic; | |
305 | break; | |
306 | case CHIP_RS690: | |
307 | case CHIP_RS740: | |
308 | rdev->asic = &rs690_asic; | |
309 | break; | |
310 | case CHIP_RV515: | |
311 | rdev->asic = &rv515_asic; | |
312 | break; | |
313 | case CHIP_R520: | |
314 | case CHIP_RV530: | |
315 | case CHIP_RV560: | |
316 | case CHIP_RV570: | |
317 | case CHIP_R580: | |
318 | rdev->asic = &r520_asic; | |
319 | break; | |
320 | case CHIP_R600: | |
321 | case CHIP_RV610: | |
322 | case CHIP_RV630: | |
323 | case CHIP_RV620: | |
324 | case CHIP_RV635: | |
325 | case CHIP_RV670: | |
326 | case CHIP_RS780: | |
327 | case CHIP_RV770: | |
328 | case CHIP_RV730: | |
329 | case CHIP_RV710: | |
330 | default: | |
331 | /* FIXME: not supported yet */ | |
332 | return -EINVAL; | |
333 | } | |
334 | return 0; | |
335 | } | |
336 | ||
337 | ||
338 | /* | |
339 | * Wrapper around modesetting bits. | |
340 | */ | |
341 | int radeon_clocks_init(struct radeon_device *rdev) | |
342 | { | |
343 | int r; | |
344 | ||
345 | radeon_get_clock_info(rdev->ddev); | |
346 | r = radeon_static_clocks_init(rdev->ddev); | |
347 | if (r) { | |
348 | return r; | |
349 | } | |
350 | DRM_INFO("Clocks initialized !\n"); | |
351 | return 0; | |
352 | } | |
353 | ||
354 | void radeon_clocks_fini(struct radeon_device *rdev) | |
355 | { | |
356 | } | |
357 | ||
358 | /* ATOM accessor methods */ | |
359 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
360 | { | |
361 | struct radeon_device *rdev = info->dev->dev_private; | |
362 | uint32_t r; | |
363 | ||
364 | r = rdev->pll_rreg(rdev, reg); | |
365 | return r; | |
366 | } | |
367 | ||
368 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
369 | { | |
370 | struct radeon_device *rdev = info->dev->dev_private; | |
371 | ||
372 | rdev->pll_wreg(rdev, reg, val); | |
373 | } | |
374 | ||
375 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
376 | { | |
377 | struct radeon_device *rdev = info->dev->dev_private; | |
378 | uint32_t r; | |
379 | ||
380 | r = rdev->mc_rreg(rdev, reg); | |
381 | return r; | |
382 | } | |
383 | ||
384 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
385 | { | |
386 | struct radeon_device *rdev = info->dev->dev_private; | |
387 | ||
388 | rdev->mc_wreg(rdev, reg, val); | |
389 | } | |
390 | ||
391 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
392 | { | |
393 | struct radeon_device *rdev = info->dev->dev_private; | |
394 | ||
395 | WREG32(reg*4, val); | |
396 | } | |
397 | ||
398 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
399 | { | |
400 | struct radeon_device *rdev = info->dev->dev_private; | |
401 | uint32_t r; | |
402 | ||
403 | r = RREG32(reg*4); | |
404 | return r; | |
405 | } | |
406 | ||
407 | static struct card_info atom_card_info = { | |
408 | .dev = NULL, | |
409 | .reg_read = cail_reg_read, | |
410 | .reg_write = cail_reg_write, | |
411 | .mc_read = cail_mc_read, | |
412 | .mc_write = cail_mc_write, | |
413 | .pll_read = cail_pll_read, | |
414 | .pll_write = cail_pll_write, | |
415 | }; | |
416 | ||
417 | int radeon_atombios_init(struct radeon_device *rdev) | |
418 | { | |
419 | atom_card_info.dev = rdev->ddev; | |
420 | rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); | |
421 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | void radeon_atombios_fini(struct radeon_device *rdev) | |
426 | { | |
427 | kfree(rdev->mode_info.atom_context); | |
428 | } | |
429 | ||
430 | int radeon_combios_init(struct radeon_device *rdev) | |
431 | { | |
432 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
433 | return 0; | |
434 | } | |
435 | ||
436 | void radeon_combios_fini(struct radeon_device *rdev) | |
437 | { | |
438 | } | |
439 | ||
440 | int radeon_modeset_init(struct radeon_device *rdev); | |
441 | void radeon_modeset_fini(struct radeon_device *rdev); | |
442 | ||
443 | ||
444 | /* | |
445 | * Radeon device. | |
446 | */ | |
447 | int radeon_device_init(struct radeon_device *rdev, | |
448 | struct drm_device *ddev, | |
449 | struct pci_dev *pdev, | |
450 | uint32_t flags) | |
451 | { | |
452 | int r, ret; | |
ad49f501 | 453 | int dma_bits; |
771fe6b9 JG |
454 | |
455 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); | |
456 | rdev->shutdown = false; | |
457 | rdev->ddev = ddev; | |
458 | rdev->pdev = pdev; | |
459 | rdev->flags = flags; | |
460 | rdev->family = flags & RADEON_FAMILY_MASK; | |
461 | rdev->is_atom_bios = false; | |
462 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
463 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
464 | rdev->gpu_lockup = false; | |
465 | /* mutex initialization are all done here so we | |
466 | * can recall function without having locking issues */ | |
467 | mutex_init(&rdev->cs_mutex); | |
468 | mutex_init(&rdev->ib_pool.mutex); | |
469 | mutex_init(&rdev->cp.mutex); | |
470 | rwlock_init(&rdev->fence_drv.lock); | |
471 | ||
472 | if (radeon_agpmode == -1) { | |
473 | rdev->flags &= ~RADEON_IS_AGP; | |
474 | if (rdev->family > CHIP_RV515 || | |
475 | rdev->family == CHIP_RV380 || | |
476 | rdev->family == CHIP_RV410 || | |
477 | rdev->family == CHIP_R423) { | |
478 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
479 | rdev->flags |= RADEON_IS_PCIE; | |
480 | } else { | |
481 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
482 | rdev->flags |= RADEON_IS_PCI; | |
483 | } | |
484 | } | |
485 | ||
486 | /* Set asic functions */ | |
487 | r = radeon_asic_init(rdev); | |
488 | if (r) { | |
489 | return r; | |
490 | } | |
068a117c JG |
491 | r = radeon_init(rdev); |
492 | if (r) { | |
493 | return r; | |
494 | } | |
771fe6b9 | 495 | |
ad49f501 DA |
496 | /* set DMA mask + need_dma32 flags. |
497 | * PCIE - can handle 40-bits. | |
498 | * IGP - can handle 40-bits (in theory) | |
499 | * AGP - generally dma32 is safest | |
500 | * PCI - only dma32 | |
501 | */ | |
502 | rdev->need_dma32 = false; | |
503 | if (rdev->flags & RADEON_IS_AGP) | |
504 | rdev->need_dma32 = true; | |
505 | if (rdev->flags & RADEON_IS_PCI) | |
506 | rdev->need_dma32 = true; | |
507 | ||
508 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
509 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 JG |
510 | if (r) { |
511 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | |
512 | } | |
513 | ||
514 | /* Registers mapping */ | |
515 | /* TODO: block userspace mapping of io register */ | |
516 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); | |
517 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); | |
518 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); | |
519 | if (rdev->rmmio == NULL) { | |
520 | return -ENOMEM; | |
521 | } | |
522 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
523 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
524 | ||
525 | /* Setup errata flags */ | |
526 | radeon_errata(rdev); | |
527 | /* Initialize scratch registers */ | |
528 | radeon_scratch_init(rdev); | |
b1e3a6d1 MD |
529 | /* Initialize surface registers */ |
530 | radeon_surface_init(rdev); | |
531 | ||
771fe6b9 JG |
532 | /* TODO: disable VGA need to use VGA request */ |
533 | /* BIOS*/ | |
534 | if (!radeon_get_bios(rdev)) { | |
535 | if (ASIC_IS_AVIVO(rdev)) | |
536 | return -EINVAL; | |
537 | } | |
538 | if (rdev->is_atom_bios) { | |
539 | r = radeon_atombios_init(rdev); | |
540 | if (r) { | |
541 | return r; | |
542 | } | |
543 | } else { | |
544 | r = radeon_combios_init(rdev); | |
545 | if (r) { | |
546 | return r; | |
547 | } | |
548 | } | |
549 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
550 | if (radeon_gpu_reset(rdev)) { | |
551 | /* FIXME: what do we want to do here ? */ | |
552 | } | |
553 | /* check if cards are posted or not */ | |
554 | if (!radeon_card_posted(rdev) && rdev->bios) { | |
555 | DRM_INFO("GPU not posted. posting now...\n"); | |
556 | if (rdev->is_atom_bios) { | |
557 | atom_asic_init(rdev->mode_info.atom_context); | |
558 | } else { | |
559 | radeon_combios_asic_init(rdev->ddev); | |
560 | } | |
561 | } | |
562 | /* Get vram informations */ | |
563 | radeon_vram_info(rdev); | |
2a0f8918 | 564 | |
771fe6b9 JG |
565 | /* Add an MTRR for the VRAM */ |
566 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
567 | MTRR_TYPE_WRCOMB, 1); | |
568 | DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", | |
569 | rdev->mc.vram_size >> 20, | |
570 | (unsigned)rdev->mc.aper_size >> 20); | |
571 | DRM_INFO("RAM width %dbits %cDR\n", | |
572 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
573 | /* Initialize clocks */ | |
574 | r = radeon_clocks_init(rdev); | |
575 | if (r) { | |
576 | return r; | |
577 | } | |
578 | /* Initialize memory controller (also test AGP) */ | |
579 | r = radeon_mc_init(rdev); | |
580 | if (r) { | |
581 | return r; | |
582 | } | |
583 | /* Fence driver */ | |
584 | r = radeon_fence_driver_init(rdev); | |
585 | if (r) { | |
586 | return r; | |
587 | } | |
588 | r = radeon_irq_kms_init(rdev); | |
589 | if (r) { | |
590 | return r; | |
591 | } | |
592 | /* Memory manager */ | |
593 | r = radeon_object_init(rdev); | |
594 | if (r) { | |
595 | return r; | |
596 | } | |
597 | /* Initialize GART (initialize after TTM so we can allocate | |
598 | * memory through TTM but finalize after TTM) */ | |
599 | r = radeon_gart_enable(rdev); | |
600 | if (!r) { | |
601 | r = radeon_gem_init(rdev); | |
602 | } | |
603 | ||
604 | /* 1M ring buffer */ | |
605 | if (!r) { | |
606 | r = radeon_cp_init(rdev, 1024 * 1024); | |
607 | } | |
608 | if (!r) { | |
609 | r = radeon_wb_init(rdev); | |
610 | if (r) { | |
611 | DRM_ERROR("radeon: failled initializing WB (%d).\n", r); | |
612 | return r; | |
613 | } | |
614 | } | |
615 | if (!r) { | |
616 | r = radeon_ib_pool_init(rdev); | |
617 | if (r) { | |
618 | DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); | |
619 | return r; | |
620 | } | |
621 | } | |
622 | if (!r) { | |
623 | r = radeon_ib_test(rdev); | |
624 | if (r) { | |
625 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
626 | return r; | |
627 | } | |
628 | } | |
629 | ret = r; | |
630 | r = radeon_modeset_init(rdev); | |
631 | if (r) { | |
632 | return r; | |
633 | } | |
771fe6b9 JG |
634 | if (!ret) { |
635 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); | |
636 | } | |
637 | if (radeon_benchmarking) { | |
638 | radeon_benchmark(rdev); | |
639 | } | |
640 | return ret; | |
641 | } | |
642 | ||
643 | void radeon_device_fini(struct radeon_device *rdev) | |
644 | { | |
645 | if (rdev == NULL || rdev->rmmio == NULL) { | |
646 | return; | |
647 | } | |
648 | DRM_INFO("radeon: finishing device.\n"); | |
649 | rdev->shutdown = true; | |
650 | /* Order matter so becarefull if you rearrange anythings */ | |
651 | radeon_modeset_fini(rdev); | |
652 | radeon_ib_pool_fini(rdev); | |
653 | radeon_cp_fini(rdev); | |
654 | radeon_wb_fini(rdev); | |
655 | radeon_gem_fini(rdev); | |
656 | radeon_object_fini(rdev); | |
657 | /* mc_fini must be after object_fini */ | |
658 | radeon_mc_fini(rdev); | |
659 | #if __OS_HAS_AGP | |
660 | radeon_agp_fini(rdev); | |
661 | #endif | |
662 | radeon_irq_kms_fini(rdev); | |
663 | radeon_fence_driver_fini(rdev); | |
664 | radeon_clocks_fini(rdev); | |
665 | if (rdev->is_atom_bios) { | |
666 | radeon_atombios_fini(rdev); | |
667 | } else { | |
668 | radeon_combios_fini(rdev); | |
669 | } | |
670 | kfree(rdev->bios); | |
671 | rdev->bios = NULL; | |
672 | iounmap(rdev->rmmio); | |
673 | rdev->rmmio = NULL; | |
674 | } | |
675 | ||
676 | ||
677 | /* | |
678 | * Suspend & resume. | |
679 | */ | |
680 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) | |
681 | { | |
682 | struct radeon_device *rdev = dev->dev_private; | |
683 | struct drm_crtc *crtc; | |
684 | ||
685 | if (dev == NULL || rdev == NULL) { | |
686 | return -ENODEV; | |
687 | } | |
688 | if (state.event == PM_EVENT_PRETHAW) { | |
689 | return 0; | |
690 | } | |
691 | /* unpin the front buffers */ | |
692 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
693 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); | |
694 | struct radeon_object *robj; | |
695 | ||
696 | if (rfb == NULL || rfb->obj == NULL) { | |
697 | continue; | |
698 | } | |
699 | robj = rfb->obj->driver_private; | |
700 | if (robj != rdev->fbdev_robj) { | |
701 | radeon_object_unpin(robj); | |
702 | } | |
703 | } | |
704 | /* evict vram memory */ | |
705 | radeon_object_evict_vram(rdev); | |
706 | /* wait for gpu to finish processing current batch */ | |
707 | radeon_fence_wait_last(rdev); | |
708 | ||
709 | radeon_cp_disable(rdev); | |
710 | radeon_gart_disable(rdev); | |
711 | ||
712 | /* evict remaining vram memory */ | |
713 | radeon_object_evict_vram(rdev); | |
714 | ||
715 | rdev->irq.sw_int = false; | |
716 | radeon_irq_set(rdev); | |
717 | ||
718 | pci_save_state(dev->pdev); | |
719 | if (state.event == PM_EVENT_SUSPEND) { | |
720 | /* Shut down the device */ | |
721 | pci_disable_device(dev->pdev); | |
722 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
723 | } | |
724 | acquire_console_sem(); | |
725 | fb_set_suspend(rdev->fbdev_info, 1); | |
726 | release_console_sem(); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | int radeon_resume_kms(struct drm_device *dev) | |
731 | { | |
732 | struct radeon_device *rdev = dev->dev_private; | |
733 | int r; | |
734 | ||
735 | acquire_console_sem(); | |
736 | pci_set_power_state(dev->pdev, PCI_D0); | |
737 | pci_restore_state(dev->pdev); | |
738 | if (pci_enable_device(dev->pdev)) { | |
739 | release_console_sem(); | |
740 | return -1; | |
741 | } | |
742 | pci_set_master(dev->pdev); | |
743 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
744 | if (radeon_gpu_reset(rdev)) { | |
745 | /* FIXME: what do we want to do here ? */ | |
746 | } | |
747 | /* post card */ | |
748 | if (rdev->is_atom_bios) { | |
749 | atom_asic_init(rdev->mode_info.atom_context); | |
750 | } else { | |
751 | radeon_combios_asic_init(rdev->ddev); | |
752 | } | |
753 | /* Initialize clocks */ | |
754 | r = radeon_clocks_init(rdev); | |
755 | if (r) { | |
756 | release_console_sem(); | |
757 | return r; | |
758 | } | |
759 | /* Enable IRQ */ | |
760 | rdev->irq.sw_int = true; | |
761 | radeon_irq_set(rdev); | |
762 | /* Initialize GPU Memory Controller */ | |
763 | r = radeon_mc_init(rdev); | |
764 | if (r) { | |
765 | goto out; | |
766 | } | |
767 | r = radeon_gart_enable(rdev); | |
768 | if (r) { | |
769 | goto out; | |
770 | } | |
771 | r = radeon_cp_init(rdev, rdev->cp.ring_size); | |
772 | if (r) { | |
773 | goto out; | |
774 | } | |
775 | out: | |
776 | fb_set_suspend(rdev->fbdev_info, 0); | |
777 | release_console_sem(); | |
778 | ||
779 | /* blat the mode back in */ | |
780 | drm_helper_resume_force_mode(dev); | |
781 | return 0; | |
782 | } | |
783 | ||
784 | ||
785 | /* | |
786 | * Debugfs | |
787 | */ | |
788 | struct radeon_debugfs { | |
789 | struct drm_info_list *files; | |
790 | unsigned num_files; | |
791 | }; | |
792 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | |
793 | static unsigned _radeon_debugfs_count = 0; | |
794 | ||
795 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
796 | struct drm_info_list *files, | |
797 | unsigned nfiles) | |
798 | { | |
799 | unsigned i; | |
800 | ||
801 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
802 | if (_radeon_debugfs[i].files == files) { | |
803 | /* Already registered */ | |
804 | return 0; | |
805 | } | |
806 | } | |
807 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | |
808 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | |
809 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | |
810 | return -EINVAL; | |
811 | } | |
812 | _radeon_debugfs[_radeon_debugfs_count].files = files; | |
813 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | |
814 | _radeon_debugfs_count++; | |
815 | #if defined(CONFIG_DEBUG_FS) | |
816 | drm_debugfs_create_files(files, nfiles, | |
817 | rdev->ddev->control->debugfs_root, | |
818 | rdev->ddev->control); | |
819 | drm_debugfs_create_files(files, nfiles, | |
820 | rdev->ddev->primary->debugfs_root, | |
821 | rdev->ddev->primary); | |
822 | #endif | |
823 | return 0; | |
824 | } | |
825 | ||
826 | #if defined(CONFIG_DEBUG_FS) | |
827 | int radeon_debugfs_init(struct drm_minor *minor) | |
828 | { | |
829 | return 0; | |
830 | } | |
831 | ||
832 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
833 | { | |
834 | unsigned i; | |
835 | ||
836 | for (i = 0; i < _radeon_debugfs_count; i++) { | |
837 | drm_debugfs_remove_files(_radeon_debugfs[i].files, | |
838 | _radeon_debugfs[i].num_files, minor); | |
839 | } | |
840 | } | |
841 | #endif |