Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
28d52043 | 33 | #include <linux/vgaarb.h> |
6a9ee8af | 34 | #include <linux/vga_switcheroo.h> |
bcc65fd8 | 35 | #include <linux/efi.h> |
771fe6b9 JG |
36 | #include "radeon_reg.h" |
37 | #include "radeon.h" | |
771fe6b9 JG |
38 | #include "atom.h" |
39 | ||
1b5331d9 JG |
40 | static const char radeon_family_name[][16] = { |
41 | "R100", | |
42 | "RV100", | |
43 | "RS100", | |
44 | "RV200", | |
45 | "RS200", | |
46 | "R200", | |
47 | "RV250", | |
48 | "RS300", | |
49 | "RV280", | |
50 | "R300", | |
51 | "R350", | |
52 | "RV350", | |
53 | "RV380", | |
54 | "R420", | |
55 | "R423", | |
56 | "RV410", | |
57 | "RS400", | |
58 | "RS480", | |
59 | "RS600", | |
60 | "RS690", | |
61 | "RS740", | |
62 | "RV515", | |
63 | "R520", | |
64 | "RV530", | |
65 | "RV560", | |
66 | "RV570", | |
67 | "R580", | |
68 | "R600", | |
69 | "RV610", | |
70 | "RV630", | |
71 | "RV670", | |
72 | "RV620", | |
73 | "RV635", | |
74 | "RS780", | |
75 | "RS880", | |
76 | "RV770", | |
77 | "RV730", | |
78 | "RV710", | |
79 | "RV740", | |
80 | "CEDAR", | |
81 | "REDWOOD", | |
82 | "JUNIPER", | |
83 | "CYPRESS", | |
84 | "HEMLOCK", | |
b08ebe7e | 85 | "PALM", |
4df64e65 AD |
86 | "SUMO", |
87 | "SUMO2", | |
1fe18305 AD |
88 | "BARTS", |
89 | "TURKS", | |
90 | "CAICOS", | |
b7cfc9fe | 91 | "CAYMAN", |
8848f759 | 92 | "ARUBA", |
cb28bb34 AD |
93 | "TAHITI", |
94 | "PITCAIRN", | |
95 | "VERDE", | |
624d3524 | 96 | "OLAND", |
b5d9d726 | 97 | "HAINAN", |
6eac752e AD |
98 | "BONAIRE", |
99 | "KAVERI", | |
100 | "KABINI", | |
3bf599e8 | 101 | "HAWAII", |
b0a9f22a | 102 | "MULLINS", |
1b5331d9 JG |
103 | "LAST", |
104 | }; | |
105 | ||
4807c5a8 AD |
106 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
107 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) | |
108 | ||
109 | struct radeon_px_quirk { | |
110 | u32 chip_vendor; | |
111 | u32 chip_device; | |
112 | u32 subsys_vendor; | |
113 | u32 subsys_device; | |
114 | u32 px_quirk_flags; | |
115 | }; | |
116 | ||
117 | static struct radeon_px_quirk radeon_px_quirk_list[] = { | |
118 | /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) | |
119 | * https://bugzilla.kernel.org/show_bug.cgi?id=74551 | |
120 | */ | |
121 | { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, | |
122 | /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU | |
123 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 | |
124 | */ | |
125 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, | |
ff1b1294 AD |
126 | /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
127 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 | |
128 | */ | |
129 | { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, | |
4807c5a8 AD |
130 | /* macbook pro 8.2 */ |
131 | { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, | |
132 | { 0, 0, 0, 0, 0 }, | |
133 | }; | |
134 | ||
90c4cde9 AD |
135 | bool radeon_is_px(struct drm_device *dev) |
136 | { | |
137 | struct radeon_device *rdev = dev->dev_private; | |
138 | ||
139 | if (rdev->flags & RADEON_IS_PX) | |
140 | return true; | |
141 | return false; | |
142 | } | |
10ebc0bc | 143 | |
4807c5a8 AD |
144 | static void radeon_device_handle_px_quirks(struct radeon_device *rdev) |
145 | { | |
146 | struct radeon_px_quirk *p = radeon_px_quirk_list; | |
147 | ||
148 | /* Apply PX quirks */ | |
149 | while (p && p->chip_device != 0) { | |
150 | if (rdev->pdev->vendor == p->chip_vendor && | |
151 | rdev->pdev->device == p->chip_device && | |
152 | rdev->pdev->subsystem_vendor == p->subsys_vendor && | |
153 | rdev->pdev->subsystem_device == p->subsys_device) { | |
154 | rdev->px_quirk_flags = p->px_quirk_flags; | |
155 | break; | |
156 | } | |
157 | ++p; | |
158 | } | |
159 | ||
160 | if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) | |
161 | rdev->flags &= ~RADEON_IS_PX; | |
162 | } | |
163 | ||
2e1b65f9 AD |
164 | /** |
165 | * radeon_program_register_sequence - program an array of registers. | |
166 | * | |
167 | * @rdev: radeon_device pointer | |
168 | * @registers: pointer to the register array | |
169 | * @array_size: size of the register array | |
170 | * | |
171 | * Programs an array or registers with and and or masks. | |
172 | * This is a helper for setting golden registers. | |
173 | */ | |
174 | void radeon_program_register_sequence(struct radeon_device *rdev, | |
175 | const u32 *registers, | |
176 | const u32 array_size) | |
177 | { | |
178 | u32 tmp, reg, and_mask, or_mask; | |
179 | int i; | |
180 | ||
181 | if (array_size % 3) | |
182 | return; | |
183 | ||
184 | for (i = 0; i < array_size; i +=3) { | |
185 | reg = registers[i + 0]; | |
186 | and_mask = registers[i + 1]; | |
187 | or_mask = registers[i + 2]; | |
188 | ||
189 | if (and_mask == 0xffffffff) { | |
190 | tmp = or_mask; | |
191 | } else { | |
192 | tmp = RREG32(reg); | |
193 | tmp &= ~and_mask; | |
194 | tmp |= or_mask; | |
195 | } | |
196 | WREG32(reg, tmp); | |
197 | } | |
198 | } | |
199 | ||
1a0041b8 AD |
200 | void radeon_pci_config_reset(struct radeon_device *rdev) |
201 | { | |
202 | pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); | |
203 | } | |
204 | ||
0c195119 AD |
205 | /** |
206 | * radeon_surface_init - Clear GPU surface registers. | |
207 | * | |
208 | * @rdev: radeon_device pointer | |
209 | * | |
210 | * Clear GPU surface registers (r1xx-r5xx). | |
b1e3a6d1 | 211 | */ |
3ce0a23d | 212 | void radeon_surface_init(struct radeon_device *rdev) |
b1e3a6d1 MD |
213 | { |
214 | /* FIXME: check this out */ | |
215 | if (rdev->family < CHIP_R600) { | |
216 | int i; | |
217 | ||
550e2d92 DA |
218 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
219 | if (rdev->surface_regs[i].bo) | |
220 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); | |
221 | else | |
222 | radeon_clear_surface_reg(rdev, i); | |
b1e3a6d1 | 223 | } |
e024e110 DA |
224 | /* enable surfaces */ |
225 | WREG32(RADEON_SURFACE_CNTL, 0); | |
b1e3a6d1 MD |
226 | } |
227 | } | |
228 | ||
771fe6b9 JG |
229 | /* |
230 | * GPU scratch registers helpers function. | |
231 | */ | |
0c195119 AD |
232 | /** |
233 | * radeon_scratch_init - Init scratch register driver information. | |
234 | * | |
235 | * @rdev: radeon_device pointer | |
236 | * | |
237 | * Init CP scratch register driver information (r1xx-r5xx) | |
238 | */ | |
3ce0a23d | 239 | void radeon_scratch_init(struct radeon_device *rdev) |
771fe6b9 JG |
240 | { |
241 | int i; | |
242 | ||
243 | /* FIXME: check this out */ | |
244 | if (rdev->family < CHIP_R300) { | |
245 | rdev->scratch.num_reg = 5; | |
246 | } else { | |
247 | rdev->scratch.num_reg = 7; | |
248 | } | |
724c80e1 | 249 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
771fe6b9 JG |
250 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
251 | rdev->scratch.free[i] = true; | |
724c80e1 | 252 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
771fe6b9 JG |
253 | } |
254 | } | |
255 | ||
0c195119 AD |
256 | /** |
257 | * radeon_scratch_get - Allocate a scratch register | |
258 | * | |
259 | * @rdev: radeon_device pointer | |
260 | * @reg: scratch register mmio offset | |
261 | * | |
262 | * Allocate a CP scratch register for use by the driver (all asics). | |
263 | * Returns 0 on success or -EINVAL on failure. | |
264 | */ | |
771fe6b9 JG |
265 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
266 | { | |
267 | int i; | |
268 | ||
269 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
270 | if (rdev->scratch.free[i]) { | |
271 | rdev->scratch.free[i] = false; | |
272 | *reg = rdev->scratch.reg[i]; | |
273 | return 0; | |
274 | } | |
275 | } | |
276 | return -EINVAL; | |
277 | } | |
278 | ||
0c195119 AD |
279 | /** |
280 | * radeon_scratch_free - Free a scratch register | |
281 | * | |
282 | * @rdev: radeon_device pointer | |
283 | * @reg: scratch register mmio offset | |
284 | * | |
285 | * Free a CP scratch register allocated for use by the driver (all asics) | |
286 | */ | |
771fe6b9 JG |
287 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
288 | { | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
292 | if (rdev->scratch.reg[i] == reg) { | |
293 | rdev->scratch.free[i] = true; | |
294 | return; | |
295 | } | |
296 | } | |
297 | } | |
298 | ||
75efdee1 AD |
299 | /* |
300 | * GPU doorbell aperture helpers function. | |
301 | */ | |
302 | /** | |
303 | * radeon_doorbell_init - Init doorbell driver information. | |
304 | * | |
305 | * @rdev: radeon_device pointer | |
306 | * | |
307 | * Init doorbell driver information (CIK) | |
308 | * Returns 0 on success, error on failure. | |
309 | */ | |
28f5a6cd | 310 | static int radeon_doorbell_init(struct radeon_device *rdev) |
75efdee1 | 311 | { |
75efdee1 AD |
312 | /* doorbell bar mapping */ |
313 | rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); | |
314 | rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); | |
315 | ||
d5754ab8 AL |
316 | rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); |
317 | if (rdev->doorbell.num_doorbells == 0) | |
318 | return -EINVAL; | |
75efdee1 | 319 | |
d5754ab8 | 320 | rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); |
75efdee1 AD |
321 | if (rdev->doorbell.ptr == NULL) { |
322 | return -ENOMEM; | |
323 | } | |
324 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); | |
325 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); | |
326 | ||
d5754ab8 | 327 | memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); |
75efdee1 | 328 | |
75efdee1 AD |
329 | return 0; |
330 | } | |
331 | ||
332 | /** | |
333 | * radeon_doorbell_fini - Tear down doorbell driver information. | |
334 | * | |
335 | * @rdev: radeon_device pointer | |
336 | * | |
337 | * Tear down doorbell driver information (CIK) | |
338 | */ | |
28f5a6cd | 339 | static void radeon_doorbell_fini(struct radeon_device *rdev) |
75efdee1 AD |
340 | { |
341 | iounmap(rdev->doorbell.ptr); | |
342 | rdev->doorbell.ptr = NULL; | |
343 | } | |
344 | ||
345 | /** | |
d5754ab8 | 346 | * radeon_doorbell_get - Allocate a doorbell entry |
75efdee1 AD |
347 | * |
348 | * @rdev: radeon_device pointer | |
d5754ab8 | 349 | * @doorbell: doorbell index |
75efdee1 | 350 | * |
d5754ab8 | 351 | * Allocate a doorbell for use by the driver (all asics). |
75efdee1 AD |
352 | * Returns 0 on success or -EINVAL on failure. |
353 | */ | |
354 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) | |
355 | { | |
d5754ab8 AL |
356 | unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); |
357 | if (offset < rdev->doorbell.num_doorbells) { | |
358 | __set_bit(offset, rdev->doorbell.used); | |
359 | *doorbell = offset; | |
360 | return 0; | |
361 | } else { | |
362 | return -EINVAL; | |
75efdee1 | 363 | } |
75efdee1 AD |
364 | } |
365 | ||
366 | /** | |
d5754ab8 | 367 | * radeon_doorbell_free - Free a doorbell entry |
75efdee1 AD |
368 | * |
369 | * @rdev: radeon_device pointer | |
d5754ab8 | 370 | * @doorbell: doorbell index |
75efdee1 | 371 | * |
d5754ab8 | 372 | * Free a doorbell allocated for use by the driver (all asics) |
75efdee1 AD |
373 | */ |
374 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) | |
375 | { | |
d5754ab8 AL |
376 | if (doorbell < rdev->doorbell.num_doorbells) |
377 | __clear_bit(doorbell, rdev->doorbell.used); | |
75efdee1 AD |
378 | } |
379 | ||
0c195119 AD |
380 | /* |
381 | * radeon_wb_*() | |
382 | * Writeback is the the method by which the the GPU updates special pages | |
383 | * in memory with the status of certain GPU events (fences, ring pointers, | |
384 | * etc.). | |
385 | */ | |
386 | ||
387 | /** | |
388 | * radeon_wb_disable - Disable Writeback | |
389 | * | |
390 | * @rdev: radeon_device pointer | |
391 | * | |
392 | * Disables Writeback (all asics). Used for suspend. | |
393 | */ | |
724c80e1 AD |
394 | void radeon_wb_disable(struct radeon_device *rdev) |
395 | { | |
724c80e1 AD |
396 | rdev->wb.enabled = false; |
397 | } | |
398 | ||
0c195119 AD |
399 | /** |
400 | * radeon_wb_fini - Disable Writeback and free memory | |
401 | * | |
402 | * @rdev: radeon_device pointer | |
403 | * | |
404 | * Disables Writeback and frees the Writeback memory (all asics). | |
405 | * Used at driver shutdown. | |
406 | */ | |
724c80e1 AD |
407 | void radeon_wb_fini(struct radeon_device *rdev) |
408 | { | |
409 | radeon_wb_disable(rdev); | |
410 | if (rdev->wb.wb_obj) { | |
089920f2 JG |
411 | if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { |
412 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
413 | radeon_bo_unpin(rdev->wb.wb_obj); | |
414 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
415 | } | |
724c80e1 AD |
416 | radeon_bo_unref(&rdev->wb.wb_obj); |
417 | rdev->wb.wb = NULL; | |
418 | rdev->wb.wb_obj = NULL; | |
419 | } | |
420 | } | |
421 | ||
0c195119 AD |
422 | /** |
423 | * radeon_wb_init- Init Writeback driver info and allocate memory | |
424 | * | |
425 | * @rdev: radeon_device pointer | |
426 | * | |
427 | * Disables Writeback and frees the Writeback memory (all asics). | |
428 | * Used at driver startup. | |
429 | * Returns 0 on success or an -error on failure. | |
430 | */ | |
724c80e1 AD |
431 | int radeon_wb_init(struct radeon_device *rdev) |
432 | { | |
433 | int r; | |
434 | ||
435 | if (rdev->wb.wb_obj == NULL) { | |
441921d5 | 436 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
02376d82 MD |
437 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
438 | &rdev->wb.wb_obj); | |
724c80e1 AD |
439 | if (r) { |
440 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); | |
441 | return r; | |
442 | } | |
089920f2 JG |
443 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
444 | if (unlikely(r != 0)) { | |
445 | radeon_wb_fini(rdev); | |
446 | return r; | |
447 | } | |
448 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, | |
449 | &rdev->wb.gpu_addr); | |
450 | if (r) { | |
451 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
452 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
453 | radeon_wb_fini(rdev); | |
454 | return r; | |
455 | } | |
456 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); | |
724c80e1 | 457 | radeon_bo_unreserve(rdev->wb.wb_obj); |
089920f2 JG |
458 | if (r) { |
459 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); | |
460 | radeon_wb_fini(rdev); | |
461 | return r; | |
462 | } | |
724c80e1 AD |
463 | } |
464 | ||
e6ba7599 AD |
465 | /* clear wb memory */ |
466 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); | |
d0f8a854 AD |
467 | /* disable event_write fences */ |
468 | rdev->wb.use_event = false; | |
724c80e1 | 469 | /* disabled via module param */ |
3b7a2b24 | 470 | if (radeon_no_wb == 1) { |
724c80e1 | 471 | rdev->wb.enabled = false; |
3b7a2b24 | 472 | } else { |
724c80e1 | 473 | if (rdev->flags & RADEON_IS_AGP) { |
28eebb70 AD |
474 | /* often unreliable on AGP */ |
475 | rdev->wb.enabled = false; | |
476 | } else if (rdev->family < CHIP_R300) { | |
477 | /* often unreliable on pre-r300 */ | |
724c80e1 | 478 | rdev->wb.enabled = false; |
d0f8a854 | 479 | } else { |
724c80e1 | 480 | rdev->wb.enabled = true; |
d0f8a854 | 481 | /* event_write fences are only available on r600+ */ |
3b7a2b24 | 482 | if (rdev->family >= CHIP_R600) { |
d0f8a854 | 483 | rdev->wb.use_event = true; |
3b7a2b24 | 484 | } |
d0f8a854 | 485 | } |
724c80e1 | 486 | } |
c994ead6 AD |
487 | /* always use writeback/events on NI, APUs */ |
488 | if (rdev->family >= CHIP_PALM) { | |
7d52785d AD |
489 | rdev->wb.enabled = true; |
490 | rdev->wb.use_event = true; | |
491 | } | |
724c80e1 AD |
492 | |
493 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
d594e46a JG |
498 | /** |
499 | * radeon_vram_location - try to find VRAM location | |
500 | * @rdev: radeon device structure holding all necessary informations | |
501 | * @mc: memory controller structure holding memory informations | |
502 | * @base: base address at which to put VRAM | |
503 | * | |
504 | * Function will place try to place VRAM at base address provided | |
505 | * as parameter (which is so far either PCI aperture address or | |
506 | * for IGP TOM base address). | |
507 | * | |
508 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
509 | * address space then we limit the VRAM size to the aperture. | |
510 | * | |
511 | * If we are using AGP and if the AGP aperture doesn't allow us to have | |
512 | * room for all the VRAM than we restrict the VRAM to the PCI aperture | |
513 | * size and print a warning. | |
514 | * | |
515 | * This function will never fails, worst case are limiting VRAM. | |
516 | * | |
517 | * Note: GTT start, end, size should be initialized before calling this | |
518 | * function on AGP platform. | |
519 | * | |
25985edc | 520 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
d594e46a JG |
521 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
522 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
523 | * not IGP. | |
524 | * | |
525 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
526 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
527 | * Novell bug 204882 + along with lots of ubuntu ones | |
528 | * | |
529 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
530 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
531 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
532 | * ones) | |
533 | * | |
534 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
535 | * explicitly check for that thought. | |
536 | * | |
537 | * FIXME: when reducing VRAM size align new size on power of 2. | |
771fe6b9 | 538 | */ |
d594e46a | 539 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
771fe6b9 | 540 | { |
1bcb04f7 CK |
541 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
542 | ||
d594e46a | 543 | mc->vram_start = base; |
9ed8b1f9 | 544 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
d594e46a JG |
545 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
546 | mc->real_vram_size = mc->aper_size; | |
547 | mc->mc_vram_size = mc->aper_size; | |
548 | } | |
549 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
2cbeb4ef | 550 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
d594e46a JG |
551 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
552 | mc->real_vram_size = mc->aper_size; | |
553 | mc->mc_vram_size = mc->aper_size; | |
554 | } | |
555 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
1bcb04f7 CK |
556 | if (limit && limit < mc->real_vram_size) |
557 | mc->real_vram_size = limit; | |
dd7cc55a | 558 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
d594e46a JG |
559 | mc->mc_vram_size >> 20, mc->vram_start, |
560 | mc->vram_end, mc->real_vram_size >> 20); | |
561 | } | |
771fe6b9 | 562 | |
d594e46a JG |
563 | /** |
564 | * radeon_gtt_location - try to find GTT location | |
565 | * @rdev: radeon device structure holding all necessary informations | |
566 | * @mc: memory controller structure holding memory informations | |
567 | * | |
568 | * Function will place try to place GTT before or after VRAM. | |
569 | * | |
570 | * If GTT size is bigger than space left then we ajust GTT size. | |
571 | * Thus function will never fails. | |
572 | * | |
573 | * FIXME: when reducing GTT size align new size on power of 2. | |
574 | */ | |
575 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
576 | { | |
577 | u64 size_af, size_bf; | |
578 | ||
9ed8b1f9 | 579 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
8d369bb1 | 580 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
d594e46a JG |
581 | if (size_bf > size_af) { |
582 | if (mc->gtt_size > size_bf) { | |
583 | dev_warn(rdev->dev, "limiting GTT\n"); | |
584 | mc->gtt_size = size_bf; | |
771fe6b9 | 585 | } |
8d369bb1 | 586 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
771fe6b9 | 587 | } else { |
d594e46a JG |
588 | if (mc->gtt_size > size_af) { |
589 | dev_warn(rdev->dev, "limiting GTT\n"); | |
590 | mc->gtt_size = size_af; | |
591 | } | |
8d369bb1 | 592 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
771fe6b9 | 593 | } |
d594e46a | 594 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
dd7cc55a | 595 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
d594e46a | 596 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
771fe6b9 JG |
597 | } |
598 | ||
771fe6b9 JG |
599 | /* |
600 | * GPU helpers function. | |
601 | */ | |
0c195119 AD |
602 | /** |
603 | * radeon_card_posted - check if the hw has already been initialized | |
604 | * | |
605 | * @rdev: radeon_device pointer | |
606 | * | |
607 | * Check if the asic has been initialized (all asics). | |
608 | * Used at driver startup. | |
609 | * Returns true if initialized or false if not. | |
610 | */ | |
9f022ddf | 611 | bool radeon_card_posted(struct radeon_device *rdev) |
771fe6b9 JG |
612 | { |
613 | uint32_t reg; | |
614 | ||
50a583f6 | 615 | /* required for EFI mode on macbook2,1 which uses an r5xx asic */ |
83e68189 | 616 | if (efi_enabled(EFI_BOOT) && |
50a583f6 AD |
617 | (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
618 | (rdev->family < CHIP_R600)) | |
bcc65fd8 MG |
619 | return false; |
620 | ||
2cf3a4fc AD |
621 | if (ASIC_IS_NODCE(rdev)) |
622 | goto check_memsize; | |
623 | ||
771fe6b9 | 624 | /* first check CRTCs */ |
09fb8bd1 | 625 | if (ASIC_IS_DCE4(rdev)) { |
18007401 AD |
626 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
627 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
09fb8bd1 AD |
628 | if (rdev->num_crtc >= 4) { |
629 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | |
630 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
631 | } | |
632 | if (rdev->num_crtc >= 6) { | |
633 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | |
634 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
635 | } | |
bcc1c2a1 AD |
636 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
637 | return true; | |
638 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
639 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
640 | RREG32(AVIVO_D2CRTC_CONTROL); | |
641 | if (reg & AVIVO_CRTC_EN) { | |
642 | return true; | |
643 | } | |
644 | } else { | |
645 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | | |
646 | RREG32(RADEON_CRTC2_GEN_CNTL); | |
647 | if (reg & RADEON_CRTC_EN) { | |
648 | return true; | |
649 | } | |
650 | } | |
651 | ||
2cf3a4fc | 652 | check_memsize: |
771fe6b9 JG |
653 | /* then check MEM_SIZE, in case the crtcs are off */ |
654 | if (rdev->family >= CHIP_R600) | |
655 | reg = RREG32(R600_CONFIG_MEMSIZE); | |
656 | else | |
657 | reg = RREG32(RADEON_CONFIG_MEMSIZE); | |
658 | ||
659 | if (reg) | |
660 | return true; | |
661 | ||
662 | return false; | |
663 | ||
664 | } | |
665 | ||
0c195119 AD |
666 | /** |
667 | * radeon_update_bandwidth_info - update display bandwidth params | |
668 | * | |
669 | * @rdev: radeon_device pointer | |
670 | * | |
671 | * Used when sclk/mclk are switched or display modes are set. | |
672 | * params are used to calculate display watermarks (all asics) | |
673 | */ | |
f47299c5 AD |
674 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
675 | { | |
676 | fixed20_12 a; | |
8807286e AD |
677 | u32 sclk = rdev->pm.current_sclk; |
678 | u32 mclk = rdev->pm.current_mclk; | |
f47299c5 | 679 | |
8807286e AD |
680 | /* sclk/mclk in Mhz */ |
681 | a.full = dfixed_const(100); | |
682 | rdev->pm.sclk.full = dfixed_const(sclk); | |
683 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); | |
684 | rdev->pm.mclk.full = dfixed_const(mclk); | |
685 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); | |
f47299c5 | 686 | |
8807286e | 687 | if (rdev->flags & RADEON_IS_IGP) { |
68adac5e | 688 | a.full = dfixed_const(16); |
f47299c5 | 689 | /* core_bandwidth = sclk(Mhz) * 16 */ |
68adac5e | 690 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
f47299c5 AD |
691 | } |
692 | } | |
693 | ||
0c195119 AD |
694 | /** |
695 | * radeon_boot_test_post_card - check and possibly initialize the hw | |
696 | * | |
697 | * @rdev: radeon_device pointer | |
698 | * | |
699 | * Check if the asic is initialized and if not, attempt to initialize | |
700 | * it (all asics). | |
701 | * Returns true if initialized or false if not. | |
702 | */ | |
72542d77 DA |
703 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
704 | { | |
705 | if (radeon_card_posted(rdev)) | |
706 | return true; | |
707 | ||
708 | if (rdev->bios) { | |
709 | DRM_INFO("GPU not posted. posting now...\n"); | |
710 | if (rdev->is_atom_bios) | |
711 | atom_asic_init(rdev->mode_info.atom_context); | |
712 | else | |
713 | radeon_combios_asic_init(rdev->ddev); | |
714 | return true; | |
715 | } else { | |
716 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
717 | return false; | |
718 | } | |
719 | } | |
720 | ||
0c195119 AD |
721 | /** |
722 | * radeon_dummy_page_init - init dummy page used by the driver | |
723 | * | |
724 | * @rdev: radeon_device pointer | |
725 | * | |
726 | * Allocate the dummy page used by the driver (all asics). | |
727 | * This dummy page is used by the driver as a filler for gart entries | |
728 | * when pages are taken out of the GART | |
729 | * Returns 0 on sucess, -ENOMEM on failure. | |
730 | */ | |
3ce0a23d JG |
731 | int radeon_dummy_page_init(struct radeon_device *rdev) |
732 | { | |
82568565 DA |
733 | if (rdev->dummy_page.page) |
734 | return 0; | |
3ce0a23d JG |
735 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
736 | if (rdev->dummy_page.page == NULL) | |
737 | return -ENOMEM; | |
738 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, | |
739 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
a30f6fb7 BH |
740 | if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { |
741 | dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
3ce0a23d JG |
742 | __free_page(rdev->dummy_page.page); |
743 | rdev->dummy_page.page = NULL; | |
744 | return -ENOMEM; | |
745 | } | |
746 | return 0; | |
747 | } | |
748 | ||
0c195119 AD |
749 | /** |
750 | * radeon_dummy_page_fini - free dummy page used by the driver | |
751 | * | |
752 | * @rdev: radeon_device pointer | |
753 | * | |
754 | * Frees the dummy page used by the driver (all asics). | |
755 | */ | |
3ce0a23d JG |
756 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
757 | { | |
758 | if (rdev->dummy_page.page == NULL) | |
759 | return; | |
760 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, | |
761 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
762 | __free_page(rdev->dummy_page.page); | |
763 | rdev->dummy_page.page = NULL; | |
764 | } | |
765 | ||
771fe6b9 | 766 | |
771fe6b9 | 767 | /* ATOM accessor methods */ |
0c195119 AD |
768 | /* |
769 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
770 | * driver registers callbacks to access registers and the interpreter | |
771 | * in the driver parses the tables and executes then to program specific | |
772 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, | |
773 | * atombios.h, and atom.c | |
774 | */ | |
775 | ||
776 | /** | |
777 | * cail_pll_read - read PLL register | |
778 | * | |
779 | * @info: atom card_info pointer | |
780 | * @reg: PLL register offset | |
781 | * | |
782 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
783 | * Returns the value of the PLL register. | |
784 | */ | |
771fe6b9 JG |
785 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
786 | { | |
787 | struct radeon_device *rdev = info->dev->dev_private; | |
788 | uint32_t r; | |
789 | ||
790 | r = rdev->pll_rreg(rdev, reg); | |
791 | return r; | |
792 | } | |
793 | ||
0c195119 AD |
794 | /** |
795 | * cail_pll_write - write PLL register | |
796 | * | |
797 | * @info: atom card_info pointer | |
798 | * @reg: PLL register offset | |
799 | * @val: value to write to the pll register | |
800 | * | |
801 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
802 | */ | |
771fe6b9 JG |
803 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
804 | { | |
805 | struct radeon_device *rdev = info->dev->dev_private; | |
806 | ||
807 | rdev->pll_wreg(rdev, reg, val); | |
808 | } | |
809 | ||
0c195119 AD |
810 | /** |
811 | * cail_mc_read - read MC (Memory Controller) register | |
812 | * | |
813 | * @info: atom card_info pointer | |
814 | * @reg: MC register offset | |
815 | * | |
816 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
817 | * Returns the value of the MC register. | |
818 | */ | |
771fe6b9 JG |
819 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
820 | { | |
821 | struct radeon_device *rdev = info->dev->dev_private; | |
822 | uint32_t r; | |
823 | ||
824 | r = rdev->mc_rreg(rdev, reg); | |
825 | return r; | |
826 | } | |
827 | ||
0c195119 AD |
828 | /** |
829 | * cail_mc_write - write MC (Memory Controller) register | |
830 | * | |
831 | * @info: atom card_info pointer | |
832 | * @reg: MC register offset | |
833 | * @val: value to write to the pll register | |
834 | * | |
835 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
836 | */ | |
771fe6b9 JG |
837 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
838 | { | |
839 | struct radeon_device *rdev = info->dev->dev_private; | |
840 | ||
841 | rdev->mc_wreg(rdev, reg, val); | |
842 | } | |
843 | ||
0c195119 AD |
844 | /** |
845 | * cail_reg_write - write MMIO register | |
846 | * | |
847 | * @info: atom card_info pointer | |
848 | * @reg: MMIO register offset | |
849 | * @val: value to write to the pll register | |
850 | * | |
851 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
852 | */ | |
771fe6b9 JG |
853 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
854 | { | |
855 | struct radeon_device *rdev = info->dev->dev_private; | |
856 | ||
857 | WREG32(reg*4, val); | |
858 | } | |
859 | ||
0c195119 AD |
860 | /** |
861 | * cail_reg_read - read MMIO register | |
862 | * | |
863 | * @info: atom card_info pointer | |
864 | * @reg: MMIO register offset | |
865 | * | |
866 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
867 | * Returns the value of the MMIO register. | |
868 | */ | |
771fe6b9 JG |
869 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
870 | { | |
871 | struct radeon_device *rdev = info->dev->dev_private; | |
872 | uint32_t r; | |
873 | ||
874 | r = RREG32(reg*4); | |
875 | return r; | |
876 | } | |
877 | ||
0c195119 AD |
878 | /** |
879 | * cail_ioreg_write - write IO register | |
880 | * | |
881 | * @info: atom card_info pointer | |
882 | * @reg: IO register offset | |
883 | * @val: value to write to the pll register | |
884 | * | |
885 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
886 | */ | |
351a52a2 AD |
887 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
888 | { | |
889 | struct radeon_device *rdev = info->dev->dev_private; | |
890 | ||
891 | WREG32_IO(reg*4, val); | |
892 | } | |
893 | ||
0c195119 AD |
894 | /** |
895 | * cail_ioreg_read - read IO register | |
896 | * | |
897 | * @info: atom card_info pointer | |
898 | * @reg: IO register offset | |
899 | * | |
900 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
901 | * Returns the value of the IO register. | |
902 | */ | |
351a52a2 AD |
903 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
904 | { | |
905 | struct radeon_device *rdev = info->dev->dev_private; | |
906 | uint32_t r; | |
907 | ||
908 | r = RREG32_IO(reg*4); | |
909 | return r; | |
910 | } | |
911 | ||
0c195119 AD |
912 | /** |
913 | * radeon_atombios_init - init the driver info and callbacks for atombios | |
914 | * | |
915 | * @rdev: radeon_device pointer | |
916 | * | |
917 | * Initializes the driver info and register access callbacks for the | |
918 | * ATOM interpreter (r4xx+). | |
919 | * Returns 0 on sucess, -ENOMEM on failure. | |
920 | * Called at driver startup. | |
921 | */ | |
771fe6b9 JG |
922 | int radeon_atombios_init(struct radeon_device *rdev) |
923 | { | |
61c4b24b MF |
924 | struct card_info *atom_card_info = |
925 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
926 | ||
927 | if (!atom_card_info) | |
928 | return -ENOMEM; | |
929 | ||
930 | rdev->mode_info.atom_card_info = atom_card_info; | |
931 | atom_card_info->dev = rdev->ddev; | |
932 | atom_card_info->reg_read = cail_reg_read; | |
933 | atom_card_info->reg_write = cail_reg_write; | |
351a52a2 AD |
934 | /* needed for iio ops */ |
935 | if (rdev->rio_mem) { | |
936 | atom_card_info->ioreg_read = cail_ioreg_read; | |
937 | atom_card_info->ioreg_write = cail_ioreg_write; | |
938 | } else { | |
939 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
940 | atom_card_info->ioreg_read = cail_reg_read; | |
941 | atom_card_info->ioreg_write = cail_reg_write; | |
942 | } | |
61c4b24b MF |
943 | atom_card_info->mc_read = cail_mc_read; |
944 | atom_card_info->mc_write = cail_mc_write; | |
945 | atom_card_info->pll_read = cail_pll_read; | |
946 | atom_card_info->pll_write = cail_pll_write; | |
947 | ||
948 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); | |
0e34d094 TG |
949 | if (!rdev->mode_info.atom_context) { |
950 | radeon_atombios_fini(rdev); | |
951 | return -ENOMEM; | |
952 | } | |
953 | ||
c31ad97f | 954 | mutex_init(&rdev->mode_info.atom_context->mutex); |
771fe6b9 | 955 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
d904ef9b | 956 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
771fe6b9 JG |
957 | return 0; |
958 | } | |
959 | ||
0c195119 AD |
960 | /** |
961 | * radeon_atombios_fini - free the driver info and callbacks for atombios | |
962 | * | |
963 | * @rdev: radeon_device pointer | |
964 | * | |
965 | * Frees the driver info and register access callbacks for the ATOM | |
966 | * interpreter (r4xx+). | |
967 | * Called at driver shutdown. | |
968 | */ | |
771fe6b9 JG |
969 | void radeon_atombios_fini(struct radeon_device *rdev) |
970 | { | |
4a04a844 JG |
971 | if (rdev->mode_info.atom_context) { |
972 | kfree(rdev->mode_info.atom_context->scratch); | |
4a04a844 | 973 | } |
0e34d094 TG |
974 | kfree(rdev->mode_info.atom_context); |
975 | rdev->mode_info.atom_context = NULL; | |
61c4b24b | 976 | kfree(rdev->mode_info.atom_card_info); |
0e34d094 | 977 | rdev->mode_info.atom_card_info = NULL; |
771fe6b9 JG |
978 | } |
979 | ||
0c195119 AD |
980 | /* COMBIOS */ |
981 | /* | |
982 | * COMBIOS is the bios format prior to ATOM. It provides | |
983 | * command tables similar to ATOM, but doesn't have a unified | |
984 | * parser. See radeon_combios.c | |
985 | */ | |
986 | ||
987 | /** | |
988 | * radeon_combios_init - init the driver info for combios | |
989 | * | |
990 | * @rdev: radeon_device pointer | |
991 | * | |
992 | * Initializes the driver info for combios (r1xx-r3xx). | |
993 | * Returns 0 on sucess. | |
994 | * Called at driver startup. | |
995 | */ | |
771fe6b9 JG |
996 | int radeon_combios_init(struct radeon_device *rdev) |
997 | { | |
998 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); | |
999 | return 0; | |
1000 | } | |
1001 | ||
0c195119 AD |
1002 | /** |
1003 | * radeon_combios_fini - free the driver info for combios | |
1004 | * | |
1005 | * @rdev: radeon_device pointer | |
1006 | * | |
1007 | * Frees the driver info for combios (r1xx-r3xx). | |
1008 | * Called at driver shutdown. | |
1009 | */ | |
771fe6b9 JG |
1010 | void radeon_combios_fini(struct radeon_device *rdev) |
1011 | { | |
1012 | } | |
1013 | ||
0c195119 AD |
1014 | /* if we get transitioned to only one device, take VGA back */ |
1015 | /** | |
1016 | * radeon_vga_set_decode - enable/disable vga decode | |
1017 | * | |
1018 | * @cookie: radeon_device pointer | |
1019 | * @state: enable/disable vga decode | |
1020 | * | |
1021 | * Enable/disable vga decode (all asics). | |
1022 | * Returns VGA resource flags. | |
1023 | */ | |
28d52043 DA |
1024 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
1025 | { | |
1026 | struct radeon_device *rdev = cookie; | |
28d52043 DA |
1027 | radeon_vga_set_state(rdev, state); |
1028 | if (state) | |
1029 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1030 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1031 | else | |
1032 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1033 | } | |
c1176d6f | 1034 | |
1bcb04f7 CK |
1035 | /** |
1036 | * radeon_check_pot_argument - check that argument is a power of two | |
1037 | * | |
1038 | * @arg: value to check | |
1039 | * | |
1040 | * Validates that a certain argument is a power of two (all asics). | |
1041 | * Returns true if argument is valid. | |
1042 | */ | |
1043 | static bool radeon_check_pot_argument(int arg) | |
1044 | { | |
1045 | return (arg & (arg - 1)) == 0; | |
1046 | } | |
1047 | ||
0c195119 AD |
1048 | /** |
1049 | * radeon_check_arguments - validate module params | |
1050 | * | |
1051 | * @rdev: radeon_device pointer | |
1052 | * | |
1053 | * Validates certain module parameters and updates | |
1054 | * the associated values used by the driver (all asics). | |
1055 | */ | |
1109ca09 | 1056 | static void radeon_check_arguments(struct radeon_device *rdev) |
36421338 JG |
1057 | { |
1058 | /* vramlimit must be a power of two */ | |
1bcb04f7 | 1059 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
36421338 JG |
1060 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
1061 | radeon_vram_limit); | |
1062 | radeon_vram_limit = 0; | |
36421338 | 1063 | } |
1bcb04f7 | 1064 | |
edcd26e8 AD |
1065 | if (radeon_gart_size == -1) { |
1066 | /* default to a larger gart size on newer asics */ | |
1067 | if (rdev->family >= CHIP_RV770) | |
1068 | radeon_gart_size = 1024; | |
1069 | else | |
1070 | radeon_gart_size = 512; | |
1071 | } | |
36421338 | 1072 | /* gtt size must be power of two and greater or equal to 32M */ |
1bcb04f7 | 1073 | if (radeon_gart_size < 32) { |
edcd26e8 | 1074 | dev_warn(rdev->dev, "gart size (%d) too small\n", |
36421338 | 1075 | radeon_gart_size); |
edcd26e8 AD |
1076 | if (rdev->family >= CHIP_RV770) |
1077 | radeon_gart_size = 1024; | |
1078 | else | |
1079 | radeon_gart_size = 512; | |
1bcb04f7 | 1080 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
36421338 JG |
1081 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
1082 | radeon_gart_size); | |
edcd26e8 AD |
1083 | if (rdev->family >= CHIP_RV770) |
1084 | radeon_gart_size = 1024; | |
1085 | else | |
1086 | radeon_gart_size = 512; | |
36421338 | 1087 | } |
1bcb04f7 CK |
1088 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
1089 | ||
36421338 JG |
1090 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
1091 | switch (radeon_agpmode) { | |
1092 | case -1: | |
1093 | case 0: | |
1094 | case 1: | |
1095 | case 2: | |
1096 | case 4: | |
1097 | case 8: | |
1098 | break; | |
1099 | default: | |
1100 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " | |
1101 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); | |
1102 | radeon_agpmode = 0; | |
1103 | break; | |
1104 | } | |
c1c44132 CK |
1105 | |
1106 | if (!radeon_check_pot_argument(radeon_vm_size)) { | |
1107 | dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", | |
1108 | radeon_vm_size); | |
20b2656d | 1109 | radeon_vm_size = 4; |
c1c44132 CK |
1110 | } |
1111 | ||
20b2656d CK |
1112 | if (radeon_vm_size < 1) { |
1113 | dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", | |
c1c44132 | 1114 | radeon_vm_size); |
20b2656d | 1115 | radeon_vm_size = 4; |
c1c44132 CK |
1116 | } |
1117 | ||
1118 | /* | |
1119 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
1120 | */ | |
20b2656d CK |
1121 | if (radeon_vm_size > 1024) { |
1122 | dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", | |
c1c44132 | 1123 | radeon_vm_size); |
20b2656d | 1124 | radeon_vm_size = 4; |
c1c44132 | 1125 | } |
4510fb98 CK |
1126 | |
1127 | /* defines number of bits in page table versus page directory, | |
1128 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1129 | * page table and the remaining bits are in the page directory */ | |
dfc230f9 CK |
1130 | if (radeon_vm_block_size == -1) { |
1131 | ||
1132 | /* Total bits covered by PD + PTs */ | |
1133 | unsigned bits = ilog2(radeon_vm_size) + 17; | |
1134 | ||
1135 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1136 | Above that split equal between PD and PTs */ | |
1137 | if (radeon_vm_size <= 8) | |
1138 | radeon_vm_block_size = bits - 9; | |
1139 | else | |
1140 | radeon_vm_block_size = (bits + 3) / 2; | |
1141 | ||
1142 | } else if (radeon_vm_block_size < 9) { | |
20b2656d | 1143 | dev_warn(rdev->dev, "VM page table size (%d) too small\n", |
4510fb98 CK |
1144 | radeon_vm_block_size); |
1145 | radeon_vm_block_size = 9; | |
1146 | } | |
1147 | ||
1148 | if (radeon_vm_block_size > 24 || | |
20b2656d CK |
1149 | (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { |
1150 | dev_warn(rdev->dev, "VM page table size (%d) too large\n", | |
4510fb98 CK |
1151 | radeon_vm_block_size); |
1152 | radeon_vm_block_size = 9; | |
1153 | } | |
36421338 JG |
1154 | } |
1155 | ||
0c195119 AD |
1156 | /** |
1157 | * radeon_switcheroo_set_state - set switcheroo state | |
1158 | * | |
1159 | * @pdev: pci dev pointer | |
1160 | * @state: vga switcheroo state | |
1161 | * | |
1162 | * Callback for the switcheroo driver. Suspends or resumes the | |
1163 | * the asics before or after it is powered up using ACPI methods. | |
1164 | */ | |
6a9ee8af DA |
1165 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1166 | { | |
1167 | struct drm_device *dev = pci_get_drvdata(pdev); | |
4807c5a8 | 1168 | struct radeon_device *rdev = dev->dev_private; |
10ebc0bc | 1169 | |
90c4cde9 | 1170 | if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) |
10ebc0bc DA |
1171 | return; |
1172 | ||
6a9ee8af | 1173 | if (state == VGA_SWITCHEROO_ON) { |
d1f9809e ML |
1174 | unsigned d3_delay = dev->pdev->d3_delay; |
1175 | ||
6a9ee8af DA |
1176 | printk(KERN_INFO "radeon: switched on\n"); |
1177 | /* don't suspend or resume card normally */ | |
5bcf719b | 1178 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
d1f9809e | 1179 | |
4807c5a8 | 1180 | if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) |
d1f9809e ML |
1181 | dev->pdev->d3_delay = 20; |
1182 | ||
10ebc0bc | 1183 | radeon_resume_kms(dev, true, true); |
d1f9809e ML |
1184 | |
1185 | dev->pdev->d3_delay = d3_delay; | |
1186 | ||
5bcf719b | 1187 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
fbf81762 | 1188 | drm_kms_helper_poll_enable(dev); |
6a9ee8af DA |
1189 | } else { |
1190 | printk(KERN_INFO "radeon: switched off\n"); | |
fbf81762 | 1191 | drm_kms_helper_poll_disable(dev); |
5bcf719b | 1192 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
10ebc0bc | 1193 | radeon_suspend_kms(dev, true, true); |
5bcf719b | 1194 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1195 | } |
1196 | } | |
1197 | ||
0c195119 AD |
1198 | /** |
1199 | * radeon_switcheroo_can_switch - see if switcheroo state can change | |
1200 | * | |
1201 | * @pdev: pci dev pointer | |
1202 | * | |
1203 | * Callback for the switcheroo driver. Check of the switcheroo | |
1204 | * state can be changed. | |
1205 | * Returns true if the state can be changed, false if not. | |
1206 | */ | |
6a9ee8af DA |
1207 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) |
1208 | { | |
1209 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 1210 | |
fc8fd40e DV |
1211 | /* |
1212 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1213 | * locking inversion with the driver load path. And the access here is | |
1214 | * completely racy anyway. So don't bother with locking for now. | |
1215 | */ | |
1216 | return dev->open_count == 0; | |
6a9ee8af DA |
1217 | } |
1218 | ||
26ec685f TI |
1219 | static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { |
1220 | .set_gpu_state = radeon_switcheroo_set_state, | |
1221 | .reprobe = NULL, | |
1222 | .can_switch = radeon_switcheroo_can_switch, | |
1223 | }; | |
6a9ee8af | 1224 | |
0c195119 AD |
1225 | /** |
1226 | * radeon_device_init - initialize the driver | |
1227 | * | |
1228 | * @rdev: radeon_device pointer | |
1229 | * @pdev: drm dev pointer | |
1230 | * @pdev: pci dev pointer | |
1231 | * @flags: driver flags | |
1232 | * | |
1233 | * Initializes the driver info and hw (all asics). | |
1234 | * Returns 0 for success or an error on failure. | |
1235 | * Called at driver startup. | |
1236 | */ | |
771fe6b9 JG |
1237 | int radeon_device_init(struct radeon_device *rdev, |
1238 | struct drm_device *ddev, | |
1239 | struct pci_dev *pdev, | |
1240 | uint32_t flags) | |
1241 | { | |
351a52a2 | 1242 | int r, i; |
ad49f501 | 1243 | int dma_bits; |
10ebc0bc | 1244 | bool runtime = false; |
771fe6b9 | 1245 | |
771fe6b9 | 1246 | rdev->shutdown = false; |
9f022ddf | 1247 | rdev->dev = &pdev->dev; |
771fe6b9 JG |
1248 | rdev->ddev = ddev; |
1249 | rdev->pdev = pdev; | |
1250 | rdev->flags = flags; | |
1251 | rdev->family = flags & RADEON_FAMILY_MASK; | |
1252 | rdev->is_atom_bios = false; | |
1253 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; | |
edcd26e8 | 1254 | rdev->mc.gtt_size = 512 * 1024 * 1024; |
733289c2 | 1255 | rdev->accel_working = false; |
8b25ed34 AD |
1256 | /* set up ring ids */ |
1257 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | |
1258 | rdev->ring[i].idx = i; | |
1259 | } | |
1b5331d9 | 1260 | |
d522d9cc TR |
1261 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
1262 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, | |
1263 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1b5331d9 | 1264 | |
771fe6b9 JG |
1265 | /* mutex initialization are all done here so we |
1266 | * can recall function without having locking issues */ | |
d6999bc7 | 1267 | mutex_init(&rdev->ring_lock); |
40bacf16 | 1268 | mutex_init(&rdev->dc_hw_i2c_mutex); |
c20dc369 | 1269 | atomic_set(&rdev->ih.lock, 0); |
4c788679 | 1270 | mutex_init(&rdev->gem.mutex); |
c913e23a | 1271 | mutex_init(&rdev->pm.mutex); |
6759a0a7 | 1272 | mutex_init(&rdev->gpu_clock_mutex); |
f61d5b46 | 1273 | mutex_init(&rdev->srbm_mutex); |
db7fce39 | 1274 | init_rwsem(&rdev->pm.mclk_lock); |
dee53e7f | 1275 | init_rwsem(&rdev->exclusive_lock); |
73a6d3fc | 1276 | init_waitqueue_head(&rdev->irq.vblank_queue); |
1b9c3dd0 AD |
1277 | r = radeon_gem_init(rdev); |
1278 | if (r) | |
1279 | return r; | |
529364e0 | 1280 | |
c1c44132 | 1281 | radeon_check_arguments(rdev); |
23d4f1f2 | 1282 | /* Adjust VM size here. |
c1c44132 | 1283 | * Max GPUVM size for cayman+ is 40 bits. |
23d4f1f2 | 1284 | */ |
20b2656d | 1285 | rdev->vm_manager.max_pfn = radeon_vm_size << 18; |
771fe6b9 | 1286 | |
4aac0473 JG |
1287 | /* Set asic functions */ |
1288 | r = radeon_asic_init(rdev); | |
36421338 | 1289 | if (r) |
4aac0473 | 1290 | return r; |
4aac0473 | 1291 | |
f95df9ca AD |
1292 | /* all of the newer IGP chips have an internal gart |
1293 | * However some rs4xx report as AGP, so remove that here. | |
1294 | */ | |
1295 | if ((rdev->family >= CHIP_RS400) && | |
1296 | (rdev->flags & RADEON_IS_IGP)) { | |
1297 | rdev->flags &= ~RADEON_IS_AGP; | |
1298 | } | |
1299 | ||
30256a3f | 1300 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
b574f251 | 1301 | radeon_agp_disable(rdev); |
771fe6b9 JG |
1302 | } |
1303 | ||
9ed8b1f9 AD |
1304 | /* Set the internal MC address mask |
1305 | * This is the max address of the GPU's | |
1306 | * internal address space. | |
1307 | */ | |
1308 | if (rdev->family >= CHIP_CAYMAN) | |
1309 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ | |
1310 | else if (rdev->family >= CHIP_CEDAR) | |
1311 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ | |
1312 | else | |
1313 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ | |
1314 | ||
ad49f501 DA |
1315 | /* set DMA mask + need_dma32 flags. |
1316 | * PCIE - can handle 40-bits. | |
005a83f1 | 1317 | * IGP - can handle 40-bits |
ad49f501 | 1318 | * AGP - generally dma32 is safest |
005a83f1 | 1319 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
ad49f501 DA |
1320 | */ |
1321 | rdev->need_dma32 = false; | |
1322 | if (rdev->flags & RADEON_IS_AGP) | |
1323 | rdev->need_dma32 = true; | |
005a83f1 | 1324 | if ((rdev->flags & RADEON_IS_PCI) && |
4a2b6662 | 1325 | (rdev->family <= CHIP_RS740)) |
ad49f501 DA |
1326 | rdev->need_dma32 = true; |
1327 | ||
1328 | dma_bits = rdev->need_dma32 ? 32 : 40; | |
1329 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | |
771fe6b9 | 1330 | if (r) { |
62fff811 | 1331 | rdev->need_dma32 = true; |
c52494f6 | 1332 | dma_bits = 32; |
771fe6b9 JG |
1333 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
1334 | } | |
c52494f6 KRW |
1335 | r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
1336 | if (r) { | |
1337 | pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); | |
1338 | printk(KERN_WARNING "radeon: No coherent DMA available.\n"); | |
1339 | } | |
771fe6b9 JG |
1340 | |
1341 | /* Registers mapping */ | |
1342 | /* TODO: block userspace mapping of io register */ | |
2c385151 | 1343 | spin_lock_init(&rdev->mmio_idx_lock); |
fe78118c | 1344 | spin_lock_init(&rdev->smc_idx_lock); |
0a5b7b0b AD |
1345 | spin_lock_init(&rdev->pll_idx_lock); |
1346 | spin_lock_init(&rdev->mc_idx_lock); | |
1347 | spin_lock_init(&rdev->pcie_idx_lock); | |
1348 | spin_lock_init(&rdev->pciep_idx_lock); | |
1349 | spin_lock_init(&rdev->pif_idx_lock); | |
1350 | spin_lock_init(&rdev->cg_idx_lock); | |
1351 | spin_lock_init(&rdev->uvd_idx_lock); | |
1352 | spin_lock_init(&rdev->rcu_idx_lock); | |
1353 | spin_lock_init(&rdev->didt_idx_lock); | |
1354 | spin_lock_init(&rdev->end_idx_lock); | |
efad86db AD |
1355 | if (rdev->family >= CHIP_BONAIRE) { |
1356 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); | |
1357 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); | |
1358 | } else { | |
1359 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); | |
1360 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); | |
1361 | } | |
771fe6b9 JG |
1362 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
1363 | if (rdev->rmmio == NULL) { | |
1364 | return -ENOMEM; | |
1365 | } | |
1366 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); | |
1367 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); | |
1368 | ||
75efdee1 AD |
1369 | /* doorbell bar mapping */ |
1370 | if (rdev->family >= CHIP_BONAIRE) | |
1371 | radeon_doorbell_init(rdev); | |
1372 | ||
351a52a2 AD |
1373 | /* io port mapping */ |
1374 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1375 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { | |
1376 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); | |
1377 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); | |
1378 | break; | |
1379 | } | |
1380 | } | |
1381 | if (rdev->rio_mem == NULL) | |
1382 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1383 | ||
4807c5a8 AD |
1384 | if (rdev->flags & RADEON_IS_PX) |
1385 | radeon_device_handle_px_quirks(rdev); | |
1386 | ||
28d52043 | 1387 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
93239ea1 DA |
1388 | /* this will fail for cards that aren't VGA class devices, just |
1389 | * ignore it */ | |
1390 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); | |
10ebc0bc | 1391 | |
90c4cde9 | 1392 | if (rdev->flags & RADEON_IS_PX) |
10ebc0bc DA |
1393 | runtime = true; |
1394 | vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); | |
1395 | if (runtime) | |
1396 | vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); | |
28d52043 | 1397 | |
3ce0a23d | 1398 | r = radeon_init(rdev); |
b574f251 | 1399 | if (r) |
2e97140d | 1400 | goto failed; |
3ce0a23d | 1401 | |
04eb2206 CK |
1402 | r = radeon_ib_ring_tests(rdev); |
1403 | if (r) | |
1404 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1405 | ||
409851f4 JG |
1406 | r = radeon_gem_debugfs_init(rdev); |
1407 | if (r) { | |
1408 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1409 | } | |
1410 | ||
b574f251 JG |
1411 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
1412 | /* Acceleration not working on AGP card try again | |
1413 | * with fallback to PCI or PCIE GART | |
1414 | */ | |
a2d07b74 | 1415 | radeon_asic_reset(rdev); |
b574f251 JG |
1416 | radeon_fini(rdev); |
1417 | radeon_agp_disable(rdev); | |
1418 | r = radeon_init(rdev); | |
4aac0473 | 1419 | if (r) |
2e97140d | 1420 | goto failed; |
771fe6b9 | 1421 | } |
6c7bccea | 1422 | |
60a7e396 | 1423 | if ((radeon_testing & 1)) { |
4a1132a0 AD |
1424 | if (rdev->accel_working) |
1425 | radeon_test_moves(rdev); | |
1426 | else | |
1427 | DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); | |
ecc0b326 | 1428 | } |
60a7e396 | 1429 | if ((radeon_testing & 2)) { |
4a1132a0 AD |
1430 | if (rdev->accel_working) |
1431 | radeon_test_syncing(rdev); | |
1432 | else | |
1433 | DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); | |
60a7e396 | 1434 | } |
771fe6b9 | 1435 | if (radeon_benchmarking) { |
4a1132a0 AD |
1436 | if (rdev->accel_working) |
1437 | radeon_benchmark(rdev, radeon_benchmarking); | |
1438 | else | |
1439 | DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); | |
771fe6b9 | 1440 | } |
6cf8a3f5 | 1441 | return 0; |
2e97140d AD |
1442 | |
1443 | failed: | |
1444 | if (runtime) | |
1445 | vga_switcheroo_fini_domain_pm_ops(rdev->dev); | |
1446 | return r; | |
771fe6b9 JG |
1447 | } |
1448 | ||
4d8bf9ae CK |
1449 | static void radeon_debugfs_remove_files(struct radeon_device *rdev); |
1450 | ||
0c195119 AD |
1451 | /** |
1452 | * radeon_device_fini - tear down the driver | |
1453 | * | |
1454 | * @rdev: radeon_device pointer | |
1455 | * | |
1456 | * Tear down the driver info (all asics). | |
1457 | * Called at driver shutdown. | |
1458 | */ | |
771fe6b9 JG |
1459 | void radeon_device_fini(struct radeon_device *rdev) |
1460 | { | |
771fe6b9 JG |
1461 | DRM_INFO("radeon: finishing device.\n"); |
1462 | rdev->shutdown = true; | |
90aca4d2 JG |
1463 | /* evict vram memory */ |
1464 | radeon_bo_evict_vram(rdev); | |
62a8ea3f | 1465 | radeon_fini(rdev); |
6a9ee8af | 1466 | vga_switcheroo_unregister_client(rdev->pdev); |
2e97140d AD |
1467 | if (rdev->flags & RADEON_IS_PX) |
1468 | vga_switcheroo_fini_domain_pm_ops(rdev->dev); | |
c1176d6f | 1469 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
e0a2ca73 AD |
1470 | if (rdev->rio_mem) |
1471 | pci_iounmap(rdev->pdev, rdev->rio_mem); | |
351a52a2 | 1472 | rdev->rio_mem = NULL; |
771fe6b9 JG |
1473 | iounmap(rdev->rmmio); |
1474 | rdev->rmmio = NULL; | |
75efdee1 AD |
1475 | if (rdev->family >= CHIP_BONAIRE) |
1476 | radeon_doorbell_fini(rdev); | |
4d8bf9ae | 1477 | radeon_debugfs_remove_files(rdev); |
771fe6b9 JG |
1478 | } |
1479 | ||
1480 | ||
1481 | /* | |
1482 | * Suspend & resume. | |
1483 | */ | |
0c195119 AD |
1484 | /** |
1485 | * radeon_suspend_kms - initiate device suspend | |
1486 | * | |
1487 | * @pdev: drm dev pointer | |
1488 | * @state: suspend state | |
1489 | * | |
1490 | * Puts the hw in the suspend state (all asics). | |
1491 | * Returns 0 for success or an error on failure. | |
1492 | * Called at driver suspend. | |
1493 | */ | |
10ebc0bc | 1494 | int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) |
771fe6b9 | 1495 | { |
875c1866 | 1496 | struct radeon_device *rdev; |
771fe6b9 | 1497 | struct drm_crtc *crtc; |
d8dcaa1d | 1498 | struct drm_connector *connector; |
7465280c | 1499 | int i, r; |
5f8f635e | 1500 | bool force_completion = false; |
771fe6b9 | 1501 | |
875c1866 | 1502 | if (dev == NULL || dev->dev_private == NULL) { |
771fe6b9 JG |
1503 | return -ENODEV; |
1504 | } | |
7473e830 | 1505 | |
875c1866 DJ |
1506 | rdev = dev->dev_private; |
1507 | ||
5bcf719b | 1508 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
6a9ee8af | 1509 | return 0; |
d8dcaa1d | 1510 | |
86698c20 SF |
1511 | drm_kms_helper_poll_disable(dev); |
1512 | ||
d8dcaa1d AD |
1513 | /* turn off display hw */ |
1514 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1515 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1516 | } | |
1517 | ||
771fe6b9 JG |
1518 | /* unpin the front buffers */ |
1519 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
f4510a27 | 1520 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); |
4c788679 | 1521 | struct radeon_bo *robj; |
771fe6b9 JG |
1522 | |
1523 | if (rfb == NULL || rfb->obj == NULL) { | |
1524 | continue; | |
1525 | } | |
7e4d15d9 | 1526 | robj = gem_to_radeon_bo(rfb->obj); |
38651674 DA |
1527 | /* don't unpin kernel fb objects */ |
1528 | if (!radeon_fbdev_robj_is_fb(rdev, robj)) { | |
4c788679 | 1529 | r = radeon_bo_reserve(robj, false); |
38651674 | 1530 | if (r == 0) { |
4c788679 JG |
1531 | radeon_bo_unpin(robj); |
1532 | radeon_bo_unreserve(robj); | |
1533 | } | |
771fe6b9 JG |
1534 | } |
1535 | } | |
1536 | /* evict vram memory */ | |
4c788679 | 1537 | radeon_bo_evict_vram(rdev); |
8a47cc9e | 1538 | |
771fe6b9 | 1539 | /* wait for gpu to finish processing current batch */ |
5f8f635e | 1540 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
37615527 | 1541 | r = radeon_fence_wait_empty(rdev, i); |
5f8f635e JG |
1542 | if (r) { |
1543 | /* delay GPU reset to resume */ | |
1544 | force_completion = true; | |
1545 | } | |
1546 | } | |
1547 | if (force_completion) { | |
1548 | radeon_fence_driver_force_completion(rdev); | |
1549 | } | |
771fe6b9 | 1550 | |
f657c2a7 YZ |
1551 | radeon_save_bios_scratch_regs(rdev); |
1552 | ||
62a8ea3f | 1553 | radeon_suspend(rdev); |
d4877cf2 | 1554 | radeon_hpd_fini(rdev); |
771fe6b9 | 1555 | /* evict remaining vram memory */ |
4c788679 | 1556 | radeon_bo_evict_vram(rdev); |
771fe6b9 | 1557 | |
10b06122 JG |
1558 | radeon_agp_suspend(rdev); |
1559 | ||
771fe6b9 | 1560 | pci_save_state(dev->pdev); |
7473e830 | 1561 | if (suspend) { |
771fe6b9 JG |
1562 | /* Shut down the device */ |
1563 | pci_disable_device(dev->pdev); | |
1564 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
1565 | } | |
10ebc0bc DA |
1566 | |
1567 | if (fbcon) { | |
1568 | console_lock(); | |
1569 | radeon_fbdev_set_suspend(rdev, 1); | |
1570 | console_unlock(); | |
1571 | } | |
771fe6b9 JG |
1572 | return 0; |
1573 | } | |
1574 | ||
0c195119 AD |
1575 | /** |
1576 | * radeon_resume_kms - initiate device resume | |
1577 | * | |
1578 | * @pdev: drm dev pointer | |
1579 | * | |
1580 | * Bring the hw back to operating state (all asics). | |
1581 | * Returns 0 for success or an error on failure. | |
1582 | * Called at driver resume. | |
1583 | */ | |
10ebc0bc | 1584 | int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) |
771fe6b9 | 1585 | { |
09bdf591 | 1586 | struct drm_connector *connector; |
771fe6b9 | 1587 | struct radeon_device *rdev = dev->dev_private; |
04eb2206 | 1588 | int r; |
771fe6b9 | 1589 | |
5bcf719b | 1590 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
6a9ee8af DA |
1591 | return 0; |
1592 | ||
10ebc0bc DA |
1593 | if (fbcon) { |
1594 | console_lock(); | |
1595 | } | |
7473e830 DA |
1596 | if (resume) { |
1597 | pci_set_power_state(dev->pdev, PCI_D0); | |
1598 | pci_restore_state(dev->pdev); | |
1599 | if (pci_enable_device(dev->pdev)) { | |
10ebc0bc DA |
1600 | if (fbcon) |
1601 | console_unlock(); | |
7473e830 DA |
1602 | return -1; |
1603 | } | |
771fe6b9 | 1604 | } |
0ebf1717 DA |
1605 | /* resume AGP if in use */ |
1606 | radeon_agp_resume(rdev); | |
62a8ea3f | 1607 | radeon_resume(rdev); |
04eb2206 CK |
1608 | |
1609 | r = radeon_ib_ring_tests(rdev); | |
1610 | if (r) | |
1611 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1612 | ||
bc6a6295 | 1613 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
6c7bccea AD |
1614 | /* do dpm late init */ |
1615 | r = radeon_pm_late_init(rdev); | |
1616 | if (r) { | |
1617 | rdev->pm.dpm_enabled = false; | |
1618 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | |
1619 | } | |
bc6a6295 AD |
1620 | } else { |
1621 | /* resume old pm late */ | |
1622 | radeon_pm_resume(rdev); | |
6c7bccea AD |
1623 | } |
1624 | ||
f657c2a7 | 1625 | radeon_restore_bios_scratch_regs(rdev); |
09bdf591 | 1626 | |
3fa47d9e AD |
1627 | /* init dig PHYs, disp eng pll */ |
1628 | if (rdev->is_atom_bios) { | |
ac89af1e | 1629 | radeon_atom_encoder_init(rdev); |
f3f1f03e | 1630 | radeon_atom_disp_eng_pll_init(rdev); |
bced76f2 AD |
1631 | /* turn on the BL */ |
1632 | if (rdev->mode_info.bl_encoder) { | |
1633 | u8 bl_level = radeon_get_backlight_level(rdev, | |
1634 | rdev->mode_info.bl_encoder); | |
1635 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, | |
1636 | bl_level); | |
1637 | } | |
3fa47d9e | 1638 | } |
d4877cf2 AD |
1639 | /* reset hpd state */ |
1640 | radeon_hpd_init(rdev); | |
771fe6b9 | 1641 | /* blat the mode back in */ |
ec9954fc DA |
1642 | if (fbcon) { |
1643 | drm_helper_resume_force_mode(dev); | |
1644 | /* turn on display hw */ | |
1645 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1646 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
1647 | } | |
a93f344d | 1648 | } |
86698c20 SF |
1649 | |
1650 | drm_kms_helper_poll_enable(dev); | |
18ee37a4 | 1651 | |
3640da2f AD |
1652 | /* set the power state here in case we are a PX system or headless */ |
1653 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) | |
1654 | radeon_pm_compute_clocks(rdev); | |
1655 | ||
18ee37a4 DV |
1656 | if (fbcon) { |
1657 | radeon_fbdev_set_suspend(rdev, 0); | |
1658 | console_unlock(); | |
1659 | } | |
1660 | ||
771fe6b9 JG |
1661 | return 0; |
1662 | } | |
1663 | ||
0c195119 AD |
1664 | /** |
1665 | * radeon_gpu_reset - reset the asic | |
1666 | * | |
1667 | * @rdev: radeon device pointer | |
1668 | * | |
1669 | * Attempt the reset the GPU if it has hung (all asics). | |
1670 | * Returns 0 for success or an error on failure. | |
1671 | */ | |
90aca4d2 JG |
1672 | int radeon_gpu_reset(struct radeon_device *rdev) |
1673 | { | |
55d7c221 CK |
1674 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
1675 | uint32_t *ring_data[RADEON_NUM_RINGS]; | |
1676 | ||
1677 | bool saved = false; | |
1678 | ||
1679 | int i, r; | |
8fd1b84c | 1680 | int resched; |
90aca4d2 | 1681 | |
dee53e7f | 1682 | down_write(&rdev->exclusive_lock); |
f9eaf9ae CK |
1683 | |
1684 | if (!rdev->needs_reset) { | |
1685 | up_write(&rdev->exclusive_lock); | |
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | rdev->needs_reset = false; | |
1690 | ||
90aca4d2 | 1691 | radeon_save_bios_scratch_regs(rdev); |
8fd1b84c DA |
1692 | /* block TTM */ |
1693 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | |
90aca4d2 | 1694 | radeon_suspend(rdev); |
73ef0e0d | 1695 | radeon_hpd_fini(rdev); |
90aca4d2 | 1696 | |
55d7c221 CK |
1697 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1698 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], | |
1699 | &ring_data[i]); | |
1700 | if (ring_sizes[i]) { | |
1701 | saved = true; | |
1702 | dev_info(rdev->dev, "Saved %d dwords of commands " | |
1703 | "on ring %d.\n", ring_sizes[i], i); | |
1704 | } | |
1705 | } | |
1706 | ||
1707 | retry: | |
90aca4d2 JG |
1708 | r = radeon_asic_reset(rdev); |
1709 | if (!r) { | |
55d7c221 | 1710 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
90aca4d2 | 1711 | radeon_resume(rdev); |
55d7c221 | 1712 | } |
04eb2206 | 1713 | |
55d7c221 | 1714 | radeon_restore_bios_scratch_regs(rdev); |
04eb2206 | 1715 | |
55d7c221 CK |
1716 | if (!r) { |
1717 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
1718 | radeon_ring_restore(rdev, &rdev->ring[i], | |
1719 | ring_sizes[i], ring_data[i]); | |
f54b350d CK |
1720 | ring_sizes[i] = 0; |
1721 | ring_data[i] = NULL; | |
55d7c221 CK |
1722 | } |
1723 | ||
1724 | r = radeon_ib_ring_tests(rdev); | |
1725 | if (r) { | |
1726 | dev_err(rdev->dev, "ib ring test failed (%d).\n", r); | |
1727 | if (saved) { | |
f54b350d | 1728 | saved = false; |
55d7c221 CK |
1729 | radeon_suspend(rdev); |
1730 | goto retry; | |
1731 | } | |
1732 | } | |
1733 | } else { | |
76903b96 | 1734 | radeon_fence_driver_force_completion(rdev); |
55d7c221 CK |
1735 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1736 | kfree(ring_data[i]); | |
1737 | } | |
90aca4d2 | 1738 | } |
7a1619b9 | 1739 | |
c940b447 AD |
1740 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
1741 | /* do dpm late init */ | |
1742 | r = radeon_pm_late_init(rdev); | |
1743 | if (r) { | |
1744 | rdev->pm.dpm_enabled = false; | |
1745 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | |
1746 | } | |
1747 | } else { | |
1748 | /* resume old pm late */ | |
1749 | radeon_pm_resume(rdev); | |
1750 | } | |
1751 | ||
73ef0e0d AD |
1752 | /* init dig PHYs, disp eng pll */ |
1753 | if (rdev->is_atom_bios) { | |
1754 | radeon_atom_encoder_init(rdev); | |
1755 | radeon_atom_disp_eng_pll_init(rdev); | |
1756 | /* turn on the BL */ | |
1757 | if (rdev->mode_info.bl_encoder) { | |
1758 | u8 bl_level = radeon_get_backlight_level(rdev, | |
1759 | rdev->mode_info.bl_encoder); | |
1760 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, | |
1761 | bl_level); | |
1762 | } | |
1763 | } | |
1764 | /* reset hpd state */ | |
1765 | radeon_hpd_init(rdev); | |
1766 | ||
d3493574 JG |
1767 | drm_helper_resume_force_mode(rdev->ddev); |
1768 | ||
c940b447 AD |
1769 | /* set the power state here in case we are a PX system or headless */ |
1770 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) | |
1771 | radeon_pm_compute_clocks(rdev); | |
1772 | ||
55d7c221 | 1773 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
7a1619b9 MD |
1774 | if (r) { |
1775 | /* bad news, how to tell it to userspace ? */ | |
1776 | dev_info(rdev->dev, "GPU reset failed\n"); | |
1777 | } | |
1778 | ||
dee53e7f | 1779 | up_write(&rdev->exclusive_lock); |
90aca4d2 JG |
1780 | return r; |
1781 | } | |
1782 | ||
771fe6b9 JG |
1783 | |
1784 | /* | |
1785 | * Debugfs | |
1786 | */ | |
771fe6b9 JG |
1787 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1788 | struct drm_info_list *files, | |
1789 | unsigned nfiles) | |
1790 | { | |
1791 | unsigned i; | |
1792 | ||
4d8bf9ae CK |
1793 | for (i = 0; i < rdev->debugfs_count; i++) { |
1794 | if (rdev->debugfs[i].files == files) { | |
771fe6b9 JG |
1795 | /* Already registered */ |
1796 | return 0; | |
1797 | } | |
1798 | } | |
c245cb9e | 1799 | |
4d8bf9ae | 1800 | i = rdev->debugfs_count + 1; |
c245cb9e MW |
1801 | if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { |
1802 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
1803 | DRM_ERROR("Report so we increase " | |
1804 | "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); | |
771fe6b9 JG |
1805 | return -EINVAL; |
1806 | } | |
4d8bf9ae CK |
1807 | rdev->debugfs[rdev->debugfs_count].files = files; |
1808 | rdev->debugfs[rdev->debugfs_count].num_files = nfiles; | |
1809 | rdev->debugfs_count = i; | |
771fe6b9 JG |
1810 | #if defined(CONFIG_DEBUG_FS) |
1811 | drm_debugfs_create_files(files, nfiles, | |
1812 | rdev->ddev->control->debugfs_root, | |
1813 | rdev->ddev->control); | |
1814 | drm_debugfs_create_files(files, nfiles, | |
1815 | rdev->ddev->primary->debugfs_root, | |
1816 | rdev->ddev->primary); | |
1817 | #endif | |
1818 | return 0; | |
1819 | } | |
1820 | ||
4d8bf9ae CK |
1821 | static void radeon_debugfs_remove_files(struct radeon_device *rdev) |
1822 | { | |
1823 | #if defined(CONFIG_DEBUG_FS) | |
1824 | unsigned i; | |
1825 | ||
1826 | for (i = 0; i < rdev->debugfs_count; i++) { | |
1827 | drm_debugfs_remove_files(rdev->debugfs[i].files, | |
1828 | rdev->debugfs[i].num_files, | |
1829 | rdev->ddev->control); | |
1830 | drm_debugfs_remove_files(rdev->debugfs[i].files, | |
1831 | rdev->debugfs[i].num_files, | |
1832 | rdev->ddev->primary); | |
1833 | } | |
1834 | #endif | |
1835 | } | |
1836 | ||
771fe6b9 JG |
1837 | #if defined(CONFIG_DEBUG_FS) |
1838 | int radeon_debugfs_init(struct drm_minor *minor) | |
1839 | { | |
1840 | return 0; | |
1841 | } | |
1842 | ||
1843 | void radeon_debugfs_cleanup(struct drm_minor *minor) | |
1844 | { | |
771fe6b9 JG |
1845 | } |
1846 | #endif |