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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
10ebc0bc 33#include <linux/pm_runtime.h>
760285e7 34#include <drm/drm_crtc_helper.h>
3cb9ae4f 35#include <drm/drm_plane_helper.h>
760285e7 36#include <drm/drm_edid.h>
771fe6b9 37
32167016
CK		 38#include <linux/gcd.h>
39
771fe6b9
JG		 40static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41{
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 int i;
46
d9fdaafb 47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61
62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
63 for (i = 0; i < 256; i++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR,
65 (radeon_crtc->lut_r[i] << 20) |
66 (radeon_crtc->lut_g[i] << 10) |
67 (radeon_crtc->lut_b[i] << 0));
68 }
69
4366f3b5
MK		 70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
771fe6b9
JG		 72}
73
fee298fd 74static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 75{
76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
77 struct drm_device *dev = crtc->dev;
78 struct radeon_device *rdev = dev->dev_private;
79 int i;
80
d9fdaafb 81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
83
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
87
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
91
677d0768
AD		 92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 94
677d0768 95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 96 for (i = 0; i < 256; i++) {
677d0768 97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 98 (radeon_crtc->lut_r[i] << 20) |
99 (radeon_crtc->lut_g[i] << 10) |
100 (radeon_crtc->lut_b[i] << 0));
101 }
102}
103
fee298fd
AD		 104static void dce5_crtc_load_lut(struct drm_crtc *crtc)
105{
106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
107 struct drm_device *dev = crtc->dev;
108 struct radeon_device *rdev = dev->dev_private;
109 int i;
110
111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
112
113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
117 NI_GRPH_PRESCALE_BYPASS);
118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
119 NI_OVL_PRESCALE_BYPASS);
120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
123
124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
125
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
129
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
133
134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
136
137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
138 for (i = 0; i < 256; i++) {
139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
140 (radeon_crtc->lut_r[i] << 20) |
141 (radeon_crtc->lut_g[i] << 10) |
142 (radeon_crtc->lut_b[i] << 0));
143 }
144
145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
643b1f56 157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
fee298fd
AD		 158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 161 if (ASIC_IS_DCE8(rdev)) {
162 /* XXX this only needs to be programmed once per crtc at startup,
163 * not sure where the best place for it is
164 */
165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
166 CIK_CURSOR_ALPHA_BLND_ENA);
167 }
fee298fd
AD		 168}
169
771fe6b9
JG		 170static void legacy_crtc_load_lut(struct drm_crtc *crtc)
171{
172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
173 struct drm_device *dev = crtc->dev;
174 struct radeon_device *rdev = dev->dev_private;
175 int i;
176 uint32_t dac2_cntl;
177
178 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
179 if (radeon_crtc->crtc_id == 0)
180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
181 else
182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
183 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
184
185 WREG8(RADEON_PALETTE_INDEX, 0);
186 for (i = 0; i < 256; i++) {
187 WREG32(RADEON_PALETTE_30_DATA,
188 (radeon_crtc->lut_r[i] << 20) |
189 (radeon_crtc->lut_g[i] << 10) |
190 (radeon_crtc->lut_b[i] << 0));
191 }
192}
193
194void radeon_crtc_load_lut(struct drm_crtc *crtc)
195{
196 struct drm_device *dev = crtc->dev;
197 struct radeon_device *rdev = dev->dev_private;
198
199 if (!crtc->enabled)
200 return;
201
fee298fd
AD		 202 if (ASIC_IS_DCE5(rdev))
203 dce5_crtc_load_lut(crtc);
204 else if (ASIC_IS_DCE4(rdev))
205 dce4_crtc_load_lut(crtc);
bcc1c2a1 206 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 207 avivo_crtc_load_lut(crtc);
208 else
209 legacy_crtc_load_lut(crtc);
210}
211
b8c00ac5 212/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 213void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
214 u16 blue, int regno)
215{
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217
771fe6b9
JG		 218 radeon_crtc->lut_r[regno] = red >> 6;
219 radeon_crtc->lut_g[regno] = green >> 6;
220 radeon_crtc->lut_b[regno] = blue >> 6;
221}
222
b8c00ac5
DA		 223/** Gets the color ramps on behalf of fbcon */
224void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
225 u16 *blue, int regno)
226{
227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
228
229 *red = radeon_crtc->lut_r[regno] << 6;
230 *green = radeon_crtc->lut_g[regno] << 6;
231 *blue = radeon_crtc->lut_b[regno] << 6;
232}
233
771fe6b9 234static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 235 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 236{
237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 238 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 239
b8c00ac5 240 /* userspace palettes are always correct as is */
7203425a 241 for (i = start; i < end; i++) {
b8c00ac5
DA		 242 radeon_crtc->lut_r[i] = red[i] >> 6;
243 radeon_crtc->lut_g[i] = green[i] >> 6;
244 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 245 }
771fe6b9
JG		 246 radeon_crtc_load_lut(crtc);
247}
248
249static void radeon_crtc_destroy(struct drm_crtc *crtc)
250{
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252
771fe6b9 253 drm_crtc_cleanup(crtc);
fa7f517c 254 destroy_workqueue(radeon_crtc->flip_queue);
771fe6b9
JG		 255 kfree(radeon_crtc);
256}
257
fa7f517c
CK		 258/**
259 * radeon_unpin_work_func - unpin old buffer object
260 *
261 * @__work - kernel work item
262 *
263 * Unpin the old frame buffer object outside of the interrupt handler
6f34be50
AD		 264 */
265static void radeon_unpin_work_func(struct work_struct *__work)
266{
fa7f517c
CK		 267 struct radeon_flip_work *work =
268 container_of(__work, struct radeon_flip_work, unpin_work);
6f34be50
AD		 269 int r;
270
271 /* unpin of the old buffer */
272 r = radeon_bo_reserve(work->old_rbo, false);
273 if (likely(r == 0)) {
274 r = radeon_bo_unpin(work->old_rbo);
275 if (unlikely(r != 0)) {
276 DRM_ERROR("failed to unpin buffer after flip\n");
277 }
278 radeon_bo_unreserve(work->old_rbo);
279 } else
280 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 281
282 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 283 kfree(work);
284}
285
1a0e7918 286void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
6f34be50
AD		 287{
288 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
6f34be50
AD		 289 unsigned long flags;
290 u32 update_pending;
291 int vpos, hpos;
292
f5d636d2
CK		 293 /* can happen during initialization */
294 if (radeon_crtc == NULL)
295 return;
6f34be50 296
39dc5454
MK		 297 /* Skip the pageflip completion check below (based on polling) on
298 * asics which reliably support hw pageflip completion irqs. pflip
299 * irqs are a reliable and race-free method of handling pageflip
300 * completion detection. A use_pflipirq module parameter < 2 allows
301 * to override this in case of asics with faulty pflip irqs.
302 * A module parameter of 0 would only use this polling based path,
303 * a parameter of 1 would use pflip irq only as a backup to this
304 * path, as in Linux 3.16.
305 */
306 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
307 return;
308
6f34be50 309 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
a2b6d3b3
MD		 310 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
311 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
312 "RADEON_FLIP_SUBMITTED(%d)\n",
313 radeon_crtc->flip_status,
314 RADEON_FLIP_SUBMITTED);
6f34be50
AD		 315 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
316 return;
317 }
fa7f517c
CK		 318
319 update_pending = radeon_page_flip_pending(rdev, crtc_id);
6f34be50
AD		 320
321 /* Has the pageflip already completed in crtc, or is it certain
322 * to complete in this vblank?
323 */
324 if (update_pending &&
5b5561b3
MK		 325 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
326 crtc_id,
327 USE_REAL_VBLANKSTART,
3bb403bf
VS		 328 &vpos, &hpos, NULL, NULL,
329 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
81ffbbed
FK		 330 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
331 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
332 /* crtc didn't flip in this target vblank interval,
333 * but flip is pending in crtc. Based on the current
334 * scanout position we know that the current frame is
335 * (nearly) complete and the flip will (likely)
336 * complete before the start of the next frame.
337 */
338 update_pending = 0;
339 }
fa7f517c
CK		 340 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
341 if (!update_pending)
1a0e7918 342 radeon_crtc_handle_flip(rdev, crtc_id);
1a0e7918
CK		 343}
344
345/**
346 * radeon_crtc_handle_flip - page flip completed
347 *
348 * @rdev: radeon device pointer
349 * @crtc_id: crtc number this event is for
350 *
351 * Called when we are sure that a page flip for this crtc is completed.
352 */
353void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
354{
355 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
fa7f517c 356 struct radeon_flip_work *work;
1a0e7918
CK		 357 unsigned long flags;
358
359 /* this can happen at init */
360 if (radeon_crtc == NULL)
361 return;
362
363 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
fa7f517c 364 work = radeon_crtc->flip_work;
a2b6d3b3
MD		 365 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
366 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
367 "RADEON_FLIP_SUBMITTED(%d)\n",
368 radeon_crtc->flip_status,
369 RADEON_FLIP_SUBMITTED);
1a0e7918
CK		 370 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
371 return;
6f34be50
AD		 372 }
373
fa7f517c 374 /* Pageflip completed. Clean up. */
a2b6d3b3 375 radeon_crtc->flip_status = RADEON_FLIP_NONE;
fa7f517c 376 radeon_crtc->flip_work = NULL;
6f34be50
AD		 377
378 /* wakeup userspace */
26ae4667 379 if (work->event)
eba92811 380 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
26ae4667 381
6f34be50
AD		 382 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
383
ca721b79 384 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
46889d95 385 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
fa7f517c 386 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
6f34be50
AD		 387}
388
fa7f517c
CK		 389/**
390 * radeon_flip_work_func - page flip framebuffer
391 *
392 * @work - kernel work item
393 *
394 * Wait for the buffer object to become idle and do the actual page flip
395 */
396static void radeon_flip_work_func(struct work_struct *__work)
6f34be50 397{
fa7f517c
CK		 398 struct radeon_flip_work *work =
399 container_of(__work, struct radeon_flip_work, flip_work);
400 struct radeon_device *rdev = work->rdev;
401 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
6f34be50 402
fa7f517c 403 struct drm_crtc *crtc = &radeon_crtc->base;
fa7f517c
CK		 404 unsigned long flags;
405 int r;
2b8341b3
MK		 406 int vpos, hpos, stat, min_udelay = 0;
407 unsigned repcnt = 4;
5b5561b3 408 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
9af20792 409
3cf8bb1a 410 down_read(&rdev->exclusive_lock);
306f98d9 411 if (work->fence) {
a0e84764
ML		 412 struct radeon_fence *fence;
413
414 fence = to_radeon_fence(work->fence);
415 if (fence && fence->rdev == rdev) {
416 r = radeon_fence_wait(fence, false);
417 if (r == -EDEADLK) {
418 up_read(&rdev->exclusive_lock);
419 do {
420 r = radeon_gpu_reset(rdev);
421 } while (r == -EAGAIN);
422 down_read(&rdev->exclusive_lock);
423 }
424 } else
425 r = fence_wait(work->fence, false);
426
306f98d9
MD		 427 if (r)
428 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
6f34be50 429
306f98d9
MD		 430 /* We continue with the page flip even if we failed to wait on
431 * the fence, otherwise the DRM core and userspace will be
432 * confused about which BO the CRTC is scanning out
433 */
434
a0e84764
ML		 435 fence_put(work->fence);
436 work->fence = NULL;
6f34be50 437 }
6f34be50 438
c60381bd
MD		 439 /* We borrow the event spin lock for protecting flip_status */
440 spin_lock_irqsave(&crtc->dev->event_lock, flags);
441
442 /* set the proper interrupt */
443 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
444
5b5561b3
MK		 445 /* If this happens to execute within the "virtually extended" vblank
446 * interval before the start of the real vblank interval then it needs
447 * to delay programming the mmio flip until the real vblank is entered.
448 * This prevents completing a flip too early due to the way we fudge
449 * our vblank counter and vblank timestamps in order to work around the
450 * problem that the hw fires vblank interrupts before actual start of
451 * vblank (when line buffer refilling is done for a frame). It
452 * complements the fudging logic in radeon_get_crtc_scanoutpos() for
453 * timestamping and radeon_get_vblank_counter_kms() for vblank counts.
454 *
455 * In practice this won't execute very often unless on very fast
456 * machines because the time window for this to happen is very small.
457 */
1e1490a3 458 while (radeon_crtc->enabled && --repcnt) {
5b5561b3
MK		 459 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
460 * start in hpos, and to the "fudged earlier" vblank start in
461 * vpos.
462 */
463 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id,
464 GET_DISTANCE_TO_VBLANKSTART,
465 &vpos, &hpos, NULL, NULL,
466 &crtc->hwmode);
467
468 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
469 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
470 !(vpos >= 0 && hpos <= 0))
471 break;
472
473 /* Sleep at least until estimated real start of hw vblank */
5b5561b3 474 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
2b8341b3
MK		 475 if (min_udelay > vblank->framedur_ns / 2000) {
476 /* Don't wait ridiculously long - something is wrong */
477 repcnt = 0;
478 break;
479 }
1e1490a3 480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
5b5561b3
MK		 481 usleep_range(min_udelay, 2 * min_udelay);
482 spin_lock_irqsave(&crtc->dev->event_lock, flags);
483 };
484
2b8341b3
MK		 485 if (!repcnt)
486 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
487 "framedur %d, linedur %d, stat %d, vpos %d, "
488 "hpos %d\n", work->crtc_id, min_udelay,
489 vblank->framedur_ns / 1000,
490 vblank->linedur_ns / 1000, stat, vpos, hpos);
491
5f87e090 492 /* do the flip (mmio) */
c63dd758 493 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
5f87e090 494
c60381bd
MD		 495 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
496 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
497 up_read(&rdev->exclusive_lock);
c60381bd
MD		 498}
499
500static int radeon_crtc_page_flip(struct drm_crtc *crtc,
501 struct drm_framebuffer *fb,
502 struct drm_pending_vblank_event *event,
503 uint32_t page_flip_flags)
504{
505 struct drm_device *dev = crtc->dev;
506 struct radeon_device *rdev = dev->dev_private;
507 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
508 struct radeon_framebuffer *old_radeon_fb;
509 struct radeon_framebuffer *new_radeon_fb;
510 struct drm_gem_object *obj;
511 struct radeon_flip_work *work;
512 struct radeon_bo *new_rbo;
513 uint32_t tiling_flags, pitch_pixels;
514 uint64_t base;
515 unsigned long flags;
516 int r;
517
518 work = kzalloc(sizeof *work, GFP_KERNEL);
519 if (work == NULL)
520 return -ENOMEM;
521
522 INIT_WORK(&work->flip_work, radeon_flip_work_func);
523 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
524
525 work->rdev = rdev;
526 work->crtc_id = radeon_crtc->crtc_id;
527 work->event = event;
c63dd758 528 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
c60381bd
MD		 529
530 /* schedule unpin of the old buffer */
531 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
532 obj = old_radeon_fb->obj;
533
534 /* take a reference to the old object */
535 drm_gem_object_reference(obj);
536 work->old_rbo = gem_to_radeon_bo(obj);
537
538 new_radeon_fb = to_radeon_framebuffer(fb);
539 obj = new_radeon_fb->obj;
540 new_rbo = gem_to_radeon_bo(obj);
541
6f34be50 542 /* pin the new buffer */
c60381bd
MD		 543 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
544 work->old_rbo, new_rbo);
6f34be50 545
c60381bd 546 r = radeon_bo_reserve(new_rbo, false);
6f34be50
AD		 547 if (unlikely(r != 0)) {
548 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
fa7f517c 549 goto cleanup;
6f34be50 550 }
0349af70 551 /* Only 27 bit offset for legacy CRTC */
c60381bd 552 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
0349af70 553 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50 554 if (unlikely(r != 0)) {
c60381bd 555 radeon_bo_unreserve(new_rbo);
6f34be50
AD		 556 r = -EINVAL;
557 DRM_ERROR("failed to pin new rbo buffer before flip\n");
fa7f517c 558 goto cleanup;
6f34be50 559 }
a0e84764 560 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
c60381bd
MD		 561 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
562 radeon_bo_unreserve(new_rbo);
6f34be50
AD		 563
564 if (!ASIC_IS_AVIVO(rdev)) {
565 /* crtc offset is from display base addr not FB location */
566 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 567 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 568
569 if (tiling_flags & RADEON_TILING_MACRO) {
570 if (ASIC_IS_R300(rdev)) {
571 base &= ~0x7ff;
572 } else {
573 int byteshift = fb->bits_per_pixel >> 4;
574 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
575 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
576 }
577 } else {
578 int offset = crtc->y * pitch_pixels + crtc->x;
579 switch (fb->bits_per_pixel) {
580 case 8:
581 default:
582 offset *= 1;
583 break;
584 case 15:
585 case 16:
586 offset *= 2;
587 break;
588 case 24:
589 offset *= 3;
590 break;
591 case 32:
592 offset *= 4;
593 break;
594 }
595 base += offset;
596 }
597 base &= ~7;
598 }
c60381bd 599 work->base = base;
6f34be50 600
ca721b79
MD		 601 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
602 if (r) {
603 DRM_ERROR("failed to get vblank before flip\n");
604 goto pflip_cleanup;
605 }
606
fa7f517c
CK		 607 /* We borrow the event spin lock for protecting flip_work */
608 spin_lock_irqsave(&crtc->dev->event_lock, flags);
b15eb4ea 609
c60381bd
MD		 610 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
611 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
612 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
613 r = -EBUSY;
82648497 614 goto vblank_cleanup;
c60381bd
MD		 615 }
616 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
617 radeon_crtc->flip_work = work;
6f34be50 618
c60381bd
MD		 619 /* update crtc fb */
620 crtc->primary->fb = fb;
fa7f517c
CK		 621
622 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
fa7f517c 623
c60381bd
MD		 624 queue_work(radeon_crtc->flip_queue, &work->flip_work);
625 return 0;
1aab5514 626
82648497
MK		 627vblank_cleanup:
628 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
629
ca721b79 630pflip_cleanup:
c60381bd 631 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
ca721b79
MD		 632 DRM_ERROR("failed to reserve new rbo in error path\n");
633 goto cleanup;
634 }
c60381bd 635 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
ca721b79
MD		 636 DRM_ERROR("failed to unpin new rbo in error path\n");
637 }
c60381bd 638 radeon_bo_unreserve(new_rbo);
ca721b79 639
fa7f517c
CK		 640cleanup:
641 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
a0e84764 642 fence_put(work->fence);
6f34be50 643 kfree(work);
c60381bd 644 return r;
6f34be50
AD		 645}
646
10ebc0bc
DA		 647static int
648radeon_crtc_set_config(struct drm_mode_set *set)
649{
650 struct drm_device *dev;
651 struct radeon_device *rdev;
652 struct drm_crtc *crtc;
653 bool active = false;
654 int ret;
655
656 if (!set || !set->crtc)
657 return -EINVAL;
658
659 dev = set->crtc->dev;
660
661 ret = pm_runtime_get_sync(dev->dev);
662 if (ret < 0)
663 return ret;
664
665 ret = drm_crtc_helper_set_config(set);
666
667 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
668 if (crtc->enabled)
669 active = true;
670
671 pm_runtime_mark_last_busy(dev->dev);
672
673 rdev = dev->dev_private;
674 /* if we have active crtcs and we don't have a power ref,
675 take the current one */
676 if (active && !rdev->have_disp_power_ref) {
677 rdev->have_disp_power_ref = true;
678 return ret;
679 }
680 /* if we have no active crtcs, then drop the power ref
681 we got before */
682 if (!active && rdev->have_disp_power_ref) {
683 pm_runtime_put_autosuspend(dev->dev);
684 rdev->have_disp_power_ref = false;
685 }
686
687 /* drop the power reference we got coming in here */
688 pm_runtime_put_autosuspend(dev->dev);
689 return ret;
690}
771fe6b9 691static const struct drm_crtc_funcs radeon_crtc_funcs = {
78b1a601 692 .cursor_set2 = radeon_crtc_cursor_set2,
771fe6b9
JG		 693 .cursor_move = radeon_crtc_cursor_move,
694 .gamma_set = radeon_crtc_gamma_set,
10ebc0bc 695 .set_config = radeon_crtc_set_config,
771fe6b9 696 .destroy = radeon_crtc_destroy,
6f34be50 697 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 698};
699
700static void radeon_crtc_init(struct drm_device *dev, int index)
701{
702 struct radeon_device *rdev = dev->dev_private;
703 struct radeon_crtc *radeon_crtc;
704 int i;
705
706 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
707 if (radeon_crtc == NULL)
708 return;
709
710 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
711
712 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
713 radeon_crtc->crtc_id = index;
fa7f517c 714 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
c93bb85b 715 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 716
9e05fa1d
AD		 717 if (rdev->family >= CHIP_BONAIRE) {
718 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
719 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
720 } else {
721 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
722 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
723 }
bea61c59
AD		 724 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
725 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
9e05fa1d 726
785b93ef 727#if 0
771fe6b9
JG		 728 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
729 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
730 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 731#endif
771fe6b9
JG		 732
733 for (i = 0; i < 256; i++) {
734 radeon_crtc->lut_r[i] = i << 2;
735 radeon_crtc->lut_g[i] = i << 2;
736 radeon_crtc->lut_b[i] = i << 2;
737 }
738
739 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
740 radeon_atombios_init_crtc(dev, radeon_crtc);
741 else
742 radeon_legacy_init_crtc(dev, radeon_crtc);
743}
744
e68adef8 745static const char *encoder_names[38] = {
771fe6b9
JG		 746 "NONE",
747 "INTERNAL_LVDS",
748 "INTERNAL_TMDS1",
749 "INTERNAL_TMDS2",
750 "INTERNAL_DAC1",
751 "INTERNAL_DAC2",
752 "INTERNAL_SDVOA",
753 "INTERNAL_SDVOB",
754 "SI170B",
755 "CH7303",
756 "CH7301",
757 "INTERNAL_DVO1",
758 "EXTERNAL_SDVOA",
759 "EXTERNAL_SDVOB",
760 "TITFP513",
761 "INTERNAL_LVTM1",
762 "VT1623",
763 "HDMI_SI1930",
764 "HDMI_INTERNAL",
765 "INTERNAL_KLDSCP_TMDS1",
766 "INTERNAL_KLDSCP_DVO1",
767 "INTERNAL_KLDSCP_DAC1",
768 "INTERNAL_KLDSCP_DAC2",
769 "SI178",
770 "MVPU_FPGA",
771 "INTERNAL_DDI",
772 "VT1625",
773 "HDMI_SI1932",
774 "DP_AN9801",
775 "DP_DP501",
776 "INTERNAL_UNIPHY",
777 "INTERNAL_KLDSCP_LVTMA",
778 "INTERNAL_UNIPHY1",
779 "INTERNAL_UNIPHY2",
bf982ebf
AD		 780 "NUTMEG",
781 "TRAVIS",
e68adef8
AD		 782 "INTERNAL_VCE",
783 "INTERNAL_UNIPHY3",
771fe6b9
JG		 784};
785
cbd4623d 786static const char *hpd_names[6] = {
eed45b30
AD		 787 "HPD1",
788 "HPD2",
789 "HPD3",
790 "HPD4",
791 "HPD5",
792 "HPD6",
793};
794
771fe6b9
JG		 795static void radeon_print_display_setup(struct drm_device *dev)
796{
797 struct drm_connector *connector;
798 struct radeon_connector *radeon_connector;
799 struct drm_encoder *encoder;
800 struct radeon_encoder *radeon_encoder;
801 uint32_t devices;
802 int i = 0;
803
804 DRM_INFO("Radeon Display Connectors\n");
805 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
806 radeon_connector = to_radeon_connector(connector);
807 DRM_INFO("Connector %d:\n", i);
72082093 808 DRM_INFO(" %s\n", connector->name);
eed45b30
AD		 809 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
810 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 811 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 812 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
813 radeon_connector->ddc_bus->rec.mask_clk_reg,
814 radeon_connector->ddc_bus->rec.mask_data_reg,
815 radeon_connector->ddc_bus->rec.a_clk_reg,
816 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 817 radeon_connector->ddc_bus->rec.en_clk_reg,
818 radeon_connector->ddc_bus->rec.en_data_reg,
819 radeon_connector->ddc_bus->rec.y_clk_reg,
820 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 821 if (radeon_connector->router.ddc_valid)
26b5bc98 822 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 823 radeon_connector->router.ddc_mux_control_pin,
824 radeon_connector->router.ddc_mux_state);
825 if (radeon_connector->router.cd_valid)
826 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
827 radeon_connector->router.cd_mux_control_pin,
828 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 829 } else {
830 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
831 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
832 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
833 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
834 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
835 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
836 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
837 }
771fe6b9
JG		 838 DRM_INFO(" Encoders:\n");
839 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
840 radeon_encoder = to_radeon_encoder(encoder);
841 devices = radeon_encoder->devices & radeon_connector->devices;
842 if (devices) {
843 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
844 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
845 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
846 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
847 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
848 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
849 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
850 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
851 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
852 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
853 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
854 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
855 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
856 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
857 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
858 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 859 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
860 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 861 if (devices & ATOM_DEVICE_TV1_SUPPORT)
862 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
863 if (devices & ATOM_DEVICE_CV_SUPPORT)
864 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
865 }
866 }
867 i++;
868 }
869}
870
4ce001ab 871static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 872{
873 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 874 bool ret = false;
875
876 if (rdev->bios) {
877 if (rdev->is_atom_bios) {
a084e6ee
AD		 878 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
879 if (ret == false)
771fe6b9 880 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 881 } else {
771fe6b9 882 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 883 if (ret == false)
884 ret = radeon_get_legacy_connector_info_from_table(dev);
885 }
771fe6b9
JG		 886 } else {
887 if (!ASIC_IS_AVIVO(rdev))
888 ret = radeon_get_legacy_connector_info_from_table(dev);
889 }
890 if (ret) {
1f3b6a45 891 radeon_setup_encoder_clones(dev);
771fe6b9 892 radeon_print_display_setup(dev);
771fe6b9
JG		 893 }
894
895 return ret;
896}
897
f523f74e 898/* avivo */
f523f74e 899
32167016
CK		 900/**
901 * avivo_reduce_ratio - fractional number reduction
902 *
903 * @nom: nominator
904 * @den: denominator
905 * @nom_min: minimum value for nominator
906 * @den_min: minimum value for denominator
907 *
908 * Find the greatest common divisor and apply it on both nominator and
909 * denominator, but make nominator and denominator are at least as large
910 * as their minimum values.
911 */
912static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
913 unsigned nom_min, unsigned den_min)
f523f74e 914{
32167016
CK		 915 unsigned tmp;
916
917 /* reduce the numbers to a simpler ratio */
918 tmp = gcd(*nom, *den);
919 *nom /= tmp;
920 *den /= tmp;
921
922 /* make sure nominator is large enough */
3cf8bb1a 923 if (*nom < nom_min) {
3b333c55 924 tmp = DIV_ROUND_UP(nom_min, *nom);
32167016
CK		 925 *nom *= tmp;
926 *den *= tmp;
f523f74e
AD		 927 }
928
32167016
CK		 929 /* make sure the denominator is large enough */
930 if (*den < den_min) {
3b333c55 931 tmp = DIV_ROUND_UP(den_min, *den);
32167016
CK		 932 *nom *= tmp;
933 *den *= tmp;
f523f74e 934 }
f523f74e
AD		 935}
936
c2fb3094
CK		 937/**
938 * avivo_get_fb_ref_div - feedback and ref divider calculation
939 *
940 * @nom: nominator
941 * @den: denominator
942 * @post_div: post divider
943 * @fb_div_max: feedback divider maximum
944 * @ref_div_max: reference divider maximum
945 * @fb_div: resulting feedback divider
946 * @ref_div: resulting reference divider
947 *
948 * Calculate feedback and reference divider for a given post divider. Makes
949 * sure we stay within the limits.
950 */
951static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
952 unsigned fb_div_max, unsigned ref_div_max,
953 unsigned *fb_div, unsigned *ref_div)
954{
955 /* limit reference * post divider to a maximum */
4b21ce1b 956 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
c2fb3094
CK		 957
958 /* get matching reference and feedback divider */
959 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
960 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
961
962 /* limit fb divider to its maximum */
3cf8bb1a 963 if (*fb_div > fb_div_max) {
c2fb3094
CK		 964 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
965 *fb_div = fb_div_max;
966 }
967}
968
32167016
CK		 969/**
970 * radeon_compute_pll_avivo - compute PLL paramaters
971 *
972 * @pll: information about the PLL
973 * @dot_clock_p: resulting pixel clock
974 * fb_div_p: resulting feedback divider
975 * frac_fb_div_p: fractional part of the feedback divider
976 * ref_div_p: resulting reference divider
977 * post_div_p: resulting reference divider
978 *
979 * Try to calculate the PLL parameters to generate the given frequency:
980 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
981 */
f523f74e
AD		 982void radeon_compute_pll_avivo(struct radeon_pll *pll,
983 u32 freq,
984 u32 *dot_clock_p,
985 u32 *fb_div_p,
986 u32 *frac_fb_div_p,
987 u32 *ref_div_p,
988 u32 *post_div_p)
989{
c2fb3094
CK		 990 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
991 freq : freq / 10;
992
32167016
CK		 993 unsigned fb_div_min, fb_div_max, fb_div;
994 unsigned post_div_min, post_div_max, post_div;
995 unsigned ref_div_min, ref_div_max, ref_div;
996 unsigned post_div_best, diff_best;
f8a2645e 997 unsigned nom, den;
f523f74e 998
32167016
CK		 999 /* determine allowed feedback divider range */
1000 fb_div_min = pll->min_feedback_div;
1001 fb_div_max = pll->max_feedback_div;
f523f74e
AD		 1002
1003 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
32167016
CK		 1004 fb_div_min *= 10;
1005 fb_div_max *= 10;
1006 }
1007
1008 /* determine allowed ref divider range */
1009 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1010 ref_div_min = pll->reference_div;
1011 else
1012 ref_div_min = pll->min_ref_div;
24315814
CK		 1013
1014 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1015 pll->flags & RADEON_PLL_USE_REF_DIV)
1016 ref_div_max = pll->reference_div;
72edd83c
CK		 1017 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1018 /* fix for problems on RS880 */
1019 ref_div_max = min(pll->max_ref_div, 7u);
24315814
CK		 1020 else
1021 ref_div_max = pll->max_ref_div;
32167016
CK		 1022
1023 /* determine allowed post divider range */
1024 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1025 post_div_min = pll->post_div;
1026 post_div_max = pll->post_div;
1027 } else {
32167016
CK		 1028 unsigned vco_min, vco_max;
1029
1030 if (pll->flags & RADEON_PLL_IS_LCD) {
1031 vco_min = pll->lcd_pll_out_min;
1032 vco_max = pll->lcd_pll_out_max;
1033 } else {
1034 vco_min = pll->pll_out_min;
1035 vco_max = pll->pll_out_max;
f523f74e 1036 }
32167016 1037
c2fb3094
CK		 1038 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1039 vco_min *= 10;
1040 vco_max *= 10;
1041 }
1042
32167016
CK		 1043 post_div_min = vco_min / target_clock;
1044 if ((target_clock * post_div_min) < vco_min)
1045 ++post_div_min;
1046 if (post_div_min < pll->min_post_div)
1047 post_div_min = pll->min_post_div;
1048
1049 post_div_max = vco_max / target_clock;
1050 if ((target_clock * post_div_max) > vco_max)
1051 --post_div_max;
1052 if (post_div_max > pll->max_post_div)
1053 post_div_max = pll->max_post_div;
1054 }
1055
1056 /* represent the searched ratio as fractional number */
c2fb3094 1057 nom = target_clock;
32167016
CK		 1058 den = pll->reference_freq;
1059
1060 /* reduce the numbers to a simpler ratio */
1061 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1062
1063 /* now search for a post divider */
1064 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1065 post_div_best = post_div_min;
1066 else
1067 post_div_best = post_div_max;
1068 diff_best = ~0;
1069
1070 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
c2fb3094
CK		 1071 unsigned diff;
1072 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1073 ref_div_max, &fb_div, &ref_div);
1074 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1075 (ref_div * post_div));
1076
32167016
CK		 1077 if (diff < diff_best || (diff == diff_best &&
1078 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1079
1080 post_div_best = post_div;
1081 diff_best = diff;
f523f74e 1082 }
32167016
CK		 1083 }
1084 post_div = post_div_best;
1085
c2fb3094
CK		 1086 /* get the feedback and reference divider for the optimal value */
1087 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1088 &fb_div, &ref_div);
32167016
CK		 1089
1090 /* reduce the numbers to a simpler ratio once more */
1091 /* this also makes sure that the reference divider is large enough */
1092 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1093
3b333c55
CK		 1094 /* avoid high jitter with small fractional dividers */
1095 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
74ad54f2 1096 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
3b333c55
CK		 1097 if (fb_div < fb_div_min) {
1098 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1099 fb_div *= tmp;
1100 ref_div *= tmp;
1101 }
1102 }
1103
32167016
CK		 1104 /* and finally save the result */
1105 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1106 *fb_div_p = fb_div / 10;
1107 *frac_fb_div_p = fb_div % 10;
f523f74e 1108 } else {
32167016
CK		 1109 *fb_div_p = fb_div;
1110 *frac_fb_div_p = 0;
f523f74e
AD		 1111 }
1112
32167016
CK		 1113 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1114 (pll->reference_freq * *frac_fb_div_p)) /
1115 (ref_div * post_div * 10);
f523f74e
AD		 1116 *ref_div_p = ref_div;
1117 *post_div_p = post_div;
32167016
CK		 1118
1119 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
c2fb3094 1120 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
32167016 1121 ref_div, post_div);
f523f74e
AD		 1122}
1123
1124/* pre-avivo */
771fe6b9
JG		 1125static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1126{
1127 uint64_t mod;
1128
1129 n += d / 2;
1130
1131 mod = do_div(n, d);
1132 return n;
1133}
1134
f523f74e
AD		 1135void radeon_compute_pll_legacy(struct radeon_pll *pll,
1136 uint64_t freq,
1137 uint32_t *dot_clock_p,
1138 uint32_t *fb_div_p,
1139 uint32_t *frac_fb_div_p,
1140 uint32_t *ref_div_p,
1141 uint32_t *post_div_p)
771fe6b9
JG		 1142{
1143 uint32_t min_ref_div = pll->min_ref_div;
1144 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 1145 uint32_t min_post_div = pll->min_post_div;
1146 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 1147 uint32_t min_fractional_feed_div = 0;
1148 uint32_t max_fractional_feed_div = 0;
1149 uint32_t best_vco = pll->best_vco;
1150 uint32_t best_post_div = 1;
1151 uint32_t best_ref_div = 1;
1152 uint32_t best_feedback_div = 1;
1153 uint32_t best_frac_feedback_div = 0;
1154 uint32_t best_freq = -1;
1155 uint32_t best_error = 0xffffffff;
1156 uint32_t best_vco_diff = 1;
1157 uint32_t post_div;
86cb2bbf 1158 u32 pll_out_min, pll_out_max;
771fe6b9 1159
d9fdaafb 1160 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 1161 freq = freq * 1000;
1162
86cb2bbf
AD		 1163 if (pll->flags & RADEON_PLL_IS_LCD) {
1164 pll_out_min = pll->lcd_pll_out_min;
1165 pll_out_max = pll->lcd_pll_out_max;
1166 } else {
1167 pll_out_min = pll->pll_out_min;
1168 pll_out_max = pll->pll_out_max;
1169 }
1170
619efb10
AD		 1171 if (pll_out_min > 64800)
1172 pll_out_min = 64800;
1173
fc10332b 1174 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 1175 min_ref_div = max_ref_div = pll->reference_div;
1176 else {
1177 while (min_ref_div < max_ref_div-1) {
1178 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1179 uint32_t pll_in = pll->reference_freq / mid;
1180 if (pll_in < pll->pll_in_min)
1181 max_ref_div = mid;
1182 else if (pll_in > pll->pll_in_max)
1183 min_ref_div = mid;
1184 else
1185 break;
1186 }
1187 }
1188
fc10332b
AD		 1189 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1190 min_post_div = max_post_div = pll->post_div;
1191
1192 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 1193 min_fractional_feed_div = pll->min_frac_feedback_div;
1194 max_fractional_feed_div = pll->max_frac_feedback_div;
1195 }
1196
bd6a60af 1197 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 1198 uint32_t ref_div;
1199
fc10332b 1200 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 1201 continue;
1202
1203 /* legacy radeons only have a few post_divs */
fc10332b 1204 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 1205 if ((post_div == 5) ||
1206 (post_div == 7) ||
1207 (post_div == 9) ||
1208 (post_div == 10) ||
1209 (post_div == 11) ||
1210 (post_div == 13) ||
1211 (post_div == 14) ||
1212 (post_div == 15))
1213 continue;
1214 }
1215
1216 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1217 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1218 uint32_t pll_in = pll->reference_freq / ref_div;
1219 uint32_t min_feed_div = pll->min_feedback_div;
1220 uint32_t max_feed_div = pll->max_feedback_div + 1;
1221
1222 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1223 continue;
1224
1225 while (min_feed_div < max_feed_div) {
1226 uint32_t vco;
1227 uint32_t min_frac_feed_div = min_fractional_feed_div;
1228 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1229 uint32_t frac_feedback_div;
1230 uint64_t tmp;
1231
1232 feedback_div = (min_feed_div + max_feed_div) / 2;
1233
1234 tmp = (uint64_t)pll->reference_freq * feedback_div;
1235 vco = radeon_div(tmp, ref_div);
1236
86cb2bbf 1237 if (vco < pll_out_min) {
771fe6b9
JG		 1238 min_feed_div = feedback_div + 1;
1239 continue;
86cb2bbf 1240 } else if (vco > pll_out_max) {
771fe6b9
JG		 1241 max_feed_div = feedback_div;
1242 continue;
1243 }
1244
1245 while (min_frac_feed_div < max_frac_feed_div) {
1246 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1247 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1248 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1249 current_freq = radeon_div(tmp, ref_div * post_div);
1250
fc10332b 1251 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 1252 if (freq < current_freq)
1253 error = 0xffffffff;
1254 else
1255 error = freq - current_freq;
d0e275a9
AD		 1256 } else
1257 error = abs(current_freq - freq);
771fe6b9
JG		 1258 vco_diff = abs(vco - best_vco);
1259
1260 if ((best_vco == 0 && error < best_error) ||
1261 (best_vco != 0 &&
167ffc44 1262 ((best_error > 100 && error < best_error - 100) ||
5480f727 1263 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1264 best_post_div = post_div;
1265 best_ref_div = ref_div;
1266 best_feedback_div = feedback_div;
1267 best_frac_feedback_div = frac_feedback_div;
1268 best_freq = current_freq;
1269 best_error = error;
1270 best_vco_diff = vco_diff;
5480f727
DA		 1271 } else if (current_freq == freq) {
1272 if (best_freq == -1) {
1273 best_post_div = post_div;
1274 best_ref_div = ref_div;
1275 best_feedback_div = feedback_div;
1276 best_frac_feedback_div = frac_feedback_div;
1277 best_freq = current_freq;
1278 best_error = error;
1279 best_vco_diff = vco_diff;
1280 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1281 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1282 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1283 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1284 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1285 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1286 best_post_div = post_div;
1287 best_ref_div = ref_div;
1288 best_feedback_div = feedback_div;
1289 best_frac_feedback_div = frac_feedback_div;
1290 best_freq = current_freq;
1291 best_error = error;
1292 best_vco_diff = vco_diff;
1293 }
771fe6b9
JG		 1294 }
1295 if (current_freq < freq)
1296 min_frac_feed_div = frac_feedback_div + 1;
1297 else
1298 max_frac_feed_div = frac_feedback_div;
1299 }
1300 if (current_freq < freq)
1301 min_feed_div = feedback_div + 1;
1302 else
1303 max_feed_div = feedback_div;
1304 }
1305 }
1306 }
1307
1308 *dot_clock_p = best_freq / 10000;
1309 *fb_div_p = best_feedback_div;
1310 *frac_fb_div_p = best_frac_feedback_div;
1311 *ref_div_p = best_ref_div;
1312 *post_div_p = best_post_div;
bbb0aef5
JP		 1313 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1314 (long long)freq,
1315 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1316 best_ref_div, best_post_div);
1317
771fe6b9
JG		 1318}
1319
1320static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1321{
1322 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1323
29d08b3e 1324 if (radeon_fb->obj) {
bc9025bd 1325 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1326 }
771fe6b9
JG		 1327 drm_framebuffer_cleanup(fb);
1328 kfree(radeon_fb);
1329}
1330
1331static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1332 struct drm_file *file_priv,
1333 unsigned int *handle)
1334{
1335 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1336
1337 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1338}
1339
1340static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1341 .destroy = radeon_user_framebuffer_destroy,
1342 .create_handle = radeon_user_framebuffer_create_handle,
1343};
1344
aaefcd42 1345int
38651674
DA		 1346radeon_framebuffer_init(struct drm_device *dev,
1347 struct radeon_framebuffer *rfb,
1eb83451 1348 const struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1349 struct drm_gem_object *obj)
771fe6b9 1350{
aaefcd42 1351 int ret;
38651674 1352 rfb->obj = obj;
c7d73f6a 1353 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1354 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1355 if (ret) {
1356 rfb->obj = NULL;
1357 return ret;
1358 }
aaefcd42 1359 return 0;
771fe6b9
JG		 1360}
1361
1362static struct drm_framebuffer *
1363radeon_user_framebuffer_create(struct drm_device *dev,
1364 struct drm_file *file_priv,
1eb83451 1365 const struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1366{
1367 struct drm_gem_object *obj;
38651674 1368 struct radeon_framebuffer *radeon_fb;
aaefcd42 1369 int ret;
771fe6b9 1370
a8ad0bd8 1371 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1372 if (obj == NULL) {
1373 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1374 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1375 return ERR_PTR(-ENOENT);
7e71c9e2 1376 }
38651674
DA		 1377
1378 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1379 if (radeon_fb == NULL) {
1380 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1381 return ERR_PTR(-ENOMEM);
f2d68cf4 1382 }
38651674 1383
aaefcd42
DA		 1384 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1385 if (ret) {
1386 kfree(radeon_fb);
1387 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1388 return ERR_PTR(ret);
aaefcd42 1389 }
38651674
DA		 1390
1391 return &radeon_fb->base;
771fe6b9
JG		 1392}
1393
eb1f8e4f
DA		 1394static void radeon_output_poll_changed(struct drm_device *dev)
1395{
1396 struct radeon_device *rdev = dev->dev_private;
1397 radeon_fb_output_poll_changed(rdev);
1398}
1399
771fe6b9
JG		 1400static const struct drm_mode_config_funcs radeon_mode_funcs = {
1401 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1402 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1403};
1404
445282db
DA		 1405static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1406{ { 0, "driver" },
1407 { 1, "bios" },
1408};
1409
1410static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1411{ { TV_STD_NTSC, "ntsc" },
1412 { TV_STD_PAL, "pal" },
1413 { TV_STD_PAL_M, "pal-m" },
1414 { TV_STD_PAL_60, "pal-60" },
1415 { TV_STD_NTSC_J, "ntsc-j" },
1416 { TV_STD_SCART_PAL, "scart-pal" },
1417 { TV_STD_PAL_CN, "pal-cn" },
1418 { TV_STD_SECAM, "secam" },
1419};
1420
5b1714d3
AD		 1421static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1422{ { UNDERSCAN_OFF, "off" },
1423 { UNDERSCAN_ON, "on" },
1424 { UNDERSCAN_AUTO, "auto" },
1425};
1426
8666c076
AD		 1427static struct drm_prop_enum_list radeon_audio_enum_list[] =
1428{ { RADEON_AUDIO_DISABLE, "off" },
1429 { RADEON_AUDIO_ENABLE, "on" },
1430 { RADEON_AUDIO_AUTO, "auto" },
1431};
1432
6214bb74
AD		 1433/* XXX support different dither options? spatial, temporal, both, etc. */
1434static struct drm_prop_enum_list radeon_dither_enum_list[] =
1435{ { RADEON_FMT_DITHER_DISABLE, "off" },
1436 { RADEON_FMT_DITHER_ENABLE, "on" },
1437};
1438
67ba31d3
AD		 1439static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1440{ { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1441 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1442 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1443 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1444};
1445
d79766fa 1446static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1447{
4a67d391 1448 int sz;
445282db
DA		 1449
1450 if (rdev->is_atom_bios) {
1451 rdev->mode_info.coherent_mode_property =
d9bc3c02 1452 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1453 if (!rdev->mode_info.coherent_mode_property)
1454 return -ENOMEM;
445282db
DA		 1455 }
1456
1457 if (!ASIC_IS_AVIVO(rdev)) {
1458 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1459 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1460 drm_property_create_enum(rdev->ddev, 0,
1461 "tmds_pll",
1462 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1463 }
1464
1465 rdev->mode_info.load_detect_property =
d9bc3c02 1466 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1467 if (!rdev->mode_info.load_detect_property)
1468 return -ENOMEM;
445282db
DA		 1469
1470 drm_mode_create_scaling_mode_property(rdev->ddev);
1471
1472 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1473 rdev->mode_info.tv_std_property =
4a67d391
SH		 1474 drm_property_create_enum(rdev->ddev, 0,
1475 "tv standard",
1476 radeon_tv_std_enum_list, sz);
445282db 1477
5b1714d3
AD		 1478 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1479 rdev->mode_info.underscan_property =
4a67d391
SH		 1480 drm_property_create_enum(rdev->ddev, 0,
1481 "underscan",
1482 radeon_underscan_enum_list, sz);
5b1714d3 1483
5bccf5e3 1484 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1485 drm_property_create_range(rdev->ddev, 0,
1486 "underscan hborder", 0, 128);
5bccf5e3
MG		 1487 if (!rdev->mode_info.underscan_hborder_property)
1488 return -ENOMEM;
5bccf5e3
MG		 1489
1490 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1491 drm_property_create_range(rdev->ddev, 0,
1492 "underscan vborder", 0, 128);
5bccf5e3
MG		 1493 if (!rdev->mode_info.underscan_vborder_property)
1494 return -ENOMEM;
5bccf5e3 1495
8666c076
AD		 1496 sz = ARRAY_SIZE(radeon_audio_enum_list);
1497 rdev->mode_info.audio_property =
1498 drm_property_create_enum(rdev->ddev, 0,
1499 "audio",
1500 radeon_audio_enum_list, sz);
1501
6214bb74
AD		 1502 sz = ARRAY_SIZE(radeon_dither_enum_list);
1503 rdev->mode_info.dither_property =
1504 drm_property_create_enum(rdev->ddev, 0,
1505 "dither",
1506 radeon_dither_enum_list, sz);
1507
67ba31d3
AD		 1508 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1509 rdev->mode_info.output_csc_property =
1510 drm_property_create_enum(rdev->ddev, 0,
1511 "output_csc",
1512 radeon_output_csc_enum_list, sz);
1513
445282db
DA		 1514 return 0;
1515}
1516
f46c0120
AD		 1517void radeon_update_display_priority(struct radeon_device *rdev)
1518{
1519 /* adjustment options for the display watermarks */
1520 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1521 /* set display priority to high for r3xx, rv515 chips
1522 * this avoids flickering due to underflow to the
1523 * display controllers during heavy acceleration.
45737447
AD		 1524 * Don't force high on rs4xx igp chips as it seems to
1525 * affect the sound card. See kernel bug 15982.
f46c0120 1526 */
45737447
AD		 1527 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1528 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1529 rdev->disp_priority = 2;
1530 else
1531 rdev->disp_priority = 0;
1532 } else
1533 rdev->disp_priority = radeon_disp_priority;
1534
1535}
1536
0783986a
AD		 1537/*
1538 * Allocate hdmi structs and determine register offsets
1539 */
1540static void radeon_afmt_init(struct radeon_device *rdev)
1541{
1542 int i;
1543
1544 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1545 rdev->mode_info.afmt[i] = NULL;
1546
b530602f
AD		 1547 if (ASIC_IS_NODCE(rdev)) {
1548 /* nothing to do */
0783986a 1549 } else if (ASIC_IS_DCE4(rdev)) {
a4d39e68
RM		 1550 static uint32_t eg_offsets[] = {
1551 EVERGREEN_CRTC0_REGISTER_OFFSET,
1552 EVERGREEN_CRTC1_REGISTER_OFFSET,
1553 EVERGREEN_CRTC2_REGISTER_OFFSET,
1554 EVERGREEN_CRTC3_REGISTER_OFFSET,
1555 EVERGREEN_CRTC4_REGISTER_OFFSET,
1556 EVERGREEN_CRTC5_REGISTER_OFFSET,
b530602f 1557 0x13830 - 0x7030,
a4d39e68
RM		 1558 };
1559 int num_afmt;
1560
b530602f
AD		 1561 /* DCE8 has 7 audio blocks tied to DIG encoders */
1562 /* DCE6 has 6 audio blocks tied to DIG encoders */
0783986a
AD		 1563 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1564 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
b530602f
AD		 1565 if (ASIC_IS_DCE8(rdev))
1566 num_afmt = 7;
1567 else if (ASIC_IS_DCE6(rdev))
1568 num_afmt = 6;
1569 else if (ASIC_IS_DCE5(rdev))
a4d39e68
RM		 1570 num_afmt = 6;
1571 else if (ASIC_IS_DCE41(rdev))
1572 num_afmt = 2;
1573 else /* DCE4 */
1574 num_afmt = 6;
1575
1576 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1577 for (i = 0; i < num_afmt; i++) {
1578 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1579 if (rdev->mode_info.afmt[i]) {
1580 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1581 rdev->mode_info.afmt[i]->id = i;
0783986a
AD		 1582 }
1583 }
1584 } else if (ASIC_IS_DCE3(rdev)) {
1585 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1586 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1587 if (rdev->mode_info.afmt[0]) {
1588 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1589 rdev->mode_info.afmt[0]->id = 0;
1590 }
1591 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1592 if (rdev->mode_info.afmt[1]) {
1593 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1594 rdev->mode_info.afmt[1]->id = 1;
1595 }
1596 } else if (ASIC_IS_DCE2(rdev)) {
1597 /* DCE2 has at least 1 routable audio block */
1598 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1599 if (rdev->mode_info.afmt[0]) {
1600 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1601 rdev->mode_info.afmt[0]->id = 0;
1602 }
1603 /* r6xx has 2 routable audio blocks */
1604 if (rdev->family >= CHIP_R600) {
1605 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1606 if (rdev->mode_info.afmt[1]) {
1607 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1608 rdev->mode_info.afmt[1]->id = 1;
1609 }
1610 }
1611 }
1612}
1613
1614static void radeon_afmt_fini(struct radeon_device *rdev)
1615{
1616 int i;
1617
1618 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1619 kfree(rdev->mode_info.afmt[i]);
1620 rdev->mode_info.afmt[i] = NULL;
1621 }
1622}
1623
771fe6b9
JG		 1624int radeon_modeset_init(struct radeon_device *rdev)
1625{
18917b60 1626 int i;
771fe6b9
JG		 1627 int ret;
1628
1629 drm_mode_config_init(rdev->ddev);
1630 rdev->mode_info.mode_config_initialized = true;
1631
e6ecefaa 1632 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1633
c63dd758
MD		 1634 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1635 rdev->ddev->mode_config.async_page_flip = true;
1636
881dd74e
AD		 1637 if (ASIC_IS_DCE5(rdev)) {
1638 rdev->ddev->mode_config.max_width = 16384;
1639 rdev->ddev->mode_config.max_height = 16384;
1640 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1641 rdev->ddev->mode_config.max_width = 8192;
1642 rdev->ddev->mode_config.max_height = 8192;
1643 } else {
1644 rdev->ddev->mode_config.max_width = 4096;
1645 rdev->ddev->mode_config.max_height = 4096;
1646 }
1647
019d96cb
DA		 1648 rdev->ddev->mode_config.preferred_depth = 24;
1649 rdev->ddev->mode_config.prefer_shadow = 1;
1650
771fe6b9
JG		 1651 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1652
445282db
DA		 1653 ret = radeon_modeset_create_props(rdev);
1654 if (ret) {
1655 return ret;
1656 }
dfee5614 1657
f376b94f
AD		 1658 /* init i2c buses */
1659 radeon_i2c_init(rdev);
1660
3c537889
AD		 1661 /* check combios for a valid hardcoded EDID - Sun servers */
1662 if (!rdev->is_atom_bios) {
1663 /* check for hardcoded EDID in BIOS */
1664 radeon_combios_check_hardcoded_edid(rdev);
1665 }
1666
dfee5614 1667 /* allocate crtcs */
18917b60 1668 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1669 radeon_crtc_init(rdev->ddev, i);
1670 }
1671
1672 /* okay we should have all the bios connectors */
1673 ret = radeon_setup_enc_conn(rdev->ddev);
1674 if (!ret) {
1675 return ret;
1676 }
ac89af1e 1677
3fa47d9e
AD		 1678 /* init dig PHYs, disp eng pll */
1679 if (rdev->is_atom_bios) {
ac89af1e 1680 radeon_atom_encoder_init(rdev);
f3f1f03e 1681 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1682 }
ac89af1e 1683
d4877cf2
AD		 1684 /* initialize hpd */
1685 radeon_hpd_init(rdev);
38651674 1686
0783986a
AD		 1687 /* setup afmt */
1688 radeon_afmt_init(rdev);
1689
e5f243bd
AD		 1690 radeon_fbdev_init(rdev);
1691 drm_kms_helper_poll_init(rdev->ddev);
eb1f8e4f 1692
51a4726b
AD		 1693 /* do pm late init */
1694 ret = radeon_pm_late_init(rdev);
6c7bccea 1695
771fe6b9
JG		 1696 return 0;
1697}
1698
1699void radeon_modeset_fini(struct radeon_device *rdev)
1700{
38651674 1701 radeon_fbdev_fini(rdev);
3c537889
AD		 1702 kfree(rdev->mode_info.bios_hardcoded_edid);
1703
477d9f0e
LW		 1704 /* free i2c buses */
1705 radeon_i2c_fini(rdev);
1706
771fe6b9 1707 if (rdev->mode_info.mode_config_initialized) {
0783986a 1708 radeon_afmt_fini(rdev);
eb1f8e4f 1709 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1710 radeon_hpd_fini(rdev);
771fe6b9
JG		 1711 drm_mode_config_cleanup(rdev->ddev);
1712 rdev->mode_info.mode_config_initialized = false;
1713 }
1714}
1715
e811f5ae 1716static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1717{
1718 /* try and guess if this is a tv or a monitor */
1719 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1720 (mode->vdisplay == 576) || /* 576p */
1721 (mode->vdisplay == 720) || /* 720p */
1722 (mode->vdisplay == 1080)) /* 1080p */
1723 return true;
1724 else
1725 return false;
1726}
1727
c93bb85b 1728bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1729 const struct drm_display_mode *mode,
c93bb85b 1730 struct drm_display_mode *adjusted_mode)
771fe6b9 1731{
c93bb85b 1732 struct drm_device *dev = crtc->dev;
5b1714d3 1733 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1734 struct drm_encoder *encoder;
1735 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1736 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1737 struct drm_connector *connector;
1738 struct radeon_connector *radeon_connector;
c93bb85b 1739 bool first = true;
d65d65b1
AD		 1740 u32 src_v = 1, dst_v = 1;
1741 u32 src_h = 1, dst_h = 1;
771fe6b9 1742
5b1714d3
AD		 1743 radeon_crtc->h_border = 0;
1744 radeon_crtc->v_border = 0;
1745
c93bb85b 1746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1747 if (encoder->crtc != crtc)
1748 continue;
d65d65b1 1749 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1750 connector = radeon_get_connector_for_encoder(encoder);
1751 radeon_connector = to_radeon_connector(connector);
1752
c93bb85b 1753 if (first) {
80297e87
AD		 1754 /* set scaling */
1755 if (radeon_encoder->rmx_type == RMX_OFF)
1756 radeon_crtc->rmx_type = RMX_OFF;
1757 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1758 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1759 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1760 else
1761 radeon_crtc->rmx_type = RMX_OFF;
1762 /* copy native mode */
c93bb85b 1763 memcpy(&radeon_crtc->native_mode,
80297e87 1764 &radeon_encoder->native_mode,
de2103e4 1765 sizeof(struct drm_display_mode));
ff32a59d
AD		 1766 src_v = crtc->mode.vdisplay;
1767 dst_v = radeon_crtc->native_mode.vdisplay;
1768 src_h = crtc->mode.hdisplay;
1769 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1770
1771 /* fix up for overscan on hdmi */
1772 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1773 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1774 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1775 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
377bd8a9 1776 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
039ed2d9 1777 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1778 if (radeon_encoder->underscan_hborder != 0)
1779 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1780 else
1781 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1782 if (radeon_encoder->underscan_vborder != 0)
1783 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1784 else
1785 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1786 radeon_crtc->rmx_type = RMX_FULL;
1787 src_v = crtc->mode.vdisplay;
1788 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1789 src_h = crtc->mode.hdisplay;
1790 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1791 }
c93bb85b
JG		 1792 first = false;
1793 } else {
1794 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1795 /* WARNING: Right now this can't happen but
1796 * in the future we need to check that scaling
d65d65b1 1797 * are consistent across different encoder
c93bb85b
JG		 1798 * (ie all encoder can work with the same
1799 * scaling).
1800 */
d65d65b1 1801 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1802 return false;
1803 }
771fe6b9
JG		 1804 }
1805 }
c93bb85b
JG		 1806 if (radeon_crtc->rmx_type != RMX_OFF) {
1807 fixed20_12 a, b;
d65d65b1
AD		 1808 a.full = dfixed_const(src_v);
1809 b.full = dfixed_const(dst_v);
68adac5e 1810 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1811 a.full = dfixed_const(src_h);
1812 b.full = dfixed_const(dst_h);
68adac5e 1813 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1814 } else {
68adac5e
BS		 1815 radeon_crtc->vsc.full = dfixed_const(1);
1816 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1817 }
c93bb85b 1818 return true;
771fe6b9 1819}
6383cf7d
MK		 1820
1821/*
d47abc58
MK		 1822 * Retrieve current video scanout position of crtc on a given gpu, and
1823 * an optional accurate timestamp of when query happened.
6383cf7d 1824 *
f5a80209 1825 * \param dev Device to query.
6383cf7d 1826 * \param crtc Crtc to query.
abca9e45 1827 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
5b5561b3
MK		 1828 * For driver internal use only also supports these flags:
1829 *
1830 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1831 * of a fudged earlier start of vblank.
1832 *
1833 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1834 * fudged earlier start of vblank in *vpos and the distance
1835 * to true start of vblank in *hpos.
1836 *
6383cf7d
MK		 1837 * \param *vpos Location where vertical scanout position should be stored.
1838 * \param *hpos Location where horizontal scanout position should go.
d47abc58
MK		 1839 * \param *stime Target location for timestamp taken immediately before
1840 * scanout position query. Can be NULL to skip timestamp.
1841 * \param *etime Target location for timestamp taken immediately after
1842 * scanout position query. Can be NULL to skip timestamp.
6383cf7d
MK		 1843 *
1844 * Returns vpos as a positive number while in active scanout area.
1845 * Returns vpos as a negative number inside vblank, counting the number
1846 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1847 * until start of active scanout / end of vblank."
1848 *
1849 * \return Flags, or'ed together as follows:
1850 *
25985edc 1851 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1852 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1853 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1854 * this flag means that returned position may be offset by a constant but
1855 * unknown small number of scanlines wrt. real scanout position.
1856 *
1857 */
88e72717
TR		 1858int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1859 unsigned int flags, int *vpos, int *hpos,
1860 ktime_t *stime, ktime_t *etime,
3bb403bf 1861 const struct drm_display_mode *mode)
6383cf7d
MK		 1862{
1863 u32 stat_crtc = 0, vbl = 0, position = 0;
1864 int vbl_start, vbl_end, vtotal, ret = 0;
1865 bool in_vbl = true;
1866
f5a80209
MK		 1867 struct radeon_device *rdev = dev->dev_private;
1868
d47abc58
MK		 1869 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1870
1871 /* Get optional system timestamp before query. */
1872 if (stime)
1873 *stime = ktime_get();
1874
6383cf7d 1875 if (ASIC_IS_DCE4(rdev)) {
88e72717 1876 if (pipe == 0) {
6383cf7d
MK		 1877 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1878 EVERGREEN_CRTC0_REGISTER_OFFSET);
1879 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1880 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1881 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1882 }
88e72717 1883 if (pipe == 1) {
6383cf7d
MK		 1884 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1885 EVERGREEN_CRTC1_REGISTER_OFFSET);
1886 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1887 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1888 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1889 }
88e72717 1890 if (pipe == 2) {
6383cf7d
MK		 1891 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1892 EVERGREEN_CRTC2_REGISTER_OFFSET);
1893 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1894 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1895 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1896 }
88e72717 1897 if (pipe == 3) {
6383cf7d
MK		 1898 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1899 EVERGREEN_CRTC3_REGISTER_OFFSET);
1900 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1901 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1902 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1903 }
88e72717 1904 if (pipe == 4) {
6383cf7d
MK		 1905 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1906 EVERGREEN_CRTC4_REGISTER_OFFSET);
1907 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1908 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1909 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1910 }
88e72717 1911 if (pipe == 5) {
6383cf7d
MK		 1912 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1913 EVERGREEN_CRTC5_REGISTER_OFFSET);
1914 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1915 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1916 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1917 }
1918 } else if (ASIC_IS_AVIVO(rdev)) {
88e72717 1919 if (pipe == 0) {
6383cf7d
MK		 1920 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1921 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1922 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1923 }
88e72717 1924 if (pipe == 1) {
6383cf7d
MK		 1925 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1926 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1927 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1928 }
1929 } else {
1930 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
88e72717 1931 if (pipe == 0) {
6383cf7d
MK		 1932 /* Assume vbl_end == 0, get vbl_start from
1933 * upper 16 bits.
1934 */
1935 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1936 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1937 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1938 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1939 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1940 if (!(stat_crtc & 1))
1941 in_vbl = false;
1942
f5a80209 1943 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d 1944 }
88e72717 1945 if (pipe == 1) {
6383cf7d
MK		 1946 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1947 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1948 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1949 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1950 if (!(stat_crtc & 1))
1951 in_vbl = false;
1952
f5a80209 1953 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1954 }
1955 }
1956
d47abc58
MK		 1957 /* Get optional system timestamp after query. */
1958 if (etime)
1959 *etime = ktime_get();
1960
1961 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1962
6383cf7d
MK		 1963 /* Decode into vertical and horizontal scanout position. */
1964 *vpos = position & 0x1fff;
1965 *hpos = (position >> 16) & 0x1fff;
1966
1967 /* Valid vblank area boundaries from gpu retrieved? */
1968 if (vbl > 0) {
1969 /* Yes: Decode. */
f5a80209 1970 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1971 vbl_start = vbl & 0x1fff;
1972 vbl_end = (vbl >> 16) & 0x1fff;
1973 }
1974 else {
1975 /* No: Fake something reasonable which gives at least ok results. */
3bb403bf 1976 vbl_start = mode->crtc_vdisplay;
6383cf7d
MK		 1977 vbl_end = 0;
1978 }
1979
5b5561b3
MK		 1980 /* Called from driver internal vblank counter query code? */
1981 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1982 /* Caller wants distance from real vbl_start in *hpos */
1983 *hpos = *vpos - vbl_start;
1984 }
1985
1986 /* Fudge vblank to start a few scanlines earlier to handle the
1987 * problem that vblank irqs fire a few scanlines before start
1988 * of vblank. Some driver internal callers need the true vblank
1989 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1990 *
1991 * The cause of the "early" vblank irq is that the irq is triggered
1992 * by the line buffer logic when the line buffer read position enters
1993 * the vblank, whereas our crtc scanout position naturally lags the
1994 * line buffer read position.
1995 */
1996 if (!(flags & USE_REAL_VBLANKSTART))
1997 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1998
6383cf7d
MK		 1999 /* Test scanout position against vblank region. */
2000 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
2001 in_vbl = false;
2002
5b5561b3
MK		 2003 /* In vblank? */
2004 if (in_vbl)
2005 ret |= DRM_SCANOUTPOS_IN_VBLANK;
2006
2007 /* Called from driver internal vblank counter query code? */
2008 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
2009 /* Caller wants distance from fudged earlier vbl_start */
2010 *vpos -= vbl_start;
2011 return ret;
2012 }
2013
6383cf7d
MK		 2014 /* Check if inside vblank area and apply corrective offsets:
2015 * vpos will then be >=0 in video scanout area, but negative
2016 * within vblank area, counting down the number of lines until
2017 * start of scanout.
2018 */
2019
2020 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2021 if (in_vbl && (*vpos >= vbl_start)) {
3bb403bf 2022 vtotal = mode->crtc_vtotal;
6383cf7d
MK		 2023 *vpos = *vpos - vtotal;
2024 }
2025
2026 /* Correct for shifted end of vbl at vbl_end. */
2027 *vpos = *vpos - vbl_end;
2028
6383cf7d
MK		 2029 return ret;
2030}
Linux kernel - Deliverables
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