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drm/radeon: fix a semaphore deadlock on pre cayman asics
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
771fe6b9
JG		 36static void avivo_crtc_load_lut(struct drm_crtc *crtc)
37{
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 int i;
42
d9fdaafb 43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
45
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
53
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
57
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
64 }
65
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
67}
68
fee298fd 69static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 70{
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
74 int i;
75
d9fdaafb 76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
78
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
86
677d0768
AD		 87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 89
677d0768 90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 91 for (i = 0; i < 256; i++) {
677d0768 92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
96 }
97}
98
fee298fd
AD		 99static void dce5_crtc_load_lut(struct drm_crtc *crtc)
100{
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
104 int i;
105
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
107
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
118
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
120
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
128
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
131
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
138 }
139
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
156
157}
158
771fe6b9
JG		 159static void legacy_crtc_load_lut(struct drm_crtc *crtc)
160{
161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
163 struct radeon_device *rdev = dev->dev_private;
164 int i;
165 uint32_t dac2_cntl;
166
167 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
168 if (radeon_crtc->crtc_id == 0)
169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
170 else
171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
172 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
173
174 WREG8(RADEON_PALETTE_INDEX, 0);
175 for (i = 0; i < 256; i++) {
176 WREG32(RADEON_PALETTE_30_DATA,
177 (radeon_crtc->lut_r[i] << 20) |
178 (radeon_crtc->lut_g[i] << 10) |
179 (radeon_crtc->lut_b[i] << 0));
180 }
181}
182
183void radeon_crtc_load_lut(struct drm_crtc *crtc)
184{
185 struct drm_device *dev = crtc->dev;
186 struct radeon_device *rdev = dev->dev_private;
187
188 if (!crtc->enabled)
189 return;
190
fee298fd
AD		 191 if (ASIC_IS_DCE5(rdev))
192 dce5_crtc_load_lut(crtc);
193 else if (ASIC_IS_DCE4(rdev))
194 dce4_crtc_load_lut(crtc);
bcc1c2a1 195 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 196 avivo_crtc_load_lut(crtc);
197 else
198 legacy_crtc_load_lut(crtc);
199}
200
b8c00ac5 201/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 202void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
203 u16 blue, int regno)
204{
205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
206
771fe6b9
JG		 207 radeon_crtc->lut_r[regno] = red >> 6;
208 radeon_crtc->lut_g[regno] = green >> 6;
209 radeon_crtc->lut_b[regno] = blue >> 6;
210}
211
b8c00ac5
DA		 212/** Gets the color ramps on behalf of fbcon */
213void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
214 u16 *blue, int regno)
215{
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217
218 *red = radeon_crtc->lut_r[regno] << 6;
219 *green = radeon_crtc->lut_g[regno] << 6;
220 *blue = radeon_crtc->lut_b[regno] << 6;
221}
222
771fe6b9 223static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 224 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 227 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 228
b8c00ac5 229 /* userspace palettes are always correct as is */
7203425a 230 for (i = start; i < end; i++) {
b8c00ac5
DA		 231 radeon_crtc->lut_r[i] = red[i] >> 6;
232 radeon_crtc->lut_g[i] = green[i] >> 6;
233 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 234 }
771fe6b9
JG		 235 radeon_crtc_load_lut(crtc);
236}
237
238static void radeon_crtc_destroy(struct drm_crtc *crtc)
239{
240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241
771fe6b9
JG		 242 drm_crtc_cleanup(crtc);
243 kfree(radeon_crtc);
244}
245
6f34be50
AD		 246/*
247 * Handle unpin events outside the interrupt handler proper.
248 */
249static void radeon_unpin_work_func(struct work_struct *__work)
250{
251 struct radeon_unpin_work *work =
252 container_of(__work, struct radeon_unpin_work, work);
253 int r;
254
255 /* unpin of the old buffer */
256 r = radeon_bo_reserve(work->old_rbo, false);
257 if (likely(r == 0)) {
258 r = radeon_bo_unpin(work->old_rbo);
259 if (unlikely(r != 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
261 }
262 radeon_bo_unreserve(work->old_rbo);
263 } else
264 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 265
266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 267 kfree(work);
268}
269
270void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
271{
272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273 struct radeon_unpin_work *work;
274 struct drm_pending_vblank_event *e;
275 struct timeval now;
276 unsigned long flags;
277 u32 update_pending;
278 int vpos, hpos;
279
280 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281 work = radeon_crtc->unpin_work;
282 if (work == NULL ||
fcc485d6 283 (work->fence && !radeon_fence_signaled(work->fence))) {
6f34be50
AD		 284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
285 return;
286 }
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc->deferred_flip_completion) {
289 /* do the flip (mmio) */
290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
291 } else {
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
295 */
296 update_pending = 0;
297 radeon_crtc->deferred_flip_completion = 0;
298 }
299
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
302 */
303 if (update_pending &&
304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
305 &vpos, &hpos)) &&
306 (vpos >=0) &&
307 (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. It will complete it
310 * in next vblank interval, so complete the flip at
311 * next vblank irq.
312 */
313 radeon_crtc->deferred_flip_completion = 1;
314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
315 return;
316 }
317
318 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
319 radeon_crtc->unpin_work = NULL;
320
321 /* wakeup userspace */
322 if (work->event) {
323 e = work->event;
b6724405 324 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
6f34be50
AD		 325 e->event.tv_sec = now.tv_sec;
326 e->event.tv_usec = now.tv_usec;
327 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
328 wake_up_interruptible(&e->base.file_priv->event_wait);
329 }
330 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
331
332 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
333 radeon_fence_unref(&work->fence);
334 radeon_post_page_flip(work->rdev, work->crtc_id);
335 schedule_work(&work->work);
336}
337
338static int radeon_crtc_page_flip(struct drm_crtc *crtc,
339 struct drm_framebuffer *fb,
340 struct drm_pending_vblank_event *event)
341{
342 struct drm_device *dev = crtc->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
345 struct radeon_framebuffer *old_radeon_fb;
346 struct radeon_framebuffer *new_radeon_fb;
347 struct drm_gem_object *obj;
348 struct radeon_bo *rbo;
6f34be50
AD		 349 struct radeon_unpin_work *work;
350 unsigned long flags;
351 u32 tiling_flags, pitch_pixels;
352 u64 base;
353 int r;
354
355 work = kzalloc(sizeof *work, GFP_KERNEL);
356 if (work == NULL)
357 return -ENOMEM;
358
6f34be50
AD		 359 work->event = event;
360 work->rdev = rdev;
361 work->crtc_id = radeon_crtc->crtc_id;
6f34be50
AD		 362 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
363 new_radeon_fb = to_radeon_framebuffer(fb);
364 /* schedule unpin of the old buffer */
365 obj = old_radeon_fb->obj;
498c555f
DA		 366 /* take a reference to the old object */
367 drm_gem_object_reference(obj);
7e4d15d9 368 rbo = gem_to_radeon_bo(obj);
6f34be50 369 work->old_rbo = rbo;
fcc485d6
MD		 370 obj = new_radeon_fb->obj;
371 rbo = gem_to_radeon_bo(obj);
372 if (rbo->tbo.sync_obj)
373 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
6f34be50
AD		 374 INIT_WORK(&work->work, radeon_unpin_work_func);
375
376 /* We borrow the event spin lock for protecting unpin_work */
377 spin_lock_irqsave(&dev->event_lock, flags);
378 if (radeon_crtc->unpin_work) {
6f34be50 379 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
498c555f
DA		 380 r = -EBUSY;
381 goto unlock_free;
6f34be50
AD		 382 }
383 radeon_crtc->unpin_work = work;
384 radeon_crtc->deferred_flip_completion = 0;
385 spin_unlock_irqrestore(&dev->event_lock, flags);
386
387 /* pin the new buffer */
6f34be50
AD		 388 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
389 work->old_rbo, rbo);
390
391 r = radeon_bo_reserve(rbo, false);
392 if (unlikely(r != 0)) {
393 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
394 goto pflip_cleanup;
395 }
396 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
397 if (unlikely(r != 0)) {
398 radeon_bo_unreserve(rbo);
399 r = -EINVAL;
400 DRM_ERROR("failed to pin new rbo buffer before flip\n");
401 goto pflip_cleanup;
402 }
403 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
404 radeon_bo_unreserve(rbo);
405
406 if (!ASIC_IS_AVIVO(rdev)) {
407 /* crtc offset is from display base addr not FB location */
408 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 409 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 410
411 if (tiling_flags & RADEON_TILING_MACRO) {
412 if (ASIC_IS_R300(rdev)) {
413 base &= ~0x7ff;
414 } else {
415 int byteshift = fb->bits_per_pixel >> 4;
416 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
417 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
418 }
419 } else {
420 int offset = crtc->y * pitch_pixels + crtc->x;
421 switch (fb->bits_per_pixel) {
422 case 8:
423 default:
424 offset *= 1;
425 break;
426 case 15:
427 case 16:
428 offset *= 2;
429 break;
430 case 24:
431 offset *= 3;
432 break;
433 case 32:
434 offset *= 4;
435 break;
436 }
437 base += offset;
438 }
439 base &= ~7;
440 }
441
442 spin_lock_irqsave(&dev->event_lock, flags);
443 work->new_crtc_base = base;
444 spin_unlock_irqrestore(&dev->event_lock, flags);
445
446 /* update crtc fb */
447 crtc->fb = fb;
448
449 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
450 if (r) {
451 DRM_ERROR("failed to get vblank before flip\n");
452 goto pflip_cleanup1;
453 }
454
6f34be50
AD		 455 /* set the proper interrupt */
456 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
6f34be50
AD		 457
458 return 0;
459
6f34be50 460pflip_cleanup1:
d0254d56 461 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
6f34be50
AD		 462 DRM_ERROR("failed to reserve new rbo in error path\n");
463 goto pflip_cleanup;
464 }
d0254d56 465 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
6f34be50 466 DRM_ERROR("failed to unpin new rbo in error path\n");
6f34be50
AD		 467 }
468 radeon_bo_unreserve(rbo);
469
470pflip_cleanup:
471 spin_lock_irqsave(&dev->event_lock, flags);
472 radeon_crtc->unpin_work = NULL;
498c555f 473unlock_free:
6f34be50 474 spin_unlock_irqrestore(&dev->event_lock, flags);
db318d7a 475 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
fcc485d6 476 radeon_fence_unref(&work->fence);
6f34be50
AD		 477 kfree(work);
478
479 return r;
480}
481
771fe6b9
JG		 482static const struct drm_crtc_funcs radeon_crtc_funcs = {
483 .cursor_set = radeon_crtc_cursor_set,
484 .cursor_move = radeon_crtc_cursor_move,
485 .gamma_set = radeon_crtc_gamma_set,
486 .set_config = drm_crtc_helper_set_config,
487 .destroy = radeon_crtc_destroy,
6f34be50 488 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 489};
490
491static void radeon_crtc_init(struct drm_device *dev, int index)
492{
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_crtc *radeon_crtc;
495 int i;
496
497 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
498 if (radeon_crtc == NULL)
499 return;
500
501 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
502
503 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
504 radeon_crtc->crtc_id = index;
c93bb85b 505 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 506
785b93ef 507#if 0
771fe6b9
JG		 508 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
509 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
510 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 511#endif
771fe6b9
JG		 512
513 for (i = 0; i < 256; i++) {
514 radeon_crtc->lut_r[i] = i << 2;
515 radeon_crtc->lut_g[i] = i << 2;
516 radeon_crtc->lut_b[i] = i << 2;
517 }
518
519 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
520 radeon_atombios_init_crtc(dev, radeon_crtc);
521 else
522 radeon_legacy_init_crtc(dev, radeon_crtc);
523}
524
bf982ebf 525static const char *encoder_names[36] = {
771fe6b9
JG		 526 "NONE",
527 "INTERNAL_LVDS",
528 "INTERNAL_TMDS1",
529 "INTERNAL_TMDS2",
530 "INTERNAL_DAC1",
531 "INTERNAL_DAC2",
532 "INTERNAL_SDVOA",
533 "INTERNAL_SDVOB",
534 "SI170B",
535 "CH7303",
536 "CH7301",
537 "INTERNAL_DVO1",
538 "EXTERNAL_SDVOA",
539 "EXTERNAL_SDVOB",
540 "TITFP513",
541 "INTERNAL_LVTM1",
542 "VT1623",
543 "HDMI_SI1930",
544 "HDMI_INTERNAL",
545 "INTERNAL_KLDSCP_TMDS1",
546 "INTERNAL_KLDSCP_DVO1",
547 "INTERNAL_KLDSCP_DAC1",
548 "INTERNAL_KLDSCP_DAC2",
549 "SI178",
550 "MVPU_FPGA",
551 "INTERNAL_DDI",
552 "VT1625",
553 "HDMI_SI1932",
554 "DP_AN9801",
555 "DP_DP501",
556 "INTERNAL_UNIPHY",
557 "INTERNAL_KLDSCP_LVTMA",
558 "INTERNAL_UNIPHY1",
559 "INTERNAL_UNIPHY2",
bf982ebf
AD		 560 "NUTMEG",
561 "TRAVIS",
771fe6b9
JG		 562};
563
196c58d2 564static const char *connector_names[15] = {
771fe6b9
JG		 565 "Unknown",
566 "VGA",
567 "DVI-I",
568 "DVI-D",
569 "DVI-A",
570 "Composite",
571 "S-video",
572 "LVDS",
573 "Component",
574 "DIN",
575 "DisplayPort",
576 "HDMI-A",
577 "HDMI-B",
196c58d2
AD		 578 "TV",
579 "eDP",
771fe6b9
JG		 580};
581
cbd4623d 582static const char *hpd_names[6] = {
eed45b30
AD		 583 "HPD1",
584 "HPD2",
585 "HPD3",
586 "HPD4",
587 "HPD5",
588 "HPD6",
589};
590
771fe6b9
JG		 591static void radeon_print_display_setup(struct drm_device *dev)
592{
593 struct drm_connector *connector;
594 struct radeon_connector *radeon_connector;
595 struct drm_encoder *encoder;
596 struct radeon_encoder *radeon_encoder;
597 uint32_t devices;
598 int i = 0;
599
600 DRM_INFO("Radeon Display Connectors\n");
601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
602 radeon_connector = to_radeon_connector(connector);
603 DRM_INFO("Connector %d:\n", i);
604 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 605 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
606 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 607 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 608 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
609 radeon_connector->ddc_bus->rec.mask_clk_reg,
610 radeon_connector->ddc_bus->rec.mask_data_reg,
611 radeon_connector->ddc_bus->rec.a_clk_reg,
612 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 613 radeon_connector->ddc_bus->rec.en_clk_reg,
614 radeon_connector->ddc_bus->rec.en_data_reg,
615 radeon_connector->ddc_bus->rec.y_clk_reg,
616 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 617 if (radeon_connector->router.ddc_valid)
26b5bc98 618 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 619 radeon_connector->router.ddc_mux_control_pin,
620 radeon_connector->router.ddc_mux_state);
621 if (radeon_connector->router.cd_valid)
622 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
623 radeon_connector->router.cd_mux_control_pin,
624 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 625 } else {
626 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
627 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
628 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
629 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
630 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
631 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
632 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
633 }
771fe6b9
JG		 634 DRM_INFO(" Encoders:\n");
635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
636 radeon_encoder = to_radeon_encoder(encoder);
637 devices = radeon_encoder->devices & radeon_connector->devices;
638 if (devices) {
639 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
640 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
641 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
642 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
644 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
646 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
648 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
650 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
652 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
654 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 655 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
656 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 657 if (devices & ATOM_DEVICE_TV1_SUPPORT)
658 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_CV_SUPPORT)
660 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 }
662 }
663 i++;
664 }
665}
666
4ce001ab 667static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 668{
669 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 670 bool ret = false;
671
672 if (rdev->bios) {
673 if (rdev->is_atom_bios) {
a084e6ee
AD		 674 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
675 if (ret == false)
771fe6b9 676 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 677 } else {
771fe6b9 678 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 679 if (ret == false)
680 ret = radeon_get_legacy_connector_info_from_table(dev);
681 }
771fe6b9
JG		 682 } else {
683 if (!ASIC_IS_AVIVO(rdev))
684 ret = radeon_get_legacy_connector_info_from_table(dev);
685 }
686 if (ret) {
1f3b6a45 687 radeon_setup_encoder_clones(dev);
771fe6b9 688 radeon_print_display_setup(dev);
771fe6b9
JG		 689 }
690
691 return ret;
692}
693
694int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
695{
3c537889
AD		 696 struct drm_device *dev = radeon_connector->base.dev;
697 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 698 int ret = 0;
699
26b5bc98 700 /* on hw with routers, select right port */
fb939dfc
AD		 701 if (radeon_connector->router.ddc_valid)
702 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 703
196c58d2 704 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
b06947b5 705 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
1d33e1fc
AD		 706 (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
707 ENCODER_OBJECT_ID_NONE)) {
746c1aa4 708 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
b06947b5 709
7a15cbd4
DA		 710 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
711 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
b06947b5
AD		 712 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
713 &dig->dp_i2c_bus->adapter);
714 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
715 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
716 &radeon_connector->ddc_bus->adapter);
717 } else {
718 if (radeon_connector->ddc_bus && !radeon_connector->edid)
719 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
720 &radeon_connector->ddc_bus->adapter);
0294cf4f 721 }
c324acd5
AD		 722
723 if (!radeon_connector->edid) {
724 if (rdev->is_atom_bios) {
725 /* some laptops provide a hardcoded edid in rom for LCDs */
726 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
727 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
728 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
729 } else
730 /* some servers provide a hardcoded edid in rom for KVMs */
731 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
732 }
0294cf4f
AD		 733 if (radeon_connector->edid) {
734 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
735 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 736 return ret;
737 }
738 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 739 return 0;
771fe6b9
JG		 740}
741
f523f74e
AD		 742/* avivo */
743static void avivo_get_fb_div(struct radeon_pll *pll,
744 u32 target_clock,
745 u32 post_div,
746 u32 ref_div,
747 u32 *fb_div,
748 u32 *frac_fb_div)
749{
750 u32 tmp = post_div * ref_div;
751
752 tmp *= target_clock;
753 *fb_div = tmp / pll->reference_freq;
754 *frac_fb_div = tmp % pll->reference_freq;
a4b40d5d
AD		 755
756 if (*fb_div > pll->max_feedback_div)
757 *fb_div = pll->max_feedback_div;
758 else if (*fb_div < pll->min_feedback_div)
759 *fb_div = pll->min_feedback_div;
f523f74e
AD		 760}
761
762static u32 avivo_get_post_div(struct radeon_pll *pll,
763 u32 target_clock)
764{
765 u32 vco, post_div, tmp;
766
767 if (pll->flags & RADEON_PLL_USE_POST_DIV)
768 return pll->post_div;
769
770 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
771 if (pll->flags & RADEON_PLL_IS_LCD)
772 vco = pll->lcd_pll_out_min;
773 else
774 vco = pll->pll_out_min;
775 } else {
776 if (pll->flags & RADEON_PLL_IS_LCD)
777 vco = pll->lcd_pll_out_max;
778 else
779 vco = pll->pll_out_max;
780 }
781
782 post_div = vco / target_clock;
783 tmp = vco % target_clock;
784
785 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
786 if (tmp)
787 post_div++;
788 } else {
789 if (!tmp)
790 post_div--;
791 }
792
a4b40d5d
AD		 793 if (post_div > pll->max_post_div)
794 post_div = pll->max_post_div;
795 else if (post_div < pll->min_post_div)
796 post_div = pll->min_post_div;
797
f523f74e
AD		 798 return post_div;
799}
800
801#define MAX_TOLERANCE 10
802
803void radeon_compute_pll_avivo(struct radeon_pll *pll,
804 u32 freq,
805 u32 *dot_clock_p,
806 u32 *fb_div_p,
807 u32 *frac_fb_div_p,
808 u32 *ref_div_p,
809 u32 *post_div_p)
810{
811 u32 target_clock = freq / 10;
812 u32 post_div = avivo_get_post_div(pll, target_clock);
813 u32 ref_div = pll->min_ref_div;
814 u32 fb_div = 0, frac_fb_div = 0, tmp;
815
816 if (pll->flags & RADEON_PLL_USE_REF_DIV)
817 ref_div = pll->reference_div;
818
819 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
820 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
821 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
822 if (frac_fb_div >= 5) {
823 frac_fb_div -= 5;
824 frac_fb_div = frac_fb_div / 10;
825 frac_fb_div++;
826 }
827 if (frac_fb_div >= 10) {
828 fb_div++;
829 frac_fb_div = 0;
830 }
831 } else {
832 while (ref_div <= pll->max_ref_div) {
833 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
834 &fb_div, &frac_fb_div);
835 if (frac_fb_div >= (pll->reference_freq / 2))
836 fb_div++;
837 frac_fb_div = 0;
838 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
839 tmp = (tmp * 10000) / target_clock;
840
841 if (tmp > (10000 + MAX_TOLERANCE))
842 ref_div++;
843 else if (tmp >= (10000 - MAX_TOLERANCE))
844 break;
845 else
846 ref_div++;
847 }
848 }
849
850 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
851 (ref_div * post_div * 10);
852 *fb_div_p = fb_div;
853 *frac_fb_div_p = frac_fb_div;
854 *ref_div_p = ref_div;
855 *post_div_p = post_div;
856 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
857 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
858}
859
860/* pre-avivo */
771fe6b9
JG		 861static inline uint32_t radeon_div(uint64_t n, uint32_t d)
862{
863 uint64_t mod;
864
865 n += d / 2;
866
867 mod = do_div(n, d);
868 return n;
869}
870
f523f74e
AD		 871void radeon_compute_pll_legacy(struct radeon_pll *pll,
872 uint64_t freq,
873 uint32_t *dot_clock_p,
874 uint32_t *fb_div_p,
875 uint32_t *frac_fb_div_p,
876 uint32_t *ref_div_p,
877 uint32_t *post_div_p)
771fe6b9
JG		 878{
879 uint32_t min_ref_div = pll->min_ref_div;
880 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 881 uint32_t min_post_div = pll->min_post_div;
882 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 883 uint32_t min_fractional_feed_div = 0;
884 uint32_t max_fractional_feed_div = 0;
885 uint32_t best_vco = pll->best_vco;
886 uint32_t best_post_div = 1;
887 uint32_t best_ref_div = 1;
888 uint32_t best_feedback_div = 1;
889 uint32_t best_frac_feedback_div = 0;
890 uint32_t best_freq = -1;
891 uint32_t best_error = 0xffffffff;
892 uint32_t best_vco_diff = 1;
893 uint32_t post_div;
86cb2bbf 894 u32 pll_out_min, pll_out_max;
771fe6b9 895
d9fdaafb 896 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 897 freq = freq * 1000;
898
86cb2bbf
AD		 899 if (pll->flags & RADEON_PLL_IS_LCD) {
900 pll_out_min = pll->lcd_pll_out_min;
901 pll_out_max = pll->lcd_pll_out_max;
902 } else {
903 pll_out_min = pll->pll_out_min;
904 pll_out_max = pll->pll_out_max;
905 }
906
619efb10
AD		 907 if (pll_out_min > 64800)
908 pll_out_min = 64800;
909
fc10332b 910 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 911 min_ref_div = max_ref_div = pll->reference_div;
912 else {
913 while (min_ref_div < max_ref_div-1) {
914 uint32_t mid = (min_ref_div + max_ref_div) / 2;
915 uint32_t pll_in = pll->reference_freq / mid;
916 if (pll_in < pll->pll_in_min)
917 max_ref_div = mid;
918 else if (pll_in > pll->pll_in_max)
919 min_ref_div = mid;
920 else
921 break;
922 }
923 }
924
fc10332b
AD		 925 if (pll->flags & RADEON_PLL_USE_POST_DIV)
926 min_post_div = max_post_div = pll->post_div;
927
928 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 929 min_fractional_feed_div = pll->min_frac_feedback_div;
930 max_fractional_feed_div = pll->max_frac_feedback_div;
931 }
932
bd6a60af 933 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 934 uint32_t ref_div;
935
fc10332b 936 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 937 continue;
938
939 /* legacy radeons only have a few post_divs */
fc10332b 940 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 941 if ((post_div == 5) ||
942 (post_div == 7) ||
943 (post_div == 9) ||
944 (post_div == 10) ||
945 (post_div == 11) ||
946 (post_div == 13) ||
947 (post_div == 14) ||
948 (post_div == 15))
949 continue;
950 }
951
952 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
953 uint32_t feedback_div, current_freq = 0, error, vco_diff;
954 uint32_t pll_in = pll->reference_freq / ref_div;
955 uint32_t min_feed_div = pll->min_feedback_div;
956 uint32_t max_feed_div = pll->max_feedback_div + 1;
957
958 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
959 continue;
960
961 while (min_feed_div < max_feed_div) {
962 uint32_t vco;
963 uint32_t min_frac_feed_div = min_fractional_feed_div;
964 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
965 uint32_t frac_feedback_div;
966 uint64_t tmp;
967
968 feedback_div = (min_feed_div + max_feed_div) / 2;
969
970 tmp = (uint64_t)pll->reference_freq * feedback_div;
971 vco = radeon_div(tmp, ref_div);
972
86cb2bbf 973 if (vco < pll_out_min) {
771fe6b9
JG		 974 min_feed_div = feedback_div + 1;
975 continue;
86cb2bbf 976 } else if (vco > pll_out_max) {
771fe6b9
JG		 977 max_feed_div = feedback_div;
978 continue;
979 }
980
981 while (min_frac_feed_div < max_frac_feed_div) {
982 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
983 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
984 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
985 current_freq = radeon_div(tmp, ref_div * post_div);
986
fc10332b 987 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 988 if (freq < current_freq)
989 error = 0xffffffff;
990 else
991 error = freq - current_freq;
d0e275a9
AD		 992 } else
993 error = abs(current_freq - freq);
771fe6b9
JG		 994 vco_diff = abs(vco - best_vco);
995
996 if ((best_vco == 0 && error < best_error) ||
997 (best_vco != 0 &&
167ffc44 998 ((best_error > 100 && error < best_error - 100) ||
5480f727 999 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1000 best_post_div = post_div;
1001 best_ref_div = ref_div;
1002 best_feedback_div = feedback_div;
1003 best_frac_feedback_div = frac_feedback_div;
1004 best_freq = current_freq;
1005 best_error = error;
1006 best_vco_diff = vco_diff;
5480f727
DA		 1007 } else if (current_freq == freq) {
1008 if (best_freq == -1) {
1009 best_post_div = post_div;
1010 best_ref_div = ref_div;
1011 best_feedback_div = feedback_div;
1012 best_frac_feedback_div = frac_feedback_div;
1013 best_freq = current_freq;
1014 best_error = error;
1015 best_vco_diff = vco_diff;
1016 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1017 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1018 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1019 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1020 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1021 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1022 best_post_div = post_div;
1023 best_ref_div = ref_div;
1024 best_feedback_div = feedback_div;
1025 best_frac_feedback_div = frac_feedback_div;
1026 best_freq = current_freq;
1027 best_error = error;
1028 best_vco_diff = vco_diff;
1029 }
771fe6b9
JG		 1030 }
1031 if (current_freq < freq)
1032 min_frac_feed_div = frac_feedback_div + 1;
1033 else
1034 max_frac_feed_div = frac_feedback_div;
1035 }
1036 if (current_freq < freq)
1037 min_feed_div = feedback_div + 1;
1038 else
1039 max_feed_div = feedback_div;
1040 }
1041 }
1042 }
1043
1044 *dot_clock_p = best_freq / 10000;
1045 *fb_div_p = best_feedback_div;
1046 *frac_fb_div_p = best_frac_feedback_div;
1047 *ref_div_p = best_ref_div;
1048 *post_div_p = best_post_div;
bbb0aef5
JP		 1049 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1050 (long long)freq,
1051 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1052 best_ref_div, best_post_div);
1053
771fe6b9
JG		 1054}
1055
1056static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1057{
1058 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1059
29d08b3e 1060 if (radeon_fb->obj) {
bc9025bd 1061 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1062 }
771fe6b9
JG		 1063 drm_framebuffer_cleanup(fb);
1064 kfree(radeon_fb);
1065}
1066
1067static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1068 struct drm_file *file_priv,
1069 unsigned int *handle)
1070{
1071 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1072
1073 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1074}
1075
1076static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1077 .destroy = radeon_user_framebuffer_destroy,
1078 .create_handle = radeon_user_framebuffer_create_handle,
1079};
1080
38651674
DA		 1081void
1082radeon_framebuffer_init(struct drm_device *dev,
1083 struct radeon_framebuffer *rfb,
308e5bcb 1084 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1085 struct drm_gem_object *obj)
771fe6b9 1086{
38651674
DA		 1087 rfb->obj = obj;
1088 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1089 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
771fe6b9
JG		 1090}
1091
1092static struct drm_framebuffer *
1093radeon_user_framebuffer_create(struct drm_device *dev,
1094 struct drm_file *file_priv,
308e5bcb 1095 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1096{
1097 struct drm_gem_object *obj;
38651674 1098 struct radeon_framebuffer *radeon_fb;
771fe6b9 1099
308e5bcb 1100 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1101 if (obj == NULL) {
1102 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1103 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1104 return ERR_PTR(-ENOENT);
7e71c9e2 1105 }
38651674
DA		 1106
1107 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
cce13ff7
CW		 1108 if (radeon_fb == NULL)
1109 return ERR_PTR(-ENOMEM);
38651674
DA		 1110
1111 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1112
1113 return &radeon_fb->base;
771fe6b9
JG		 1114}
1115
eb1f8e4f
DA		 1116static void radeon_output_poll_changed(struct drm_device *dev)
1117{
1118 struct radeon_device *rdev = dev->dev_private;
1119 radeon_fb_output_poll_changed(rdev);
1120}
1121
771fe6b9
JG		 1122static const struct drm_mode_config_funcs radeon_mode_funcs = {
1123 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1124 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1125};
1126
445282db
DA		 1127struct drm_prop_enum_list {
1128 int type;
1129 char *name;
1130};
1131
1132static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1133{ { 0, "driver" },
1134 { 1, "bios" },
1135};
1136
1137static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1138{ { TV_STD_NTSC, "ntsc" },
1139 { TV_STD_PAL, "pal" },
1140 { TV_STD_PAL_M, "pal-m" },
1141 { TV_STD_PAL_60, "pal-60" },
1142 { TV_STD_NTSC_J, "ntsc-j" },
1143 { TV_STD_SCART_PAL, "scart-pal" },
1144 { TV_STD_PAL_CN, "pal-cn" },
1145 { TV_STD_SECAM, "secam" },
1146};
1147
5b1714d3
AD		 1148static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1149{ { UNDERSCAN_OFF, "off" },
1150 { UNDERSCAN_ON, "on" },
1151 { UNDERSCAN_AUTO, "auto" },
1152};
1153
d79766fa 1154static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db
DA		 1155{
1156 int i, sz;
1157
1158 if (rdev->is_atom_bios) {
1159 rdev->mode_info.coherent_mode_property =
1160 drm_property_create(rdev->ddev,
1161 DRM_MODE_PROP_RANGE,
1162 "coherent", 2);
1163 if (!rdev->mode_info.coherent_mode_property)
1164 return -ENOMEM;
1165
1166 rdev->mode_info.coherent_mode_property->values[0] = 0;
390d0bbe 1167 rdev->mode_info.coherent_mode_property->values[1] = 1;
445282db
DA		 1168 }
1169
1170 if (!ASIC_IS_AVIVO(rdev)) {
1171 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1172 rdev->mode_info.tmds_pll_property =
1173 drm_property_create(rdev->ddev,
1174 DRM_MODE_PROP_ENUM,
1175 "tmds_pll", sz);
1176 for (i = 0; i < sz; i++) {
1177 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1178 i,
1179 radeon_tmds_pll_enum_list[i].type,
1180 radeon_tmds_pll_enum_list[i].name);
1181 }
1182 }
1183
1184 rdev->mode_info.load_detect_property =
1185 drm_property_create(rdev->ddev,
1186 DRM_MODE_PROP_RANGE,
1187 "load detection", 2);
1188 if (!rdev->mode_info.load_detect_property)
1189 return -ENOMEM;
1190 rdev->mode_info.load_detect_property->values[0] = 0;
390d0bbe 1191 rdev->mode_info.load_detect_property->values[1] = 1;
445282db
DA		 1192
1193 drm_mode_create_scaling_mode_property(rdev->ddev);
1194
1195 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1196 rdev->mode_info.tv_std_property =
1197 drm_property_create(rdev->ddev,
1198 DRM_MODE_PROP_ENUM,
1199 "tv standard", sz);
1200 for (i = 0; i < sz; i++) {
1201 drm_property_add_enum(rdev->mode_info.tv_std_property,
1202 i,
1203 radeon_tv_std_enum_list[i].type,
1204 radeon_tv_std_enum_list[i].name);
1205 }
1206
5b1714d3
AD		 1207 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1208 rdev->mode_info.underscan_property =
1209 drm_property_create(rdev->ddev,
1210 DRM_MODE_PROP_ENUM,
1211 "underscan", sz);
1212 for (i = 0; i < sz; i++) {
1213 drm_property_add_enum(rdev->mode_info.underscan_property,
1214 i,
1215 radeon_underscan_enum_list[i].type,
1216 radeon_underscan_enum_list[i].name);
1217 }
1218
5bccf5e3
MG		 1219 rdev->mode_info.underscan_hborder_property =
1220 drm_property_create(rdev->ddev,
1221 DRM_MODE_PROP_RANGE,
1222 "underscan hborder", 2);
1223 if (!rdev->mode_info.underscan_hborder_property)
1224 return -ENOMEM;
1225 rdev->mode_info.underscan_hborder_property->values[0] = 0;
1226 rdev->mode_info.underscan_hborder_property->values[1] = 128;
1227
1228 rdev->mode_info.underscan_vborder_property =
1229 drm_property_create(rdev->ddev,
1230 DRM_MODE_PROP_RANGE,
1231 "underscan vborder", 2);
1232 if (!rdev->mode_info.underscan_vborder_property)
1233 return -ENOMEM;
1234 rdev->mode_info.underscan_vborder_property->values[0] = 0;
1235 rdev->mode_info.underscan_vborder_property->values[1] = 128;
1236
445282db
DA		 1237 return 0;
1238}
1239
f46c0120
AD		 1240void radeon_update_display_priority(struct radeon_device *rdev)
1241{
1242 /* adjustment options for the display watermarks */
1243 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1244 /* set display priority to high for r3xx, rv515 chips
1245 * this avoids flickering due to underflow to the
1246 * display controllers during heavy acceleration.
45737447
AD		 1247 * Don't force high on rs4xx igp chips as it seems to
1248 * affect the sound card. See kernel bug 15982.
f46c0120 1249 */
45737447
AD		 1250 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1251 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1252 rdev->disp_priority = 2;
1253 else
1254 rdev->disp_priority = 0;
1255 } else
1256 rdev->disp_priority = radeon_disp_priority;
1257
1258}
1259
771fe6b9
JG		 1260int radeon_modeset_init(struct radeon_device *rdev)
1261{
18917b60 1262 int i;
771fe6b9
JG		 1263 int ret;
1264
1265 drm_mode_config_init(rdev->ddev);
1266 rdev->mode_info.mode_config_initialized = true;
1267
1268 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1269
881dd74e
AD		 1270 if (ASIC_IS_DCE5(rdev)) {
1271 rdev->ddev->mode_config.max_width = 16384;
1272 rdev->ddev->mode_config.max_height = 16384;
1273 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1274 rdev->ddev->mode_config.max_width = 8192;
1275 rdev->ddev->mode_config.max_height = 8192;
1276 } else {
1277 rdev->ddev->mode_config.max_width = 4096;
1278 rdev->ddev->mode_config.max_height = 4096;
1279 }
1280
1281 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1282
445282db
DA		 1283 ret = radeon_modeset_create_props(rdev);
1284 if (ret) {
1285 return ret;
1286 }
dfee5614 1287
f376b94f
AD		 1288 /* init i2c buses */
1289 radeon_i2c_init(rdev);
1290
3c537889
AD		 1291 /* check combios for a valid hardcoded EDID - Sun servers */
1292 if (!rdev->is_atom_bios) {
1293 /* check for hardcoded EDID in BIOS */
1294 radeon_combios_check_hardcoded_edid(rdev);
1295 }
1296
dfee5614 1297 /* allocate crtcs */
18917b60 1298 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1299 radeon_crtc_init(rdev->ddev, i);
1300 }
1301
1302 /* okay we should have all the bios connectors */
1303 ret = radeon_setup_enc_conn(rdev->ddev);
1304 if (!ret) {
1305 return ret;
1306 }
ac89af1e 1307
3fa47d9e
AD		 1308 /* init dig PHYs, disp eng pll */
1309 if (rdev->is_atom_bios) {
ac89af1e 1310 radeon_atom_encoder_init(rdev);
3fa47d9e
AD		 1311 radeon_atom_dcpll_init(rdev);
1312 }
ac89af1e 1313
d4877cf2
AD		 1314 /* initialize hpd */
1315 radeon_hpd_init(rdev);
38651674 1316
ce8f5370
AD		 1317 /* Initialize power management */
1318 radeon_pm_init(rdev);
1319
38651674 1320 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1321 drm_kms_helper_poll_init(rdev->ddev);
1322
771fe6b9
JG		 1323 return 0;
1324}
1325
1326void radeon_modeset_fini(struct radeon_device *rdev)
1327{
38651674 1328 radeon_fbdev_fini(rdev);
3c537889 1329 kfree(rdev->mode_info.bios_hardcoded_edid);
ce8f5370 1330 radeon_pm_fini(rdev);
3c537889 1331
771fe6b9 1332 if (rdev->mode_info.mode_config_initialized) {
eb1f8e4f 1333 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1334 radeon_hpd_fini(rdev);
771fe6b9
JG		 1335 drm_mode_config_cleanup(rdev->ddev);
1336 rdev->mode_info.mode_config_initialized = false;
1337 }
f376b94f
AD		 1338 /* free i2c buses */
1339 radeon_i2c_fini(rdev);
771fe6b9
JG		 1340}
1341
039ed2d9
AD		 1342static bool is_hdtv_mode(struct drm_display_mode *mode)
1343{
1344 /* try and guess if this is a tv or a monitor */
1345 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1346 (mode->vdisplay == 576) || /* 576p */
1347 (mode->vdisplay == 720) || /* 720p */
1348 (mode->vdisplay == 1080)) /* 1080p */
1349 return true;
1350 else
1351 return false;
1352}
1353
c93bb85b
JG		 1354bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1355 struct drm_display_mode *mode,
1356 struct drm_display_mode *adjusted_mode)
771fe6b9 1357{
c93bb85b 1358 struct drm_device *dev = crtc->dev;
5b1714d3 1359 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1360 struct drm_encoder *encoder;
1361 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1362 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1363 struct drm_connector *connector;
1364 struct radeon_connector *radeon_connector;
c93bb85b 1365 bool first = true;
d65d65b1
AD		 1366 u32 src_v = 1, dst_v = 1;
1367 u32 src_h = 1, dst_h = 1;
771fe6b9 1368
5b1714d3
AD		 1369 radeon_crtc->h_border = 0;
1370 radeon_crtc->v_border = 0;
1371
c93bb85b 1372 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1373 if (encoder->crtc != crtc)
1374 continue;
d65d65b1 1375 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1376 connector = radeon_get_connector_for_encoder(encoder);
1377 radeon_connector = to_radeon_connector(connector);
1378
c93bb85b 1379 if (first) {
80297e87
AD		 1380 /* set scaling */
1381 if (radeon_encoder->rmx_type == RMX_OFF)
1382 radeon_crtc->rmx_type = RMX_OFF;
1383 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1384 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1385 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1386 else
1387 radeon_crtc->rmx_type = RMX_OFF;
1388 /* copy native mode */
c93bb85b 1389 memcpy(&radeon_crtc->native_mode,
80297e87 1390 &radeon_encoder->native_mode,
de2103e4 1391 sizeof(struct drm_display_mode));
ff32a59d
AD		 1392 src_v = crtc->mode.vdisplay;
1393 dst_v = radeon_crtc->native_mode.vdisplay;
1394 src_h = crtc->mode.hdisplay;
1395 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1396
1397 /* fix up for overscan on hdmi */
1398 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1399 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1400 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1401 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1402 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1403 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1404 if (radeon_encoder->underscan_hborder != 0)
1405 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1406 else
1407 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1408 if (radeon_encoder->underscan_vborder != 0)
1409 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1410 else
1411 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1412 radeon_crtc->rmx_type = RMX_FULL;
1413 src_v = crtc->mode.vdisplay;
1414 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1415 src_h = crtc->mode.hdisplay;
1416 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1417 }
c93bb85b
JG		 1418 first = false;
1419 } else {
1420 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1421 /* WARNING: Right now this can't happen but
1422 * in the future we need to check that scaling
d65d65b1 1423 * are consistent across different encoder
c93bb85b
JG		 1424 * (ie all encoder can work with the same
1425 * scaling).
1426 */
d65d65b1 1427 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1428 return false;
1429 }
771fe6b9
JG		 1430 }
1431 }
c93bb85b
JG		 1432 if (radeon_crtc->rmx_type != RMX_OFF) {
1433 fixed20_12 a, b;
d65d65b1
AD		 1434 a.full = dfixed_const(src_v);
1435 b.full = dfixed_const(dst_v);
68adac5e 1436 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1437 a.full = dfixed_const(src_h);
1438 b.full = dfixed_const(dst_h);
68adac5e 1439 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1440 } else {
68adac5e
BS		 1441 radeon_crtc->vsc.full = dfixed_const(1);
1442 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1443 }
c93bb85b 1444 return true;
771fe6b9 1445}
6383cf7d
MK		 1446
1447/*
1448 * Retrieve current video scanout position of crtc on a given gpu.
1449 *
f5a80209 1450 * \param dev Device to query.
6383cf7d
MK		 1451 * \param crtc Crtc to query.
1452 * \param *vpos Location where vertical scanout position should be stored.
1453 * \param *hpos Location where horizontal scanout position should go.
1454 *
1455 * Returns vpos as a positive number while in active scanout area.
1456 * Returns vpos as a negative number inside vblank, counting the number
1457 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1458 * until start of active scanout / end of vblank."
1459 *
1460 * \return Flags, or'ed together as follows:
1461 *
25985edc 1462 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1463 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1464 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1465 * this flag means that returned position may be offset by a constant but
1466 * unknown small number of scanlines wrt. real scanout position.
1467 *
1468 */
f5a80209 1469int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
6383cf7d
MK		 1470{
1471 u32 stat_crtc = 0, vbl = 0, position = 0;
1472 int vbl_start, vbl_end, vtotal, ret = 0;
1473 bool in_vbl = true;
1474
f5a80209
MK		 1475 struct radeon_device *rdev = dev->dev_private;
1476
6383cf7d
MK		 1477 if (ASIC_IS_DCE4(rdev)) {
1478 if (crtc == 0) {
1479 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1480 EVERGREEN_CRTC0_REGISTER_OFFSET);
1481 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1482 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1483 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1484 }
1485 if (crtc == 1) {
1486 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1487 EVERGREEN_CRTC1_REGISTER_OFFSET);
1488 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1489 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1490 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1491 }
1492 if (crtc == 2) {
1493 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1494 EVERGREEN_CRTC2_REGISTER_OFFSET);
1495 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1496 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1497 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1498 }
1499 if (crtc == 3) {
1500 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1501 EVERGREEN_CRTC3_REGISTER_OFFSET);
1502 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1503 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1504 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1505 }
1506 if (crtc == 4) {
1507 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1508 EVERGREEN_CRTC4_REGISTER_OFFSET);
1509 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1510 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1511 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1512 }
1513 if (crtc == 5) {
1514 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1515 EVERGREEN_CRTC5_REGISTER_OFFSET);
1516 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1517 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1518 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1519 }
1520 } else if (ASIC_IS_AVIVO(rdev)) {
1521 if (crtc == 0) {
1522 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1523 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1524 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1525 }
1526 if (crtc == 1) {
1527 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1528 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1529 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1530 }
1531 } else {
1532 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1533 if (crtc == 0) {
1534 /* Assume vbl_end == 0, get vbl_start from
1535 * upper 16 bits.
1536 */
1537 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1538 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1539 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1540 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1541 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1542 if (!(stat_crtc & 1))
1543 in_vbl = false;
1544
f5a80209 1545 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1546 }
1547 if (crtc == 1) {
1548 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1549 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1550 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1551 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1552 if (!(stat_crtc & 1))
1553 in_vbl = false;
1554
f5a80209 1555 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1556 }
1557 }
1558
1559 /* Decode into vertical and horizontal scanout position. */
1560 *vpos = position & 0x1fff;
1561 *hpos = (position >> 16) & 0x1fff;
1562
1563 /* Valid vblank area boundaries from gpu retrieved? */
1564 if (vbl > 0) {
1565 /* Yes: Decode. */
f5a80209 1566 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1567 vbl_start = vbl & 0x1fff;
1568 vbl_end = (vbl >> 16) & 0x1fff;
1569 }
1570 else {
1571 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1572 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1573 vbl_end = 0;
1574 }
1575
1576 /* Test scanout position against vblank region. */
1577 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1578 in_vbl = false;
1579
1580 /* Check if inside vblank area and apply corrective offsets:
1581 * vpos will then be >=0 in video scanout area, but negative
1582 * within vblank area, counting down the number of lines until
1583 * start of scanout.
1584 */
1585
1586 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1587 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1588 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1589 *vpos = *vpos - vtotal;
1590 }
1591
1592 /* Correct for shifted end of vbl at vbl_end. */
1593 *vpos = *vpos - vbl_end;
1594
1595 /* In vblank? */
1596 if (in_vbl)
f5a80209 1597 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d
MK		 1598
1599 return ret;
1600}
Linux kernel - Deliverables
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