Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | #include "drm_edid.h" | |
35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); | |
37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |
39 | { | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | struct drm_device *dev = crtc->dev; | |
42 | struct radeon_device *rdev = dev->dev_private; | |
43 | int i; | |
44 | ||
d9fdaafb | 45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
771fe6b9 JG |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
61 | for (i = 0; i < 256; i++) { | |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
63 | (radeon_crtc->lut_r[i] << 20) | | |
64 | (radeon_crtc->lut_g[i] << 10) | | |
65 | (radeon_crtc->lut_b[i] << 0)); | |
66 | } | |
67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
69 | } | |
70 | ||
bcc1c2a1 AD |
71 | static void evergreen_crtc_load_lut(struct drm_crtc *crtc) |
72 | { | |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
74 | struct drm_device *dev = crtc->dev; | |
75 | struct radeon_device *rdev = dev->dev_private; | |
76 | int i; | |
77 | ||
d9fdaafb | 78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
bcc1c2a1 AD |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
80 | ||
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
84 | ||
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
88 | ||
677d0768 AD |
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
bcc1c2a1 | 91 | |
677d0768 | 92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
bcc1c2a1 | 93 | for (i = 0; i < 256; i++) { |
677d0768 | 94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
bcc1c2a1 AD |
95 | (radeon_crtc->lut_r[i] << 20) | |
96 | (radeon_crtc->lut_g[i] << 10) | | |
97 | (radeon_crtc->lut_b[i] << 0)); | |
98 | } | |
99 | } | |
100 | ||
771fe6b9 JG |
101 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
102 | { | |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
104 | struct drm_device *dev = crtc->dev; | |
105 | struct radeon_device *rdev = dev->dev_private; | |
106 | int i; | |
107 | uint32_t dac2_cntl; | |
108 | ||
109 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
110 | if (radeon_crtc->crtc_id == 0) | |
111 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
112 | else | |
113 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
114 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
115 | ||
116 | WREG8(RADEON_PALETTE_INDEX, 0); | |
117 | for (i = 0; i < 256; i++) { | |
118 | WREG32(RADEON_PALETTE_30_DATA, | |
119 | (radeon_crtc->lut_r[i] << 20) | | |
120 | (radeon_crtc->lut_g[i] << 10) | | |
121 | (radeon_crtc->lut_b[i] << 0)); | |
122 | } | |
123 | } | |
124 | ||
125 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
126 | { | |
127 | struct drm_device *dev = crtc->dev; | |
128 | struct radeon_device *rdev = dev->dev_private; | |
129 | ||
130 | if (!crtc->enabled) | |
131 | return; | |
132 | ||
bcc1c2a1 AD |
133 | if (ASIC_IS_DCE4(rdev)) |
134 | evergreen_crtc_load_lut(crtc); | |
135 | else if (ASIC_IS_AVIVO(rdev)) | |
771fe6b9 JG |
136 | avivo_crtc_load_lut(crtc); |
137 | else | |
138 | legacy_crtc_load_lut(crtc); | |
139 | } | |
140 | ||
b8c00ac5 | 141 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
142 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
143 | u16 blue, int regno) | |
144 | { | |
145 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
146 | ||
771fe6b9 JG |
147 | radeon_crtc->lut_r[regno] = red >> 6; |
148 | radeon_crtc->lut_g[regno] = green >> 6; | |
149 | radeon_crtc->lut_b[regno] = blue >> 6; | |
150 | } | |
151 | ||
b8c00ac5 DA |
152 | /** Gets the color ramps on behalf of fbcon */ |
153 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
154 | u16 *blue, int regno) | |
155 | { | |
156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
157 | ||
158 | *red = radeon_crtc->lut_r[regno] << 6; | |
159 | *green = radeon_crtc->lut_g[regno] << 6; | |
160 | *blue = radeon_crtc->lut_b[regno] << 6; | |
161 | } | |
162 | ||
771fe6b9 JG |
163 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
164 | u16 *blue, uint32_t size) | |
165 | { | |
166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
b8c00ac5 | 167 | int i; |
771fe6b9 JG |
168 | |
169 | if (size != 256) { | |
170 | return; | |
171 | } | |
771fe6b9 | 172 | |
b8c00ac5 DA |
173 | /* userspace palettes are always correct as is */ |
174 | for (i = 0; i < 256; i++) { | |
175 | radeon_crtc->lut_r[i] = red[i] >> 6; | |
176 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
177 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 178 | } |
771fe6b9 JG |
179 | radeon_crtc_load_lut(crtc); |
180 | } | |
181 | ||
182 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
183 | { | |
184 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
185 | ||
771fe6b9 JG |
186 | drm_crtc_cleanup(crtc); |
187 | kfree(radeon_crtc); | |
188 | } | |
189 | ||
190 | static const struct drm_crtc_funcs radeon_crtc_funcs = { | |
191 | .cursor_set = radeon_crtc_cursor_set, | |
192 | .cursor_move = radeon_crtc_cursor_move, | |
193 | .gamma_set = radeon_crtc_gamma_set, | |
194 | .set_config = drm_crtc_helper_set_config, | |
195 | .destroy = radeon_crtc_destroy, | |
196 | }; | |
197 | ||
198 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
199 | { | |
200 | struct radeon_device *rdev = dev->dev_private; | |
201 | struct radeon_crtc *radeon_crtc; | |
202 | int i; | |
203 | ||
204 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
205 | if (radeon_crtc == NULL) | |
206 | return; | |
207 | ||
208 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
209 | ||
210 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
211 | radeon_crtc->crtc_id = index; | |
c93bb85b | 212 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 213 | |
785b93ef | 214 | #if 0 |
771fe6b9 JG |
215 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
216 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
217 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 218 | #endif |
771fe6b9 JG |
219 | |
220 | for (i = 0; i < 256; i++) { | |
221 | radeon_crtc->lut_r[i] = i << 2; | |
222 | radeon_crtc->lut_g[i] = i << 2; | |
223 | radeon_crtc->lut_b[i] = i << 2; | |
224 | } | |
225 | ||
226 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
227 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
228 | else | |
229 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
230 | } | |
231 | ||
232 | static const char *encoder_names[34] = { | |
233 | "NONE", | |
234 | "INTERNAL_LVDS", | |
235 | "INTERNAL_TMDS1", | |
236 | "INTERNAL_TMDS2", | |
237 | "INTERNAL_DAC1", | |
238 | "INTERNAL_DAC2", | |
239 | "INTERNAL_SDVOA", | |
240 | "INTERNAL_SDVOB", | |
241 | "SI170B", | |
242 | "CH7303", | |
243 | "CH7301", | |
244 | "INTERNAL_DVO1", | |
245 | "EXTERNAL_SDVOA", | |
246 | "EXTERNAL_SDVOB", | |
247 | "TITFP513", | |
248 | "INTERNAL_LVTM1", | |
249 | "VT1623", | |
250 | "HDMI_SI1930", | |
251 | "HDMI_INTERNAL", | |
252 | "INTERNAL_KLDSCP_TMDS1", | |
253 | "INTERNAL_KLDSCP_DVO1", | |
254 | "INTERNAL_KLDSCP_DAC1", | |
255 | "INTERNAL_KLDSCP_DAC2", | |
256 | "SI178", | |
257 | "MVPU_FPGA", | |
258 | "INTERNAL_DDI", | |
259 | "VT1625", | |
260 | "HDMI_SI1932", | |
261 | "DP_AN9801", | |
262 | "DP_DP501", | |
263 | "INTERNAL_UNIPHY", | |
264 | "INTERNAL_KLDSCP_LVTMA", | |
265 | "INTERNAL_UNIPHY1", | |
266 | "INTERNAL_UNIPHY2", | |
267 | }; | |
268 | ||
196c58d2 | 269 | static const char *connector_names[15] = { |
771fe6b9 JG |
270 | "Unknown", |
271 | "VGA", | |
272 | "DVI-I", | |
273 | "DVI-D", | |
274 | "DVI-A", | |
275 | "Composite", | |
276 | "S-video", | |
277 | "LVDS", | |
278 | "Component", | |
279 | "DIN", | |
280 | "DisplayPort", | |
281 | "HDMI-A", | |
282 | "HDMI-B", | |
196c58d2 AD |
283 | "TV", |
284 | "eDP", | |
771fe6b9 JG |
285 | }; |
286 | ||
cbd4623d | 287 | static const char *hpd_names[6] = { |
eed45b30 AD |
288 | "HPD1", |
289 | "HPD2", | |
290 | "HPD3", | |
291 | "HPD4", | |
292 | "HPD5", | |
293 | "HPD6", | |
294 | }; | |
295 | ||
771fe6b9 JG |
296 | static void radeon_print_display_setup(struct drm_device *dev) |
297 | { | |
298 | struct drm_connector *connector; | |
299 | struct radeon_connector *radeon_connector; | |
300 | struct drm_encoder *encoder; | |
301 | struct radeon_encoder *radeon_encoder; | |
302 | uint32_t devices; | |
303 | int i = 0; | |
304 | ||
305 | DRM_INFO("Radeon Display Connectors\n"); | |
306 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
307 | radeon_connector = to_radeon_connector(connector); | |
308 | DRM_INFO("Connector %d:\n", i); | |
309 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); | |
eed45b30 AD |
310 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
311 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); | |
4b9d2a21 | 312 | if (radeon_connector->ddc_bus) { |
771fe6b9 JG |
313 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
314 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
315 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
316 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
317 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
318 | radeon_connector->ddc_bus->rec.en_clk_reg, |
319 | radeon_connector->ddc_bus->rec.en_data_reg, | |
320 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
321 | radeon_connector->ddc_bus->rec.y_data_reg); | |
26b5bc98 AD |
322 | if (radeon_connector->router_bus) |
323 | DRM_INFO(" DDC Router 0x%x/0x%x\n", | |
324 | radeon_connector->router.mux_control_pin, | |
325 | radeon_connector->router.mux_state); | |
4b9d2a21 DA |
326 | } else { |
327 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
328 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
329 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
330 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
331 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
332 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
333 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
334 | } | |
771fe6b9 JG |
335 | DRM_INFO(" Encoders:\n"); |
336 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
337 | radeon_encoder = to_radeon_encoder(encoder); | |
338 | devices = radeon_encoder->devices & radeon_connector->devices; | |
339 | if (devices) { | |
340 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
341 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
342 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
343 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
344 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
345 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
346 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
347 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
348 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
349 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
350 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
351 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
352 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
353 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
354 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
355 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
356 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
357 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
358 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
359 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
360 | } | |
361 | } | |
362 | i++; | |
363 | } | |
364 | } | |
365 | ||
4ce001ab | 366 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
367 | { |
368 | struct radeon_device *rdev = dev->dev_private; | |
369 | struct drm_connector *drm_connector; | |
370 | bool ret = false; | |
371 | ||
372 | if (rdev->bios) { | |
373 | if (rdev->is_atom_bios) { | |
a084e6ee AD |
374 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
375 | if (ret == false) | |
771fe6b9 | 376 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
b9597a1c | 377 | } else { |
771fe6b9 | 378 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
b9597a1c AD |
379 | if (ret == false) |
380 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
381 | } | |
771fe6b9 JG |
382 | } else { |
383 | if (!ASIC_IS_AVIVO(rdev)) | |
384 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
385 | } | |
386 | if (ret) { | |
1f3b6a45 | 387 | radeon_setup_encoder_clones(dev); |
771fe6b9 JG |
388 | radeon_print_display_setup(dev); |
389 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) | |
390 | radeon_ddc_dump(drm_connector); | |
391 | } | |
392 | ||
393 | return ret; | |
394 | } | |
395 | ||
396 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
397 | { | |
3c537889 AD |
398 | struct drm_device *dev = radeon_connector->base.dev; |
399 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
400 | int ret = 0; |
401 | ||
26b5bc98 AD |
402 | /* on hw with routers, select right port */ |
403 | if (radeon_connector->router.valid) | |
404 | radeon_router_select_port(radeon_connector); | |
405 | ||
196c58d2 AD |
406 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
407 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
746c1aa4 | 408 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
7a15cbd4 DA |
409 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
410 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) | |
9fa05c98 | 411 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
746c1aa4 | 412 | } |
771fe6b9 JG |
413 | if (!radeon_connector->ddc_bus) |
414 | return -1; | |
4ce001ab | 415 | if (!radeon_connector->edid) { |
0294cf4f | 416 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
0294cf4f | 417 | } |
3c537889 AD |
418 | /* some servers provide a hardcoded edid in rom for KVMs */ |
419 | if (!radeon_connector->edid) | |
420 | radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); | |
0294cf4f AD |
421 | if (radeon_connector->edid) { |
422 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
423 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
771fe6b9 JG |
424 | return ret; |
425 | } | |
426 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 427 | return 0; |
771fe6b9 JG |
428 | } |
429 | ||
430 | static int radeon_ddc_dump(struct drm_connector *connector) | |
431 | { | |
432 | struct edid *edid; | |
433 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
434 | int ret = 0; | |
435 | ||
26b5bc98 AD |
436 | /* on hw with routers, select right port */ |
437 | if (radeon_connector->router.valid) | |
438 | radeon_router_select_port(radeon_connector); | |
439 | ||
771fe6b9 JG |
440 | if (!radeon_connector->ddc_bus) |
441 | return -1; | |
771fe6b9 | 442 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
771fe6b9 JG |
443 | if (edid) { |
444 | kfree(edid); | |
445 | } | |
446 | return ret; | |
447 | } | |
448 | ||
449 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) | |
450 | { | |
451 | uint64_t mod; | |
452 | ||
453 | n += d / 2; | |
454 | ||
455 | mod = do_div(n, d); | |
456 | return n; | |
457 | } | |
458 | ||
7c27f87d AD |
459 | static void radeon_compute_pll_legacy(struct radeon_pll *pll, |
460 | uint64_t freq, | |
461 | uint32_t *dot_clock_p, | |
462 | uint32_t *fb_div_p, | |
463 | uint32_t *frac_fb_div_p, | |
464 | uint32_t *ref_div_p, | |
465 | uint32_t *post_div_p) | |
771fe6b9 JG |
466 | { |
467 | uint32_t min_ref_div = pll->min_ref_div; | |
468 | uint32_t max_ref_div = pll->max_ref_div; | |
fc10332b AD |
469 | uint32_t min_post_div = pll->min_post_div; |
470 | uint32_t max_post_div = pll->max_post_div; | |
771fe6b9 JG |
471 | uint32_t min_fractional_feed_div = 0; |
472 | uint32_t max_fractional_feed_div = 0; | |
473 | uint32_t best_vco = pll->best_vco; | |
474 | uint32_t best_post_div = 1; | |
475 | uint32_t best_ref_div = 1; | |
476 | uint32_t best_feedback_div = 1; | |
477 | uint32_t best_frac_feedback_div = 0; | |
478 | uint32_t best_freq = -1; | |
479 | uint32_t best_error = 0xffffffff; | |
480 | uint32_t best_vco_diff = 1; | |
481 | uint32_t post_div; | |
86cb2bbf | 482 | u32 pll_out_min, pll_out_max; |
771fe6b9 | 483 | |
d9fdaafb | 484 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
771fe6b9 JG |
485 | freq = freq * 1000; |
486 | ||
86cb2bbf AD |
487 | if (pll->flags & RADEON_PLL_IS_LCD) { |
488 | pll_out_min = pll->lcd_pll_out_min; | |
489 | pll_out_max = pll->lcd_pll_out_max; | |
490 | } else { | |
491 | pll_out_min = pll->pll_out_min; | |
492 | pll_out_max = pll->pll_out_max; | |
493 | } | |
494 | ||
fc10332b | 495 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
771fe6b9 JG |
496 | min_ref_div = max_ref_div = pll->reference_div; |
497 | else { | |
498 | while (min_ref_div < max_ref_div-1) { | |
499 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
500 | uint32_t pll_in = pll->reference_freq / mid; | |
501 | if (pll_in < pll->pll_in_min) | |
502 | max_ref_div = mid; | |
503 | else if (pll_in > pll->pll_in_max) | |
504 | min_ref_div = mid; | |
505 | else | |
506 | break; | |
507 | } | |
508 | } | |
509 | ||
fc10332b AD |
510 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
511 | min_post_div = max_post_div = pll->post_div; | |
512 | ||
513 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
771fe6b9 JG |
514 | min_fractional_feed_div = pll->min_frac_feedback_div; |
515 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
516 | } | |
517 | ||
fc10332b | 518 | for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { |
771fe6b9 JG |
519 | uint32_t ref_div; |
520 | ||
fc10332b | 521 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
771fe6b9 JG |
522 | continue; |
523 | ||
524 | /* legacy radeons only have a few post_divs */ | |
fc10332b | 525 | if (pll->flags & RADEON_PLL_LEGACY) { |
771fe6b9 JG |
526 | if ((post_div == 5) || |
527 | (post_div == 7) || | |
528 | (post_div == 9) || | |
529 | (post_div == 10) || | |
530 | (post_div == 11) || | |
531 | (post_div == 13) || | |
532 | (post_div == 14) || | |
533 | (post_div == 15)) | |
534 | continue; | |
535 | } | |
536 | ||
537 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
538 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
539 | uint32_t pll_in = pll->reference_freq / ref_div; | |
540 | uint32_t min_feed_div = pll->min_feedback_div; | |
541 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
542 | ||
543 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
544 | continue; | |
545 | ||
546 | while (min_feed_div < max_feed_div) { | |
547 | uint32_t vco; | |
548 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
549 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
550 | uint32_t frac_feedback_div; | |
551 | uint64_t tmp; | |
552 | ||
553 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
554 | ||
555 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
556 | vco = radeon_div(tmp, ref_div); | |
557 | ||
86cb2bbf | 558 | if (vco < pll_out_min) { |
771fe6b9 JG |
559 | min_feed_div = feedback_div + 1; |
560 | continue; | |
86cb2bbf | 561 | } else if (vco > pll_out_max) { |
771fe6b9 JG |
562 | max_feed_div = feedback_div; |
563 | continue; | |
564 | } | |
565 | ||
566 | while (min_frac_feed_div < max_frac_feed_div) { | |
567 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
568 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
569 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
570 | current_freq = radeon_div(tmp, ref_div * post_div); | |
571 | ||
fc10332b | 572 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
167ffc44 DC |
573 | if (freq < current_freq) |
574 | error = 0xffffffff; | |
575 | else | |
576 | error = freq - current_freq; | |
d0e275a9 AD |
577 | } else |
578 | error = abs(current_freq - freq); | |
771fe6b9 JG |
579 | vco_diff = abs(vco - best_vco); |
580 | ||
581 | if ((best_vco == 0 && error < best_error) || | |
582 | (best_vco != 0 && | |
167ffc44 | 583 | ((best_error > 100 && error < best_error - 100) || |
771fe6b9 JG |
584 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
585 | best_post_div = post_div; | |
586 | best_ref_div = ref_div; | |
587 | best_feedback_div = feedback_div; | |
588 | best_frac_feedback_div = frac_feedback_div; | |
589 | best_freq = current_freq; | |
590 | best_error = error; | |
591 | best_vco_diff = vco_diff; | |
592 | } else if (current_freq == freq) { | |
593 | if (best_freq == -1) { | |
594 | best_post_div = post_div; | |
595 | best_ref_div = ref_div; | |
596 | best_feedback_div = feedback_div; | |
597 | best_frac_feedback_div = frac_feedback_div; | |
598 | best_freq = current_freq; | |
599 | best_error = error; | |
600 | best_vco_diff = vco_diff; | |
fc10332b AD |
601 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
602 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
603 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
604 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
605 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
606 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
771fe6b9 JG |
607 | best_post_div = post_div; |
608 | best_ref_div = ref_div; | |
609 | best_feedback_div = feedback_div; | |
610 | best_frac_feedback_div = frac_feedback_div; | |
611 | best_freq = current_freq; | |
612 | best_error = error; | |
613 | best_vco_diff = vco_diff; | |
614 | } | |
615 | } | |
616 | if (current_freq < freq) | |
617 | min_frac_feed_div = frac_feedback_div + 1; | |
618 | else | |
619 | max_frac_feed_div = frac_feedback_div; | |
620 | } | |
621 | if (current_freq < freq) | |
622 | min_feed_div = feedback_div + 1; | |
623 | else | |
624 | max_feed_div = feedback_div; | |
625 | } | |
626 | } | |
627 | } | |
628 | ||
629 | *dot_clock_p = best_freq / 10000; | |
630 | *fb_div_p = best_feedback_div; | |
631 | *frac_fb_div_p = best_frac_feedback_div; | |
632 | *ref_div_p = best_ref_div; | |
633 | *post_div_p = best_post_div; | |
634 | } | |
635 | ||
383be5d1 AD |
636 | static bool |
637 | calc_fb_div(struct radeon_pll *pll, | |
638 | uint32_t freq, | |
639 | uint32_t post_div, | |
640 | uint32_t ref_div, | |
641 | uint32_t *fb_div, | |
642 | uint32_t *fb_div_frac) | |
b27b6375 | 643 | { |
383be5d1 AD |
644 | fixed20_12 feedback_divider, a, b; |
645 | u32 vco_freq; | |
b27b6375 | 646 | |
383be5d1 AD |
647 | vco_freq = freq * post_div; |
648 | /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ | |
68adac5e BS |
649 | a.full = dfixed_const(pll->reference_freq); |
650 | feedback_divider.full = dfixed_const(vco_freq); | |
651 | feedback_divider.full = dfixed_div(feedback_divider, a); | |
652 | a.full = dfixed_const(ref_div); | |
653 | feedback_divider.full = dfixed_mul(feedback_divider, a); | |
b27b6375 | 654 | |
383be5d1 AD |
655 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
656 | /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ | |
68adac5e BS |
657 | a.full = dfixed_const(10); |
658 | feedback_divider.full = dfixed_mul(feedback_divider, a); | |
659 | feedback_divider.full += dfixed_const_half(0); | |
660 | feedback_divider.full = dfixed_floor(feedback_divider); | |
661 | feedback_divider.full = dfixed_div(feedback_divider, a); | |
383be5d1 AD |
662 | |
663 | /* *fb_div = floor(feedback_divider); */ | |
68adac5e BS |
664 | a.full = dfixed_floor(feedback_divider); |
665 | *fb_div = dfixed_trunc(a); | |
383be5d1 | 666 | /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ |
68adac5e BS |
667 | a.full = dfixed_const(10); |
668 | b.full = dfixed_mul(feedback_divider, a); | |
383be5d1 | 669 | |
68adac5e BS |
670 | feedback_divider.full = dfixed_floor(feedback_divider); |
671 | feedback_divider.full = dfixed_mul(feedback_divider, a); | |
383be5d1 | 672 | feedback_divider.full = b.full - feedback_divider.full; |
68adac5e | 673 | *fb_div_frac = dfixed_trunc(feedback_divider); |
383be5d1 AD |
674 | } else { |
675 | /* *fb_div = floor(feedback_divider + 0.5); */ | |
68adac5e BS |
676 | feedback_divider.full += dfixed_const_half(0); |
677 | feedback_divider.full = dfixed_floor(feedback_divider); | |
b27b6375 | 678 | |
68adac5e | 679 | *fb_div = dfixed_trunc(feedback_divider); |
383be5d1 AD |
680 | *fb_div_frac = 0; |
681 | } | |
b27b6375 | 682 | |
383be5d1 AD |
683 | if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div)) |
684 | return false; | |
685 | else | |
686 | return true; | |
687 | } | |
b27b6375 | 688 | |
383be5d1 AD |
689 | static bool |
690 | calc_fb_ref_div(struct radeon_pll *pll, | |
691 | uint32_t freq, | |
692 | uint32_t post_div, | |
693 | uint32_t *fb_div, | |
694 | uint32_t *fb_div_frac, | |
695 | uint32_t *ref_div) | |
696 | { | |
697 | fixed20_12 ffreq, max_error, error, pll_out, a; | |
698 | u32 vco; | |
86cb2bbf AD |
699 | u32 pll_out_min, pll_out_max; |
700 | ||
701 | if (pll->flags & RADEON_PLL_IS_LCD) { | |
702 | pll_out_min = pll->lcd_pll_out_min; | |
703 | pll_out_max = pll->lcd_pll_out_max; | |
704 | } else { | |
705 | pll_out_min = pll->pll_out_min; | |
706 | pll_out_max = pll->pll_out_max; | |
707 | } | |
b27b6375 | 708 | |
68adac5e | 709 | ffreq.full = dfixed_const(freq); |
383be5d1 | 710 | /* max_error = ffreq * 0.0025; */ |
68adac5e BS |
711 | a.full = dfixed_const(400); |
712 | max_error.full = dfixed_div(ffreq, a); | |
b27b6375 | 713 | |
383be5d1 AD |
714 | for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { |
715 | if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { | |
716 | vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); | |
717 | vco = vco / ((*ref_div) * 10); | |
b27b6375 | 718 | |
86cb2bbf | 719 | if ((vco < pll_out_min) || (vco > pll_out_max)) |
383be5d1 | 720 | continue; |
b27b6375 | 721 | |
383be5d1 | 722 | /* pll_out = vco / post_div; */ |
68adac5e BS |
723 | a.full = dfixed_const(post_div); |
724 | pll_out.full = dfixed_const(vco); | |
725 | pll_out.full = dfixed_div(pll_out, a); | |
b27b6375 | 726 | |
383be5d1 AD |
727 | if (pll_out.full >= ffreq.full) { |
728 | error.full = pll_out.full - ffreq.full; | |
729 | if (error.full <= max_error.full) | |
730 | return true; | |
731 | } | |
732 | } | |
733 | } | |
734 | return false; | |
735 | } | |
b27b6375 | 736 | |
383be5d1 AD |
737 | static void radeon_compute_pll_new(struct radeon_pll *pll, |
738 | uint64_t freq, | |
739 | uint32_t *dot_clock_p, | |
740 | uint32_t *fb_div_p, | |
741 | uint32_t *frac_fb_div_p, | |
742 | uint32_t *ref_div_p, | |
743 | uint32_t *post_div_p) | |
744 | { | |
745 | u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; | |
746 | u32 best_freq = 0, vco_frequency; | |
86cb2bbf AD |
747 | u32 pll_out_min, pll_out_max; |
748 | ||
749 | if (pll->flags & RADEON_PLL_IS_LCD) { | |
750 | pll_out_min = pll->lcd_pll_out_min; | |
751 | pll_out_max = pll->lcd_pll_out_max; | |
752 | } else { | |
753 | pll_out_min = pll->pll_out_min; | |
754 | pll_out_max = pll->pll_out_max; | |
755 | } | |
b27b6375 | 756 | |
383be5d1 AD |
757 | /* freq = freq / 10; */ |
758 | do_div(freq, 10); | |
b27b6375 | 759 | |
383be5d1 AD |
760 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
761 | post_div = pll->post_div; | |
762 | if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) | |
763 | goto done; | |
764 | ||
765 | vco_frequency = freq * post_div; | |
86cb2bbf | 766 | if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) |
383be5d1 AD |
767 | goto done; |
768 | ||
769 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { | |
770 | ref_div = pll->reference_div; | |
771 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) | |
772 | goto done; | |
773 | if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) | |
774 | goto done; | |
775 | } | |
776 | } else { | |
777 | for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { | |
778 | if (pll->flags & RADEON_PLL_LEGACY) { | |
779 | if ((post_div == 5) || | |
780 | (post_div == 7) || | |
781 | (post_div == 9) || | |
782 | (post_div == 10) || | |
783 | (post_div == 11)) | |
784 | continue; | |
785 | } | |
786 | ||
787 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) | |
788 | continue; | |
789 | ||
790 | vco_frequency = freq * post_div; | |
86cb2bbf | 791 | if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max)) |
383be5d1 AD |
792 | continue; |
793 | if (pll->flags & RADEON_PLL_USE_REF_DIV) { | |
794 | ref_div = pll->reference_div; | |
795 | if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) | |
796 | goto done; | |
797 | if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) | |
798 | break; | |
799 | } else { | |
800 | if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div)) | |
801 | break; | |
802 | } | |
b27b6375 AD |
803 | } |
804 | } | |
805 | ||
383be5d1 AD |
806 | best_freq = pll->reference_freq * 10 * fb_div; |
807 | best_freq += pll->reference_freq * fb_div_frac; | |
808 | best_freq = best_freq / (ref_div * post_div); | |
b27b6375 | 809 | |
383be5d1 AD |
810 | done: |
811 | if (best_freq == 0) | |
812 | DRM_ERROR("Couldn't find valid PLL dividers\n"); | |
b27b6375 | 813 | |
383be5d1 AD |
814 | *dot_clock_p = best_freq / 10; |
815 | *fb_div_p = fb_div; | |
816 | *frac_fb_div_p = fb_div_frac; | |
817 | *ref_div_p = ref_div; | |
818 | *post_div_p = post_div; | |
b27b6375 | 819 | |
d9fdaafb | 820 | DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
b27b6375 AD |
821 | } |
822 | ||
7c27f87d AD |
823 | void radeon_compute_pll(struct radeon_pll *pll, |
824 | uint64_t freq, | |
825 | uint32_t *dot_clock_p, | |
826 | uint32_t *fb_div_p, | |
827 | uint32_t *frac_fb_div_p, | |
828 | uint32_t *ref_div_p, | |
829 | uint32_t *post_div_p) | |
830 | { | |
831 | switch (pll->algo) { | |
383be5d1 AD |
832 | case PLL_ALGO_NEW: |
833 | radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p, | |
834 | frac_fb_div_p, ref_div_p, post_div_p); | |
7c27f87d AD |
835 | break; |
836 | case PLL_ALGO_LEGACY: | |
837 | default: | |
838 | radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p, | |
839 | frac_fb_div_p, ref_div_p, post_div_p); | |
840 | break; | |
841 | } | |
b27b6375 AD |
842 | } |
843 | ||
771fe6b9 JG |
844 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
845 | { | |
846 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
771fe6b9 | 847 | |
bc9025bd LB |
848 | if (radeon_fb->obj) |
849 | drm_gem_object_unreference_unlocked(radeon_fb->obj); | |
771fe6b9 JG |
850 | drm_framebuffer_cleanup(fb); |
851 | kfree(radeon_fb); | |
852 | } | |
853 | ||
854 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
855 | struct drm_file *file_priv, | |
856 | unsigned int *handle) | |
857 | { | |
858 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
859 | ||
860 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
861 | } | |
862 | ||
863 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
864 | .destroy = radeon_user_framebuffer_destroy, | |
865 | .create_handle = radeon_user_framebuffer_create_handle, | |
866 | }; | |
867 | ||
38651674 DA |
868 | void |
869 | radeon_framebuffer_init(struct drm_device *dev, | |
870 | struct radeon_framebuffer *rfb, | |
871 | struct drm_mode_fb_cmd *mode_cmd, | |
872 | struct drm_gem_object *obj) | |
771fe6b9 | 873 | { |
38651674 DA |
874 | rfb->obj = obj; |
875 | drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); | |
876 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); | |
771fe6b9 JG |
877 | } |
878 | ||
879 | static struct drm_framebuffer * | |
880 | radeon_user_framebuffer_create(struct drm_device *dev, | |
881 | struct drm_file *file_priv, | |
882 | struct drm_mode_fb_cmd *mode_cmd) | |
883 | { | |
884 | struct drm_gem_object *obj; | |
38651674 | 885 | struct radeon_framebuffer *radeon_fb; |
771fe6b9 JG |
886 | |
887 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); | |
7e71c9e2 JG |
888 | if (obj == NULL) { |
889 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
890 | "can't create framebuffer\n", mode_cmd->handle); | |
891 | return NULL; | |
892 | } | |
38651674 DA |
893 | |
894 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
895 | if (radeon_fb == NULL) { | |
896 | return NULL; | |
897 | } | |
898 | ||
899 | radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); | |
900 | ||
901 | return &radeon_fb->base; | |
771fe6b9 JG |
902 | } |
903 | ||
eb1f8e4f DA |
904 | static void radeon_output_poll_changed(struct drm_device *dev) |
905 | { | |
906 | struct radeon_device *rdev = dev->dev_private; | |
907 | radeon_fb_output_poll_changed(rdev); | |
908 | } | |
909 | ||
771fe6b9 JG |
910 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
911 | .fb_create = radeon_user_framebuffer_create, | |
eb1f8e4f | 912 | .output_poll_changed = radeon_output_poll_changed |
771fe6b9 JG |
913 | }; |
914 | ||
445282db DA |
915 | struct drm_prop_enum_list { |
916 | int type; | |
917 | char *name; | |
918 | }; | |
919 | ||
920 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = | |
921 | { { 0, "driver" }, | |
922 | { 1, "bios" }, | |
923 | }; | |
924 | ||
925 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
926 | { { TV_STD_NTSC, "ntsc" }, | |
927 | { TV_STD_PAL, "pal" }, | |
928 | { TV_STD_PAL_M, "pal-m" }, | |
929 | { TV_STD_PAL_60, "pal-60" }, | |
930 | { TV_STD_NTSC_J, "ntsc-j" }, | |
931 | { TV_STD_SCART_PAL, "scart-pal" }, | |
932 | { TV_STD_PAL_CN, "pal-cn" }, | |
933 | { TV_STD_SECAM, "secam" }, | |
934 | }; | |
935 | ||
5b1714d3 AD |
936 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
937 | { { UNDERSCAN_OFF, "off" }, | |
938 | { UNDERSCAN_ON, "on" }, | |
939 | { UNDERSCAN_AUTO, "auto" }, | |
940 | }; | |
941 | ||
d79766fa | 942 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
445282db DA |
943 | { |
944 | int i, sz; | |
945 | ||
946 | if (rdev->is_atom_bios) { | |
947 | rdev->mode_info.coherent_mode_property = | |
948 | drm_property_create(rdev->ddev, | |
949 | DRM_MODE_PROP_RANGE, | |
950 | "coherent", 2); | |
951 | if (!rdev->mode_info.coherent_mode_property) | |
952 | return -ENOMEM; | |
953 | ||
954 | rdev->mode_info.coherent_mode_property->values[0] = 0; | |
390d0bbe | 955 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
445282db DA |
956 | } |
957 | ||
958 | if (!ASIC_IS_AVIVO(rdev)) { | |
959 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
960 | rdev->mode_info.tmds_pll_property = | |
961 | drm_property_create(rdev->ddev, | |
962 | DRM_MODE_PROP_ENUM, | |
963 | "tmds_pll", sz); | |
964 | for (i = 0; i < sz; i++) { | |
965 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, | |
966 | i, | |
967 | radeon_tmds_pll_enum_list[i].type, | |
968 | radeon_tmds_pll_enum_list[i].name); | |
969 | } | |
970 | } | |
971 | ||
972 | rdev->mode_info.load_detect_property = | |
973 | drm_property_create(rdev->ddev, | |
974 | DRM_MODE_PROP_RANGE, | |
975 | "load detection", 2); | |
976 | if (!rdev->mode_info.load_detect_property) | |
977 | return -ENOMEM; | |
978 | rdev->mode_info.load_detect_property->values[0] = 0; | |
390d0bbe | 979 | rdev->mode_info.load_detect_property->values[1] = 1; |
445282db DA |
980 | |
981 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
982 | ||
983 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
984 | rdev->mode_info.tv_std_property = | |
985 | drm_property_create(rdev->ddev, | |
986 | DRM_MODE_PROP_ENUM, | |
987 | "tv standard", sz); | |
988 | for (i = 0; i < sz; i++) { | |
989 | drm_property_add_enum(rdev->mode_info.tv_std_property, | |
990 | i, | |
991 | radeon_tv_std_enum_list[i].type, | |
992 | radeon_tv_std_enum_list[i].name); | |
993 | } | |
994 | ||
5b1714d3 AD |
995 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
996 | rdev->mode_info.underscan_property = | |
997 | drm_property_create(rdev->ddev, | |
998 | DRM_MODE_PROP_ENUM, | |
999 | "underscan", sz); | |
1000 | for (i = 0; i < sz; i++) { | |
1001 | drm_property_add_enum(rdev->mode_info.underscan_property, | |
1002 | i, | |
1003 | radeon_underscan_enum_list[i].type, | |
1004 | radeon_underscan_enum_list[i].name); | |
1005 | } | |
1006 | ||
445282db DA |
1007 | return 0; |
1008 | } | |
1009 | ||
f46c0120 AD |
1010 | void radeon_update_display_priority(struct radeon_device *rdev) |
1011 | { | |
1012 | /* adjustment options for the display watermarks */ | |
1013 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { | |
1014 | /* set display priority to high for r3xx, rv515 chips | |
1015 | * this avoids flickering due to underflow to the | |
1016 | * display controllers during heavy acceleration. | |
45737447 AD |
1017 | * Don't force high on rs4xx igp chips as it seems to |
1018 | * affect the sound card. See kernel bug 15982. | |
f46c0120 | 1019 | */ |
45737447 AD |
1020 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1021 | !(rdev->flags & RADEON_IS_IGP)) | |
f46c0120 AD |
1022 | rdev->disp_priority = 2; |
1023 | else | |
1024 | rdev->disp_priority = 0; | |
1025 | } else | |
1026 | rdev->disp_priority = radeon_disp_priority; | |
1027 | ||
1028 | } | |
1029 | ||
771fe6b9 JG |
1030 | int radeon_modeset_init(struct radeon_device *rdev) |
1031 | { | |
18917b60 | 1032 | int i; |
771fe6b9 JG |
1033 | int ret; |
1034 | ||
1035 | drm_mode_config_init(rdev->ddev); | |
1036 | rdev->mode_info.mode_config_initialized = true; | |
1037 | ||
1038 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; | |
1039 | ||
1040 | if (ASIC_IS_AVIVO(rdev)) { | |
1041 | rdev->ddev->mode_config.max_width = 8192; | |
1042 | rdev->ddev->mode_config.max_height = 8192; | |
1043 | } else { | |
1044 | rdev->ddev->mode_config.max_width = 4096; | |
1045 | rdev->ddev->mode_config.max_height = 4096; | |
1046 | } | |
1047 | ||
1048 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; | |
1049 | ||
445282db DA |
1050 | ret = radeon_modeset_create_props(rdev); |
1051 | if (ret) { | |
1052 | return ret; | |
1053 | } | |
dfee5614 | 1054 | |
f376b94f AD |
1055 | /* init i2c buses */ |
1056 | radeon_i2c_init(rdev); | |
1057 | ||
3c537889 AD |
1058 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1059 | if (!rdev->is_atom_bios) { | |
1060 | /* check for hardcoded EDID in BIOS */ | |
1061 | radeon_combios_check_hardcoded_edid(rdev); | |
1062 | } | |
1063 | ||
dfee5614 | 1064 | /* allocate crtcs */ |
18917b60 | 1065 | for (i = 0; i < rdev->num_crtc; i++) { |
771fe6b9 JG |
1066 | radeon_crtc_init(rdev->ddev, i); |
1067 | } | |
1068 | ||
1069 | /* okay we should have all the bios connectors */ | |
1070 | ret = radeon_setup_enc_conn(rdev->ddev); | |
1071 | if (!ret) { | |
1072 | return ret; | |
1073 | } | |
d4877cf2 AD |
1074 | /* initialize hpd */ |
1075 | radeon_hpd_init(rdev); | |
38651674 | 1076 | |
ce8f5370 AD |
1077 | /* Initialize power management */ |
1078 | radeon_pm_init(rdev); | |
1079 | ||
38651674 | 1080 | radeon_fbdev_init(rdev); |
eb1f8e4f DA |
1081 | drm_kms_helper_poll_init(rdev->ddev); |
1082 | ||
771fe6b9 JG |
1083 | return 0; |
1084 | } | |
1085 | ||
1086 | void radeon_modeset_fini(struct radeon_device *rdev) | |
1087 | { | |
38651674 | 1088 | radeon_fbdev_fini(rdev); |
3c537889 | 1089 | kfree(rdev->mode_info.bios_hardcoded_edid); |
ce8f5370 | 1090 | radeon_pm_fini(rdev); |
3c537889 | 1091 | |
771fe6b9 | 1092 | if (rdev->mode_info.mode_config_initialized) { |
eb1f8e4f | 1093 | drm_kms_helper_poll_fini(rdev->ddev); |
d4877cf2 | 1094 | radeon_hpd_fini(rdev); |
771fe6b9 JG |
1095 | drm_mode_config_cleanup(rdev->ddev); |
1096 | rdev->mode_info.mode_config_initialized = false; | |
1097 | } | |
f376b94f AD |
1098 | /* free i2c buses */ |
1099 | radeon_i2c_fini(rdev); | |
771fe6b9 JG |
1100 | } |
1101 | ||
c93bb85b JG |
1102 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1103 | struct drm_display_mode *mode, | |
1104 | struct drm_display_mode *adjusted_mode) | |
771fe6b9 | 1105 | { |
c93bb85b | 1106 | struct drm_device *dev = crtc->dev; |
5b1714d3 | 1107 | struct radeon_device *rdev = dev->dev_private; |
c93bb85b JG |
1108 | struct drm_encoder *encoder; |
1109 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1110 | struct radeon_encoder *radeon_encoder; | |
5b1714d3 AD |
1111 | struct drm_connector *connector; |
1112 | struct radeon_connector *radeon_connector; | |
c93bb85b | 1113 | bool first = true; |
d65d65b1 AD |
1114 | u32 src_v = 1, dst_v = 1; |
1115 | u32 src_h = 1, dst_h = 1; | |
771fe6b9 | 1116 | |
5b1714d3 AD |
1117 | radeon_crtc->h_border = 0; |
1118 | radeon_crtc->v_border = 0; | |
1119 | ||
c93bb85b | 1120 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
c93bb85b JG |
1121 | if (encoder->crtc != crtc) |
1122 | continue; | |
d65d65b1 | 1123 | radeon_encoder = to_radeon_encoder(encoder); |
5b1714d3 AD |
1124 | connector = radeon_get_connector_for_encoder(encoder); |
1125 | radeon_connector = to_radeon_connector(connector); | |
1126 | ||
c93bb85b | 1127 | if (first) { |
80297e87 AD |
1128 | /* set scaling */ |
1129 | if (radeon_encoder->rmx_type == RMX_OFF) | |
1130 | radeon_crtc->rmx_type = RMX_OFF; | |
1131 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
1132 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
1133 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
1134 | else | |
1135 | radeon_crtc->rmx_type = RMX_OFF; | |
d65d65b1 AD |
1136 | src_v = crtc->mode.vdisplay; |
1137 | dst_v = radeon_crtc->native_mode.vdisplay; | |
1138 | src_h = crtc->mode.hdisplay; | |
1139 | dst_h = radeon_crtc->native_mode.vdisplay; | |
80297e87 | 1140 | /* copy native mode */ |
c93bb85b | 1141 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 1142 | &radeon_encoder->native_mode, |
de2103e4 | 1143 | sizeof(struct drm_display_mode)); |
5b1714d3 AD |
1144 | |
1145 | /* fix up for overscan on hdmi */ | |
1146 | if (ASIC_IS_AVIVO(rdev) && | |
1147 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || | |
1148 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && | |
1149 | drm_detect_hdmi_monitor(radeon_connector->edid)))) { | |
1150 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
1151 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
1152 | radeon_crtc->rmx_type = RMX_FULL; | |
1153 | src_v = crtc->mode.vdisplay; | |
1154 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); | |
1155 | src_h = crtc->mode.hdisplay; | |
1156 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); | |
1157 | } | |
c93bb85b JG |
1158 | first = false; |
1159 | } else { | |
1160 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
1161 | /* WARNING: Right now this can't happen but | |
1162 | * in the future we need to check that scaling | |
d65d65b1 | 1163 | * are consistent across different encoder |
c93bb85b JG |
1164 | * (ie all encoder can work with the same |
1165 | * scaling). | |
1166 | */ | |
d65d65b1 | 1167 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
c93bb85b JG |
1168 | return false; |
1169 | } | |
771fe6b9 JG |
1170 | } |
1171 | } | |
c93bb85b JG |
1172 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1173 | fixed20_12 a, b; | |
d65d65b1 AD |
1174 | a.full = dfixed_const(src_v); |
1175 | b.full = dfixed_const(dst_v); | |
68adac5e | 1176 | radeon_crtc->vsc.full = dfixed_div(a, b); |
d65d65b1 AD |
1177 | a.full = dfixed_const(src_h); |
1178 | b.full = dfixed_const(dst_h); | |
68adac5e | 1179 | radeon_crtc->hsc.full = dfixed_div(a, b); |
771fe6b9 | 1180 | } else { |
68adac5e BS |
1181 | radeon_crtc->vsc.full = dfixed_const(1); |
1182 | radeon_crtc->hsc.full = dfixed_const(1); | |
771fe6b9 | 1183 | } |
c93bb85b | 1184 | return true; |
771fe6b9 | 1185 | } |