Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include <asm/div64.h> | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | #include "drm_edid.h" | |
35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); | |
37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |
39 | { | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | struct drm_device *dev = crtc->dev; | |
42 | struct radeon_device *rdev = dev->dev_private; | |
43 | int i; | |
44 | ||
d9fdaafb | 45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
771fe6b9 JG |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); | |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); | |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); | |
59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); | |
61 | for (i = 0; i < 256; i++) { | |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, | |
63 | (radeon_crtc->lut_r[i] << 20) | | |
64 | (radeon_crtc->lut_g[i] << 10) | | |
65 | (radeon_crtc->lut_b[i] << 0)); | |
66 | } | |
67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); | |
69 | } | |
70 | ||
fee298fd | 71 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
bcc1c2a1 AD |
72 | { |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
74 | struct drm_device *dev = crtc->dev; | |
75 | struct radeon_device *rdev = dev->dev_private; | |
76 | int i; | |
77 | ||
d9fdaafb | 78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
bcc1c2a1 AD |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
80 | ||
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
84 | ||
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
88 | ||
677d0768 AD |
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
bcc1c2a1 | 91 | |
677d0768 | 92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
bcc1c2a1 | 93 | for (i = 0; i < 256; i++) { |
677d0768 | 94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
bcc1c2a1 AD |
95 | (radeon_crtc->lut_r[i] << 20) | |
96 | (radeon_crtc->lut_g[i] << 10) | | |
97 | (radeon_crtc->lut_b[i] << 0)); | |
98 | } | |
99 | } | |
100 | ||
fee298fd AD |
101 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
102 | { | |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
104 | struct drm_device *dev = crtc->dev; | |
105 | struct radeon_device *rdev = dev->dev_private; | |
106 | int i; | |
107 | ||
108 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); | |
109 | ||
110 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
111 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | | |
112 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); | |
113 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, | |
114 | NI_GRPH_PRESCALE_BYPASS); | |
115 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, | |
116 | NI_OVL_PRESCALE_BYPASS); | |
117 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, | |
118 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | | |
119 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); | |
120 | ||
121 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); | |
122 | ||
123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | |
124 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); | |
125 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); | |
126 | ||
127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); | |
128 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | |
129 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | |
130 | ||
131 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); | |
132 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); | |
133 | ||
134 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); | |
135 | for (i = 0; i < 256; i++) { | |
136 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, | |
137 | (radeon_crtc->lut_r[i] << 20) | | |
138 | (radeon_crtc->lut_g[i] << 10) | | |
139 | (radeon_crtc->lut_b[i] << 0)); | |
140 | } | |
141 | ||
142 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
143 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
144 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
145 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | | |
146 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); | |
147 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, | |
148 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | | |
149 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); | |
150 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, | |
151 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | | |
152 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); | |
153 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, | |
154 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | | |
155 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); | |
156 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ | |
157 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); | |
158 | ||
159 | } | |
160 | ||
771fe6b9 JG |
161 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
162 | { | |
163 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
164 | struct drm_device *dev = crtc->dev; | |
165 | struct radeon_device *rdev = dev->dev_private; | |
166 | int i; | |
167 | uint32_t dac2_cntl; | |
168 | ||
169 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
170 | if (radeon_crtc->crtc_id == 0) | |
171 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; | |
172 | else | |
173 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; | |
174 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
175 | ||
176 | WREG8(RADEON_PALETTE_INDEX, 0); | |
177 | for (i = 0; i < 256; i++) { | |
178 | WREG32(RADEON_PALETTE_30_DATA, | |
179 | (radeon_crtc->lut_r[i] << 20) | | |
180 | (radeon_crtc->lut_g[i] << 10) | | |
181 | (radeon_crtc->lut_b[i] << 0)); | |
182 | } | |
183 | } | |
184 | ||
185 | void radeon_crtc_load_lut(struct drm_crtc *crtc) | |
186 | { | |
187 | struct drm_device *dev = crtc->dev; | |
188 | struct radeon_device *rdev = dev->dev_private; | |
189 | ||
190 | if (!crtc->enabled) | |
191 | return; | |
192 | ||
fee298fd AD |
193 | if (ASIC_IS_DCE5(rdev)) |
194 | dce5_crtc_load_lut(crtc); | |
195 | else if (ASIC_IS_DCE4(rdev)) | |
196 | dce4_crtc_load_lut(crtc); | |
bcc1c2a1 | 197 | else if (ASIC_IS_AVIVO(rdev)) |
771fe6b9 JG |
198 | avivo_crtc_load_lut(crtc); |
199 | else | |
200 | legacy_crtc_load_lut(crtc); | |
201 | } | |
202 | ||
b8c00ac5 | 203 | /** Sets the color ramps on behalf of fbcon */ |
771fe6b9 JG |
204 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
205 | u16 blue, int regno) | |
206 | { | |
207 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
208 | ||
771fe6b9 JG |
209 | radeon_crtc->lut_r[regno] = red >> 6; |
210 | radeon_crtc->lut_g[regno] = green >> 6; | |
211 | radeon_crtc->lut_b[regno] = blue >> 6; | |
212 | } | |
213 | ||
b8c00ac5 DA |
214 | /** Gets the color ramps on behalf of fbcon */ |
215 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
216 | u16 *blue, int regno) | |
217 | { | |
218 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
219 | ||
220 | *red = radeon_crtc->lut_r[regno] << 6; | |
221 | *green = radeon_crtc->lut_g[regno] << 6; | |
222 | *blue = radeon_crtc->lut_b[regno] << 6; | |
223 | } | |
224 | ||
771fe6b9 | 225 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 226 | u16 *blue, uint32_t start, uint32_t size) |
771fe6b9 JG |
227 | { |
228 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
7203425a | 229 | int end = (start + size > 256) ? 256 : start + size, i; |
771fe6b9 | 230 | |
b8c00ac5 | 231 | /* userspace palettes are always correct as is */ |
7203425a | 232 | for (i = start; i < end; i++) { |
b8c00ac5 DA |
233 | radeon_crtc->lut_r[i] = red[i] >> 6; |
234 | radeon_crtc->lut_g[i] = green[i] >> 6; | |
235 | radeon_crtc->lut_b[i] = blue[i] >> 6; | |
771fe6b9 | 236 | } |
771fe6b9 JG |
237 | radeon_crtc_load_lut(crtc); |
238 | } | |
239 | ||
240 | static void radeon_crtc_destroy(struct drm_crtc *crtc) | |
241 | { | |
242 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
243 | ||
771fe6b9 JG |
244 | drm_crtc_cleanup(crtc); |
245 | kfree(radeon_crtc); | |
246 | } | |
247 | ||
6f34be50 AD |
248 | /* |
249 | * Handle unpin events outside the interrupt handler proper. | |
250 | */ | |
251 | static void radeon_unpin_work_func(struct work_struct *__work) | |
252 | { | |
253 | struct radeon_unpin_work *work = | |
254 | container_of(__work, struct radeon_unpin_work, work); | |
255 | int r; | |
256 | ||
257 | /* unpin of the old buffer */ | |
258 | r = radeon_bo_reserve(work->old_rbo, false); | |
259 | if (likely(r == 0)) { | |
260 | r = radeon_bo_unpin(work->old_rbo); | |
261 | if (unlikely(r != 0)) { | |
262 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
263 | } | |
264 | radeon_bo_unreserve(work->old_rbo); | |
265 | } else | |
266 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
267 | kfree(work); | |
268 | } | |
269 | ||
270 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) | |
271 | { | |
272 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
273 | struct radeon_unpin_work *work; | |
274 | struct drm_pending_vblank_event *e; | |
275 | struct timeval now; | |
276 | unsigned long flags; | |
277 | u32 update_pending; | |
278 | int vpos, hpos; | |
279 | ||
280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); | |
281 | work = radeon_crtc->unpin_work; | |
282 | if (work == NULL || | |
283 | !radeon_fence_signaled(work->fence)) { | |
284 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
285 | return; | |
286 | } | |
287 | /* New pageflip, or just completion of a previous one? */ | |
288 | if (!radeon_crtc->deferred_flip_completion) { | |
289 | /* do the flip (mmio) */ | |
290 | update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); | |
291 | } else { | |
292 | /* This is just a completion of a flip queued in crtc | |
293 | * at last invocation. Make sure we go directly to | |
294 | * completion routine. | |
295 | */ | |
296 | update_pending = 0; | |
297 | radeon_crtc->deferred_flip_completion = 0; | |
298 | } | |
299 | ||
300 | /* Has the pageflip already completed in crtc, or is it certain | |
301 | * to complete in this vblank? | |
302 | */ | |
303 | if (update_pending && | |
304 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, | |
305 | &vpos, &hpos)) && | |
306 | (vpos >=0) && | |
307 | (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) { | |
308 | /* crtc didn't flip in this target vblank interval, | |
309 | * but flip is pending in crtc. It will complete it | |
310 | * in next vblank interval, so complete the flip at | |
311 | * next vblank irq. | |
312 | */ | |
313 | radeon_crtc->deferred_flip_completion = 1; | |
314 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
315 | return; | |
316 | } | |
317 | ||
318 | /* Pageflip (will be) certainly completed in this vblank. Clean up. */ | |
319 | radeon_crtc->unpin_work = NULL; | |
320 | ||
321 | /* wakeup userspace */ | |
322 | if (work->event) { | |
323 | e = work->event; | |
b6724405 | 324 | e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); |
6f34be50 AD |
325 | e->event.tv_sec = now.tv_sec; |
326 | e->event.tv_usec = now.tv_usec; | |
327 | list_add_tail(&e->base.link, &e->base.file_priv->event_list); | |
328 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
329 | } | |
330 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); | |
331 | ||
332 | drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); | |
333 | radeon_fence_unref(&work->fence); | |
334 | radeon_post_page_flip(work->rdev, work->crtc_id); | |
335 | schedule_work(&work->work); | |
336 | } | |
337 | ||
338 | static int radeon_crtc_page_flip(struct drm_crtc *crtc, | |
339 | struct drm_framebuffer *fb, | |
340 | struct drm_pending_vblank_event *event) | |
341 | { | |
342 | struct drm_device *dev = crtc->dev; | |
343 | struct radeon_device *rdev = dev->dev_private; | |
344 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
345 | struct radeon_framebuffer *old_radeon_fb; | |
346 | struct radeon_framebuffer *new_radeon_fb; | |
347 | struct drm_gem_object *obj; | |
348 | struct radeon_bo *rbo; | |
349 | struct radeon_fence *fence; | |
350 | struct radeon_unpin_work *work; | |
351 | unsigned long flags; | |
352 | u32 tiling_flags, pitch_pixels; | |
353 | u64 base; | |
354 | int r; | |
355 | ||
356 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
357 | if (work == NULL) | |
358 | return -ENOMEM; | |
359 | ||
360 | r = radeon_fence_create(rdev, &fence); | |
361 | if (unlikely(r != 0)) { | |
362 | kfree(work); | |
363 | DRM_ERROR("flip queue: failed to create fence.\n"); | |
364 | return -ENOMEM; | |
365 | } | |
366 | work->event = event; | |
367 | work->rdev = rdev; | |
368 | work->crtc_id = radeon_crtc->crtc_id; | |
369 | work->fence = radeon_fence_ref(fence); | |
370 | old_radeon_fb = to_radeon_framebuffer(crtc->fb); | |
371 | new_radeon_fb = to_radeon_framebuffer(fb); | |
372 | /* schedule unpin of the old buffer */ | |
373 | obj = old_radeon_fb->obj; | |
374 | rbo = obj->driver_private; | |
375 | work->old_rbo = rbo; | |
376 | INIT_WORK(&work->work, radeon_unpin_work_func); | |
377 | ||
378 | /* We borrow the event spin lock for protecting unpin_work */ | |
379 | spin_lock_irqsave(&dev->event_lock, flags); | |
380 | if (radeon_crtc->unpin_work) { | |
381 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
382 | kfree(work); | |
383 | radeon_fence_unref(&fence); | |
384 | ||
385 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
386 | return -EBUSY; | |
387 | } | |
388 | radeon_crtc->unpin_work = work; | |
389 | radeon_crtc->deferred_flip_completion = 0; | |
390 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
391 | ||
392 | /* pin the new buffer */ | |
393 | obj = new_radeon_fb->obj; | |
394 | rbo = obj->driver_private; | |
395 | ||
396 | DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", | |
397 | work->old_rbo, rbo); | |
398 | ||
399 | r = radeon_bo_reserve(rbo, false); | |
400 | if (unlikely(r != 0)) { | |
401 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); | |
402 | goto pflip_cleanup; | |
403 | } | |
404 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base); | |
405 | if (unlikely(r != 0)) { | |
406 | radeon_bo_unreserve(rbo); | |
407 | r = -EINVAL; | |
408 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); | |
409 | goto pflip_cleanup; | |
410 | } | |
411 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); | |
412 | radeon_bo_unreserve(rbo); | |
413 | ||
414 | if (!ASIC_IS_AVIVO(rdev)) { | |
415 | /* crtc offset is from display base addr not FB location */ | |
416 | base -= radeon_crtc->legacy_display_base_addr; | |
417 | pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8); | |
418 | ||
419 | if (tiling_flags & RADEON_TILING_MACRO) { | |
420 | if (ASIC_IS_R300(rdev)) { | |
421 | base &= ~0x7ff; | |
422 | } else { | |
423 | int byteshift = fb->bits_per_pixel >> 4; | |
424 | int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; | |
425 | base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); | |
426 | } | |
427 | } else { | |
428 | int offset = crtc->y * pitch_pixels + crtc->x; | |
429 | switch (fb->bits_per_pixel) { | |
430 | case 8: | |
431 | default: | |
432 | offset *= 1; | |
433 | break; | |
434 | case 15: | |
435 | case 16: | |
436 | offset *= 2; | |
437 | break; | |
438 | case 24: | |
439 | offset *= 3; | |
440 | break; | |
441 | case 32: | |
442 | offset *= 4; | |
443 | break; | |
444 | } | |
445 | base += offset; | |
446 | } | |
447 | base &= ~7; | |
448 | } | |
449 | ||
450 | spin_lock_irqsave(&dev->event_lock, flags); | |
451 | work->new_crtc_base = base; | |
452 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
453 | ||
454 | /* update crtc fb */ | |
455 | crtc->fb = fb; | |
456 | ||
457 | r = drm_vblank_get(dev, radeon_crtc->crtc_id); | |
458 | if (r) { | |
459 | DRM_ERROR("failed to get vblank before flip\n"); | |
460 | goto pflip_cleanup1; | |
461 | } | |
462 | ||
463 | /* 32 ought to cover us */ | |
464 | r = radeon_ring_lock(rdev, 32); | |
465 | if (r) { | |
466 | DRM_ERROR("failed to lock the ring before flip\n"); | |
467 | goto pflip_cleanup2; | |
468 | } | |
469 | ||
470 | /* emit the fence */ | |
471 | radeon_fence_emit(rdev, fence); | |
472 | /* set the proper interrupt */ | |
473 | radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); | |
474 | /* fire the ring */ | |
475 | radeon_ring_unlock_commit(rdev); | |
476 | ||
477 | return 0; | |
478 | ||
479 | pflip_cleanup2: | |
480 | drm_vblank_put(dev, radeon_crtc->crtc_id); | |
481 | ||
482 | pflip_cleanup1: | |
483 | r = radeon_bo_reserve(rbo, false); | |
484 | if (unlikely(r != 0)) { | |
485 | DRM_ERROR("failed to reserve new rbo in error path\n"); | |
486 | goto pflip_cleanup; | |
487 | } | |
488 | r = radeon_bo_unpin(rbo); | |
489 | if (unlikely(r != 0)) { | |
490 | radeon_bo_unreserve(rbo); | |
491 | r = -EINVAL; | |
492 | DRM_ERROR("failed to unpin new rbo in error path\n"); | |
493 | goto pflip_cleanup; | |
494 | } | |
495 | radeon_bo_unreserve(rbo); | |
496 | ||
497 | pflip_cleanup: | |
498 | spin_lock_irqsave(&dev->event_lock, flags); | |
499 | radeon_crtc->unpin_work = NULL; | |
500 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
501 | radeon_fence_unref(&fence); | |
502 | kfree(work); | |
503 | ||
504 | return r; | |
505 | } | |
506 | ||
771fe6b9 JG |
507 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
508 | .cursor_set = radeon_crtc_cursor_set, | |
509 | .cursor_move = radeon_crtc_cursor_move, | |
510 | .gamma_set = radeon_crtc_gamma_set, | |
511 | .set_config = drm_crtc_helper_set_config, | |
512 | .destroy = radeon_crtc_destroy, | |
6f34be50 | 513 | .page_flip = radeon_crtc_page_flip, |
771fe6b9 JG |
514 | }; |
515 | ||
516 | static void radeon_crtc_init(struct drm_device *dev, int index) | |
517 | { | |
518 | struct radeon_device *rdev = dev->dev_private; | |
519 | struct radeon_crtc *radeon_crtc; | |
520 | int i; | |
521 | ||
522 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
523 | if (radeon_crtc == NULL) | |
524 | return; | |
525 | ||
526 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); | |
527 | ||
528 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); | |
529 | radeon_crtc->crtc_id = index; | |
c93bb85b | 530 | rdev->mode_info.crtcs[index] = radeon_crtc; |
771fe6b9 | 531 | |
785b93ef | 532 | #if 0 |
771fe6b9 JG |
533 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
534 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); | |
535 | radeon_crtc->mode_set.num_connectors = 0; | |
785b93ef | 536 | #endif |
771fe6b9 JG |
537 | |
538 | for (i = 0; i < 256; i++) { | |
539 | radeon_crtc->lut_r[i] = i << 2; | |
540 | radeon_crtc->lut_g[i] = i << 2; | |
541 | radeon_crtc->lut_b[i] = i << 2; | |
542 | } | |
543 | ||
544 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) | |
545 | radeon_atombios_init_crtc(dev, radeon_crtc); | |
546 | else | |
547 | radeon_legacy_init_crtc(dev, radeon_crtc); | |
548 | } | |
549 | ||
bf982ebf | 550 | static const char *encoder_names[36] = { |
771fe6b9 JG |
551 | "NONE", |
552 | "INTERNAL_LVDS", | |
553 | "INTERNAL_TMDS1", | |
554 | "INTERNAL_TMDS2", | |
555 | "INTERNAL_DAC1", | |
556 | "INTERNAL_DAC2", | |
557 | "INTERNAL_SDVOA", | |
558 | "INTERNAL_SDVOB", | |
559 | "SI170B", | |
560 | "CH7303", | |
561 | "CH7301", | |
562 | "INTERNAL_DVO1", | |
563 | "EXTERNAL_SDVOA", | |
564 | "EXTERNAL_SDVOB", | |
565 | "TITFP513", | |
566 | "INTERNAL_LVTM1", | |
567 | "VT1623", | |
568 | "HDMI_SI1930", | |
569 | "HDMI_INTERNAL", | |
570 | "INTERNAL_KLDSCP_TMDS1", | |
571 | "INTERNAL_KLDSCP_DVO1", | |
572 | "INTERNAL_KLDSCP_DAC1", | |
573 | "INTERNAL_KLDSCP_DAC2", | |
574 | "SI178", | |
575 | "MVPU_FPGA", | |
576 | "INTERNAL_DDI", | |
577 | "VT1625", | |
578 | "HDMI_SI1932", | |
579 | "DP_AN9801", | |
580 | "DP_DP501", | |
581 | "INTERNAL_UNIPHY", | |
582 | "INTERNAL_KLDSCP_LVTMA", | |
583 | "INTERNAL_UNIPHY1", | |
584 | "INTERNAL_UNIPHY2", | |
bf982ebf AD |
585 | "NUTMEG", |
586 | "TRAVIS", | |
771fe6b9 JG |
587 | }; |
588 | ||
196c58d2 | 589 | static const char *connector_names[15] = { |
771fe6b9 JG |
590 | "Unknown", |
591 | "VGA", | |
592 | "DVI-I", | |
593 | "DVI-D", | |
594 | "DVI-A", | |
595 | "Composite", | |
596 | "S-video", | |
597 | "LVDS", | |
598 | "Component", | |
599 | "DIN", | |
600 | "DisplayPort", | |
601 | "HDMI-A", | |
602 | "HDMI-B", | |
196c58d2 AD |
603 | "TV", |
604 | "eDP", | |
771fe6b9 JG |
605 | }; |
606 | ||
cbd4623d | 607 | static const char *hpd_names[6] = { |
eed45b30 AD |
608 | "HPD1", |
609 | "HPD2", | |
610 | "HPD3", | |
611 | "HPD4", | |
612 | "HPD5", | |
613 | "HPD6", | |
614 | }; | |
615 | ||
771fe6b9 JG |
616 | static void radeon_print_display_setup(struct drm_device *dev) |
617 | { | |
618 | struct drm_connector *connector; | |
619 | struct radeon_connector *radeon_connector; | |
620 | struct drm_encoder *encoder; | |
621 | struct radeon_encoder *radeon_encoder; | |
622 | uint32_t devices; | |
623 | int i = 0; | |
624 | ||
625 | DRM_INFO("Radeon Display Connectors\n"); | |
626 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
627 | radeon_connector = to_radeon_connector(connector); | |
628 | DRM_INFO("Connector %d:\n", i); | |
629 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); | |
eed45b30 AD |
630 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
631 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); | |
4b9d2a21 | 632 | if (radeon_connector->ddc_bus) { |
771fe6b9 JG |
633 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
634 | radeon_connector->ddc_bus->rec.mask_clk_reg, | |
635 | radeon_connector->ddc_bus->rec.mask_data_reg, | |
636 | radeon_connector->ddc_bus->rec.a_clk_reg, | |
637 | radeon_connector->ddc_bus->rec.a_data_reg, | |
9b9fe724 AD |
638 | radeon_connector->ddc_bus->rec.en_clk_reg, |
639 | radeon_connector->ddc_bus->rec.en_data_reg, | |
640 | radeon_connector->ddc_bus->rec.y_clk_reg, | |
641 | radeon_connector->ddc_bus->rec.y_data_reg); | |
fb939dfc | 642 | if (radeon_connector->router.ddc_valid) |
26b5bc98 | 643 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
fb939dfc AD |
644 | radeon_connector->router.ddc_mux_control_pin, |
645 | radeon_connector->router.ddc_mux_state); | |
646 | if (radeon_connector->router.cd_valid) | |
647 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
648 | radeon_connector->router.cd_mux_control_pin, | |
649 | radeon_connector->router.cd_mux_state); | |
4b9d2a21 DA |
650 | } else { |
651 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
652 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
653 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
654 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
655 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
656 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
657 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
658 | } | |
771fe6b9 JG |
659 | DRM_INFO(" Encoders:\n"); |
660 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
661 | radeon_encoder = to_radeon_encoder(encoder); | |
662 | devices = radeon_encoder->devices & radeon_connector->devices; | |
663 | if (devices) { | |
664 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
665 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
666 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
667 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
668 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
669 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
670 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
671 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
672 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
673 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
674 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
675 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
676 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
677 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
678 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
679 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
73758a5d AD |
680 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
681 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
771fe6b9 JG |
682 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
683 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
684 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
685 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); | |
686 | } | |
687 | } | |
688 | i++; | |
689 | } | |
690 | } | |
691 | ||
4ce001ab | 692 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
771fe6b9 JG |
693 | { |
694 | struct radeon_device *rdev = dev->dev_private; | |
695 | struct drm_connector *drm_connector; | |
696 | bool ret = false; | |
697 | ||
698 | if (rdev->bios) { | |
699 | if (rdev->is_atom_bios) { | |
a084e6ee AD |
700 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
701 | if (ret == false) | |
771fe6b9 | 702 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
b9597a1c | 703 | } else { |
771fe6b9 | 704 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
b9597a1c AD |
705 | if (ret == false) |
706 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
707 | } | |
771fe6b9 JG |
708 | } else { |
709 | if (!ASIC_IS_AVIVO(rdev)) | |
710 | ret = radeon_get_legacy_connector_info_from_table(dev); | |
711 | } | |
712 | if (ret) { | |
1f3b6a45 | 713 | radeon_setup_encoder_clones(dev); |
771fe6b9 JG |
714 | radeon_print_display_setup(dev); |
715 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) | |
716 | radeon_ddc_dump(drm_connector); | |
717 | } | |
718 | ||
719 | return ret; | |
720 | } | |
721 | ||
722 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) | |
723 | { | |
3c537889 AD |
724 | struct drm_device *dev = radeon_connector->base.dev; |
725 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
726 | int ret = 0; |
727 | ||
26b5bc98 | 728 | /* on hw with routers, select right port */ |
fb939dfc AD |
729 | if (radeon_connector->router.ddc_valid) |
730 | radeon_router_select_ddc_port(radeon_connector); | |
26b5bc98 | 731 | |
196c58d2 AD |
732 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
733 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
746c1aa4 | 734 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
7a15cbd4 DA |
735 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
736 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) | |
9fa05c98 | 737 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
746c1aa4 | 738 | } |
771fe6b9 JG |
739 | if (!radeon_connector->ddc_bus) |
740 | return -1; | |
4ce001ab | 741 | if (!radeon_connector->edid) { |
0294cf4f | 742 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
0294cf4f | 743 | } |
c324acd5 AD |
744 | |
745 | if (!radeon_connector->edid) { | |
746 | if (rdev->is_atom_bios) { | |
747 | /* some laptops provide a hardcoded edid in rom for LCDs */ | |
748 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || | |
749 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) | |
750 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
751 | } else | |
752 | /* some servers provide a hardcoded edid in rom for KVMs */ | |
753 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
754 | } | |
0294cf4f AD |
755 | if (radeon_connector->edid) { |
756 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); | |
757 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); | |
771fe6b9 JG |
758 | return ret; |
759 | } | |
760 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); | |
42dea5dd | 761 | return 0; |
771fe6b9 JG |
762 | } |
763 | ||
764 | static int radeon_ddc_dump(struct drm_connector *connector) | |
765 | { | |
766 | struct edid *edid; | |
767 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
768 | int ret = 0; | |
769 | ||
26b5bc98 | 770 | /* on hw with routers, select right port */ |
fb939dfc AD |
771 | if (radeon_connector->router.ddc_valid) |
772 | radeon_router_select_ddc_port(radeon_connector); | |
26b5bc98 | 773 | |
771fe6b9 JG |
774 | if (!radeon_connector->ddc_bus) |
775 | return -1; | |
771fe6b9 | 776 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
771fe6b9 JG |
777 | if (edid) { |
778 | kfree(edid); | |
779 | } | |
780 | return ret; | |
781 | } | |
782 | ||
783 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) | |
784 | { | |
785 | uint64_t mod; | |
786 | ||
787 | n += d / 2; | |
788 | ||
789 | mod = do_div(n, d); | |
790 | return n; | |
791 | } | |
792 | ||
48dfaaeb AD |
793 | void radeon_compute_pll(struct radeon_pll *pll, |
794 | uint64_t freq, | |
795 | uint32_t *dot_clock_p, | |
796 | uint32_t *fb_div_p, | |
797 | uint32_t *frac_fb_div_p, | |
798 | uint32_t *ref_div_p, | |
799 | uint32_t *post_div_p) | |
771fe6b9 JG |
800 | { |
801 | uint32_t min_ref_div = pll->min_ref_div; | |
802 | uint32_t max_ref_div = pll->max_ref_div; | |
fc10332b AD |
803 | uint32_t min_post_div = pll->min_post_div; |
804 | uint32_t max_post_div = pll->max_post_div; | |
771fe6b9 JG |
805 | uint32_t min_fractional_feed_div = 0; |
806 | uint32_t max_fractional_feed_div = 0; | |
807 | uint32_t best_vco = pll->best_vco; | |
808 | uint32_t best_post_div = 1; | |
809 | uint32_t best_ref_div = 1; | |
810 | uint32_t best_feedback_div = 1; | |
811 | uint32_t best_frac_feedback_div = 0; | |
812 | uint32_t best_freq = -1; | |
813 | uint32_t best_error = 0xffffffff; | |
814 | uint32_t best_vco_diff = 1; | |
815 | uint32_t post_div; | |
86cb2bbf | 816 | u32 pll_out_min, pll_out_max; |
771fe6b9 | 817 | |
d9fdaafb | 818 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
771fe6b9 JG |
819 | freq = freq * 1000; |
820 | ||
86cb2bbf AD |
821 | if (pll->flags & RADEON_PLL_IS_LCD) { |
822 | pll_out_min = pll->lcd_pll_out_min; | |
823 | pll_out_max = pll->lcd_pll_out_max; | |
824 | } else { | |
825 | pll_out_min = pll->pll_out_min; | |
826 | pll_out_max = pll->pll_out_max; | |
827 | } | |
828 | ||
fc10332b | 829 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
771fe6b9 JG |
830 | min_ref_div = max_ref_div = pll->reference_div; |
831 | else { | |
832 | while (min_ref_div < max_ref_div-1) { | |
833 | uint32_t mid = (min_ref_div + max_ref_div) / 2; | |
834 | uint32_t pll_in = pll->reference_freq / mid; | |
835 | if (pll_in < pll->pll_in_min) | |
836 | max_ref_div = mid; | |
837 | else if (pll_in > pll->pll_in_max) | |
838 | min_ref_div = mid; | |
839 | else | |
840 | break; | |
841 | } | |
842 | } | |
843 | ||
fc10332b AD |
844 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
845 | min_post_div = max_post_div = pll->post_div; | |
846 | ||
847 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { | |
771fe6b9 JG |
848 | min_fractional_feed_div = pll->min_frac_feedback_div; |
849 | max_fractional_feed_div = pll->max_frac_feedback_div; | |
850 | } | |
851 | ||
a6f97617 | 852 | for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { |
771fe6b9 JG |
853 | uint32_t ref_div; |
854 | ||
fc10332b | 855 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
771fe6b9 JG |
856 | continue; |
857 | ||
858 | /* legacy radeons only have a few post_divs */ | |
fc10332b | 859 | if (pll->flags & RADEON_PLL_LEGACY) { |
771fe6b9 JG |
860 | if ((post_div == 5) || |
861 | (post_div == 7) || | |
862 | (post_div == 9) || | |
863 | (post_div == 10) || | |
864 | (post_div == 11) || | |
865 | (post_div == 13) || | |
866 | (post_div == 14) || | |
867 | (post_div == 15)) | |
868 | continue; | |
869 | } | |
870 | ||
871 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { | |
872 | uint32_t feedback_div, current_freq = 0, error, vco_diff; | |
873 | uint32_t pll_in = pll->reference_freq / ref_div; | |
874 | uint32_t min_feed_div = pll->min_feedback_div; | |
875 | uint32_t max_feed_div = pll->max_feedback_div + 1; | |
876 | ||
877 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) | |
878 | continue; | |
879 | ||
880 | while (min_feed_div < max_feed_div) { | |
881 | uint32_t vco; | |
882 | uint32_t min_frac_feed_div = min_fractional_feed_div; | |
883 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; | |
884 | uint32_t frac_feedback_div; | |
885 | uint64_t tmp; | |
886 | ||
887 | feedback_div = (min_feed_div + max_feed_div) / 2; | |
888 | ||
889 | tmp = (uint64_t)pll->reference_freq * feedback_div; | |
890 | vco = radeon_div(tmp, ref_div); | |
891 | ||
86cb2bbf | 892 | if (vco < pll_out_min) { |
771fe6b9 JG |
893 | min_feed_div = feedback_div + 1; |
894 | continue; | |
86cb2bbf | 895 | } else if (vco > pll_out_max) { |
771fe6b9 JG |
896 | max_feed_div = feedback_div; |
897 | continue; | |
898 | } | |
899 | ||
900 | while (min_frac_feed_div < max_frac_feed_div) { | |
901 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; | |
902 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; | |
903 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; | |
904 | current_freq = radeon_div(tmp, ref_div * post_div); | |
905 | ||
fc10332b | 906 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
167ffc44 DC |
907 | if (freq < current_freq) |
908 | error = 0xffffffff; | |
909 | else | |
910 | error = freq - current_freq; | |
d0e275a9 AD |
911 | } else |
912 | error = abs(current_freq - freq); | |
771fe6b9 JG |
913 | vco_diff = abs(vco - best_vco); |
914 | ||
915 | if ((best_vco == 0 && error < best_error) || | |
916 | (best_vco != 0 && | |
167ffc44 | 917 | ((best_error > 100 && error < best_error - 100) || |
5480f727 | 918 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
771fe6b9 JG |
919 | best_post_div = post_div; |
920 | best_ref_div = ref_div; | |
921 | best_feedback_div = feedback_div; | |
922 | best_frac_feedback_div = frac_feedback_div; | |
923 | best_freq = current_freq; | |
924 | best_error = error; | |
925 | best_vco_diff = vco_diff; | |
5480f727 DA |
926 | } else if (current_freq == freq) { |
927 | if (best_freq == -1) { | |
928 | best_post_div = post_div; | |
929 | best_ref_div = ref_div; | |
930 | best_feedback_div = feedback_div; | |
931 | best_frac_feedback_div = frac_feedback_div; | |
932 | best_freq = current_freq; | |
933 | best_error = error; | |
934 | best_vco_diff = vco_diff; | |
935 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || | |
936 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || | |
937 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || | |
938 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || | |
939 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || | |
940 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { | |
941 | best_post_div = post_div; | |
942 | best_ref_div = ref_div; | |
943 | best_feedback_div = feedback_div; | |
944 | best_frac_feedback_div = frac_feedback_div; | |
945 | best_freq = current_freq; | |
946 | best_error = error; | |
947 | best_vco_diff = vco_diff; | |
948 | } | |
771fe6b9 JG |
949 | } |
950 | if (current_freq < freq) | |
951 | min_frac_feed_div = frac_feedback_div + 1; | |
952 | else | |
953 | max_frac_feed_div = frac_feedback_div; | |
954 | } | |
955 | if (current_freq < freq) | |
956 | min_feed_div = feedback_div + 1; | |
957 | else | |
958 | max_feed_div = feedback_div; | |
959 | } | |
960 | } | |
961 | } | |
962 | ||
963 | *dot_clock_p = best_freq / 10000; | |
964 | *fb_div_p = best_feedback_div; | |
965 | *frac_fb_div_p = best_frac_feedback_div; | |
966 | *ref_div_p = best_ref_div; | |
967 | *post_div_p = best_post_div; | |
51d4bf84 AD |
968 | DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
969 | freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div, | |
970 | best_ref_div, best_post_div); | |
971 | ||
771fe6b9 JG |
972 | } |
973 | ||
974 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
975 | { | |
976 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
771fe6b9 | 977 | |
29d08b3e | 978 | if (radeon_fb->obj) { |
bc9025bd | 979 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
29d08b3e | 980 | } |
771fe6b9 JG |
981 | drm_framebuffer_cleanup(fb); |
982 | kfree(radeon_fb); | |
983 | } | |
984 | ||
985 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
986 | struct drm_file *file_priv, | |
987 | unsigned int *handle) | |
988 | { | |
989 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); | |
990 | ||
991 | return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); | |
992 | } | |
993 | ||
994 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { | |
995 | .destroy = radeon_user_framebuffer_destroy, | |
996 | .create_handle = radeon_user_framebuffer_create_handle, | |
997 | }; | |
998 | ||
38651674 DA |
999 | void |
1000 | radeon_framebuffer_init(struct drm_device *dev, | |
1001 | struct radeon_framebuffer *rfb, | |
1002 | struct drm_mode_fb_cmd *mode_cmd, | |
1003 | struct drm_gem_object *obj) | |
771fe6b9 | 1004 | { |
38651674 DA |
1005 | rfb->obj = obj; |
1006 | drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); | |
1007 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); | |
771fe6b9 JG |
1008 | } |
1009 | ||
1010 | static struct drm_framebuffer * | |
1011 | radeon_user_framebuffer_create(struct drm_device *dev, | |
1012 | struct drm_file *file_priv, | |
1013 | struct drm_mode_fb_cmd *mode_cmd) | |
1014 | { | |
1015 | struct drm_gem_object *obj; | |
38651674 | 1016 | struct radeon_framebuffer *radeon_fb; |
771fe6b9 JG |
1017 | |
1018 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); | |
7e71c9e2 JG |
1019 | if (obj == NULL) { |
1020 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
1021 | "can't create framebuffer\n", mode_cmd->handle); | |
cce13ff7 | 1022 | return ERR_PTR(-ENOENT); |
7e71c9e2 | 1023 | } |
38651674 DA |
1024 | |
1025 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); | |
cce13ff7 CW |
1026 | if (radeon_fb == NULL) |
1027 | return ERR_PTR(-ENOMEM); | |
38651674 DA |
1028 | |
1029 | radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); | |
1030 | ||
1031 | return &radeon_fb->base; | |
771fe6b9 JG |
1032 | } |
1033 | ||
eb1f8e4f DA |
1034 | static void radeon_output_poll_changed(struct drm_device *dev) |
1035 | { | |
1036 | struct radeon_device *rdev = dev->dev_private; | |
1037 | radeon_fb_output_poll_changed(rdev); | |
1038 | } | |
1039 | ||
771fe6b9 JG |
1040 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1041 | .fb_create = radeon_user_framebuffer_create, | |
eb1f8e4f | 1042 | .output_poll_changed = radeon_output_poll_changed |
771fe6b9 JG |
1043 | }; |
1044 | ||
445282db DA |
1045 | struct drm_prop_enum_list { |
1046 | int type; | |
1047 | char *name; | |
1048 | }; | |
1049 | ||
1050 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = | |
1051 | { { 0, "driver" }, | |
1052 | { 1, "bios" }, | |
1053 | }; | |
1054 | ||
1055 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = | |
1056 | { { TV_STD_NTSC, "ntsc" }, | |
1057 | { TV_STD_PAL, "pal" }, | |
1058 | { TV_STD_PAL_M, "pal-m" }, | |
1059 | { TV_STD_PAL_60, "pal-60" }, | |
1060 | { TV_STD_NTSC_J, "ntsc-j" }, | |
1061 | { TV_STD_SCART_PAL, "scart-pal" }, | |
1062 | { TV_STD_PAL_CN, "pal-cn" }, | |
1063 | { TV_STD_SECAM, "secam" }, | |
1064 | }; | |
1065 | ||
5b1714d3 AD |
1066 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1067 | { { UNDERSCAN_OFF, "off" }, | |
1068 | { UNDERSCAN_ON, "on" }, | |
1069 | { UNDERSCAN_AUTO, "auto" }, | |
1070 | }; | |
1071 | ||
d79766fa | 1072 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
445282db DA |
1073 | { |
1074 | int i, sz; | |
1075 | ||
1076 | if (rdev->is_atom_bios) { | |
1077 | rdev->mode_info.coherent_mode_property = | |
1078 | drm_property_create(rdev->ddev, | |
1079 | DRM_MODE_PROP_RANGE, | |
1080 | "coherent", 2); | |
1081 | if (!rdev->mode_info.coherent_mode_property) | |
1082 | return -ENOMEM; | |
1083 | ||
1084 | rdev->mode_info.coherent_mode_property->values[0] = 0; | |
390d0bbe | 1085 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
445282db DA |
1086 | } |
1087 | ||
1088 | if (!ASIC_IS_AVIVO(rdev)) { | |
1089 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); | |
1090 | rdev->mode_info.tmds_pll_property = | |
1091 | drm_property_create(rdev->ddev, | |
1092 | DRM_MODE_PROP_ENUM, | |
1093 | "tmds_pll", sz); | |
1094 | for (i = 0; i < sz; i++) { | |
1095 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, | |
1096 | i, | |
1097 | radeon_tmds_pll_enum_list[i].type, | |
1098 | radeon_tmds_pll_enum_list[i].name); | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | rdev->mode_info.load_detect_property = | |
1103 | drm_property_create(rdev->ddev, | |
1104 | DRM_MODE_PROP_RANGE, | |
1105 | "load detection", 2); | |
1106 | if (!rdev->mode_info.load_detect_property) | |
1107 | return -ENOMEM; | |
1108 | rdev->mode_info.load_detect_property->values[0] = 0; | |
390d0bbe | 1109 | rdev->mode_info.load_detect_property->values[1] = 1; |
445282db DA |
1110 | |
1111 | drm_mode_create_scaling_mode_property(rdev->ddev); | |
1112 | ||
1113 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); | |
1114 | rdev->mode_info.tv_std_property = | |
1115 | drm_property_create(rdev->ddev, | |
1116 | DRM_MODE_PROP_ENUM, | |
1117 | "tv standard", sz); | |
1118 | for (i = 0; i < sz; i++) { | |
1119 | drm_property_add_enum(rdev->mode_info.tv_std_property, | |
1120 | i, | |
1121 | radeon_tv_std_enum_list[i].type, | |
1122 | radeon_tv_std_enum_list[i].name); | |
1123 | } | |
1124 | ||
5b1714d3 AD |
1125 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1126 | rdev->mode_info.underscan_property = | |
1127 | drm_property_create(rdev->ddev, | |
1128 | DRM_MODE_PROP_ENUM, | |
1129 | "underscan", sz); | |
1130 | for (i = 0; i < sz; i++) { | |
1131 | drm_property_add_enum(rdev->mode_info.underscan_property, | |
1132 | i, | |
1133 | radeon_underscan_enum_list[i].type, | |
1134 | radeon_underscan_enum_list[i].name); | |
1135 | } | |
1136 | ||
5bccf5e3 MG |
1137 | rdev->mode_info.underscan_hborder_property = |
1138 | drm_property_create(rdev->ddev, | |
1139 | DRM_MODE_PROP_RANGE, | |
1140 | "underscan hborder", 2); | |
1141 | if (!rdev->mode_info.underscan_hborder_property) | |
1142 | return -ENOMEM; | |
1143 | rdev->mode_info.underscan_hborder_property->values[0] = 0; | |
1144 | rdev->mode_info.underscan_hborder_property->values[1] = 128; | |
1145 | ||
1146 | rdev->mode_info.underscan_vborder_property = | |
1147 | drm_property_create(rdev->ddev, | |
1148 | DRM_MODE_PROP_RANGE, | |
1149 | "underscan vborder", 2); | |
1150 | if (!rdev->mode_info.underscan_vborder_property) | |
1151 | return -ENOMEM; | |
1152 | rdev->mode_info.underscan_vborder_property->values[0] = 0; | |
1153 | rdev->mode_info.underscan_vborder_property->values[1] = 128; | |
1154 | ||
445282db DA |
1155 | return 0; |
1156 | } | |
1157 | ||
f46c0120 AD |
1158 | void radeon_update_display_priority(struct radeon_device *rdev) |
1159 | { | |
1160 | /* adjustment options for the display watermarks */ | |
1161 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { | |
1162 | /* set display priority to high for r3xx, rv515 chips | |
1163 | * this avoids flickering due to underflow to the | |
1164 | * display controllers during heavy acceleration. | |
45737447 AD |
1165 | * Don't force high on rs4xx igp chips as it seems to |
1166 | * affect the sound card. See kernel bug 15982. | |
f46c0120 | 1167 | */ |
45737447 AD |
1168 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1169 | !(rdev->flags & RADEON_IS_IGP)) | |
f46c0120 AD |
1170 | rdev->disp_priority = 2; |
1171 | else | |
1172 | rdev->disp_priority = 0; | |
1173 | } else | |
1174 | rdev->disp_priority = radeon_disp_priority; | |
1175 | ||
1176 | } | |
1177 | ||
771fe6b9 JG |
1178 | int radeon_modeset_init(struct radeon_device *rdev) |
1179 | { | |
18917b60 | 1180 | int i; |
771fe6b9 JG |
1181 | int ret; |
1182 | ||
1183 | drm_mode_config_init(rdev->ddev); | |
1184 | rdev->mode_info.mode_config_initialized = true; | |
1185 | ||
1186 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; | |
1187 | ||
881dd74e AD |
1188 | if (ASIC_IS_DCE5(rdev)) { |
1189 | rdev->ddev->mode_config.max_width = 16384; | |
1190 | rdev->ddev->mode_config.max_height = 16384; | |
1191 | } else if (ASIC_IS_AVIVO(rdev)) { | |
771fe6b9 JG |
1192 | rdev->ddev->mode_config.max_width = 8192; |
1193 | rdev->ddev->mode_config.max_height = 8192; | |
1194 | } else { | |
1195 | rdev->ddev->mode_config.max_width = 4096; | |
1196 | rdev->ddev->mode_config.max_height = 4096; | |
1197 | } | |
1198 | ||
1199 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; | |
1200 | ||
445282db DA |
1201 | ret = radeon_modeset_create_props(rdev); |
1202 | if (ret) { | |
1203 | return ret; | |
1204 | } | |
dfee5614 | 1205 | |
f376b94f AD |
1206 | /* init i2c buses */ |
1207 | radeon_i2c_init(rdev); | |
1208 | ||
3c537889 AD |
1209 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1210 | if (!rdev->is_atom_bios) { | |
1211 | /* check for hardcoded EDID in BIOS */ | |
1212 | radeon_combios_check_hardcoded_edid(rdev); | |
1213 | } | |
1214 | ||
dfee5614 | 1215 | /* allocate crtcs */ |
18917b60 | 1216 | for (i = 0; i < rdev->num_crtc; i++) { |
771fe6b9 JG |
1217 | radeon_crtc_init(rdev->ddev, i); |
1218 | } | |
1219 | ||
1220 | /* okay we should have all the bios connectors */ | |
1221 | ret = radeon_setup_enc_conn(rdev->ddev); | |
1222 | if (!ret) { | |
1223 | return ret; | |
1224 | } | |
d4877cf2 AD |
1225 | /* initialize hpd */ |
1226 | radeon_hpd_init(rdev); | |
38651674 | 1227 | |
ce8f5370 AD |
1228 | /* Initialize power management */ |
1229 | radeon_pm_init(rdev); | |
1230 | ||
38651674 | 1231 | radeon_fbdev_init(rdev); |
eb1f8e4f DA |
1232 | drm_kms_helper_poll_init(rdev->ddev); |
1233 | ||
771fe6b9 JG |
1234 | return 0; |
1235 | } | |
1236 | ||
1237 | void radeon_modeset_fini(struct radeon_device *rdev) | |
1238 | { | |
38651674 | 1239 | radeon_fbdev_fini(rdev); |
3c537889 | 1240 | kfree(rdev->mode_info.bios_hardcoded_edid); |
ce8f5370 | 1241 | radeon_pm_fini(rdev); |
3c537889 | 1242 | |
771fe6b9 | 1243 | if (rdev->mode_info.mode_config_initialized) { |
eb1f8e4f | 1244 | drm_kms_helper_poll_fini(rdev->ddev); |
d4877cf2 | 1245 | radeon_hpd_fini(rdev); |
771fe6b9 JG |
1246 | drm_mode_config_cleanup(rdev->ddev); |
1247 | rdev->mode_info.mode_config_initialized = false; | |
1248 | } | |
f376b94f AD |
1249 | /* free i2c buses */ |
1250 | radeon_i2c_fini(rdev); | |
771fe6b9 JG |
1251 | } |
1252 | ||
039ed2d9 AD |
1253 | static bool is_hdtv_mode(struct drm_display_mode *mode) |
1254 | { | |
1255 | /* try and guess if this is a tv or a monitor */ | |
1256 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
1257 | (mode->vdisplay == 576) || /* 576p */ | |
1258 | (mode->vdisplay == 720) || /* 720p */ | |
1259 | (mode->vdisplay == 1080)) /* 1080p */ | |
1260 | return true; | |
1261 | else | |
1262 | return false; | |
1263 | } | |
1264 | ||
c93bb85b JG |
1265 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1266 | struct drm_display_mode *mode, | |
1267 | struct drm_display_mode *adjusted_mode) | |
771fe6b9 | 1268 | { |
c93bb85b | 1269 | struct drm_device *dev = crtc->dev; |
5b1714d3 | 1270 | struct radeon_device *rdev = dev->dev_private; |
c93bb85b JG |
1271 | struct drm_encoder *encoder; |
1272 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1273 | struct radeon_encoder *radeon_encoder; | |
5b1714d3 AD |
1274 | struct drm_connector *connector; |
1275 | struct radeon_connector *radeon_connector; | |
c93bb85b | 1276 | bool first = true; |
d65d65b1 AD |
1277 | u32 src_v = 1, dst_v = 1; |
1278 | u32 src_h = 1, dst_h = 1; | |
771fe6b9 | 1279 | |
5b1714d3 AD |
1280 | radeon_crtc->h_border = 0; |
1281 | radeon_crtc->v_border = 0; | |
1282 | ||
c93bb85b | 1283 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
c93bb85b JG |
1284 | if (encoder->crtc != crtc) |
1285 | continue; | |
d65d65b1 | 1286 | radeon_encoder = to_radeon_encoder(encoder); |
5b1714d3 AD |
1287 | connector = radeon_get_connector_for_encoder(encoder); |
1288 | radeon_connector = to_radeon_connector(connector); | |
1289 | ||
c93bb85b | 1290 | if (first) { |
80297e87 AD |
1291 | /* set scaling */ |
1292 | if (radeon_encoder->rmx_type == RMX_OFF) | |
1293 | radeon_crtc->rmx_type = RMX_OFF; | |
1294 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || | |
1295 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) | |
1296 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; | |
1297 | else | |
1298 | radeon_crtc->rmx_type = RMX_OFF; | |
1299 | /* copy native mode */ | |
c93bb85b | 1300 | memcpy(&radeon_crtc->native_mode, |
80297e87 | 1301 | &radeon_encoder->native_mode, |
de2103e4 | 1302 | sizeof(struct drm_display_mode)); |
ff32a59d AD |
1303 | src_v = crtc->mode.vdisplay; |
1304 | dst_v = radeon_crtc->native_mode.vdisplay; | |
1305 | src_h = crtc->mode.hdisplay; | |
1306 | dst_h = radeon_crtc->native_mode.hdisplay; | |
5b1714d3 AD |
1307 | |
1308 | /* fix up for overscan on hdmi */ | |
1309 | if (ASIC_IS_AVIVO(rdev) && | |
e6db0da0 | 1310 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
5b1714d3 AD |
1311 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1312 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && | |
039ed2d9 AD |
1313 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
1314 | is_hdtv_mode(mode)))) { | |
5bccf5e3 MG |
1315 | if (radeon_encoder->underscan_hborder != 0) |
1316 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; | |
1317 | else | |
1318 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
1319 | if (radeon_encoder->underscan_vborder != 0) | |
1320 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; | |
1321 | else | |
1322 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
5b1714d3 AD |
1323 | radeon_crtc->rmx_type = RMX_FULL; |
1324 | src_v = crtc->mode.vdisplay; | |
1325 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); | |
1326 | src_h = crtc->mode.hdisplay; | |
1327 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); | |
1328 | } | |
c93bb85b JG |
1329 | first = false; |
1330 | } else { | |
1331 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { | |
1332 | /* WARNING: Right now this can't happen but | |
1333 | * in the future we need to check that scaling | |
d65d65b1 | 1334 | * are consistent across different encoder |
c93bb85b JG |
1335 | * (ie all encoder can work with the same |
1336 | * scaling). | |
1337 | */ | |
d65d65b1 | 1338 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
c93bb85b JG |
1339 | return false; |
1340 | } | |
771fe6b9 JG |
1341 | } |
1342 | } | |
c93bb85b JG |
1343 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1344 | fixed20_12 a, b; | |
d65d65b1 AD |
1345 | a.full = dfixed_const(src_v); |
1346 | b.full = dfixed_const(dst_v); | |
68adac5e | 1347 | radeon_crtc->vsc.full = dfixed_div(a, b); |
d65d65b1 AD |
1348 | a.full = dfixed_const(src_h); |
1349 | b.full = dfixed_const(dst_h); | |
68adac5e | 1350 | radeon_crtc->hsc.full = dfixed_div(a, b); |
771fe6b9 | 1351 | } else { |
68adac5e BS |
1352 | radeon_crtc->vsc.full = dfixed_const(1); |
1353 | radeon_crtc->hsc.full = dfixed_const(1); | |
771fe6b9 | 1354 | } |
c93bb85b | 1355 | return true; |
771fe6b9 | 1356 | } |
6383cf7d MK |
1357 | |
1358 | /* | |
1359 | * Retrieve current video scanout position of crtc on a given gpu. | |
1360 | * | |
f5a80209 | 1361 | * \param dev Device to query. |
6383cf7d MK |
1362 | * \param crtc Crtc to query. |
1363 | * \param *vpos Location where vertical scanout position should be stored. | |
1364 | * \param *hpos Location where horizontal scanout position should go. | |
1365 | * | |
1366 | * Returns vpos as a positive number while in active scanout area. | |
1367 | * Returns vpos as a negative number inside vblank, counting the number | |
1368 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
1369 | * until start of active scanout / end of vblank." | |
1370 | * | |
1371 | * \return Flags, or'ed together as follows: | |
1372 | * | |
f5a80209 MK |
1373 | * DRM_SCANOUTPOS_VALID = Query successfull. |
1374 | * DRM_SCANOUTPOS_INVBL = Inside vblank. | |
1375 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
6383cf7d MK |
1376 | * this flag means that returned position may be offset by a constant but |
1377 | * unknown small number of scanlines wrt. real scanout position. | |
1378 | * | |
1379 | */ | |
f5a80209 | 1380 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
6383cf7d MK |
1381 | { |
1382 | u32 stat_crtc = 0, vbl = 0, position = 0; | |
1383 | int vbl_start, vbl_end, vtotal, ret = 0; | |
1384 | bool in_vbl = true; | |
1385 | ||
f5a80209 MK |
1386 | struct radeon_device *rdev = dev->dev_private; |
1387 | ||
6383cf7d MK |
1388 | if (ASIC_IS_DCE4(rdev)) { |
1389 | if (crtc == 0) { | |
1390 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1391 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
1392 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1393 | EVERGREEN_CRTC0_REGISTER_OFFSET); | |
f5a80209 | 1394 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1395 | } |
1396 | if (crtc == 1) { | |
1397 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1398 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
1399 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1400 | EVERGREEN_CRTC1_REGISTER_OFFSET); | |
f5a80209 | 1401 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1402 | } |
1403 | if (crtc == 2) { | |
1404 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1405 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
1406 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1407 | EVERGREEN_CRTC2_REGISTER_OFFSET); | |
f5a80209 | 1408 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1409 | } |
1410 | if (crtc == 3) { | |
1411 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1412 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
1413 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1414 | EVERGREEN_CRTC3_REGISTER_OFFSET); | |
f5a80209 | 1415 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1416 | } |
1417 | if (crtc == 4) { | |
1418 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1419 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
1420 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1421 | EVERGREEN_CRTC4_REGISTER_OFFSET); | |
f5a80209 | 1422 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1423 | } |
1424 | if (crtc == 5) { | |
1425 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + | |
1426 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
1427 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + | |
1428 | EVERGREEN_CRTC5_REGISTER_OFFSET); | |
f5a80209 | 1429 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1430 | } |
1431 | } else if (ASIC_IS_AVIVO(rdev)) { | |
1432 | if (crtc == 0) { | |
1433 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); | |
1434 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); | |
f5a80209 | 1435 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1436 | } |
1437 | if (crtc == 1) { | |
1438 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); | |
1439 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); | |
f5a80209 | 1440 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1441 | } |
1442 | } else { | |
1443 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ | |
1444 | if (crtc == 0) { | |
1445 | /* Assume vbl_end == 0, get vbl_start from | |
1446 | * upper 16 bits. | |
1447 | */ | |
1448 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & | |
1449 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1450 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ | |
1451 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1452 | stat_crtc = RREG32(RADEON_CRTC_STATUS); | |
1453 | if (!(stat_crtc & 1)) | |
1454 | in_vbl = false; | |
1455 | ||
f5a80209 | 1456 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1457 | } |
1458 | if (crtc == 1) { | |
1459 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & | |
1460 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; | |
1461 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
1462 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); | |
1463 | if (!(stat_crtc & 1)) | |
1464 | in_vbl = false; | |
1465 | ||
f5a80209 | 1466 | ret |= DRM_SCANOUTPOS_VALID; |
6383cf7d MK |
1467 | } |
1468 | } | |
1469 | ||
1470 | /* Decode into vertical and horizontal scanout position. */ | |
1471 | *vpos = position & 0x1fff; | |
1472 | *hpos = (position >> 16) & 0x1fff; | |
1473 | ||
1474 | /* Valid vblank area boundaries from gpu retrieved? */ | |
1475 | if (vbl > 0) { | |
1476 | /* Yes: Decode. */ | |
f5a80209 | 1477 | ret |= DRM_SCANOUTPOS_ACCURATE; |
6383cf7d MK |
1478 | vbl_start = vbl & 0x1fff; |
1479 | vbl_end = (vbl >> 16) & 0x1fff; | |
1480 | } | |
1481 | else { | |
1482 | /* No: Fake something reasonable which gives at least ok results. */ | |
f5a80209 | 1483 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
6383cf7d MK |
1484 | vbl_end = 0; |
1485 | } | |
1486 | ||
1487 | /* Test scanout position against vblank region. */ | |
1488 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
1489 | in_vbl = false; | |
1490 | ||
1491 | /* Check if inside vblank area and apply corrective offsets: | |
1492 | * vpos will then be >=0 in video scanout area, but negative | |
1493 | * within vblank area, counting down the number of lines until | |
1494 | * start of scanout. | |
1495 | */ | |
1496 | ||
1497 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
1498 | if (in_vbl && (*vpos >= vbl_start)) { | |
f5a80209 | 1499 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
6383cf7d MK |
1500 | *vpos = *vpos - vtotal; |
1501 | } | |
1502 | ||
1503 | /* Correct for shifted end of vbl at vbl_end. */ | |
1504 | *vpos = *vpos - vbl_end; | |
1505 | ||
1506 | /* In vblank? */ | |
1507 | if (in_vbl) | |
f5a80209 | 1508 | ret |= DRM_SCANOUTPOS_INVBL; |
6383cf7d MK |
1509 | |
1510 | return ret; | |
1511 | } |