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drm/radeon/kms/atom: rework crtc modeset
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
71static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77 uint32_t dac2_cntl;
78
79 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80 if (radeon_crtc->crtc_id == 0)
81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82 else
83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86 WREG8(RADEON_PALETTE_INDEX, 0);
87 for (i = 0; i < 256; i++) {
88 WREG32(RADEON_PALETTE_30_DATA,
89 (radeon_crtc->lut_r[i] << 20) |
90 (radeon_crtc->lut_g[i] << 10) |
91 (radeon_crtc->lut_b[i] << 0));
92 }
93}
94
95void radeon_crtc_load_lut(struct drm_crtc *crtc)
96{
97 struct drm_device *dev = crtc->dev;
98 struct radeon_device *rdev = dev->dev_private;
99
100 if (!crtc->enabled)
101 return;
102
103 if (ASIC_IS_AVIVO(rdev))
104 avivo_crtc_load_lut(crtc);
105 else
106 legacy_crtc_load_lut(crtc);
107}
108
b8c00ac5 109/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 110void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111 u16 blue, int regno)
112{
113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
771fe6b9
JG		 115 radeon_crtc->lut_r[regno] = red >> 6;
116 radeon_crtc->lut_g[regno] = green >> 6;
117 radeon_crtc->lut_b[regno] = blue >> 6;
118}
119
b8c00ac5
DA		 120/** Gets the color ramps on behalf of fbcon */
121void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122 u16 *blue, int regno)
123{
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126 *red = radeon_crtc->lut_r[regno] << 6;
127 *green = radeon_crtc->lut_g[regno] << 6;
128 *blue = radeon_crtc->lut_b[regno] << 6;
129}
130
771fe6b9
JG		 131static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132 u16 *blue, uint32_t size)
133{
134 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
b8c00ac5 135 int i;
771fe6b9
JG		 136
137 if (size != 256) {
138 return;
139 }
771fe6b9 140
b8c00ac5
DA		 141 /* userspace palettes are always correct as is */
142 for (i = 0; i < 256; i++) {
143 radeon_crtc->lut_r[i] = red[i] >> 6;
144 radeon_crtc->lut_g[i] = green[i] >> 6;
145 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 146 }
771fe6b9
JG		 147 radeon_crtc_load_lut(crtc);
148}
149
150static void radeon_crtc_destroy(struct drm_crtc *crtc)
151{
152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
153
771fe6b9
JG		 154 drm_crtc_cleanup(crtc);
155 kfree(radeon_crtc);
156}
157
158static const struct drm_crtc_funcs radeon_crtc_funcs = {
159 .cursor_set = radeon_crtc_cursor_set,
160 .cursor_move = radeon_crtc_cursor_move,
161 .gamma_set = radeon_crtc_gamma_set,
162 .set_config = drm_crtc_helper_set_config,
163 .destroy = radeon_crtc_destroy,
164};
165
166static void radeon_crtc_init(struct drm_device *dev, int index)
167{
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_crtc *radeon_crtc;
170 int i;
171
172 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
173 if (radeon_crtc == NULL)
174 return;
175
176 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
177
178 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
179 radeon_crtc->crtc_id = index;
c93bb85b 180 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 181
785b93ef 182#if 0
771fe6b9
JG		 183 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
184 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
185 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 186#endif
771fe6b9
JG		 187
188 for (i = 0; i < 256; i++) {
189 radeon_crtc->lut_r[i] = i << 2;
190 radeon_crtc->lut_g[i] = i << 2;
191 radeon_crtc->lut_b[i] = i << 2;
192 }
193
194 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
195 radeon_atombios_init_crtc(dev, radeon_crtc);
196 else
197 radeon_legacy_init_crtc(dev, radeon_crtc);
198}
199
200static const char *encoder_names[34] = {
201 "NONE",
202 "INTERNAL_LVDS",
203 "INTERNAL_TMDS1",
204 "INTERNAL_TMDS2",
205 "INTERNAL_DAC1",
206 "INTERNAL_DAC2",
207 "INTERNAL_SDVOA",
208 "INTERNAL_SDVOB",
209 "SI170B",
210 "CH7303",
211 "CH7301",
212 "INTERNAL_DVO1",
213 "EXTERNAL_SDVOA",
214 "EXTERNAL_SDVOB",
215 "TITFP513",
216 "INTERNAL_LVTM1",
217 "VT1623",
218 "HDMI_SI1930",
219 "HDMI_INTERNAL",
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
224 "SI178",
225 "MVPU_FPGA",
226 "INTERNAL_DDI",
227 "VT1625",
228 "HDMI_SI1932",
229 "DP_AN9801",
230 "DP_DP501",
231 "INTERNAL_UNIPHY",
232 "INTERNAL_KLDSCP_LVTMA",
233 "INTERNAL_UNIPHY1",
234 "INTERNAL_UNIPHY2",
235};
236
237static const char *connector_names[13] = {
238 "Unknown",
239 "VGA",
240 "DVI-I",
241 "DVI-D",
242 "DVI-A",
243 "Composite",
244 "S-video",
245 "LVDS",
246 "Component",
247 "DIN",
248 "DisplayPort",
249 "HDMI-A",
250 "HDMI-B",
251};
252
253static void radeon_print_display_setup(struct drm_device *dev)
254{
255 struct drm_connector *connector;
256 struct radeon_connector *radeon_connector;
257 struct drm_encoder *encoder;
258 struct radeon_encoder *radeon_encoder;
259 uint32_t devices;
260 int i = 0;
261
262 DRM_INFO("Radeon Display Connectors\n");
263 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
264 radeon_connector = to_radeon_connector(connector);
265 DRM_INFO("Connector %d:\n", i);
266 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
267 if (radeon_connector->ddc_bus)
268 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
269 radeon_connector->ddc_bus->rec.mask_clk_reg,
270 radeon_connector->ddc_bus->rec.mask_data_reg,
271 radeon_connector->ddc_bus->rec.a_clk_reg,
272 radeon_connector->ddc_bus->rec.a_data_reg,
273 radeon_connector->ddc_bus->rec.put_clk_reg,
274 radeon_connector->ddc_bus->rec.put_data_reg,
275 radeon_connector->ddc_bus->rec.get_clk_reg,
276 radeon_connector->ddc_bus->rec.get_data_reg);
277 DRM_INFO(" Encoders:\n");
278 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
279 radeon_encoder = to_radeon_encoder(encoder);
280 devices = radeon_encoder->devices & radeon_connector->devices;
281 if (devices) {
282 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
283 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
284 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
285 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
286 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
287 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
288 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
289 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
290 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
291 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
292 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
293 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
294 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
295 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
296 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
297 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
298 if (devices & ATOM_DEVICE_TV1_SUPPORT)
299 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
300 if (devices & ATOM_DEVICE_CV_SUPPORT)
301 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
302 }
303 }
304 i++;
305 }
306}
307
4ce001ab 308static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 309{
310 struct radeon_device *rdev = dev->dev_private;
311 struct drm_connector *drm_connector;
312 bool ret = false;
313
314 if (rdev->bios) {
315 if (rdev->is_atom_bios) {
316 if (rdev->family >= CHIP_R600)
317 ret = radeon_get_atom_connector_info_from_object_table(dev);
318 else
319 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
320 } else
321 ret = radeon_get_legacy_connector_info_from_bios(dev);
322 } else {
323 if (!ASIC_IS_AVIVO(rdev))
324 ret = radeon_get_legacy_connector_info_from_table(dev);
325 }
326 if (ret) {
327 radeon_print_display_setup(dev);
328 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
329 radeon_ddc_dump(drm_connector);
330 }
331
332 return ret;
333}
334
335int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
336{
337 struct edid *edid;
338 int ret = 0;
339
340 if (!radeon_connector->ddc_bus)
341 return -1;
4ce001ab
DA		 342 if (!radeon_connector->edid) {
343 radeon_i2c_do_lock(radeon_connector, 1);
344 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
345 radeon_i2c_do_lock(radeon_connector, 0);
346 } else
347 edid = radeon_connector->edid;
348
771fe6b9
JG		 349 if (edid) {
350 /* update digital bits here */
0454beab 351 if (edid->input & DRM_EDID_INPUT_DIGITAL)
771fe6b9
JG		 352 radeon_connector->use_digital = 1;
353 else
354 radeon_connector->use_digital = 0;
355 drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
356 ret = drm_add_edid_modes(&radeon_connector->base, edid);
357 kfree(edid);
358 return ret;
359 }
360 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 361 return 0;
771fe6b9
JG		 362}
363
364static int radeon_ddc_dump(struct drm_connector *connector)
365{
366 struct edid *edid;
367 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
368 int ret = 0;
369
370 if (!radeon_connector->ddc_bus)
371 return -1;
372 radeon_i2c_do_lock(radeon_connector, 1);
373 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
374 radeon_i2c_do_lock(radeon_connector, 0);
375 if (edid) {
376 kfree(edid);
377 }
378 return ret;
379}
380
381static inline uint32_t radeon_div(uint64_t n, uint32_t d)
382{
383 uint64_t mod;
384
385 n += d / 2;
386
387 mod = do_div(n, d);
388 return n;
389}
390
391void radeon_compute_pll(struct radeon_pll *pll,
392 uint64_t freq,
393 uint32_t *dot_clock_p,
394 uint32_t *fb_div_p,
395 uint32_t *frac_fb_div_p,
396 uint32_t *ref_div_p,
397 uint32_t *post_div_p,
398 int flags)
399{
400 uint32_t min_ref_div = pll->min_ref_div;
401 uint32_t max_ref_div = pll->max_ref_div;
402 uint32_t min_fractional_feed_div = 0;
403 uint32_t max_fractional_feed_div = 0;
404 uint32_t best_vco = pll->best_vco;
405 uint32_t best_post_div = 1;
406 uint32_t best_ref_div = 1;
407 uint32_t best_feedback_div = 1;
408 uint32_t best_frac_feedback_div = 0;
409 uint32_t best_freq = -1;
410 uint32_t best_error = 0xffffffff;
411 uint32_t best_vco_diff = 1;
412 uint32_t post_div;
413
414 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
415 freq = freq * 1000;
416
417 if (flags & RADEON_PLL_USE_REF_DIV)
418 min_ref_div = max_ref_div = pll->reference_div;
419 else {
420 while (min_ref_div < max_ref_div-1) {
421 uint32_t mid = (min_ref_div + max_ref_div) / 2;
422 uint32_t pll_in = pll->reference_freq / mid;
423 if (pll_in < pll->pll_in_min)
424 max_ref_div = mid;
425 else if (pll_in > pll->pll_in_max)
426 min_ref_div = mid;
427 else
428 break;
429 }
430 }
431
432 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
433 min_fractional_feed_div = pll->min_frac_feedback_div;
434 max_fractional_feed_div = pll->max_frac_feedback_div;
435 }
436
437 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
438 uint32_t ref_div;
439
440 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
441 continue;
442
443 /* legacy radeons only have a few post_divs */
444 if (flags & RADEON_PLL_LEGACY) {
445 if ((post_div == 5) ||
446 (post_div == 7) ||
447 (post_div == 9) ||
448 (post_div == 10) ||
449 (post_div == 11) ||
450 (post_div == 13) ||
451 (post_div == 14) ||
452 (post_div == 15))
453 continue;
454 }
455
456 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
457 uint32_t feedback_div, current_freq = 0, error, vco_diff;
458 uint32_t pll_in = pll->reference_freq / ref_div;
459 uint32_t min_feed_div = pll->min_feedback_div;
460 uint32_t max_feed_div = pll->max_feedback_div + 1;
461
462 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
463 continue;
464
465 while (min_feed_div < max_feed_div) {
466 uint32_t vco;
467 uint32_t min_frac_feed_div = min_fractional_feed_div;
468 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
469 uint32_t frac_feedback_div;
470 uint64_t tmp;
471
472 feedback_div = (min_feed_div + max_feed_div) / 2;
473
474 tmp = (uint64_t)pll->reference_freq * feedback_div;
475 vco = radeon_div(tmp, ref_div);
476
477 if (vco < pll->pll_out_min) {
478 min_feed_div = feedback_div + 1;
479 continue;
480 } else if (vco > pll->pll_out_max) {
481 max_feed_div = feedback_div;
482 continue;
483 }
484
485 while (min_frac_feed_div < max_frac_feed_div) {
486 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
487 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
488 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
489 current_freq = radeon_div(tmp, ref_div * post_div);
490
d0e275a9
AD		 491 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
492 error = freq - current_freq;
493 error = error < 0 ? 0xffffffff : error;
494 } else
495 error = abs(current_freq - freq);
771fe6b9
JG		 496 vco_diff = abs(vco - best_vco);
497
498 if ((best_vco == 0 && error < best_error) ||
499 (best_vco != 0 &&
500 (error < best_error - 100 ||
501 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
502 best_post_div = post_div;
503 best_ref_div = ref_div;
504 best_feedback_div = feedback_div;
505 best_frac_feedback_div = frac_feedback_div;
506 best_freq = current_freq;
507 best_error = error;
508 best_vco_diff = vco_diff;
509 } else if (current_freq == freq) {
510 if (best_freq == -1) {
511 best_post_div = post_div;
512 best_ref_div = ref_div;
513 best_feedback_div = feedback_div;
514 best_frac_feedback_div = frac_feedback_div;
515 best_freq = current_freq;
516 best_error = error;
517 best_vco_diff = vco_diff;
518 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
519 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
520 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
521 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
522 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
523 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
524 best_post_div = post_div;
525 best_ref_div = ref_div;
526 best_feedback_div = feedback_div;
527 best_frac_feedback_div = frac_feedback_div;
528 best_freq = current_freq;
529 best_error = error;
530 best_vco_diff = vco_diff;
531 }
532 }
533 if (current_freq < freq)
534 min_frac_feed_div = frac_feedback_div + 1;
535 else
536 max_frac_feed_div = frac_feedback_div;
537 }
538 if (current_freq < freq)
539 min_feed_div = feedback_div + 1;
540 else
541 max_feed_div = feedback_div;
542 }
543 }
544 }
545
546 *dot_clock_p = best_freq / 10000;
547 *fb_div_p = best_feedback_div;
548 *frac_fb_div_p = best_frac_feedback_div;
549 *ref_div_p = best_ref_div;
550 *post_div_p = best_post_div;
551}
552
553static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
554{
555 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
556 struct drm_device *dev = fb->dev;
557
558 if (fb->fbdev)
559 radeonfb_remove(dev, fb);
560
561 if (radeon_fb->obj) {
562 radeon_gem_object_unpin(radeon_fb->obj);
563 mutex_lock(&dev->struct_mutex);
564 drm_gem_object_unreference(radeon_fb->obj);
565 mutex_unlock(&dev->struct_mutex);
566 }
567 drm_framebuffer_cleanup(fb);
568 kfree(radeon_fb);
569}
570
571static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
572 struct drm_file *file_priv,
573 unsigned int *handle)
574{
575 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
576
577 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
578}
579
580static const struct drm_framebuffer_funcs radeon_fb_funcs = {
581 .destroy = radeon_user_framebuffer_destroy,
582 .create_handle = radeon_user_framebuffer_create_handle,
583};
584
585struct drm_framebuffer *
586radeon_framebuffer_create(struct drm_device *dev,
587 struct drm_mode_fb_cmd *mode_cmd,
588 struct drm_gem_object *obj)
589{
590 struct radeon_framebuffer *radeon_fb;
591
592 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
593 if (radeon_fb == NULL) {
594 return NULL;
595 }
596 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
597 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
598 radeon_fb->obj = obj;
599 return &radeon_fb->base;
600}
601
602static struct drm_framebuffer *
603radeon_user_framebuffer_create(struct drm_device *dev,
604 struct drm_file *file_priv,
605 struct drm_mode_fb_cmd *mode_cmd)
606{
607 struct drm_gem_object *obj;
608
609 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
610
611 return radeon_framebuffer_create(dev, mode_cmd, obj);
612}
613
614static const struct drm_mode_config_funcs radeon_mode_funcs = {
615 .fb_create = radeon_user_framebuffer_create,
616 .fb_changed = radeonfb_probe,
617};
618
445282db
DA		 619struct drm_prop_enum_list {
620 int type;
621 char *name;
622};
623
624static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
625{ { 0, "driver" },
626 { 1, "bios" },
627};
628
629static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
630{ { TV_STD_NTSC, "ntsc" },
631 { TV_STD_PAL, "pal" },
632 { TV_STD_PAL_M, "pal-m" },
633 { TV_STD_PAL_60, "pal-60" },
634 { TV_STD_NTSC_J, "ntsc-j" },
635 { TV_STD_SCART_PAL, "scart-pal" },
636 { TV_STD_PAL_CN, "pal-cn" },
637 { TV_STD_SECAM, "secam" },
638};
639
640int radeon_modeset_create_props(struct radeon_device *rdev)
641{
642 int i, sz;
643
644 if (rdev->is_atom_bios) {
645 rdev->mode_info.coherent_mode_property =
646 drm_property_create(rdev->ddev,
647 DRM_MODE_PROP_RANGE,
648 "coherent", 2);
649 if (!rdev->mode_info.coherent_mode_property)
650 return -ENOMEM;
651
652 rdev->mode_info.coherent_mode_property->values[0] = 0;
653 rdev->mode_info.coherent_mode_property->values[0] = 1;
654 }
655
656 if (!ASIC_IS_AVIVO(rdev)) {
657 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
658 rdev->mode_info.tmds_pll_property =
659 drm_property_create(rdev->ddev,
660 DRM_MODE_PROP_ENUM,
661 "tmds_pll", sz);
662 for (i = 0; i < sz; i++) {
663 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
664 i,
665 radeon_tmds_pll_enum_list[i].type,
666 radeon_tmds_pll_enum_list[i].name);
667 }
668 }
669
670 rdev->mode_info.load_detect_property =
671 drm_property_create(rdev->ddev,
672 DRM_MODE_PROP_RANGE,
673 "load detection", 2);
674 if (!rdev->mode_info.load_detect_property)
675 return -ENOMEM;
676 rdev->mode_info.load_detect_property->values[0] = 0;
677 rdev->mode_info.load_detect_property->values[0] = 1;
678
679 drm_mode_create_scaling_mode_property(rdev->ddev);
680
681 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
682 rdev->mode_info.tv_std_property =
683 drm_property_create(rdev->ddev,
684 DRM_MODE_PROP_ENUM,
685 "tv standard", sz);
686 for (i = 0; i < sz; i++) {
687 drm_property_add_enum(rdev->mode_info.tv_std_property,
688 i,
689 radeon_tv_std_enum_list[i].type,
690 radeon_tv_std_enum_list[i].name);
691 }
692
693 return 0;
694}
695
771fe6b9
JG		 696int radeon_modeset_init(struct radeon_device *rdev)
697{
698 int num_crtc = 2, i;
699 int ret;
700
701 drm_mode_config_init(rdev->ddev);
702 rdev->mode_info.mode_config_initialized = true;
703
704 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
705
706 if (ASIC_IS_AVIVO(rdev)) {
707 rdev->ddev->mode_config.max_width = 8192;
708 rdev->ddev->mode_config.max_height = 8192;
709 } else {
710 rdev->ddev->mode_config.max_width = 4096;
711 rdev->ddev->mode_config.max_height = 4096;
712 }
713
714 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
715
445282db
DA		 716 ret = radeon_modeset_create_props(rdev);
717 if (ret) {
718 return ret;
719 }
dfee5614
DA		 720
721 if (rdev->flags & RADEON_SINGLE_CRTC)
722 num_crtc = 1;
723
724 /* allocate crtcs */
771fe6b9
JG		 725 for (i = 0; i < num_crtc; i++) {
726 radeon_crtc_init(rdev->ddev, i);
727 }
728
729 /* okay we should have all the bios connectors */
730 ret = radeon_setup_enc_conn(rdev->ddev);
731 if (!ret) {
732 return ret;
733 }
734 drm_helper_initial_config(rdev->ddev);
735 return 0;
736}
737
738void radeon_modeset_fini(struct radeon_device *rdev)
739{
740 if (rdev->mode_info.mode_config_initialized) {
741 drm_mode_config_cleanup(rdev->ddev);
742 rdev->mode_info.mode_config_initialized = false;
743 }
744}
745
c93bb85b
JG		 746bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
747 struct drm_display_mode *mode,
748 struct drm_display_mode *adjusted_mode)
771fe6b9 749{
c93bb85b
JG		 750 struct drm_device *dev = crtc->dev;
751 struct drm_encoder *encoder;
752 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
753 struct radeon_encoder *radeon_encoder;
754 bool first = true;
771fe6b9 755
c93bb85b
JG		 756 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
757 radeon_encoder = to_radeon_encoder(encoder);
758 if (encoder->crtc != crtc)
759 continue;
760 if (first) {
761 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
c93bb85b
JG		 762 memcpy(&radeon_crtc->native_mode,
763 &radeon_encoder->native_mode,
764 sizeof(struct radeon_native_mode));
765 first = false;
766 } else {
767 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
768 /* WARNING: Right now this can't happen but
769 * in the future we need to check that scaling
770 * are consistent accross different encoder
771 * (ie all encoder can work with the same
772 * scaling).
773 */
774 DRM_ERROR("Scaling not consistent accross encoder.\n");
775 return false;
776 }
771fe6b9
JG		 777 }
778 }
c93bb85b
JG		 779 if (radeon_crtc->rmx_type != RMX_OFF) {
780 fixed20_12 a, b;
781 a.full = rfixed_const(crtc->mode.vdisplay);
782 b.full = rfixed_const(radeon_crtc->native_mode.panel_xres);
783 radeon_crtc->vsc.full = rfixed_div(a, b);
784 a.full = rfixed_const(crtc->mode.hdisplay);
785 b.full = rfixed_const(radeon_crtc->native_mode.panel_yres);
786 radeon_crtc->hsc.full = rfixed_div(a, b);
771fe6b9 787 } else {
c93bb85b
JG		 788 radeon_crtc->vsc.full = rfixed_const(1);
789 radeon_crtc->hsc.full = rfixed_const(1);
771fe6b9 790 }
c93bb85b 791 return true;
771fe6b9 792}
Linux kernel - Deliverables
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