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drm/radeon: restructure edid fetching
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
10ebc0bc 33#include <linux/pm_runtime.h>
760285e7
DH		 34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_edid.h>
771fe6b9 36
32167016
CK		 37#include <linux/gcd.h>
38
771fe6b9
JG		 39static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40{
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
d9fdaafb 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
4366f3b5
MK		 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
771fe6b9
JG		 71}
72
fee298fd 73static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 74{
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
78 int i;
79
d9fdaafb 80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90
677d0768
AD		 91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 93
677d0768 94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 95 for (i = 0; i < 256; i++) {
677d0768 96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
100 }
101}
102
fee298fd
AD		 103static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104{
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
108 int i;
109
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
142 }
143
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
163 */
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
166 }
fee298fd
AD		 167}
168
771fe6b9
JG		 169static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int i;
175 uint32_t dac2_cntl;
176
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 else
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183
184 WREG8(RADEON_PALETTE_INDEX, 0);
185 for (i = 0; i < 256; i++) {
186 WREG32(RADEON_PALETTE_30_DATA,
187 (radeon_crtc->lut_r[i] << 20) |
188 (radeon_crtc->lut_g[i] << 10) |
189 (radeon_crtc->lut_b[i] << 0));
190 }
191}
192
193void radeon_crtc_load_lut(struct drm_crtc *crtc)
194{
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197
198 if (!crtc->enabled)
199 return;
200
fee298fd
AD		 201 if (ASIC_IS_DCE5(rdev))
202 dce5_crtc_load_lut(crtc);
203 else if (ASIC_IS_DCE4(rdev))
204 dce4_crtc_load_lut(crtc);
bcc1c2a1 205 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 206 avivo_crtc_load_lut(crtc);
207 else
208 legacy_crtc_load_lut(crtc);
209}
210
b8c00ac5 211/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 212void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
213 u16 blue, int regno)
214{
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216
771fe6b9
JG		 217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
220}
221
b8c00ac5
DA		 222/** Gets the color ramps on behalf of fbcon */
223void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, int regno)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
231}
232
771fe6b9 233static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 234 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 235{
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 237 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 238
b8c00ac5 239 /* userspace palettes are always correct as is */
7203425a 240 for (i = start; i < end; i++) {
b8c00ac5
DA		 241 radeon_crtc->lut_r[i] = red[i] >> 6;
242 radeon_crtc->lut_g[i] = green[i] >> 6;
243 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 244 }
771fe6b9
JG		 245 radeon_crtc_load_lut(crtc);
246}
247
248static void radeon_crtc_destroy(struct drm_crtc *crtc)
249{
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251
771fe6b9 252 drm_crtc_cleanup(crtc);
fa7f517c 253 destroy_workqueue(radeon_crtc->flip_queue);
771fe6b9
JG		 254 kfree(radeon_crtc);
255}
256
fa7f517c
CK		 257/**
258 * radeon_unpin_work_func - unpin old buffer object
259 *
260 * @__work - kernel work item
261 *
262 * Unpin the old frame buffer object outside of the interrupt handler
6f34be50
AD		 263 */
264static void radeon_unpin_work_func(struct work_struct *__work)
265{
fa7f517c
CK		 266 struct radeon_flip_work *work =
267 container_of(__work, struct radeon_flip_work, unpin_work);
6f34be50
AD		 268 int r;
269
270 /* unpin of the old buffer */
271 r = radeon_bo_reserve(work->old_rbo, false);
272 if (likely(r == 0)) {
273 r = radeon_bo_unpin(work->old_rbo);
274 if (unlikely(r != 0)) {
275 DRM_ERROR("failed to unpin buffer after flip\n");
276 }
277 radeon_bo_unreserve(work->old_rbo);
278 } else
279 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 280
281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 282 kfree(work);
283}
284
1a0e7918 285void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
6f34be50
AD		 286{
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
6f34be50
AD		 288 unsigned long flags;
289 u32 update_pending;
290 int vpos, hpos;
291
f5d636d2
CK		 292 /* can happen during initialization */
293 if (radeon_crtc == NULL)
294 return;
6f34be50
AD		 295
296 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
a2b6d3b3
MD		 297 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
298 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
299 "RADEON_FLIP_SUBMITTED(%d)\n",
300 radeon_crtc->flip_status,
301 RADEON_FLIP_SUBMITTED);
6f34be50
AD		 302 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
303 return;
304 }
fa7f517c
CK		 305
306 update_pending = radeon_page_flip_pending(rdev, crtc_id);
6f34be50
AD		 307
308 /* Has the pageflip already completed in crtc, or is it certain
309 * to complete in this vblank?
310 */
311 if (update_pending &&
abca9e45 312 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
d47abc58 313 &vpos, &hpos, NULL, NULL)) &&
81ffbbed
FK		 314 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
315 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
316 /* crtc didn't flip in this target vblank interval,
317 * but flip is pending in crtc. Based on the current
318 * scanout position we know that the current frame is
319 * (nearly) complete and the flip will (likely)
320 * complete before the start of the next frame.
321 */
322 update_pending = 0;
323 }
fa7f517c
CK		 324 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
325 if (!update_pending)
1a0e7918 326 radeon_crtc_handle_flip(rdev, crtc_id);
1a0e7918
CK		 327}
328
329/**
330 * radeon_crtc_handle_flip - page flip completed
331 *
332 * @rdev: radeon device pointer
333 * @crtc_id: crtc number this event is for
334 *
335 * Called when we are sure that a page flip for this crtc is completed.
336 */
337void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
338{
339 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
fa7f517c 340 struct radeon_flip_work *work;
1a0e7918
CK		 341 unsigned long flags;
342
343 /* this can happen at init */
344 if (radeon_crtc == NULL)
345 return;
346
347 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
fa7f517c 348 work = radeon_crtc->flip_work;
a2b6d3b3
MD		 349 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
350 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
351 "RADEON_FLIP_SUBMITTED(%d)\n",
352 radeon_crtc->flip_status,
353 RADEON_FLIP_SUBMITTED);
1a0e7918
CK		 354 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
355 return;
6f34be50
AD		 356 }
357
fa7f517c 358 /* Pageflip completed. Clean up. */
a2b6d3b3 359 radeon_crtc->flip_status = RADEON_FLIP_NONE;
fa7f517c 360 radeon_crtc->flip_work = NULL;
6f34be50
AD		 361
362 /* wakeup userspace */
26ae4667
RC		 363 if (work->event)
364 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
365
6f34be50
AD		 366 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
367
ca721b79 368 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
46889d95 369 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
fa7f517c 370 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
6f34be50
AD		 371}
372
fa7f517c
CK		 373/**
374 * radeon_flip_work_func - page flip framebuffer
375 *
376 * @work - kernel work item
377 *
378 * Wait for the buffer object to become idle and do the actual page flip
379 */
380static void radeon_flip_work_func(struct work_struct *__work)
6f34be50 381{
fa7f517c
CK		 382 struct radeon_flip_work *work =
383 container_of(__work, struct radeon_flip_work, flip_work);
384 struct radeon_device *rdev = work->rdev;
385 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
6f34be50 386
fa7f517c 387 struct drm_crtc *crtc = &radeon_crtc->base;
fa7f517c
CK		 388 unsigned long flags;
389 int r;
9af20792 390
fa7f517c 391 down_read(&rdev->exclusive_lock);
306f98d9 392 if (work->fence) {
fa7f517c
CK		 393 r = radeon_fence_wait(work->fence, false);
394 if (r == -EDEADLK) {
395 up_read(&rdev->exclusive_lock);
396 r = radeon_gpu_reset(rdev);
397 down_read(&rdev->exclusive_lock);
398 }
306f98d9
MD		 399 if (r)
400 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
6f34be50 401
306f98d9
MD		 402 /* We continue with the page flip even if we failed to wait on
403 * the fence, otherwise the DRM core and userspace will be
404 * confused about which BO the CRTC is scanning out
405 */
406
407 radeon_fence_unref(&work->fence);
6f34be50 408 }
6f34be50 409
c60381bd
MD		 410 /* We borrow the event spin lock for protecting flip_status */
411 spin_lock_irqsave(&crtc->dev->event_lock, flags);
412
413 /* set the proper interrupt */
414 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
415
5f87e090
MK		 416 /* do the flip (mmio) */
417 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
418
c60381bd
MD		 419 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
420 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
421 up_read(&rdev->exclusive_lock);
c60381bd
MD		 422}
423
424static int radeon_crtc_page_flip(struct drm_crtc *crtc,
425 struct drm_framebuffer *fb,
426 struct drm_pending_vblank_event *event,
427 uint32_t page_flip_flags)
428{
429 struct drm_device *dev = crtc->dev;
430 struct radeon_device *rdev = dev->dev_private;
431 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
432 struct radeon_framebuffer *old_radeon_fb;
433 struct radeon_framebuffer *new_radeon_fb;
434 struct drm_gem_object *obj;
435 struct radeon_flip_work *work;
436 struct radeon_bo *new_rbo;
437 uint32_t tiling_flags, pitch_pixels;
438 uint64_t base;
439 unsigned long flags;
440 int r;
441
442 work = kzalloc(sizeof *work, GFP_KERNEL);
443 if (work == NULL)
444 return -ENOMEM;
445
446 INIT_WORK(&work->flip_work, radeon_flip_work_func);
447 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
448
449 work->rdev = rdev;
450 work->crtc_id = radeon_crtc->crtc_id;
451 work->event = event;
452
453 /* schedule unpin of the old buffer */
454 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
455 obj = old_radeon_fb->obj;
456
457 /* take a reference to the old object */
458 drm_gem_object_reference(obj);
459 work->old_rbo = gem_to_radeon_bo(obj);
460
461 new_radeon_fb = to_radeon_framebuffer(fb);
462 obj = new_radeon_fb->obj;
463 new_rbo = gem_to_radeon_bo(obj);
464
465 spin_lock(&new_rbo->tbo.bdev->fence_lock);
466 if (new_rbo->tbo.sync_obj)
467 work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj);
468 spin_unlock(&new_rbo->tbo.bdev->fence_lock);
469
6f34be50 470 /* pin the new buffer */
c60381bd
MD		 471 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
472 work->old_rbo, new_rbo);
6f34be50 473
c60381bd 474 r = radeon_bo_reserve(new_rbo, false);
6f34be50
AD		 475 if (unlikely(r != 0)) {
476 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
fa7f517c 477 goto cleanup;
6f34be50 478 }
0349af70 479 /* Only 27 bit offset for legacy CRTC */
c60381bd 480 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
0349af70 481 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50 482 if (unlikely(r != 0)) {
c60381bd 483 radeon_bo_unreserve(new_rbo);
6f34be50
AD		 484 r = -EINVAL;
485 DRM_ERROR("failed to pin new rbo buffer before flip\n");
fa7f517c 486 goto cleanup;
6f34be50 487 }
c60381bd
MD		 488 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
489 radeon_bo_unreserve(new_rbo);
6f34be50
AD		 490
491 if (!ASIC_IS_AVIVO(rdev)) {
492 /* crtc offset is from display base addr not FB location */
493 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 494 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 495
496 if (tiling_flags & RADEON_TILING_MACRO) {
497 if (ASIC_IS_R300(rdev)) {
498 base &= ~0x7ff;
499 } else {
500 int byteshift = fb->bits_per_pixel >> 4;
501 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
502 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
503 }
504 } else {
505 int offset = crtc->y * pitch_pixels + crtc->x;
506 switch (fb->bits_per_pixel) {
507 case 8:
508 default:
509 offset *= 1;
510 break;
511 case 15:
512 case 16:
513 offset *= 2;
514 break;
515 case 24:
516 offset *= 3;
517 break;
518 case 32:
519 offset *= 4;
520 break;
521 }
522 base += offset;
523 }
524 base &= ~7;
525 }
c60381bd 526 work->base = base;
6f34be50 527
ca721b79
MD		 528 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
529 if (r) {
530 DRM_ERROR("failed to get vblank before flip\n");
531 goto pflip_cleanup;
532 }
533
fa7f517c
CK		 534 /* We borrow the event spin lock for protecting flip_work */
535 spin_lock_irqsave(&crtc->dev->event_lock, flags);
b15eb4ea 536
c60381bd
MD		 537 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
538 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
539 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
540 r = -EBUSY;
82648497 541 goto vblank_cleanup;
c60381bd
MD		 542 }
543 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
544 radeon_crtc->flip_work = work;
6f34be50 545
c60381bd
MD		 546 /* update crtc fb */
547 crtc->primary->fb = fb;
fa7f517c
CK		 548
549 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
fa7f517c 550
c60381bd
MD		 551 queue_work(radeon_crtc->flip_queue, &work->flip_work);
552 return 0;
1aab5514 553
82648497
MK		 554vblank_cleanup:
555 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
556
ca721b79 557pflip_cleanup:
c60381bd 558 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
ca721b79
MD		 559 DRM_ERROR("failed to reserve new rbo in error path\n");
560 goto cleanup;
561 }
c60381bd 562 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
ca721b79
MD		 563 DRM_ERROR("failed to unpin new rbo in error path\n");
564 }
c60381bd 565 radeon_bo_unreserve(new_rbo);
ca721b79 566
fa7f517c
CK		 567cleanup:
568 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
fcc485d6 569 radeon_fence_unref(&work->fence);
6f34be50 570 kfree(work);
fa7f517c 571
c60381bd 572 return r;
6f34be50
AD		 573}
574
10ebc0bc
DA		 575static int
576radeon_crtc_set_config(struct drm_mode_set *set)
577{
578 struct drm_device *dev;
579 struct radeon_device *rdev;
580 struct drm_crtc *crtc;
581 bool active = false;
582 int ret;
583
584 if (!set || !set->crtc)
585 return -EINVAL;
586
587 dev = set->crtc->dev;
588
589 ret = pm_runtime_get_sync(dev->dev);
590 if (ret < 0)
591 return ret;
592
593 ret = drm_crtc_helper_set_config(set);
594
595 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
596 if (crtc->enabled)
597 active = true;
598
599 pm_runtime_mark_last_busy(dev->dev);
600
601 rdev = dev->dev_private;
602 /* if we have active crtcs and we don't have a power ref,
603 take the current one */
604 if (active && !rdev->have_disp_power_ref) {
605 rdev->have_disp_power_ref = true;
606 return ret;
607 }
608 /* if we have no active crtcs, then drop the power ref
609 we got before */
610 if (!active && rdev->have_disp_power_ref) {
611 pm_runtime_put_autosuspend(dev->dev);
612 rdev->have_disp_power_ref = false;
613 }
614
615 /* drop the power reference we got coming in here */
616 pm_runtime_put_autosuspend(dev->dev);
617 return ret;
618}
771fe6b9
JG		 619static const struct drm_crtc_funcs radeon_crtc_funcs = {
620 .cursor_set = radeon_crtc_cursor_set,
621 .cursor_move = radeon_crtc_cursor_move,
622 .gamma_set = radeon_crtc_gamma_set,
10ebc0bc 623 .set_config = radeon_crtc_set_config,
771fe6b9 624 .destroy = radeon_crtc_destroy,
6f34be50 625 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 626};
627
628static void radeon_crtc_init(struct drm_device *dev, int index)
629{
630 struct radeon_device *rdev = dev->dev_private;
631 struct radeon_crtc *radeon_crtc;
632 int i;
633
634 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
635 if (radeon_crtc == NULL)
636 return;
637
638 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
639
640 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
641 radeon_crtc->crtc_id = index;
fa7f517c 642 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
c93bb85b 643 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 644
9e05fa1d
AD		 645 if (rdev->family >= CHIP_BONAIRE) {
646 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
647 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
648 } else {
649 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
650 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
651 }
bea61c59
AD		 652 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
653 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
9e05fa1d 654
785b93ef 655#if 0
771fe6b9
JG		 656 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
657 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
658 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 659#endif
771fe6b9
JG		 660
661 for (i = 0; i < 256; i++) {
662 radeon_crtc->lut_r[i] = i << 2;
663 radeon_crtc->lut_g[i] = i << 2;
664 radeon_crtc->lut_b[i] = i << 2;
665 }
666
667 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
668 radeon_atombios_init_crtc(dev, radeon_crtc);
669 else
670 radeon_legacy_init_crtc(dev, radeon_crtc);
671}
672
e68adef8 673static const char *encoder_names[38] = {
771fe6b9
JG		 674 "NONE",
675 "INTERNAL_LVDS",
676 "INTERNAL_TMDS1",
677 "INTERNAL_TMDS2",
678 "INTERNAL_DAC1",
679 "INTERNAL_DAC2",
680 "INTERNAL_SDVOA",
681 "INTERNAL_SDVOB",
682 "SI170B",
683 "CH7303",
684 "CH7301",
685 "INTERNAL_DVO1",
686 "EXTERNAL_SDVOA",
687 "EXTERNAL_SDVOB",
688 "TITFP513",
689 "INTERNAL_LVTM1",
690 "VT1623",
691 "HDMI_SI1930",
692 "HDMI_INTERNAL",
693 "INTERNAL_KLDSCP_TMDS1",
694 "INTERNAL_KLDSCP_DVO1",
695 "INTERNAL_KLDSCP_DAC1",
696 "INTERNAL_KLDSCP_DAC2",
697 "SI178",
698 "MVPU_FPGA",
699 "INTERNAL_DDI",
700 "VT1625",
701 "HDMI_SI1932",
702 "DP_AN9801",
703 "DP_DP501",
704 "INTERNAL_UNIPHY",
705 "INTERNAL_KLDSCP_LVTMA",
706 "INTERNAL_UNIPHY1",
707 "INTERNAL_UNIPHY2",
bf982ebf
AD		 708 "NUTMEG",
709 "TRAVIS",
e68adef8
AD		 710 "INTERNAL_VCE",
711 "INTERNAL_UNIPHY3",
771fe6b9
JG		 712};
713
cbd4623d 714static const char *hpd_names[6] = {
eed45b30
AD		 715 "HPD1",
716 "HPD2",
717 "HPD3",
718 "HPD4",
719 "HPD5",
720 "HPD6",
721};
722
771fe6b9
JG		 723static void radeon_print_display_setup(struct drm_device *dev)
724{
725 struct drm_connector *connector;
726 struct radeon_connector *radeon_connector;
727 struct drm_encoder *encoder;
728 struct radeon_encoder *radeon_encoder;
729 uint32_t devices;
730 int i = 0;
731
732 DRM_INFO("Radeon Display Connectors\n");
733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
734 radeon_connector = to_radeon_connector(connector);
735 DRM_INFO("Connector %d:\n", i);
72082093 736 DRM_INFO(" %s\n", connector->name);
eed45b30
AD		 737 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
738 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 739 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 740 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
741 radeon_connector->ddc_bus->rec.mask_clk_reg,
742 radeon_connector->ddc_bus->rec.mask_data_reg,
743 radeon_connector->ddc_bus->rec.a_clk_reg,
744 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 745 radeon_connector->ddc_bus->rec.en_clk_reg,
746 radeon_connector->ddc_bus->rec.en_data_reg,
747 radeon_connector->ddc_bus->rec.y_clk_reg,
748 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 749 if (radeon_connector->router.ddc_valid)
26b5bc98 750 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 751 radeon_connector->router.ddc_mux_control_pin,
752 radeon_connector->router.ddc_mux_state);
753 if (radeon_connector->router.cd_valid)
754 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
755 radeon_connector->router.cd_mux_control_pin,
756 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 757 } else {
758 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
759 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
760 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
761 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
762 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
763 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
764 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
765 }
771fe6b9
JG		 766 DRM_INFO(" Encoders:\n");
767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
768 radeon_encoder = to_radeon_encoder(encoder);
769 devices = radeon_encoder->devices & radeon_connector->devices;
770 if (devices) {
771 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
772 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
773 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
774 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
775 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
776 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
777 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
778 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
779 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
780 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
781 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
782 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
783 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
784 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
785 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
786 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 787 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
788 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 789 if (devices & ATOM_DEVICE_TV1_SUPPORT)
790 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
791 if (devices & ATOM_DEVICE_CV_SUPPORT)
792 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
793 }
794 }
795 i++;
796 }
797}
798
4ce001ab 799static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 800{
801 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 802 bool ret = false;
803
804 if (rdev->bios) {
805 if (rdev->is_atom_bios) {
a084e6ee
AD		 806 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
807 if (ret == false)
771fe6b9 808 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 809 } else {
771fe6b9 810 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 811 if (ret == false)
812 ret = radeon_get_legacy_connector_info_from_table(dev);
813 }
771fe6b9
JG		 814 } else {
815 if (!ASIC_IS_AVIVO(rdev))
816 ret = radeon_get_legacy_connector_info_from_table(dev);
817 }
818 if (ret) {
1f3b6a45 819 radeon_setup_encoder_clones(dev);
771fe6b9 820 radeon_print_display_setup(dev);
771fe6b9
JG		 821 }
822
823 return ret;
824}
825
f523f74e 826/* avivo */
f523f74e 827
32167016
CK		 828/**
829 * avivo_reduce_ratio - fractional number reduction
830 *
831 * @nom: nominator
832 * @den: denominator
833 * @nom_min: minimum value for nominator
834 * @den_min: minimum value for denominator
835 *
836 * Find the greatest common divisor and apply it on both nominator and
837 * denominator, but make nominator and denominator are at least as large
838 * as their minimum values.
839 */
840static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
841 unsigned nom_min, unsigned den_min)
f523f74e 842{
32167016
CK		 843 unsigned tmp;
844
845 /* reduce the numbers to a simpler ratio */
846 tmp = gcd(*nom, *den);
847 *nom /= tmp;
848 *den /= tmp;
849
850 /* make sure nominator is large enough */
851 if (*nom < nom_min) {
3b333c55 852 tmp = DIV_ROUND_UP(nom_min, *nom);
32167016
CK		 853 *nom *= tmp;
854 *den *= tmp;
f523f74e
AD		 855 }
856
32167016
CK		 857 /* make sure the denominator is large enough */
858 if (*den < den_min) {
3b333c55 859 tmp = DIV_ROUND_UP(den_min, *den);
32167016
CK		 860 *nom *= tmp;
861 *den *= tmp;
f523f74e 862 }
f523f74e
AD		 863}
864
c2fb3094
CK		 865/**
866 * avivo_get_fb_ref_div - feedback and ref divider calculation
867 *
868 * @nom: nominator
869 * @den: denominator
870 * @post_div: post divider
871 * @fb_div_max: feedback divider maximum
872 * @ref_div_max: reference divider maximum
873 * @fb_div: resulting feedback divider
874 * @ref_div: resulting reference divider
875 *
876 * Calculate feedback and reference divider for a given post divider. Makes
877 * sure we stay within the limits.
878 */
879static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
880 unsigned fb_div_max, unsigned ref_div_max,
881 unsigned *fb_div, unsigned *ref_div)
882{
883 /* limit reference * post divider to a maximum */
4b21ce1b 884 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
c2fb3094
CK		 885
886 /* get matching reference and feedback divider */
887 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
888 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
889
890 /* limit fb divider to its maximum */
891 if (*fb_div > fb_div_max) {
892 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
893 *fb_div = fb_div_max;
894 }
895}
896
32167016
CK		 897/**
898 * radeon_compute_pll_avivo - compute PLL paramaters
899 *
900 * @pll: information about the PLL
901 * @dot_clock_p: resulting pixel clock
902 * fb_div_p: resulting feedback divider
903 * frac_fb_div_p: fractional part of the feedback divider
904 * ref_div_p: resulting reference divider
905 * post_div_p: resulting reference divider
906 *
907 * Try to calculate the PLL parameters to generate the given frequency:
908 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
909 */
f523f74e
AD		 910void radeon_compute_pll_avivo(struct radeon_pll *pll,
911 u32 freq,
912 u32 *dot_clock_p,
913 u32 *fb_div_p,
914 u32 *frac_fb_div_p,
915 u32 *ref_div_p,
916 u32 *post_div_p)
917{
c2fb3094
CK		 918 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
919 freq : freq / 10;
920
32167016
CK		 921 unsigned fb_div_min, fb_div_max, fb_div;
922 unsigned post_div_min, post_div_max, post_div;
923 unsigned ref_div_min, ref_div_max, ref_div;
924 unsigned post_div_best, diff_best;
f8a2645e 925 unsigned nom, den;
f523f74e 926
32167016
CK		 927 /* determine allowed feedback divider range */
928 fb_div_min = pll->min_feedback_div;
929 fb_div_max = pll->max_feedback_div;
f523f74e
AD		 930
931 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
32167016
CK		 932 fb_div_min *= 10;
933 fb_div_max *= 10;
934 }
935
936 /* determine allowed ref divider range */
937 if (pll->flags & RADEON_PLL_USE_REF_DIV)
938 ref_div_min = pll->reference_div;
939 else
940 ref_div_min = pll->min_ref_div;
24315814
CK		 941
942 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
943 pll->flags & RADEON_PLL_USE_REF_DIV)
944 ref_div_max = pll->reference_div;
945 else
946 ref_div_max = pll->max_ref_div;
32167016
CK		 947
948 /* determine allowed post divider range */
949 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
950 post_div_min = pll->post_div;
951 post_div_max = pll->post_div;
952 } else {
32167016
CK		 953 unsigned vco_min, vco_max;
954
955 if (pll->flags & RADEON_PLL_IS_LCD) {
956 vco_min = pll->lcd_pll_out_min;
957 vco_max = pll->lcd_pll_out_max;
958 } else {
959 vco_min = pll->pll_out_min;
960 vco_max = pll->pll_out_max;
f523f74e 961 }
32167016 962
c2fb3094
CK		 963 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
964 vco_min *= 10;
965 vco_max *= 10;
966 }
967
32167016
CK		 968 post_div_min = vco_min / target_clock;
969 if ((target_clock * post_div_min) < vco_min)
970 ++post_div_min;
971 if (post_div_min < pll->min_post_div)
972 post_div_min = pll->min_post_div;
973
974 post_div_max = vco_max / target_clock;
975 if ((target_clock * post_div_max) > vco_max)
976 --post_div_max;
977 if (post_div_max > pll->max_post_div)
978 post_div_max = pll->max_post_div;
979 }
980
981 /* represent the searched ratio as fractional number */
c2fb3094 982 nom = target_clock;
32167016
CK		 983 den = pll->reference_freq;
984
985 /* reduce the numbers to a simpler ratio */
986 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
987
988 /* now search for a post divider */
989 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
990 post_div_best = post_div_min;
991 else
992 post_div_best = post_div_max;
993 diff_best = ~0;
994
995 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
c2fb3094
CK		 996 unsigned diff;
997 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
998 ref_div_max, &fb_div, &ref_div);
999 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1000 (ref_div * post_div));
1001
32167016
CK		 1002 if (diff < diff_best || (diff == diff_best &&
1003 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1004
1005 post_div_best = post_div;
1006 diff_best = diff;
f523f74e 1007 }
32167016
CK		 1008 }
1009 post_div = post_div_best;
1010
c2fb3094
CK		 1011 /* get the feedback and reference divider for the optimal value */
1012 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1013 &fb_div, &ref_div);
32167016
CK		 1014
1015 /* reduce the numbers to a simpler ratio once more */
1016 /* this also makes sure that the reference divider is large enough */
1017 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1018
3b333c55
CK		 1019 /* avoid high jitter with small fractional dividers */
1020 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
74ad54f2 1021 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
3b333c55
CK		 1022 if (fb_div < fb_div_min) {
1023 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1024 fb_div *= tmp;
1025 ref_div *= tmp;
1026 }
1027 }
1028
32167016
CK		 1029 /* and finally save the result */
1030 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1031 *fb_div_p = fb_div / 10;
1032 *frac_fb_div_p = fb_div % 10;
f523f74e 1033 } else {
32167016
CK		 1034 *fb_div_p = fb_div;
1035 *frac_fb_div_p = 0;
f523f74e
AD		 1036 }
1037
32167016
CK		 1038 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1039 (pll->reference_freq * *frac_fb_div_p)) /
1040 (ref_div * post_div * 10);
f523f74e
AD		 1041 *ref_div_p = ref_div;
1042 *post_div_p = post_div;
32167016
CK		 1043
1044 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
c2fb3094 1045 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
32167016 1046 ref_div, post_div);
f523f74e
AD		 1047}
1048
1049/* pre-avivo */
771fe6b9
JG		 1050static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1051{
1052 uint64_t mod;
1053
1054 n += d / 2;
1055
1056 mod = do_div(n, d);
1057 return n;
1058}
1059
f523f74e
AD		 1060void radeon_compute_pll_legacy(struct radeon_pll *pll,
1061 uint64_t freq,
1062 uint32_t *dot_clock_p,
1063 uint32_t *fb_div_p,
1064 uint32_t *frac_fb_div_p,
1065 uint32_t *ref_div_p,
1066 uint32_t *post_div_p)
771fe6b9
JG		 1067{
1068 uint32_t min_ref_div = pll->min_ref_div;
1069 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 1070 uint32_t min_post_div = pll->min_post_div;
1071 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 1072 uint32_t min_fractional_feed_div = 0;
1073 uint32_t max_fractional_feed_div = 0;
1074 uint32_t best_vco = pll->best_vco;
1075 uint32_t best_post_div = 1;
1076 uint32_t best_ref_div = 1;
1077 uint32_t best_feedback_div = 1;
1078 uint32_t best_frac_feedback_div = 0;
1079 uint32_t best_freq = -1;
1080 uint32_t best_error = 0xffffffff;
1081 uint32_t best_vco_diff = 1;
1082 uint32_t post_div;
86cb2bbf 1083 u32 pll_out_min, pll_out_max;
771fe6b9 1084
d9fdaafb 1085 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 1086 freq = freq * 1000;
1087
86cb2bbf
AD		 1088 if (pll->flags & RADEON_PLL_IS_LCD) {
1089 pll_out_min = pll->lcd_pll_out_min;
1090 pll_out_max = pll->lcd_pll_out_max;
1091 } else {
1092 pll_out_min = pll->pll_out_min;
1093 pll_out_max = pll->pll_out_max;
1094 }
1095
619efb10
AD		 1096 if (pll_out_min > 64800)
1097 pll_out_min = 64800;
1098
fc10332b 1099 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 1100 min_ref_div = max_ref_div = pll->reference_div;
1101 else {
1102 while (min_ref_div < max_ref_div-1) {
1103 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1104 uint32_t pll_in = pll->reference_freq / mid;
1105 if (pll_in < pll->pll_in_min)
1106 max_ref_div = mid;
1107 else if (pll_in > pll->pll_in_max)
1108 min_ref_div = mid;
1109 else
1110 break;
1111 }
1112 }
1113
fc10332b
AD		 1114 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1115 min_post_div = max_post_div = pll->post_div;
1116
1117 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 1118 min_fractional_feed_div = pll->min_frac_feedback_div;
1119 max_fractional_feed_div = pll->max_frac_feedback_div;
1120 }
1121
bd6a60af 1122 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 1123 uint32_t ref_div;
1124
fc10332b 1125 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 1126 continue;
1127
1128 /* legacy radeons only have a few post_divs */
fc10332b 1129 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 1130 if ((post_div == 5) ||
1131 (post_div == 7) ||
1132 (post_div == 9) ||
1133 (post_div == 10) ||
1134 (post_div == 11) ||
1135 (post_div == 13) ||
1136 (post_div == 14) ||
1137 (post_div == 15))
1138 continue;
1139 }
1140
1141 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1142 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1143 uint32_t pll_in = pll->reference_freq / ref_div;
1144 uint32_t min_feed_div = pll->min_feedback_div;
1145 uint32_t max_feed_div = pll->max_feedback_div + 1;
1146
1147 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1148 continue;
1149
1150 while (min_feed_div < max_feed_div) {
1151 uint32_t vco;
1152 uint32_t min_frac_feed_div = min_fractional_feed_div;
1153 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1154 uint32_t frac_feedback_div;
1155 uint64_t tmp;
1156
1157 feedback_div = (min_feed_div + max_feed_div) / 2;
1158
1159 tmp = (uint64_t)pll->reference_freq * feedback_div;
1160 vco = radeon_div(tmp, ref_div);
1161
86cb2bbf 1162 if (vco < pll_out_min) {
771fe6b9
JG		 1163 min_feed_div = feedback_div + 1;
1164 continue;
86cb2bbf 1165 } else if (vco > pll_out_max) {
771fe6b9
JG		 1166 max_feed_div = feedback_div;
1167 continue;
1168 }
1169
1170 while (min_frac_feed_div < max_frac_feed_div) {
1171 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1172 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1173 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1174 current_freq = radeon_div(tmp, ref_div * post_div);
1175
fc10332b 1176 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 1177 if (freq < current_freq)
1178 error = 0xffffffff;
1179 else
1180 error = freq - current_freq;
d0e275a9
AD		 1181 } else
1182 error = abs(current_freq - freq);
771fe6b9
JG		 1183 vco_diff = abs(vco - best_vco);
1184
1185 if ((best_vco == 0 && error < best_error) ||
1186 (best_vco != 0 &&
167ffc44 1187 ((best_error > 100 && error < best_error - 100) ||
5480f727 1188 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1189 best_post_div = post_div;
1190 best_ref_div = ref_div;
1191 best_feedback_div = feedback_div;
1192 best_frac_feedback_div = frac_feedback_div;
1193 best_freq = current_freq;
1194 best_error = error;
1195 best_vco_diff = vco_diff;
5480f727
DA		 1196 } else if (current_freq == freq) {
1197 if (best_freq == -1) {
1198 best_post_div = post_div;
1199 best_ref_div = ref_div;
1200 best_feedback_div = feedback_div;
1201 best_frac_feedback_div = frac_feedback_div;
1202 best_freq = current_freq;
1203 best_error = error;
1204 best_vco_diff = vco_diff;
1205 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1206 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1207 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1208 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1209 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1210 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1211 best_post_div = post_div;
1212 best_ref_div = ref_div;
1213 best_feedback_div = feedback_div;
1214 best_frac_feedback_div = frac_feedback_div;
1215 best_freq = current_freq;
1216 best_error = error;
1217 best_vco_diff = vco_diff;
1218 }
771fe6b9
JG		 1219 }
1220 if (current_freq < freq)
1221 min_frac_feed_div = frac_feedback_div + 1;
1222 else
1223 max_frac_feed_div = frac_feedback_div;
1224 }
1225 if (current_freq < freq)
1226 min_feed_div = feedback_div + 1;
1227 else
1228 max_feed_div = feedback_div;
1229 }
1230 }
1231 }
1232
1233 *dot_clock_p = best_freq / 10000;
1234 *fb_div_p = best_feedback_div;
1235 *frac_fb_div_p = best_frac_feedback_div;
1236 *ref_div_p = best_ref_div;
1237 *post_div_p = best_post_div;
bbb0aef5
JP		 1238 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1239 (long long)freq,
1240 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1241 best_ref_div, best_post_div);
1242
771fe6b9
JG		 1243}
1244
1245static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1246{
1247 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1248
29d08b3e 1249 if (radeon_fb->obj) {
bc9025bd 1250 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1251 }
771fe6b9
JG		 1252 drm_framebuffer_cleanup(fb);
1253 kfree(radeon_fb);
1254}
1255
1256static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1257 struct drm_file *file_priv,
1258 unsigned int *handle)
1259{
1260 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1261
1262 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1263}
1264
1265static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1266 .destroy = radeon_user_framebuffer_destroy,
1267 .create_handle = radeon_user_framebuffer_create_handle,
1268};
1269
aaefcd42 1270int
38651674
DA		 1271radeon_framebuffer_init(struct drm_device *dev,
1272 struct radeon_framebuffer *rfb,
308e5bcb 1273 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1274 struct drm_gem_object *obj)
771fe6b9 1275{
aaefcd42 1276 int ret;
38651674 1277 rfb->obj = obj;
c7d73f6a 1278 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1279 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1280 if (ret) {
1281 rfb->obj = NULL;
1282 return ret;
1283 }
aaefcd42 1284 return 0;
771fe6b9
JG		 1285}
1286
1287static struct drm_framebuffer *
1288radeon_user_framebuffer_create(struct drm_device *dev,
1289 struct drm_file *file_priv,
308e5bcb 1290 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1291{
1292 struct drm_gem_object *obj;
38651674 1293 struct radeon_framebuffer *radeon_fb;
aaefcd42 1294 int ret;
771fe6b9 1295
308e5bcb 1296 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1297 if (obj == NULL) {
1298 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1299 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1300 return ERR_PTR(-ENOENT);
7e71c9e2 1301 }
38651674
DA		 1302
1303 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1304 if (radeon_fb == NULL) {
1305 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1306 return ERR_PTR(-ENOMEM);
f2d68cf4 1307 }
38651674 1308
aaefcd42
DA		 1309 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1310 if (ret) {
1311 kfree(radeon_fb);
1312 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1313 return ERR_PTR(ret);
aaefcd42 1314 }
38651674
DA		 1315
1316 return &radeon_fb->base;
771fe6b9
JG		 1317}
1318
eb1f8e4f
DA		 1319static void radeon_output_poll_changed(struct drm_device *dev)
1320{
1321 struct radeon_device *rdev = dev->dev_private;
1322 radeon_fb_output_poll_changed(rdev);
1323}
1324
771fe6b9
JG		 1325static const struct drm_mode_config_funcs radeon_mode_funcs = {
1326 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1327 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1328};
1329
445282db
DA		 1330static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1331{ { 0, "driver" },
1332 { 1, "bios" },
1333};
1334
1335static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1336{ { TV_STD_NTSC, "ntsc" },
1337 { TV_STD_PAL, "pal" },
1338 { TV_STD_PAL_M, "pal-m" },
1339 { TV_STD_PAL_60, "pal-60" },
1340 { TV_STD_NTSC_J, "ntsc-j" },
1341 { TV_STD_SCART_PAL, "scart-pal" },
1342 { TV_STD_PAL_CN, "pal-cn" },
1343 { TV_STD_SECAM, "secam" },
1344};
1345
5b1714d3
AD		 1346static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1347{ { UNDERSCAN_OFF, "off" },
1348 { UNDERSCAN_ON, "on" },
1349 { UNDERSCAN_AUTO, "auto" },
1350};
1351
8666c076
AD		 1352static struct drm_prop_enum_list radeon_audio_enum_list[] =
1353{ { RADEON_AUDIO_DISABLE, "off" },
1354 { RADEON_AUDIO_ENABLE, "on" },
1355 { RADEON_AUDIO_AUTO, "auto" },
1356};
1357
6214bb74
AD		 1358/* XXX support different dither options? spatial, temporal, both, etc. */
1359static struct drm_prop_enum_list radeon_dither_enum_list[] =
1360{ { RADEON_FMT_DITHER_DISABLE, "off" },
1361 { RADEON_FMT_DITHER_ENABLE, "on" },
1362};
1363
d79766fa 1364static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1365{
4a67d391 1366 int sz;
445282db
DA		 1367
1368 if (rdev->is_atom_bios) {
1369 rdev->mode_info.coherent_mode_property =
d9bc3c02 1370 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1371 if (!rdev->mode_info.coherent_mode_property)
1372 return -ENOMEM;
445282db
DA		 1373 }
1374
1375 if (!ASIC_IS_AVIVO(rdev)) {
1376 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1377 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1378 drm_property_create_enum(rdev->ddev, 0,
1379 "tmds_pll",
1380 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1381 }
1382
1383 rdev->mode_info.load_detect_property =
d9bc3c02 1384 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1385 if (!rdev->mode_info.load_detect_property)
1386 return -ENOMEM;
445282db
DA		 1387
1388 drm_mode_create_scaling_mode_property(rdev->ddev);
1389
1390 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1391 rdev->mode_info.tv_std_property =
4a67d391
SH		 1392 drm_property_create_enum(rdev->ddev, 0,
1393 "tv standard",
1394 radeon_tv_std_enum_list, sz);
445282db 1395
5b1714d3
AD		 1396 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1397 rdev->mode_info.underscan_property =
4a67d391
SH		 1398 drm_property_create_enum(rdev->ddev, 0,
1399 "underscan",
1400 radeon_underscan_enum_list, sz);
5b1714d3 1401
5bccf5e3 1402 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1403 drm_property_create_range(rdev->ddev, 0,
1404 "underscan hborder", 0, 128);
5bccf5e3
MG		 1405 if (!rdev->mode_info.underscan_hborder_property)
1406 return -ENOMEM;
5bccf5e3
MG		 1407
1408 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1409 drm_property_create_range(rdev->ddev, 0,
1410 "underscan vborder", 0, 128);
5bccf5e3
MG		 1411 if (!rdev->mode_info.underscan_vborder_property)
1412 return -ENOMEM;
5bccf5e3 1413
8666c076
AD		 1414 sz = ARRAY_SIZE(radeon_audio_enum_list);
1415 rdev->mode_info.audio_property =
1416 drm_property_create_enum(rdev->ddev, 0,
1417 "audio",
1418 radeon_audio_enum_list, sz);
1419
6214bb74
AD		 1420 sz = ARRAY_SIZE(radeon_dither_enum_list);
1421 rdev->mode_info.dither_property =
1422 drm_property_create_enum(rdev->ddev, 0,
1423 "dither",
1424 radeon_dither_enum_list, sz);
1425
445282db
DA		 1426 return 0;
1427}
1428
f46c0120
AD		 1429void radeon_update_display_priority(struct radeon_device *rdev)
1430{
1431 /* adjustment options for the display watermarks */
1432 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1433 /* set display priority to high for r3xx, rv515 chips
1434 * this avoids flickering due to underflow to the
1435 * display controllers during heavy acceleration.
45737447
AD		 1436 * Don't force high on rs4xx igp chips as it seems to
1437 * affect the sound card. See kernel bug 15982.
f46c0120 1438 */
45737447
AD		 1439 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1440 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1441 rdev->disp_priority = 2;
1442 else
1443 rdev->disp_priority = 0;
1444 } else
1445 rdev->disp_priority = radeon_disp_priority;
1446
1447}
1448
0783986a
AD		 1449/*
1450 * Allocate hdmi structs and determine register offsets
1451 */
1452static void radeon_afmt_init(struct radeon_device *rdev)
1453{
1454 int i;
1455
1456 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1457 rdev->mode_info.afmt[i] = NULL;
1458
b530602f
AD		 1459 if (ASIC_IS_NODCE(rdev)) {
1460 /* nothing to do */
0783986a 1461 } else if (ASIC_IS_DCE4(rdev)) {
a4d39e68
RM		 1462 static uint32_t eg_offsets[] = {
1463 EVERGREEN_CRTC0_REGISTER_OFFSET,
1464 EVERGREEN_CRTC1_REGISTER_OFFSET,
1465 EVERGREEN_CRTC2_REGISTER_OFFSET,
1466 EVERGREEN_CRTC3_REGISTER_OFFSET,
1467 EVERGREEN_CRTC4_REGISTER_OFFSET,
1468 EVERGREEN_CRTC5_REGISTER_OFFSET,
b530602f 1469 0x13830 - 0x7030,
a4d39e68
RM		 1470 };
1471 int num_afmt;
1472
b530602f
AD		 1473 /* DCE8 has 7 audio blocks tied to DIG encoders */
1474 /* DCE6 has 6 audio blocks tied to DIG encoders */
0783986a
AD		 1475 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1476 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
b530602f
AD		 1477 if (ASIC_IS_DCE8(rdev))
1478 num_afmt = 7;
1479 else if (ASIC_IS_DCE6(rdev))
1480 num_afmt = 6;
1481 else if (ASIC_IS_DCE5(rdev))
a4d39e68
RM		 1482 num_afmt = 6;
1483 else if (ASIC_IS_DCE41(rdev))
1484 num_afmt = 2;
1485 else /* DCE4 */
1486 num_afmt = 6;
1487
1488 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1489 for (i = 0; i < num_afmt; i++) {
1490 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1491 if (rdev->mode_info.afmt[i]) {
1492 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1493 rdev->mode_info.afmt[i]->id = i;
0783986a
AD		 1494 }
1495 }
1496 } else if (ASIC_IS_DCE3(rdev)) {
1497 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1498 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1499 if (rdev->mode_info.afmt[0]) {
1500 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1501 rdev->mode_info.afmt[0]->id = 0;
1502 }
1503 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1504 if (rdev->mode_info.afmt[1]) {
1505 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1506 rdev->mode_info.afmt[1]->id = 1;
1507 }
1508 } else if (ASIC_IS_DCE2(rdev)) {
1509 /* DCE2 has at least 1 routable audio block */
1510 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1511 if (rdev->mode_info.afmt[0]) {
1512 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1513 rdev->mode_info.afmt[0]->id = 0;
1514 }
1515 /* r6xx has 2 routable audio blocks */
1516 if (rdev->family >= CHIP_R600) {
1517 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1518 if (rdev->mode_info.afmt[1]) {
1519 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1520 rdev->mode_info.afmt[1]->id = 1;
1521 }
1522 }
1523 }
1524}
1525
1526static void radeon_afmt_fini(struct radeon_device *rdev)
1527{
1528 int i;
1529
1530 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1531 kfree(rdev->mode_info.afmt[i]);
1532 rdev->mode_info.afmt[i] = NULL;
1533 }
1534}
1535
771fe6b9
JG		 1536int radeon_modeset_init(struct radeon_device *rdev)
1537{
18917b60 1538 int i;
771fe6b9
JG		 1539 int ret;
1540
1541 drm_mode_config_init(rdev->ddev);
1542 rdev->mode_info.mode_config_initialized = true;
1543
e6ecefaa 1544 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1545
881dd74e
AD		 1546 if (ASIC_IS_DCE5(rdev)) {
1547 rdev->ddev->mode_config.max_width = 16384;
1548 rdev->ddev->mode_config.max_height = 16384;
1549 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1550 rdev->ddev->mode_config.max_width = 8192;
1551 rdev->ddev->mode_config.max_height = 8192;
1552 } else {
1553 rdev->ddev->mode_config.max_width = 4096;
1554 rdev->ddev->mode_config.max_height = 4096;
1555 }
1556
019d96cb
DA		 1557 rdev->ddev->mode_config.preferred_depth = 24;
1558 rdev->ddev->mode_config.prefer_shadow = 1;
1559
771fe6b9
JG		 1560 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1561
445282db
DA		 1562 ret = radeon_modeset_create_props(rdev);
1563 if (ret) {
1564 return ret;
1565 }
dfee5614 1566
f376b94f
AD		 1567 /* init i2c buses */
1568 radeon_i2c_init(rdev);
1569
3c537889
AD		 1570 /* check combios for a valid hardcoded EDID - Sun servers */
1571 if (!rdev->is_atom_bios) {
1572 /* check for hardcoded EDID in BIOS */
1573 radeon_combios_check_hardcoded_edid(rdev);
1574 }
1575
dfee5614 1576 /* allocate crtcs */
18917b60 1577 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1578 radeon_crtc_init(rdev->ddev, i);
1579 }
1580
1581 /* okay we should have all the bios connectors */
1582 ret = radeon_setup_enc_conn(rdev->ddev);
1583 if (!ret) {
1584 return ret;
1585 }
ac89af1e 1586
3fa47d9e
AD		 1587 /* init dig PHYs, disp eng pll */
1588 if (rdev->is_atom_bios) {
ac89af1e 1589 radeon_atom_encoder_init(rdev);
f3f1f03e 1590 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1591 }
ac89af1e 1592
d4877cf2
AD		 1593 /* initialize hpd */
1594 radeon_hpd_init(rdev);
38651674 1595
0783986a
AD		 1596 /* setup afmt */
1597 radeon_afmt_init(rdev);
1598
38651674 1599 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1600 drm_kms_helper_poll_init(rdev->ddev);
1601
6c7bccea
AD		 1602 if (rdev->pm.dpm_enabled) {
1603 /* do dpm late init */
1604 ret = radeon_pm_late_init(rdev);
1605 if (ret) {
1606 rdev->pm.dpm_enabled = false;
1607 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1608 }
1609 /* set the dpm state for PX since there won't be
1610 * a modeset to call this.
1611 */
1612 radeon_pm_compute_clocks(rdev);
1613 }
1614
771fe6b9
JG		 1615 return 0;
1616}
1617
1618void radeon_modeset_fini(struct radeon_device *rdev)
1619{
38651674 1620 radeon_fbdev_fini(rdev);
3c537889
AD		 1621 kfree(rdev->mode_info.bios_hardcoded_edid);
1622
771fe6b9 1623 if (rdev->mode_info.mode_config_initialized) {
0783986a 1624 radeon_afmt_fini(rdev);
eb1f8e4f 1625 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1626 radeon_hpd_fini(rdev);
771fe6b9
JG		 1627 drm_mode_config_cleanup(rdev->ddev);
1628 rdev->mode_info.mode_config_initialized = false;
1629 }
f376b94f
AD		 1630 /* free i2c buses */
1631 radeon_i2c_fini(rdev);
771fe6b9
JG		 1632}
1633
e811f5ae 1634static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1635{
1636 /* try and guess if this is a tv or a monitor */
1637 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1638 (mode->vdisplay == 576) || /* 576p */
1639 (mode->vdisplay == 720) || /* 720p */
1640 (mode->vdisplay == 1080)) /* 1080p */
1641 return true;
1642 else
1643 return false;
1644}
1645
c93bb85b 1646bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1647 const struct drm_display_mode *mode,
c93bb85b 1648 struct drm_display_mode *adjusted_mode)
771fe6b9 1649{
c93bb85b 1650 struct drm_device *dev = crtc->dev;
5b1714d3 1651 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1652 struct drm_encoder *encoder;
1653 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1654 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1655 struct drm_connector *connector;
1656 struct radeon_connector *radeon_connector;
c93bb85b 1657 bool first = true;
d65d65b1
AD		 1658 u32 src_v = 1, dst_v = 1;
1659 u32 src_h = 1, dst_h = 1;
771fe6b9 1660
5b1714d3
AD		 1661 radeon_crtc->h_border = 0;
1662 radeon_crtc->v_border = 0;
1663
c93bb85b 1664 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1665 if (encoder->crtc != crtc)
1666 continue;
d65d65b1 1667 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1668 connector = radeon_get_connector_for_encoder(encoder);
1669 radeon_connector = to_radeon_connector(connector);
1670
c93bb85b 1671 if (first) {
80297e87
AD		 1672 /* set scaling */
1673 if (radeon_encoder->rmx_type == RMX_OFF)
1674 radeon_crtc->rmx_type = RMX_OFF;
1675 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1676 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1677 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1678 else
1679 radeon_crtc->rmx_type = RMX_OFF;
1680 /* copy native mode */
c93bb85b 1681 memcpy(&radeon_crtc->native_mode,
80297e87 1682 &radeon_encoder->native_mode,
de2103e4 1683 sizeof(struct drm_display_mode));
ff32a59d
AD		 1684 src_v = crtc->mode.vdisplay;
1685 dst_v = radeon_crtc->native_mode.vdisplay;
1686 src_h = crtc->mode.hdisplay;
1687 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1688
1689 /* fix up for overscan on hdmi */
1690 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1691 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1692 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1693 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1694 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1695 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1696 if (radeon_encoder->underscan_hborder != 0)
1697 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1698 else
1699 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1700 if (radeon_encoder->underscan_vborder != 0)
1701 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1702 else
1703 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1704 radeon_crtc->rmx_type = RMX_FULL;
1705 src_v = crtc->mode.vdisplay;
1706 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1707 src_h = crtc->mode.hdisplay;
1708 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1709 }
c93bb85b
JG		 1710 first = false;
1711 } else {
1712 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1713 /* WARNING: Right now this can't happen but
1714 * in the future we need to check that scaling
d65d65b1 1715 * are consistent across different encoder
c93bb85b
JG		 1716 * (ie all encoder can work with the same
1717 * scaling).
1718 */
d65d65b1 1719 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1720 return false;
1721 }
771fe6b9
JG		 1722 }
1723 }
c93bb85b
JG		 1724 if (radeon_crtc->rmx_type != RMX_OFF) {
1725 fixed20_12 a, b;
d65d65b1
AD		 1726 a.full = dfixed_const(src_v);
1727 b.full = dfixed_const(dst_v);
68adac5e 1728 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1729 a.full = dfixed_const(src_h);
1730 b.full = dfixed_const(dst_h);
68adac5e 1731 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1732 } else {
68adac5e
BS		 1733 radeon_crtc->vsc.full = dfixed_const(1);
1734 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1735 }
c93bb85b 1736 return true;
771fe6b9 1737}
6383cf7d
MK		 1738
1739/*
d47abc58
MK		 1740 * Retrieve current video scanout position of crtc on a given gpu, and
1741 * an optional accurate timestamp of when query happened.
6383cf7d 1742 *
f5a80209 1743 * \param dev Device to query.
6383cf7d 1744 * \param crtc Crtc to query.
abca9e45 1745 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
6383cf7d
MK		 1746 * \param *vpos Location where vertical scanout position should be stored.
1747 * \param *hpos Location where horizontal scanout position should go.
d47abc58
MK		 1748 * \param *stime Target location for timestamp taken immediately before
1749 * scanout position query. Can be NULL to skip timestamp.
1750 * \param *etime Target location for timestamp taken immediately after
1751 * scanout position query. Can be NULL to skip timestamp.
6383cf7d
MK		 1752 *
1753 * Returns vpos as a positive number while in active scanout area.
1754 * Returns vpos as a negative number inside vblank, counting the number
1755 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1756 * until start of active scanout / end of vblank."
1757 *
1758 * \return Flags, or'ed together as follows:
1759 *
25985edc 1760 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1761 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1762 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1763 * this flag means that returned position may be offset by a constant but
1764 * unknown small number of scanlines wrt. real scanout position.
1765 *
1766 */
abca9e45
VS		 1767int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1768 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
6383cf7d
MK		 1769{
1770 u32 stat_crtc = 0, vbl = 0, position = 0;
1771 int vbl_start, vbl_end, vtotal, ret = 0;
1772 bool in_vbl = true;
1773
f5a80209
MK		 1774 struct radeon_device *rdev = dev->dev_private;
1775
d47abc58
MK		 1776 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1777
1778 /* Get optional system timestamp before query. */
1779 if (stime)
1780 *stime = ktime_get();
1781
6383cf7d
MK		 1782 if (ASIC_IS_DCE4(rdev)) {
1783 if (crtc == 0) {
1784 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1785 EVERGREEN_CRTC0_REGISTER_OFFSET);
1786 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1787 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1788 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1789 }
1790 if (crtc == 1) {
1791 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1792 EVERGREEN_CRTC1_REGISTER_OFFSET);
1793 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1794 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1795 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1796 }
1797 if (crtc == 2) {
1798 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1799 EVERGREEN_CRTC2_REGISTER_OFFSET);
1800 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1801 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1802 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1803 }
1804 if (crtc == 3) {
1805 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1806 EVERGREEN_CRTC3_REGISTER_OFFSET);
1807 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1808 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1809 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1810 }
1811 if (crtc == 4) {
1812 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1813 EVERGREEN_CRTC4_REGISTER_OFFSET);
1814 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1815 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1816 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1817 }
1818 if (crtc == 5) {
1819 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1820 EVERGREEN_CRTC5_REGISTER_OFFSET);
1821 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1822 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1823 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1824 }
1825 } else if (ASIC_IS_AVIVO(rdev)) {
1826 if (crtc == 0) {
1827 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1828 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1829 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1830 }
1831 if (crtc == 1) {
1832 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1833 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1834 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1835 }
1836 } else {
1837 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1838 if (crtc == 0) {
1839 /* Assume vbl_end == 0, get vbl_start from
1840 * upper 16 bits.
1841 */
1842 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1843 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1844 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1845 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1846 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1847 if (!(stat_crtc & 1))
1848 in_vbl = false;
1849
f5a80209 1850 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1851 }
1852 if (crtc == 1) {
1853 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1854 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1855 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1856 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1857 if (!(stat_crtc & 1))
1858 in_vbl = false;
1859
f5a80209 1860 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1861 }
1862 }
1863
d47abc58
MK		 1864 /* Get optional system timestamp after query. */
1865 if (etime)
1866 *etime = ktime_get();
1867
1868 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1869
6383cf7d
MK		 1870 /* Decode into vertical and horizontal scanout position. */
1871 *vpos = position & 0x1fff;
1872 *hpos = (position >> 16) & 0x1fff;
1873
1874 /* Valid vblank area boundaries from gpu retrieved? */
1875 if (vbl > 0) {
1876 /* Yes: Decode. */
f5a80209 1877 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1878 vbl_start = vbl & 0x1fff;
1879 vbl_end = (vbl >> 16) & 0x1fff;
1880 }
1881 else {
1882 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1883 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1884 vbl_end = 0;
1885 }
1886
1887 /* Test scanout position against vblank region. */
1888 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1889 in_vbl = false;
1890
1891 /* Check if inside vblank area and apply corrective offsets:
1892 * vpos will then be >=0 in video scanout area, but negative
1893 * within vblank area, counting down the number of lines until
1894 * start of scanout.
1895 */
1896
1897 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1898 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1899 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1900 *vpos = *vpos - vtotal;
1901 }
1902
1903 /* Correct for shifted end of vbl at vbl_end. */
1904 *vpos = *vpos - vbl_end;
1905
1906 /* In vblank? */
1907 if (in_vbl)
f5a80209 1908 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d 1909
8072bfa6
VS		 1910 /* Is vpos outside nominal vblank area, but less than
1911 * 1/100 of a frame height away from start of vblank?
1912 * If so, assume this isn't a massively delayed vblank
1913 * interrupt, but a vblank interrupt that fired a few
1914 * microseconds before true start of vblank. Compensate
1915 * by adding a full frame duration to the final timestamp.
1916 * Happens, e.g., on ATI R500, R600.
1917 *
1918 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1919 */
1920 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1921 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1922 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1923
1924 if (vbl_start - *vpos < vtotal / 100) {
1925 *vpos -= vtotal;
1926
1927 /* Signal this correction as "applied". */
1928 ret |= 0x8;
1929 }
1930 }
1931
6383cf7d
MK		 1932 return ret;
1933}
Linux kernel - Deliverables
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