projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/dce8: crtc_set_base updates
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
760285e7
DH		 33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
771fe6b9 35
771fe6b9
JG		 36static void avivo_crtc_load_lut(struct drm_crtc *crtc)
37{
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 int i;
42
d9fdaafb 43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
45
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
53
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
57
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
64 }
65
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
67}
68
fee298fd 69static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 70{
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
74 int i;
75
d9fdaafb 76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
78
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
86
677d0768
AD		 87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 89
677d0768 90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 91 for (i = 0; i < 256; i++) {
677d0768 92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
96 }
97}
98
fee298fd
AD		 99static void dce5_crtc_load_lut(struct drm_crtc *crtc)
100{
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
104 int i;
105
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
107
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
118
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
120
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
128
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
131
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
138 }
139
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 156 if (ASIC_IS_DCE8(rdev)) {
157 /* XXX this only needs to be programmed once per crtc at startup,
158 * not sure where the best place for it is
159 */
160 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
161 CIK_CURSOR_ALPHA_BLND_ENA);
162 }
fee298fd
AD		 163}
164
771fe6b9
JG		 165static void legacy_crtc_load_lut(struct drm_crtc *crtc)
166{
167 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
168 struct drm_device *dev = crtc->dev;
169 struct radeon_device *rdev = dev->dev_private;
170 int i;
171 uint32_t dac2_cntl;
172
173 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
174 if (radeon_crtc->crtc_id == 0)
175 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
176 else
177 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
178 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
179
180 WREG8(RADEON_PALETTE_INDEX, 0);
181 for (i = 0; i < 256; i++) {
182 WREG32(RADEON_PALETTE_30_DATA,
183 (radeon_crtc->lut_r[i] << 20) |
184 (radeon_crtc->lut_g[i] << 10) |
185 (radeon_crtc->lut_b[i] << 0));
186 }
187}
188
189void radeon_crtc_load_lut(struct drm_crtc *crtc)
190{
191 struct drm_device *dev = crtc->dev;
192 struct radeon_device *rdev = dev->dev_private;
193
194 if (!crtc->enabled)
195 return;
196
fee298fd
AD		 197 if (ASIC_IS_DCE5(rdev))
198 dce5_crtc_load_lut(crtc);
199 else if (ASIC_IS_DCE4(rdev))
200 dce4_crtc_load_lut(crtc);
bcc1c2a1 201 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 202 avivo_crtc_load_lut(crtc);
203 else
204 legacy_crtc_load_lut(crtc);
205}
206
b8c00ac5 207/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 208void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
209 u16 blue, int regno)
210{
211 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
212
771fe6b9
JG		 213 radeon_crtc->lut_r[regno] = red >> 6;
214 radeon_crtc->lut_g[regno] = green >> 6;
215 radeon_crtc->lut_b[regno] = blue >> 6;
216}
217
b8c00ac5
DA		 218/** Gets the color ramps on behalf of fbcon */
219void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
220 u16 *blue, int regno)
221{
222 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
223
224 *red = radeon_crtc->lut_r[regno] << 6;
225 *green = radeon_crtc->lut_g[regno] << 6;
226 *blue = radeon_crtc->lut_b[regno] << 6;
227}
228
771fe6b9 229static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 230 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 231{
232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 233 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 234
b8c00ac5 235 /* userspace palettes are always correct as is */
7203425a 236 for (i = start; i < end; i++) {
b8c00ac5
DA		 237 radeon_crtc->lut_r[i] = red[i] >> 6;
238 radeon_crtc->lut_g[i] = green[i] >> 6;
239 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 240 }
771fe6b9
JG		 241 radeon_crtc_load_lut(crtc);
242}
243
244static void radeon_crtc_destroy(struct drm_crtc *crtc)
245{
246 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
247
771fe6b9
JG		 248 drm_crtc_cleanup(crtc);
249 kfree(radeon_crtc);
250}
251
6f34be50
AD		 252/*
253 * Handle unpin events outside the interrupt handler proper.
254 */
255static void radeon_unpin_work_func(struct work_struct *__work)
256{
257 struct radeon_unpin_work *work =
258 container_of(__work, struct radeon_unpin_work, work);
259 int r;
260
261 /* unpin of the old buffer */
262 r = radeon_bo_reserve(work->old_rbo, false);
263 if (likely(r == 0)) {
264 r = radeon_bo_unpin(work->old_rbo);
265 if (unlikely(r != 0)) {
266 DRM_ERROR("failed to unpin buffer after flip\n");
267 }
268 radeon_bo_unreserve(work->old_rbo);
269 } else
270 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 271
272 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 273 kfree(work);
274}
275
276void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
277{
278 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
279 struct radeon_unpin_work *work;
6f34be50
AD		 280 unsigned long flags;
281 u32 update_pending;
282 int vpos, hpos;
283
284 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
285 work = radeon_crtc->unpin_work;
286 if (work == NULL ||
fcc485d6 287 (work->fence && !radeon_fence_signaled(work->fence))) {
6f34be50
AD		 288 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
289 return;
290 }
291 /* New pageflip, or just completion of a previous one? */
292 if (!radeon_crtc->deferred_flip_completion) {
293 /* do the flip (mmio) */
294 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
295 } else {
296 /* This is just a completion of a flip queued in crtc
297 * at last invocation. Make sure we go directly to
298 * completion routine.
299 */
300 update_pending = 0;
301 radeon_crtc->deferred_flip_completion = 0;
302 }
303
304 /* Has the pageflip already completed in crtc, or is it certain
305 * to complete in this vblank?
306 */
307 if (update_pending &&
308 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
309 &vpos, &hpos)) &&
81ffbbed
FK		 310 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
311 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
312 /* crtc didn't flip in this target vblank interval,
313 * but flip is pending in crtc. Based on the current
314 * scanout position we know that the current frame is
315 * (nearly) complete and the flip will (likely)
316 * complete before the start of the next frame.
317 */
318 update_pending = 0;
319 }
320 if (update_pending) {
6f34be50
AD		 321 /* crtc didn't flip in this target vblank interval,
322 * but flip is pending in crtc. It will complete it
323 * in next vblank interval, so complete the flip at
324 * next vblank irq.
325 */
326 radeon_crtc->deferred_flip_completion = 1;
327 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
328 return;
329 }
330
331 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
332 radeon_crtc->unpin_work = NULL;
333
334 /* wakeup userspace */
26ae4667
RC		 335 if (work->event)
336 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
337
6f34be50
AD		 338 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
339
340 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
341 radeon_fence_unref(&work->fence);
342 radeon_post_page_flip(work->rdev, work->crtc_id);
343 schedule_work(&work->work);
344}
345
346static int radeon_crtc_page_flip(struct drm_crtc *crtc,
347 struct drm_framebuffer *fb,
348 struct drm_pending_vblank_event *event)
349{
350 struct drm_device *dev = crtc->dev;
351 struct radeon_device *rdev = dev->dev_private;
352 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
353 struct radeon_framebuffer *old_radeon_fb;
354 struct radeon_framebuffer *new_radeon_fb;
355 struct drm_gem_object *obj;
356 struct radeon_bo *rbo;
6f34be50
AD		 357 struct radeon_unpin_work *work;
358 unsigned long flags;
359 u32 tiling_flags, pitch_pixels;
360 u64 base;
361 int r;
362
363 work = kzalloc(sizeof *work, GFP_KERNEL);
364 if (work == NULL)
365 return -ENOMEM;
366
6f34be50
AD		 367 work->event = event;
368 work->rdev = rdev;
369 work->crtc_id = radeon_crtc->crtc_id;
6f34be50
AD		 370 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
371 new_radeon_fb = to_radeon_framebuffer(fb);
372 /* schedule unpin of the old buffer */
373 obj = old_radeon_fb->obj;
498c555f
DA		 374 /* take a reference to the old object */
375 drm_gem_object_reference(obj);
7e4d15d9 376 rbo = gem_to_radeon_bo(obj);
6f34be50 377 work->old_rbo = rbo;
fcc485d6
MD		 378 obj = new_radeon_fb->obj;
379 rbo = gem_to_radeon_bo(obj);
9af20792
DV		 380
381 spin_lock(&rbo->tbo.bdev->fence_lock);
fcc485d6
MD		 382 if (rbo->tbo.sync_obj)
383 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
9af20792
DV		 384 spin_unlock(&rbo->tbo.bdev->fence_lock);
385
6f34be50
AD		 386 INIT_WORK(&work->work, radeon_unpin_work_func);
387
388 /* We borrow the event spin lock for protecting unpin_work */
389 spin_lock_irqsave(&dev->event_lock, flags);
390 if (radeon_crtc->unpin_work) {
6f34be50 391 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
498c555f
DA		 392 r = -EBUSY;
393 goto unlock_free;
6f34be50
AD		 394 }
395 radeon_crtc->unpin_work = work;
396 radeon_crtc->deferred_flip_completion = 0;
397 spin_unlock_irqrestore(&dev->event_lock, flags);
398
399 /* pin the new buffer */
6f34be50
AD		 400 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
401 work->old_rbo, rbo);
402
403 r = radeon_bo_reserve(rbo, false);
404 if (unlikely(r != 0)) {
405 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
406 goto pflip_cleanup;
407 }
0349af70
MD		 408 /* Only 27 bit offset for legacy CRTC */
409 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
410 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50
AD		 411 if (unlikely(r != 0)) {
412 radeon_bo_unreserve(rbo);
413 r = -EINVAL;
414 DRM_ERROR("failed to pin new rbo buffer before flip\n");
415 goto pflip_cleanup;
416 }
417 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
418 radeon_bo_unreserve(rbo);
419
420 if (!ASIC_IS_AVIVO(rdev)) {
421 /* crtc offset is from display base addr not FB location */
422 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 423 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 424
425 if (tiling_flags & RADEON_TILING_MACRO) {
426 if (ASIC_IS_R300(rdev)) {
427 base &= ~0x7ff;
428 } else {
429 int byteshift = fb->bits_per_pixel >> 4;
430 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
431 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
432 }
433 } else {
434 int offset = crtc->y * pitch_pixels + crtc->x;
435 switch (fb->bits_per_pixel) {
436 case 8:
437 default:
438 offset *= 1;
439 break;
440 case 15:
441 case 16:
442 offset *= 2;
443 break;
444 case 24:
445 offset *= 3;
446 break;
447 case 32:
448 offset *= 4;
449 break;
450 }
451 base += offset;
452 }
453 base &= ~7;
454 }
455
456 spin_lock_irqsave(&dev->event_lock, flags);
457 work->new_crtc_base = base;
458 spin_unlock_irqrestore(&dev->event_lock, flags);
459
460 /* update crtc fb */
461 crtc->fb = fb;
462
463 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
464 if (r) {
465 DRM_ERROR("failed to get vblank before flip\n");
466 goto pflip_cleanup1;
467 }
468
6f34be50
AD		 469 /* set the proper interrupt */
470 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
6f34be50
AD		 471
472 return 0;
473
6f34be50 474pflip_cleanup1:
d0254d56 475 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
6f34be50
AD		 476 DRM_ERROR("failed to reserve new rbo in error path\n");
477 goto pflip_cleanup;
478 }
d0254d56 479 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
6f34be50 480 DRM_ERROR("failed to unpin new rbo in error path\n");
6f34be50
AD		 481 }
482 radeon_bo_unreserve(rbo);
483
484pflip_cleanup:
485 spin_lock_irqsave(&dev->event_lock, flags);
486 radeon_crtc->unpin_work = NULL;
498c555f 487unlock_free:
6f34be50 488 spin_unlock_irqrestore(&dev->event_lock, flags);
db318d7a 489 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
fcc485d6 490 radeon_fence_unref(&work->fence);
6f34be50
AD		 491 kfree(work);
492
493 return r;
494}
495
771fe6b9
JG		 496static const struct drm_crtc_funcs radeon_crtc_funcs = {
497 .cursor_set = radeon_crtc_cursor_set,
498 .cursor_move = radeon_crtc_cursor_move,
499 .gamma_set = radeon_crtc_gamma_set,
500 .set_config = drm_crtc_helper_set_config,
501 .destroy = radeon_crtc_destroy,
6f34be50 502 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 503};
504
505static void radeon_crtc_init(struct drm_device *dev, int index)
506{
507 struct radeon_device *rdev = dev->dev_private;
508 struct radeon_crtc *radeon_crtc;
509 int i;
510
511 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
512 if (radeon_crtc == NULL)
513 return;
514
515 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
516
517 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
518 radeon_crtc->crtc_id = index;
c93bb85b 519 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 520
9e05fa1d
AD		 521 if (rdev->family >= CHIP_BONAIRE) {
522 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
523 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
524 } else {
525 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
526 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
527 }
528
785b93ef 529#if 0
771fe6b9
JG		 530 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
531 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
532 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 533#endif
771fe6b9
JG		 534
535 for (i = 0; i < 256; i++) {
536 radeon_crtc->lut_r[i] = i << 2;
537 radeon_crtc->lut_g[i] = i << 2;
538 radeon_crtc->lut_b[i] = i << 2;
539 }
540
541 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
542 radeon_atombios_init_crtc(dev, radeon_crtc);
543 else
544 radeon_legacy_init_crtc(dev, radeon_crtc);
545}
546
df391c0d 547static const char *encoder_names[37] = {
771fe6b9
JG		 548 "NONE",
549 "INTERNAL_LVDS",
550 "INTERNAL_TMDS1",
551 "INTERNAL_TMDS2",
552 "INTERNAL_DAC1",
553 "INTERNAL_DAC2",
554 "INTERNAL_SDVOA",
555 "INTERNAL_SDVOB",
556 "SI170B",
557 "CH7303",
558 "CH7301",
559 "INTERNAL_DVO1",
560 "EXTERNAL_SDVOA",
561 "EXTERNAL_SDVOB",
562 "TITFP513",
563 "INTERNAL_LVTM1",
564 "VT1623",
565 "HDMI_SI1930",
566 "HDMI_INTERNAL",
567 "INTERNAL_KLDSCP_TMDS1",
568 "INTERNAL_KLDSCP_DVO1",
569 "INTERNAL_KLDSCP_DAC1",
570 "INTERNAL_KLDSCP_DAC2",
571 "SI178",
572 "MVPU_FPGA",
573 "INTERNAL_DDI",
574 "VT1625",
575 "HDMI_SI1932",
576 "DP_AN9801",
577 "DP_DP501",
578 "INTERNAL_UNIPHY",
579 "INTERNAL_KLDSCP_LVTMA",
580 "INTERNAL_UNIPHY1",
581 "INTERNAL_UNIPHY2",
bf982ebf
AD		 582 "NUTMEG",
583 "TRAVIS",
df391c0d 584 "INTERNAL_VCE"
771fe6b9
JG		 585};
586
cbd4623d 587static const char *hpd_names[6] = {
eed45b30
AD		 588 "HPD1",
589 "HPD2",
590 "HPD3",
591 "HPD4",
592 "HPD5",
593 "HPD6",
594};
595
771fe6b9
JG		 596static void radeon_print_display_setup(struct drm_device *dev)
597{
598 struct drm_connector *connector;
599 struct radeon_connector *radeon_connector;
600 struct drm_encoder *encoder;
601 struct radeon_encoder *radeon_encoder;
602 uint32_t devices;
603 int i = 0;
604
605 DRM_INFO("Radeon Display Connectors\n");
606 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
607 radeon_connector = to_radeon_connector(connector);
608 DRM_INFO("Connector %d:\n", i);
c1d2dbd2 609 DRM_INFO(" %s\n", drm_get_connector_name(connector));
eed45b30
AD		 610 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
611 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 612 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 613 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
614 radeon_connector->ddc_bus->rec.mask_clk_reg,
615 radeon_connector->ddc_bus->rec.mask_data_reg,
616 radeon_connector->ddc_bus->rec.a_clk_reg,
617 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 618 radeon_connector->ddc_bus->rec.en_clk_reg,
619 radeon_connector->ddc_bus->rec.en_data_reg,
620 radeon_connector->ddc_bus->rec.y_clk_reg,
621 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 622 if (radeon_connector->router.ddc_valid)
26b5bc98 623 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 624 radeon_connector->router.ddc_mux_control_pin,
625 radeon_connector->router.ddc_mux_state);
626 if (radeon_connector->router.cd_valid)
627 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
628 radeon_connector->router.cd_mux_control_pin,
629 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 630 } else {
631 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
632 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
633 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
634 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
635 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
636 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
637 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
638 }
771fe6b9
JG		 639 DRM_INFO(" Encoders:\n");
640 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
641 radeon_encoder = to_radeon_encoder(encoder);
642 devices = radeon_encoder->devices & radeon_connector->devices;
643 if (devices) {
644 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
645 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
646 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
647 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
648 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
649 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
650 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
651 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
652 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
653 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
654 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
655 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
656 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
657 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
658 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
659 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 660 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
661 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 662 if (devices & ATOM_DEVICE_TV1_SUPPORT)
663 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
664 if (devices & ATOM_DEVICE_CV_SUPPORT)
665 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
666 }
667 }
668 i++;
669 }
670}
671
4ce001ab 672static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 673{
674 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 675 bool ret = false;
676
677 if (rdev->bios) {
678 if (rdev->is_atom_bios) {
a084e6ee
AD		 679 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
680 if (ret == false)
771fe6b9 681 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 682 } else {
771fe6b9 683 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 684 if (ret == false)
685 ret = radeon_get_legacy_connector_info_from_table(dev);
686 }
771fe6b9
JG		 687 } else {
688 if (!ASIC_IS_AVIVO(rdev))
689 ret = radeon_get_legacy_connector_info_from_table(dev);
690 }
691 if (ret) {
1f3b6a45 692 radeon_setup_encoder_clones(dev);
771fe6b9 693 radeon_print_display_setup(dev);
771fe6b9
JG		 694 }
695
696 return ret;
697}
698
699int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
700{
3c537889
AD		 701 struct drm_device *dev = radeon_connector->base.dev;
702 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 703 int ret = 0;
704
26b5bc98 705 /* on hw with routers, select right port */
fb939dfc
AD		 706 if (radeon_connector->router.ddc_valid)
707 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 708
0a9069d3
NOS		 709 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
710 ENCODER_OBJECT_ID_NONE) {
711 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
712
713 if (dig->dp_i2c_bus)
714 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
715 &dig->dp_i2c_bus->adapter);
716 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
717 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 718 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
b06947b5 719
7a15cbd4
DA		 720 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
721 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
b06947b5
AD		 722 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
723 &dig->dp_i2c_bus->adapter);
724 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
725 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
726 &radeon_connector->ddc_bus->adapter);
727 } else {
728 if (radeon_connector->ddc_bus && !radeon_connector->edid)
729 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
730 &radeon_connector->ddc_bus->adapter);
0294cf4f 731 }
c324acd5
AD		 732
733 if (!radeon_connector->edid) {
734 if (rdev->is_atom_bios) {
735 /* some laptops provide a hardcoded edid in rom for LCDs */
736 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
737 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
738 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
739 } else
740 /* some servers provide a hardcoded edid in rom for KVMs */
741 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
742 }
0294cf4f
AD		 743 if (radeon_connector->edid) {
744 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
745 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 746 return ret;
747 }
748 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 749 return 0;
771fe6b9
JG		 750}
751
f523f74e
AD		 752/* avivo */
753static void avivo_get_fb_div(struct radeon_pll *pll,
754 u32 target_clock,
755 u32 post_div,
756 u32 ref_div,
757 u32 *fb_div,
758 u32 *frac_fb_div)
759{
760 u32 tmp = post_div * ref_div;
761
762 tmp *= target_clock;
763 *fb_div = tmp / pll->reference_freq;
764 *frac_fb_div = tmp % pll->reference_freq;
a4b40d5d
AD		 765
766 if (*fb_div > pll->max_feedback_div)
767 *fb_div = pll->max_feedback_div;
768 else if (*fb_div < pll->min_feedback_div)
769 *fb_div = pll->min_feedback_div;
f523f74e
AD		 770}
771
772static u32 avivo_get_post_div(struct radeon_pll *pll,
773 u32 target_clock)
774{
775 u32 vco, post_div, tmp;
776
777 if (pll->flags & RADEON_PLL_USE_POST_DIV)
778 return pll->post_div;
779
780 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
781 if (pll->flags & RADEON_PLL_IS_LCD)
782 vco = pll->lcd_pll_out_min;
783 else
784 vco = pll->pll_out_min;
785 } else {
786 if (pll->flags & RADEON_PLL_IS_LCD)
787 vco = pll->lcd_pll_out_max;
788 else
789 vco = pll->pll_out_max;
790 }
791
792 post_div = vco / target_clock;
793 tmp = vco % target_clock;
794
795 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
796 if (tmp)
797 post_div++;
798 } else {
799 if (!tmp)
800 post_div--;
801 }
802
a4b40d5d
AD		 803 if (post_div > pll->max_post_div)
804 post_div = pll->max_post_div;
805 else if (post_div < pll->min_post_div)
806 post_div = pll->min_post_div;
807
f523f74e
AD		 808 return post_div;
809}
810
811#define MAX_TOLERANCE 10
812
813void radeon_compute_pll_avivo(struct radeon_pll *pll,
814 u32 freq,
815 u32 *dot_clock_p,
816 u32 *fb_div_p,
817 u32 *frac_fb_div_p,
818 u32 *ref_div_p,
819 u32 *post_div_p)
820{
821 u32 target_clock = freq / 10;
822 u32 post_div = avivo_get_post_div(pll, target_clock);
823 u32 ref_div = pll->min_ref_div;
824 u32 fb_div = 0, frac_fb_div = 0, tmp;
825
826 if (pll->flags & RADEON_PLL_USE_REF_DIV)
827 ref_div = pll->reference_div;
828
829 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
830 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
831 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
832 if (frac_fb_div >= 5) {
833 frac_fb_div -= 5;
834 frac_fb_div = frac_fb_div / 10;
835 frac_fb_div++;
836 }
837 if (frac_fb_div >= 10) {
838 fb_div++;
839 frac_fb_div = 0;
840 }
841 } else {
842 while (ref_div <= pll->max_ref_div) {
843 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
844 &fb_div, &frac_fb_div);
845 if (frac_fb_div >= (pll->reference_freq / 2))
846 fb_div++;
847 frac_fb_div = 0;
848 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
849 tmp = (tmp * 10000) / target_clock;
850
851 if (tmp > (10000 + MAX_TOLERANCE))
852 ref_div++;
853 else if (tmp >= (10000 - MAX_TOLERANCE))
854 break;
855 else
856 ref_div++;
857 }
858 }
859
860 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
861 (ref_div * post_div * 10);
862 *fb_div_p = fb_div;
863 *frac_fb_div_p = frac_fb_div;
864 *ref_div_p = ref_div;
865 *post_div_p = post_div;
866 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
867 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
868}
869
870/* pre-avivo */
771fe6b9
JG		 871static inline uint32_t radeon_div(uint64_t n, uint32_t d)
872{
873 uint64_t mod;
874
875 n += d / 2;
876
877 mod = do_div(n, d);
878 return n;
879}
880
f523f74e
AD		 881void radeon_compute_pll_legacy(struct radeon_pll *pll,
882 uint64_t freq,
883 uint32_t *dot_clock_p,
884 uint32_t *fb_div_p,
885 uint32_t *frac_fb_div_p,
886 uint32_t *ref_div_p,
887 uint32_t *post_div_p)
771fe6b9
JG		 888{
889 uint32_t min_ref_div = pll->min_ref_div;
890 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 891 uint32_t min_post_div = pll->min_post_div;
892 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 893 uint32_t min_fractional_feed_div = 0;
894 uint32_t max_fractional_feed_div = 0;
895 uint32_t best_vco = pll->best_vco;
896 uint32_t best_post_div = 1;
897 uint32_t best_ref_div = 1;
898 uint32_t best_feedback_div = 1;
899 uint32_t best_frac_feedback_div = 0;
900 uint32_t best_freq = -1;
901 uint32_t best_error = 0xffffffff;
902 uint32_t best_vco_diff = 1;
903 uint32_t post_div;
86cb2bbf 904 u32 pll_out_min, pll_out_max;
771fe6b9 905
d9fdaafb 906 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 907 freq = freq * 1000;
908
86cb2bbf
AD		 909 if (pll->flags & RADEON_PLL_IS_LCD) {
910 pll_out_min = pll->lcd_pll_out_min;
911 pll_out_max = pll->lcd_pll_out_max;
912 } else {
913 pll_out_min = pll->pll_out_min;
914 pll_out_max = pll->pll_out_max;
915 }
916
619efb10
AD		 917 if (pll_out_min > 64800)
918 pll_out_min = 64800;
919
fc10332b 920 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 921 min_ref_div = max_ref_div = pll->reference_div;
922 else {
923 while (min_ref_div < max_ref_div-1) {
924 uint32_t mid = (min_ref_div + max_ref_div) / 2;
925 uint32_t pll_in = pll->reference_freq / mid;
926 if (pll_in < pll->pll_in_min)
927 max_ref_div = mid;
928 else if (pll_in > pll->pll_in_max)
929 min_ref_div = mid;
930 else
931 break;
932 }
933 }
934
fc10332b
AD		 935 if (pll->flags & RADEON_PLL_USE_POST_DIV)
936 min_post_div = max_post_div = pll->post_div;
937
938 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 939 min_fractional_feed_div = pll->min_frac_feedback_div;
940 max_fractional_feed_div = pll->max_frac_feedback_div;
941 }
942
bd6a60af 943 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 944 uint32_t ref_div;
945
fc10332b 946 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 947 continue;
948
949 /* legacy radeons only have a few post_divs */
fc10332b 950 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 951 if ((post_div == 5) ||
952 (post_div == 7) ||
953 (post_div == 9) ||
954 (post_div == 10) ||
955 (post_div == 11) ||
956 (post_div == 13) ||
957 (post_div == 14) ||
958 (post_div == 15))
959 continue;
960 }
961
962 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
963 uint32_t feedback_div, current_freq = 0, error, vco_diff;
964 uint32_t pll_in = pll->reference_freq / ref_div;
965 uint32_t min_feed_div = pll->min_feedback_div;
966 uint32_t max_feed_div = pll->max_feedback_div + 1;
967
968 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
969 continue;
970
971 while (min_feed_div < max_feed_div) {
972 uint32_t vco;
973 uint32_t min_frac_feed_div = min_fractional_feed_div;
974 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
975 uint32_t frac_feedback_div;
976 uint64_t tmp;
977
978 feedback_div = (min_feed_div + max_feed_div) / 2;
979
980 tmp = (uint64_t)pll->reference_freq * feedback_div;
981 vco = radeon_div(tmp, ref_div);
982
86cb2bbf 983 if (vco < pll_out_min) {
771fe6b9
JG		 984 min_feed_div = feedback_div + 1;
985 continue;
86cb2bbf 986 } else if (vco > pll_out_max) {
771fe6b9
JG		 987 max_feed_div = feedback_div;
988 continue;
989 }
990
991 while (min_frac_feed_div < max_frac_feed_div) {
992 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
993 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
994 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
995 current_freq = radeon_div(tmp, ref_div * post_div);
996
fc10332b 997 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 998 if (freq < current_freq)
999 error = 0xffffffff;
1000 else
1001 error = freq - current_freq;
d0e275a9
AD		 1002 } else
1003 error = abs(current_freq - freq);
771fe6b9
JG		 1004 vco_diff = abs(vco - best_vco);
1005
1006 if ((best_vco == 0 && error < best_error) ||
1007 (best_vco != 0 &&
167ffc44 1008 ((best_error > 100 && error < best_error - 100) ||
5480f727 1009 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1010 best_post_div = post_div;
1011 best_ref_div = ref_div;
1012 best_feedback_div = feedback_div;
1013 best_frac_feedback_div = frac_feedback_div;
1014 best_freq = current_freq;
1015 best_error = error;
1016 best_vco_diff = vco_diff;
5480f727
DA		 1017 } else if (current_freq == freq) {
1018 if (best_freq == -1) {
1019 best_post_div = post_div;
1020 best_ref_div = ref_div;
1021 best_feedback_div = feedback_div;
1022 best_frac_feedback_div = frac_feedback_div;
1023 best_freq = current_freq;
1024 best_error = error;
1025 best_vco_diff = vco_diff;
1026 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1027 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1028 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1029 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1030 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1031 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1032 best_post_div = post_div;
1033 best_ref_div = ref_div;
1034 best_feedback_div = feedback_div;
1035 best_frac_feedback_div = frac_feedback_div;
1036 best_freq = current_freq;
1037 best_error = error;
1038 best_vco_diff = vco_diff;
1039 }
771fe6b9
JG		 1040 }
1041 if (current_freq < freq)
1042 min_frac_feed_div = frac_feedback_div + 1;
1043 else
1044 max_frac_feed_div = frac_feedback_div;
1045 }
1046 if (current_freq < freq)
1047 min_feed_div = feedback_div + 1;
1048 else
1049 max_feed_div = feedback_div;
1050 }
1051 }
1052 }
1053
1054 *dot_clock_p = best_freq / 10000;
1055 *fb_div_p = best_feedback_div;
1056 *frac_fb_div_p = best_frac_feedback_div;
1057 *ref_div_p = best_ref_div;
1058 *post_div_p = best_post_div;
bbb0aef5
JP		 1059 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1060 (long long)freq,
1061 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1062 best_ref_div, best_post_div);
1063
771fe6b9
JG		 1064}
1065
1066static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1067{
1068 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1069
29d08b3e 1070 if (radeon_fb->obj) {
bc9025bd 1071 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1072 }
771fe6b9
JG		 1073 drm_framebuffer_cleanup(fb);
1074 kfree(radeon_fb);
1075}
1076
1077static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1078 struct drm_file *file_priv,
1079 unsigned int *handle)
1080{
1081 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1082
1083 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1084}
1085
1086static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1087 .destroy = radeon_user_framebuffer_destroy,
1088 .create_handle = radeon_user_framebuffer_create_handle,
1089};
1090
aaefcd42 1091int
38651674
DA		 1092radeon_framebuffer_init(struct drm_device *dev,
1093 struct radeon_framebuffer *rfb,
308e5bcb 1094 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1095 struct drm_gem_object *obj)
771fe6b9 1096{
aaefcd42 1097 int ret;
38651674 1098 rfb->obj = obj;
c7d73f6a 1099 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1100 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1101 if (ret) {
1102 rfb->obj = NULL;
1103 return ret;
1104 }
aaefcd42 1105 return 0;
771fe6b9
JG		 1106}
1107
1108static struct drm_framebuffer *
1109radeon_user_framebuffer_create(struct drm_device *dev,
1110 struct drm_file *file_priv,
308e5bcb 1111 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1112{
1113 struct drm_gem_object *obj;
38651674 1114 struct radeon_framebuffer *radeon_fb;
aaefcd42 1115 int ret;
771fe6b9 1116
308e5bcb 1117 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1118 if (obj == NULL) {
1119 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1120 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1121 return ERR_PTR(-ENOENT);
7e71c9e2 1122 }
38651674
DA		 1123
1124 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1125 if (radeon_fb == NULL) {
1126 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1127 return ERR_PTR(-ENOMEM);
f2d68cf4 1128 }
38651674 1129
aaefcd42
DA		 1130 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1131 if (ret) {
1132 kfree(radeon_fb);
1133 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1134 return ERR_PTR(ret);
aaefcd42 1135 }
38651674
DA		 1136
1137 return &radeon_fb->base;
771fe6b9
JG		 1138}
1139
eb1f8e4f
DA		 1140static void radeon_output_poll_changed(struct drm_device *dev)
1141{
1142 struct radeon_device *rdev = dev->dev_private;
1143 radeon_fb_output_poll_changed(rdev);
1144}
1145
771fe6b9
JG		 1146static const struct drm_mode_config_funcs radeon_mode_funcs = {
1147 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1148 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1149};
1150
445282db
DA		 1151static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1152{ { 0, "driver" },
1153 { 1, "bios" },
1154};
1155
1156static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1157{ { TV_STD_NTSC, "ntsc" },
1158 { TV_STD_PAL, "pal" },
1159 { TV_STD_PAL_M, "pal-m" },
1160 { TV_STD_PAL_60, "pal-60" },
1161 { TV_STD_NTSC_J, "ntsc-j" },
1162 { TV_STD_SCART_PAL, "scart-pal" },
1163 { TV_STD_PAL_CN, "pal-cn" },
1164 { TV_STD_SECAM, "secam" },
1165};
1166
5b1714d3
AD		 1167static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1168{ { UNDERSCAN_OFF, "off" },
1169 { UNDERSCAN_ON, "on" },
1170 { UNDERSCAN_AUTO, "auto" },
1171};
1172
d79766fa 1173static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1174{
4a67d391 1175 int sz;
445282db
DA		 1176
1177 if (rdev->is_atom_bios) {
1178 rdev->mode_info.coherent_mode_property =
d9bc3c02 1179 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1180 if (!rdev->mode_info.coherent_mode_property)
1181 return -ENOMEM;
445282db
DA		 1182 }
1183
1184 if (!ASIC_IS_AVIVO(rdev)) {
1185 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1186 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1187 drm_property_create_enum(rdev->ddev, 0,
1188 "tmds_pll",
1189 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1190 }
1191
1192 rdev->mode_info.load_detect_property =
d9bc3c02 1193 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1194 if (!rdev->mode_info.load_detect_property)
1195 return -ENOMEM;
445282db
DA		 1196
1197 drm_mode_create_scaling_mode_property(rdev->ddev);
1198
1199 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1200 rdev->mode_info.tv_std_property =
4a67d391
SH		 1201 drm_property_create_enum(rdev->ddev, 0,
1202 "tv standard",
1203 radeon_tv_std_enum_list, sz);
445282db 1204
5b1714d3
AD		 1205 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1206 rdev->mode_info.underscan_property =
4a67d391
SH		 1207 drm_property_create_enum(rdev->ddev, 0,
1208 "underscan",
1209 radeon_underscan_enum_list, sz);
5b1714d3 1210
5bccf5e3 1211 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1212 drm_property_create_range(rdev->ddev, 0,
1213 "underscan hborder", 0, 128);
5bccf5e3
MG		 1214 if (!rdev->mode_info.underscan_hborder_property)
1215 return -ENOMEM;
5bccf5e3
MG		 1216
1217 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1218 drm_property_create_range(rdev->ddev, 0,
1219 "underscan vborder", 0, 128);
5bccf5e3
MG		 1220 if (!rdev->mode_info.underscan_vborder_property)
1221 return -ENOMEM;
5bccf5e3 1222
445282db
DA		 1223 return 0;
1224}
1225
f46c0120
AD		 1226void radeon_update_display_priority(struct radeon_device *rdev)
1227{
1228 /* adjustment options for the display watermarks */
1229 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1230 /* set display priority to high for r3xx, rv515 chips
1231 * this avoids flickering due to underflow to the
1232 * display controllers during heavy acceleration.
45737447
AD		 1233 * Don't force high on rs4xx igp chips as it seems to
1234 * affect the sound card. See kernel bug 15982.
f46c0120 1235 */
45737447
AD		 1236 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1237 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1238 rdev->disp_priority = 2;
1239 else
1240 rdev->disp_priority = 0;
1241 } else
1242 rdev->disp_priority = radeon_disp_priority;
1243
1244}
1245
0783986a
AD		 1246/*
1247 * Allocate hdmi structs and determine register offsets
1248 */
1249static void radeon_afmt_init(struct radeon_device *rdev)
1250{
1251 int i;
1252
1253 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1254 rdev->mode_info.afmt[i] = NULL;
1255
1256 if (ASIC_IS_DCE6(rdev)) {
1257 /* todo */
1258 } else if (ASIC_IS_DCE4(rdev)) {
1259 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1260 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1261 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1262 if (rdev->mode_info.afmt[0]) {
1263 rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1264 rdev->mode_info.afmt[0]->id = 0;
1265 }
1266 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1267 if (rdev->mode_info.afmt[1]) {
1268 rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1269 rdev->mode_info.afmt[1]->id = 1;
1270 }
1271 if (!ASIC_IS_DCE41(rdev)) {
1272 rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1273 if (rdev->mode_info.afmt[2]) {
1274 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1275 rdev->mode_info.afmt[2]->id = 2;
1276 }
1277 rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1278 if (rdev->mode_info.afmt[3]) {
1279 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1280 rdev->mode_info.afmt[3]->id = 3;
1281 }
1282 rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1283 if (rdev->mode_info.afmt[4]) {
1284 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1285 rdev->mode_info.afmt[4]->id = 4;
1286 }
1287 rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1288 if (rdev->mode_info.afmt[5]) {
1289 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1290 rdev->mode_info.afmt[5]->id = 5;
1291 }
1292 }
1293 } else if (ASIC_IS_DCE3(rdev)) {
1294 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1295 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1296 if (rdev->mode_info.afmt[0]) {
1297 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1298 rdev->mode_info.afmt[0]->id = 0;
1299 }
1300 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1301 if (rdev->mode_info.afmt[1]) {
1302 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1303 rdev->mode_info.afmt[1]->id = 1;
1304 }
1305 } else if (ASIC_IS_DCE2(rdev)) {
1306 /* DCE2 has at least 1 routable audio block */
1307 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1308 if (rdev->mode_info.afmt[0]) {
1309 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1310 rdev->mode_info.afmt[0]->id = 0;
1311 }
1312 /* r6xx has 2 routable audio blocks */
1313 if (rdev->family >= CHIP_R600) {
1314 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1315 if (rdev->mode_info.afmt[1]) {
1316 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1317 rdev->mode_info.afmt[1]->id = 1;
1318 }
1319 }
1320 }
1321}
1322
1323static void radeon_afmt_fini(struct radeon_device *rdev)
1324{
1325 int i;
1326
1327 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1328 kfree(rdev->mode_info.afmt[i]);
1329 rdev->mode_info.afmt[i] = NULL;
1330 }
1331}
1332
771fe6b9
JG		 1333int radeon_modeset_init(struct radeon_device *rdev)
1334{
18917b60 1335 int i;
771fe6b9
JG		 1336 int ret;
1337
1338 drm_mode_config_init(rdev->ddev);
1339 rdev->mode_info.mode_config_initialized = true;
1340
e6ecefaa 1341 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1342
881dd74e
AD		 1343 if (ASIC_IS_DCE5(rdev)) {
1344 rdev->ddev->mode_config.max_width = 16384;
1345 rdev->ddev->mode_config.max_height = 16384;
1346 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1347 rdev->ddev->mode_config.max_width = 8192;
1348 rdev->ddev->mode_config.max_height = 8192;
1349 } else {
1350 rdev->ddev->mode_config.max_width = 4096;
1351 rdev->ddev->mode_config.max_height = 4096;
1352 }
1353
019d96cb
DA		 1354 rdev->ddev->mode_config.preferred_depth = 24;
1355 rdev->ddev->mode_config.prefer_shadow = 1;
1356
771fe6b9
JG		 1357 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1358
445282db
DA		 1359 ret = radeon_modeset_create_props(rdev);
1360 if (ret) {
1361 return ret;
1362 }
dfee5614 1363
f376b94f
AD		 1364 /* init i2c buses */
1365 radeon_i2c_init(rdev);
1366
3c537889
AD		 1367 /* check combios for a valid hardcoded EDID - Sun servers */
1368 if (!rdev->is_atom_bios) {
1369 /* check for hardcoded EDID in BIOS */
1370 radeon_combios_check_hardcoded_edid(rdev);
1371 }
1372
dfee5614 1373 /* allocate crtcs */
18917b60 1374 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1375 radeon_crtc_init(rdev->ddev, i);
1376 }
1377
1378 /* okay we should have all the bios connectors */
1379 ret = radeon_setup_enc_conn(rdev->ddev);
1380 if (!ret) {
1381 return ret;
1382 }
ac89af1e 1383
3fa47d9e
AD		 1384 /* init dig PHYs, disp eng pll */
1385 if (rdev->is_atom_bios) {
ac89af1e 1386 radeon_atom_encoder_init(rdev);
f3f1f03e 1387 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1388 }
ac89af1e 1389
d4877cf2
AD		 1390 /* initialize hpd */
1391 radeon_hpd_init(rdev);
38651674 1392
0783986a
AD		 1393 /* setup afmt */
1394 radeon_afmt_init(rdev);
1395
ce8f5370
AD		 1396 /* Initialize power management */
1397 radeon_pm_init(rdev);
1398
38651674 1399 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1400 drm_kms_helper_poll_init(rdev->ddev);
1401
771fe6b9
JG		 1402 return 0;
1403}
1404
1405void radeon_modeset_fini(struct radeon_device *rdev)
1406{
38651674 1407 radeon_fbdev_fini(rdev);
3c537889 1408 kfree(rdev->mode_info.bios_hardcoded_edid);
ce8f5370 1409 radeon_pm_fini(rdev);
3c537889 1410
771fe6b9 1411 if (rdev->mode_info.mode_config_initialized) {
0783986a 1412 radeon_afmt_fini(rdev);
eb1f8e4f 1413 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1414 radeon_hpd_fini(rdev);
771fe6b9
JG		 1415 drm_mode_config_cleanup(rdev->ddev);
1416 rdev->mode_info.mode_config_initialized = false;
1417 }
f376b94f
AD		 1418 /* free i2c buses */
1419 radeon_i2c_fini(rdev);
771fe6b9
JG		 1420}
1421
e811f5ae 1422static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1423{
1424 /* try and guess if this is a tv or a monitor */
1425 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1426 (mode->vdisplay == 576) || /* 576p */
1427 (mode->vdisplay == 720) || /* 720p */
1428 (mode->vdisplay == 1080)) /* 1080p */
1429 return true;
1430 else
1431 return false;
1432}
1433
c93bb85b 1434bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1435 const struct drm_display_mode *mode,
c93bb85b 1436 struct drm_display_mode *adjusted_mode)
771fe6b9 1437{
c93bb85b 1438 struct drm_device *dev = crtc->dev;
5b1714d3 1439 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1440 struct drm_encoder *encoder;
1441 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1442 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1443 struct drm_connector *connector;
1444 struct radeon_connector *radeon_connector;
c93bb85b 1445 bool first = true;
d65d65b1
AD		 1446 u32 src_v = 1, dst_v = 1;
1447 u32 src_h = 1, dst_h = 1;
771fe6b9 1448
5b1714d3
AD		 1449 radeon_crtc->h_border = 0;
1450 radeon_crtc->v_border = 0;
1451
c93bb85b 1452 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1453 if (encoder->crtc != crtc)
1454 continue;
d65d65b1 1455 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1456 connector = radeon_get_connector_for_encoder(encoder);
1457 radeon_connector = to_radeon_connector(connector);
1458
c93bb85b 1459 if (first) {
80297e87
AD		 1460 /* set scaling */
1461 if (radeon_encoder->rmx_type == RMX_OFF)
1462 radeon_crtc->rmx_type = RMX_OFF;
1463 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1464 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1465 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1466 else
1467 radeon_crtc->rmx_type = RMX_OFF;
1468 /* copy native mode */
c93bb85b 1469 memcpy(&radeon_crtc->native_mode,
80297e87 1470 &radeon_encoder->native_mode,
de2103e4 1471 sizeof(struct drm_display_mode));
ff32a59d
AD		 1472 src_v = crtc->mode.vdisplay;
1473 dst_v = radeon_crtc->native_mode.vdisplay;
1474 src_h = crtc->mode.hdisplay;
1475 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1476
1477 /* fix up for overscan on hdmi */
1478 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1479 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1480 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1481 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1482 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1483 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1484 if (radeon_encoder->underscan_hborder != 0)
1485 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1486 else
1487 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1488 if (radeon_encoder->underscan_vborder != 0)
1489 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1490 else
1491 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1492 radeon_crtc->rmx_type = RMX_FULL;
1493 src_v = crtc->mode.vdisplay;
1494 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1495 src_h = crtc->mode.hdisplay;
1496 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1497 }
c93bb85b
JG		 1498 first = false;
1499 } else {
1500 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1501 /* WARNING: Right now this can't happen but
1502 * in the future we need to check that scaling
d65d65b1 1503 * are consistent across different encoder
c93bb85b
JG		 1504 * (ie all encoder can work with the same
1505 * scaling).
1506 */
d65d65b1 1507 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1508 return false;
1509 }
771fe6b9
JG		 1510 }
1511 }
c93bb85b
JG		 1512 if (radeon_crtc->rmx_type != RMX_OFF) {
1513 fixed20_12 a, b;
d65d65b1
AD		 1514 a.full = dfixed_const(src_v);
1515 b.full = dfixed_const(dst_v);
68adac5e 1516 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1517 a.full = dfixed_const(src_h);
1518 b.full = dfixed_const(dst_h);
68adac5e 1519 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1520 } else {
68adac5e
BS		 1521 radeon_crtc->vsc.full = dfixed_const(1);
1522 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1523 }
c93bb85b 1524 return true;
771fe6b9 1525}
6383cf7d
MK		 1526
1527/*
1528 * Retrieve current video scanout position of crtc on a given gpu.
1529 *
f5a80209 1530 * \param dev Device to query.
6383cf7d
MK		 1531 * \param crtc Crtc to query.
1532 * \param *vpos Location where vertical scanout position should be stored.
1533 * \param *hpos Location where horizontal scanout position should go.
1534 *
1535 * Returns vpos as a positive number while in active scanout area.
1536 * Returns vpos as a negative number inside vblank, counting the number
1537 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1538 * until start of active scanout / end of vblank."
1539 *
1540 * \return Flags, or'ed together as follows:
1541 *
25985edc 1542 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1543 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1544 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1545 * this flag means that returned position may be offset by a constant but
1546 * unknown small number of scanlines wrt. real scanout position.
1547 *
1548 */
f5a80209 1549int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
6383cf7d
MK		 1550{
1551 u32 stat_crtc = 0, vbl = 0, position = 0;
1552 int vbl_start, vbl_end, vtotal, ret = 0;
1553 bool in_vbl = true;
1554
f5a80209
MK		 1555 struct radeon_device *rdev = dev->dev_private;
1556
6383cf7d
MK		 1557 if (ASIC_IS_DCE4(rdev)) {
1558 if (crtc == 0) {
1559 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1560 EVERGREEN_CRTC0_REGISTER_OFFSET);
1561 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1562 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1563 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1564 }
1565 if (crtc == 1) {
1566 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1567 EVERGREEN_CRTC1_REGISTER_OFFSET);
1568 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1569 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1570 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1571 }
1572 if (crtc == 2) {
1573 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1574 EVERGREEN_CRTC2_REGISTER_OFFSET);
1575 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1576 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1577 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1578 }
1579 if (crtc == 3) {
1580 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1581 EVERGREEN_CRTC3_REGISTER_OFFSET);
1582 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1583 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1584 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1585 }
1586 if (crtc == 4) {
1587 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1588 EVERGREEN_CRTC4_REGISTER_OFFSET);
1589 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1590 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1591 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1592 }
1593 if (crtc == 5) {
1594 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1595 EVERGREEN_CRTC5_REGISTER_OFFSET);
1596 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1597 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1598 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1599 }
1600 } else if (ASIC_IS_AVIVO(rdev)) {
1601 if (crtc == 0) {
1602 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1603 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1604 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1605 }
1606 if (crtc == 1) {
1607 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1608 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1609 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1610 }
1611 } else {
1612 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1613 if (crtc == 0) {
1614 /* Assume vbl_end == 0, get vbl_start from
1615 * upper 16 bits.
1616 */
1617 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1618 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1619 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1620 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1621 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1622 if (!(stat_crtc & 1))
1623 in_vbl = false;
1624
f5a80209 1625 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1626 }
1627 if (crtc == 1) {
1628 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1629 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1630 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1631 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1632 if (!(stat_crtc & 1))
1633 in_vbl = false;
1634
f5a80209 1635 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1636 }
1637 }
1638
1639 /* Decode into vertical and horizontal scanout position. */
1640 *vpos = position & 0x1fff;
1641 *hpos = (position >> 16) & 0x1fff;
1642
1643 /* Valid vblank area boundaries from gpu retrieved? */
1644 if (vbl > 0) {
1645 /* Yes: Decode. */
f5a80209 1646 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1647 vbl_start = vbl & 0x1fff;
1648 vbl_end = (vbl >> 16) & 0x1fff;
1649 }
1650 else {
1651 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1652 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1653 vbl_end = 0;
1654 }
1655
1656 /* Test scanout position against vblank region. */
1657 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1658 in_vbl = false;
1659
1660 /* Check if inside vblank area and apply corrective offsets:
1661 * vpos will then be >=0 in video scanout area, but negative
1662 * within vblank area, counting down the number of lines until
1663 * start of scanout.
1664 */
1665
1666 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1667 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1668 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1669 *vpos = *vpos - vtotal;
1670 }
1671
1672 /* Correct for shifted end of vbl at vbl_end. */
1673 *vpos = *vpos - vbl_end;
1674
1675 /* In vblank? */
1676 if (in_vbl)
f5a80209 1677 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d
MK		 1678
1679 return ret;
1680}
Linux kernel - Deliverables
This page took 0.304386 seconds and 5 git commands to generate.