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drm/radeon: fix resuming mode in pm runtime resume path
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
10ebc0bc 33#include <linux/pm_runtime.h>
760285e7
DH		 34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_edid.h>
771fe6b9 36
771fe6b9
JG		 37static void avivo_crtc_load_lut(struct drm_crtc *crtc)
38{
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 struct drm_device *dev = crtc->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 int i;
43
d9fdaafb 44 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 45 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
46
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
50
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
54
55 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
56 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
57 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
58
59 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
60 for (i = 0; i < 256; i++) {
61 WREG32(AVIVO_DC_LUT_30_COLOR,
62 (radeon_crtc->lut_r[i] << 20) |
63 (radeon_crtc->lut_g[i] << 10) |
64 (radeon_crtc->lut_b[i] << 0));
65 }
66
67 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
68}
69
fee298fd 70static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 71{
72 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
73 struct drm_device *dev = crtc->dev;
74 struct radeon_device *rdev = dev->dev_private;
75 int i;
76
d9fdaafb 77 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 78 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
79
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
83
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
87
677d0768
AD		 88 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
89 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 90
677d0768 91 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 92 for (i = 0; i < 256; i++) {
677d0768 93 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 94 (radeon_crtc->lut_r[i] << 20) |
95 (radeon_crtc->lut_g[i] << 10) |
96 (radeon_crtc->lut_b[i] << 0));
97 }
98}
99
fee298fd
AD		 100static void dce5_crtc_load_lut(struct drm_crtc *crtc)
101{
102 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
103 struct drm_device *dev = crtc->dev;
104 struct radeon_device *rdev = dev->dev_private;
105 int i;
106
107 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
108
109 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
110 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
111 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
112 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
113 NI_GRPH_PRESCALE_BYPASS);
114 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
115 NI_OVL_PRESCALE_BYPASS);
116 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
117 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
118 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
119
120 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
121
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
125
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
129
130 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
131 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
132
133 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
134 for (i = 0; i < 256; i++) {
135 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
136 (radeon_crtc->lut_r[i] << 20) |
137 (radeon_crtc->lut_g[i] << 10) |
138 (radeon_crtc->lut_b[i] << 0));
139 }
140
141 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
142 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
146 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
147 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
148 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
149 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
151 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
152 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
153 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
154 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
155 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
156 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 157 if (ASIC_IS_DCE8(rdev)) {
158 /* XXX this only needs to be programmed once per crtc at startup,
159 * not sure where the best place for it is
160 */
161 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
162 CIK_CURSOR_ALPHA_BLND_ENA);
163 }
fee298fd
AD		 164}
165
771fe6b9
JG		 166static void legacy_crtc_load_lut(struct drm_crtc *crtc)
167{
168 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
169 struct drm_device *dev = crtc->dev;
170 struct radeon_device *rdev = dev->dev_private;
171 int i;
172 uint32_t dac2_cntl;
173
174 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
175 if (radeon_crtc->crtc_id == 0)
176 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
177 else
178 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
179 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
180
181 WREG8(RADEON_PALETTE_INDEX, 0);
182 for (i = 0; i < 256; i++) {
183 WREG32(RADEON_PALETTE_30_DATA,
184 (radeon_crtc->lut_r[i] << 20) |
185 (radeon_crtc->lut_g[i] << 10) |
186 (radeon_crtc->lut_b[i] << 0));
187 }
188}
189
190void radeon_crtc_load_lut(struct drm_crtc *crtc)
191{
192 struct drm_device *dev = crtc->dev;
193 struct radeon_device *rdev = dev->dev_private;
194
195 if (!crtc->enabled)
196 return;
197
fee298fd
AD		 198 if (ASIC_IS_DCE5(rdev))
199 dce5_crtc_load_lut(crtc);
200 else if (ASIC_IS_DCE4(rdev))
201 dce4_crtc_load_lut(crtc);
bcc1c2a1 202 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 203 avivo_crtc_load_lut(crtc);
204 else
205 legacy_crtc_load_lut(crtc);
206}
207
b8c00ac5 208/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 209void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
210 u16 blue, int regno)
211{
212 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
213
771fe6b9
JG		 214 radeon_crtc->lut_r[regno] = red >> 6;
215 radeon_crtc->lut_g[regno] = green >> 6;
216 radeon_crtc->lut_b[regno] = blue >> 6;
217}
218
b8c00ac5
DA		 219/** Gets the color ramps on behalf of fbcon */
220void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
221 u16 *blue, int regno)
222{
223 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
224
225 *red = radeon_crtc->lut_r[regno] << 6;
226 *green = radeon_crtc->lut_g[regno] << 6;
227 *blue = radeon_crtc->lut_b[regno] << 6;
228}
229
771fe6b9 230static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 231 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 232{
233 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 234 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 235
b8c00ac5 236 /* userspace palettes are always correct as is */
7203425a 237 for (i = start; i < end; i++) {
b8c00ac5
DA		 238 radeon_crtc->lut_r[i] = red[i] >> 6;
239 radeon_crtc->lut_g[i] = green[i] >> 6;
240 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 241 }
771fe6b9
JG		 242 radeon_crtc_load_lut(crtc);
243}
244
245static void radeon_crtc_destroy(struct drm_crtc *crtc)
246{
247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
248
771fe6b9
JG		 249 drm_crtc_cleanup(crtc);
250 kfree(radeon_crtc);
251}
252
6f34be50
AD		 253/*
254 * Handle unpin events outside the interrupt handler proper.
255 */
256static void radeon_unpin_work_func(struct work_struct *__work)
257{
258 struct radeon_unpin_work *work =
259 container_of(__work, struct radeon_unpin_work, work);
260 int r;
261
262 /* unpin of the old buffer */
263 r = radeon_bo_reserve(work->old_rbo, false);
264 if (likely(r == 0)) {
265 r = radeon_bo_unpin(work->old_rbo);
266 if (unlikely(r != 0)) {
267 DRM_ERROR("failed to unpin buffer after flip\n");
268 }
269 radeon_bo_unreserve(work->old_rbo);
270 } else
271 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 272
273 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 274 kfree(work);
275}
276
277void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
278{
279 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
280 struct radeon_unpin_work *work;
6f34be50
AD		 281 unsigned long flags;
282 u32 update_pending;
283 int vpos, hpos;
284
285 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
286 work = radeon_crtc->unpin_work;
287 if (work == NULL ||
fcc485d6 288 (work->fence && !radeon_fence_signaled(work->fence))) {
6f34be50
AD		 289 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
290 return;
291 }
292 /* New pageflip, or just completion of a previous one? */
293 if (!radeon_crtc->deferred_flip_completion) {
294 /* do the flip (mmio) */
295 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
296 } else {
297 /* This is just a completion of a flip queued in crtc
298 * at last invocation. Make sure we go directly to
299 * completion routine.
300 */
301 update_pending = 0;
302 radeon_crtc->deferred_flip_completion = 0;
303 }
304
305 /* Has the pageflip already completed in crtc, or is it certain
306 * to complete in this vblank?
307 */
308 if (update_pending &&
abca9e45 309 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
d47abc58 310 &vpos, &hpos, NULL, NULL)) &&
81ffbbed
FK		 311 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
312 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
313 /* crtc didn't flip in this target vblank interval,
314 * but flip is pending in crtc. Based on the current
315 * scanout position we know that the current frame is
316 * (nearly) complete and the flip will (likely)
317 * complete before the start of the next frame.
318 */
319 update_pending = 0;
320 }
321 if (update_pending) {
6f34be50
AD		 322 /* crtc didn't flip in this target vblank interval,
323 * but flip is pending in crtc. It will complete it
324 * in next vblank interval, so complete the flip at
325 * next vblank irq.
326 */
327 radeon_crtc->deferred_flip_completion = 1;
328 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
329 return;
330 }
331
332 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
333 radeon_crtc->unpin_work = NULL;
334
335 /* wakeup userspace */
26ae4667
RC		 336 if (work->event)
337 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
338
6f34be50
AD		 339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
340
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 schedule_work(&work->work);
345}
346
347static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
ed8d1975
KP		 349 struct drm_pending_vblank_event *event,
350 uint32_t page_flip_flags)
6f34be50
AD		 351{
352 struct drm_device *dev = crtc->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct radeon_framebuffer *old_radeon_fb;
356 struct radeon_framebuffer *new_radeon_fb;
357 struct drm_gem_object *obj;
358 struct radeon_bo *rbo;
6f34be50
AD		 359 struct radeon_unpin_work *work;
360 unsigned long flags;
361 u32 tiling_flags, pitch_pixels;
362 u64 base;
363 int r;
364
365 work = kzalloc(sizeof *work, GFP_KERNEL);
366 if (work == NULL)
367 return -ENOMEM;
368
6f34be50
AD		 369 work->event = event;
370 work->rdev = rdev;
371 work->crtc_id = radeon_crtc->crtc_id;
f4510a27 372 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
6f34be50
AD		 373 new_radeon_fb = to_radeon_framebuffer(fb);
374 /* schedule unpin of the old buffer */
375 obj = old_radeon_fb->obj;
498c555f
DA		 376 /* take a reference to the old object */
377 drm_gem_object_reference(obj);
7e4d15d9 378 rbo = gem_to_radeon_bo(obj);
6f34be50 379 work->old_rbo = rbo;
fcc485d6
MD		 380 obj = new_radeon_fb->obj;
381 rbo = gem_to_radeon_bo(obj);
9af20792
DV		 382
383 spin_lock(&rbo->tbo.bdev->fence_lock);
fcc485d6
MD		 384 if (rbo->tbo.sync_obj)
385 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
9af20792
DV		 386 spin_unlock(&rbo->tbo.bdev->fence_lock);
387
6f34be50
AD		 388 INIT_WORK(&work->work, radeon_unpin_work_func);
389
390 /* We borrow the event spin lock for protecting unpin_work */
391 spin_lock_irqsave(&dev->event_lock, flags);
392 if (radeon_crtc->unpin_work) {
6f34be50 393 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
498c555f
DA		 394 r = -EBUSY;
395 goto unlock_free;
6f34be50
AD		 396 }
397 radeon_crtc->unpin_work = work;
398 radeon_crtc->deferred_flip_completion = 0;
399 spin_unlock_irqrestore(&dev->event_lock, flags);
400
401 /* pin the new buffer */
6f34be50
AD		 402 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
403 work->old_rbo, rbo);
404
405 r = radeon_bo_reserve(rbo, false);
406 if (unlikely(r != 0)) {
407 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
408 goto pflip_cleanup;
409 }
0349af70
MD		 410 /* Only 27 bit offset for legacy CRTC */
411 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
412 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50
AD		 413 if (unlikely(r != 0)) {
414 radeon_bo_unreserve(rbo);
415 r = -EINVAL;
416 DRM_ERROR("failed to pin new rbo buffer before flip\n");
417 goto pflip_cleanup;
418 }
419 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
420 radeon_bo_unreserve(rbo);
421
422 if (!ASIC_IS_AVIVO(rdev)) {
423 /* crtc offset is from display base addr not FB location */
424 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 425 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 426
427 if (tiling_flags & RADEON_TILING_MACRO) {
428 if (ASIC_IS_R300(rdev)) {
429 base &= ~0x7ff;
430 } else {
431 int byteshift = fb->bits_per_pixel >> 4;
432 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
433 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
434 }
435 } else {
436 int offset = crtc->y * pitch_pixels + crtc->x;
437 switch (fb->bits_per_pixel) {
438 case 8:
439 default:
440 offset *= 1;
441 break;
442 case 15:
443 case 16:
444 offset *= 2;
445 break;
446 case 24:
447 offset *= 3;
448 break;
449 case 32:
450 offset *= 4;
451 break;
452 }
453 base += offset;
454 }
455 base &= ~7;
456 }
457
458 spin_lock_irqsave(&dev->event_lock, flags);
459 work->new_crtc_base = base;
460 spin_unlock_irqrestore(&dev->event_lock, flags);
461
462 /* update crtc fb */
f4510a27 463 crtc->primary->fb = fb;
6f34be50
AD		 464
465 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
466 if (r) {
467 DRM_ERROR("failed to get vblank before flip\n");
468 goto pflip_cleanup1;
469 }
470
6f34be50
AD		 471 /* set the proper interrupt */
472 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
6f34be50
AD		 473
474 return 0;
475
6f34be50 476pflip_cleanup1:
d0254d56 477 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
6f34be50
AD		 478 DRM_ERROR("failed to reserve new rbo in error path\n");
479 goto pflip_cleanup;
480 }
d0254d56 481 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
6f34be50 482 DRM_ERROR("failed to unpin new rbo in error path\n");
6f34be50
AD		 483 }
484 radeon_bo_unreserve(rbo);
485
486pflip_cleanup:
487 spin_lock_irqsave(&dev->event_lock, flags);
488 radeon_crtc->unpin_work = NULL;
498c555f 489unlock_free:
6f34be50 490 spin_unlock_irqrestore(&dev->event_lock, flags);
db318d7a 491 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
fcc485d6 492 radeon_fence_unref(&work->fence);
6f34be50
AD		 493 kfree(work);
494
495 return r;
496}
497
10ebc0bc
DA		 498static int
499radeon_crtc_set_config(struct drm_mode_set *set)
500{
501 struct drm_device *dev;
502 struct radeon_device *rdev;
503 struct drm_crtc *crtc;
504 bool active = false;
505 int ret;
506
507 if (!set || !set->crtc)
508 return -EINVAL;
509
510 dev = set->crtc->dev;
511
512 ret = pm_runtime_get_sync(dev->dev);
513 if (ret < 0)
514 return ret;
515
516 ret = drm_crtc_helper_set_config(set);
517
518 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
519 if (crtc->enabled)
520 active = true;
521
522 pm_runtime_mark_last_busy(dev->dev);
523
524 rdev = dev->dev_private;
525 /* if we have active crtcs and we don't have a power ref,
526 take the current one */
527 if (active && !rdev->have_disp_power_ref) {
528 rdev->have_disp_power_ref = true;
529 return ret;
530 }
531 /* if we have no active crtcs, then drop the power ref
532 we got before */
533 if (!active && rdev->have_disp_power_ref) {
534 pm_runtime_put_autosuspend(dev->dev);
535 rdev->have_disp_power_ref = false;
536 }
537
538 /* drop the power reference we got coming in here */
539 pm_runtime_put_autosuspend(dev->dev);
540 return ret;
541}
771fe6b9
JG		 542static const struct drm_crtc_funcs radeon_crtc_funcs = {
543 .cursor_set = radeon_crtc_cursor_set,
544 .cursor_move = radeon_crtc_cursor_move,
545 .gamma_set = radeon_crtc_gamma_set,
10ebc0bc 546 .set_config = radeon_crtc_set_config,
771fe6b9 547 .destroy = radeon_crtc_destroy,
6f34be50 548 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 549};
550
551static void radeon_crtc_init(struct drm_device *dev, int index)
552{
553 struct radeon_device *rdev = dev->dev_private;
554 struct radeon_crtc *radeon_crtc;
555 int i;
556
557 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
558 if (radeon_crtc == NULL)
559 return;
560
561 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
562
563 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
564 radeon_crtc->crtc_id = index;
c93bb85b 565 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 566
9e05fa1d
AD		 567 if (rdev->family >= CHIP_BONAIRE) {
568 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
569 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
570 } else {
571 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
572 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
573 }
bea61c59
AD		 574 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
575 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
9e05fa1d 576
785b93ef 577#if 0
771fe6b9
JG		 578 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
579 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
580 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 581#endif
771fe6b9
JG		 582
583 for (i = 0; i < 256; i++) {
584 radeon_crtc->lut_r[i] = i << 2;
585 radeon_crtc->lut_g[i] = i << 2;
586 radeon_crtc->lut_b[i] = i << 2;
587 }
588
589 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
590 radeon_atombios_init_crtc(dev, radeon_crtc);
591 else
592 radeon_legacy_init_crtc(dev, radeon_crtc);
593}
594
e68adef8 595static const char *encoder_names[38] = {
771fe6b9
JG		 596 "NONE",
597 "INTERNAL_LVDS",
598 "INTERNAL_TMDS1",
599 "INTERNAL_TMDS2",
600 "INTERNAL_DAC1",
601 "INTERNAL_DAC2",
602 "INTERNAL_SDVOA",
603 "INTERNAL_SDVOB",
604 "SI170B",
605 "CH7303",
606 "CH7301",
607 "INTERNAL_DVO1",
608 "EXTERNAL_SDVOA",
609 "EXTERNAL_SDVOB",
610 "TITFP513",
611 "INTERNAL_LVTM1",
612 "VT1623",
613 "HDMI_SI1930",
614 "HDMI_INTERNAL",
615 "INTERNAL_KLDSCP_TMDS1",
616 "INTERNAL_KLDSCP_DVO1",
617 "INTERNAL_KLDSCP_DAC1",
618 "INTERNAL_KLDSCP_DAC2",
619 "SI178",
620 "MVPU_FPGA",
621 "INTERNAL_DDI",
622 "VT1625",
623 "HDMI_SI1932",
624 "DP_AN9801",
625 "DP_DP501",
626 "INTERNAL_UNIPHY",
627 "INTERNAL_KLDSCP_LVTMA",
628 "INTERNAL_UNIPHY1",
629 "INTERNAL_UNIPHY2",
bf982ebf
AD		 630 "NUTMEG",
631 "TRAVIS",
e68adef8
AD		 632 "INTERNAL_VCE",
633 "INTERNAL_UNIPHY3",
771fe6b9
JG		 634};
635
cbd4623d 636static const char *hpd_names[6] = {
eed45b30
AD		 637 "HPD1",
638 "HPD2",
639 "HPD3",
640 "HPD4",
641 "HPD5",
642 "HPD6",
643};
644
771fe6b9
JG		 645static void radeon_print_display_setup(struct drm_device *dev)
646{
647 struct drm_connector *connector;
648 struct radeon_connector *radeon_connector;
649 struct drm_encoder *encoder;
650 struct radeon_encoder *radeon_encoder;
651 uint32_t devices;
652 int i = 0;
653
654 DRM_INFO("Radeon Display Connectors\n");
655 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
656 radeon_connector = to_radeon_connector(connector);
657 DRM_INFO("Connector %d:\n", i);
c1d2dbd2 658 DRM_INFO(" %s\n", drm_get_connector_name(connector));
eed45b30
AD		 659 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
660 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 661 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 662 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
663 radeon_connector->ddc_bus->rec.mask_clk_reg,
664 radeon_connector->ddc_bus->rec.mask_data_reg,
665 radeon_connector->ddc_bus->rec.a_clk_reg,
666 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 667 radeon_connector->ddc_bus->rec.en_clk_reg,
668 radeon_connector->ddc_bus->rec.en_data_reg,
669 radeon_connector->ddc_bus->rec.y_clk_reg,
670 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 671 if (radeon_connector->router.ddc_valid)
26b5bc98 672 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 673 radeon_connector->router.ddc_mux_control_pin,
674 radeon_connector->router.ddc_mux_state);
675 if (radeon_connector->router.cd_valid)
676 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
677 radeon_connector->router.cd_mux_control_pin,
678 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 679 } else {
680 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
681 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
682 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
683 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
684 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
685 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
686 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
687 }
771fe6b9
JG		 688 DRM_INFO(" Encoders:\n");
689 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
690 radeon_encoder = to_radeon_encoder(encoder);
691 devices = radeon_encoder->devices & radeon_connector->devices;
692 if (devices) {
693 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
694 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
695 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
696 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
697 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
698 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
699 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
700 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
701 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
702 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
703 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
704 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
705 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
706 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
707 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
708 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 709 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
710 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 711 if (devices & ATOM_DEVICE_TV1_SUPPORT)
712 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
713 if (devices & ATOM_DEVICE_CV_SUPPORT)
714 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
715 }
716 }
717 i++;
718 }
719}
720
4ce001ab 721static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 722{
723 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 724 bool ret = false;
725
726 if (rdev->bios) {
727 if (rdev->is_atom_bios) {
a084e6ee
AD		 728 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
729 if (ret == false)
771fe6b9 730 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 731 } else {
771fe6b9 732 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 733 if (ret == false)
734 ret = radeon_get_legacy_connector_info_from_table(dev);
735 }
771fe6b9
JG		 736 } else {
737 if (!ASIC_IS_AVIVO(rdev))
738 ret = radeon_get_legacy_connector_info_from_table(dev);
739 }
740 if (ret) {
1f3b6a45 741 radeon_setup_encoder_clones(dev);
771fe6b9 742 radeon_print_display_setup(dev);
771fe6b9
JG		 743 }
744
745 return ret;
746}
747
748int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
749{
3c537889
AD		 750 struct drm_device *dev = radeon_connector->base.dev;
751 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 752 int ret = 0;
753
26b5bc98 754 /* on hw with routers, select right port */
fb939dfc
AD		 755 if (radeon_connector->router.ddc_valid)
756 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 757
0a9069d3
NOS		 758 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
759 ENCODER_OBJECT_ID_NONE) {
760 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
761
762 if (dig->dp_i2c_bus)
763 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
764 &dig->dp_i2c_bus->adapter);
765 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
766 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 767 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
b06947b5 768
7a15cbd4
DA		 769 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
770 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
b06947b5
AD		 771 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
772 &dig->dp_i2c_bus->adapter);
773 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
774 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
775 &radeon_connector->ddc_bus->adapter);
776 } else {
777 if (radeon_connector->ddc_bus && !radeon_connector->edid)
778 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
779 &radeon_connector->ddc_bus->adapter);
0294cf4f 780 }
c324acd5
AD		 781
782 if (!radeon_connector->edid) {
783 if (rdev->is_atom_bios) {
784 /* some laptops provide a hardcoded edid in rom for LCDs */
785 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
786 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
787 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
788 } else
789 /* some servers provide a hardcoded edid in rom for KVMs */
790 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
791 }
0294cf4f
AD		 792 if (radeon_connector->edid) {
793 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
794 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 795 return ret;
796 }
797 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 798 return 0;
771fe6b9
JG		 799}
800
f523f74e
AD		 801/* avivo */
802static void avivo_get_fb_div(struct radeon_pll *pll,
803 u32 target_clock,
804 u32 post_div,
805 u32 ref_div,
806 u32 *fb_div,
807 u32 *frac_fb_div)
808{
809 u32 tmp = post_div * ref_div;
810
811 tmp *= target_clock;
812 *fb_div = tmp / pll->reference_freq;
813 *frac_fb_div = tmp % pll->reference_freq;
a4b40d5d
AD		 814
815 if (*fb_div > pll->max_feedback_div)
816 *fb_div = pll->max_feedback_div;
817 else if (*fb_div < pll->min_feedback_div)
818 *fb_div = pll->min_feedback_div;
f523f74e
AD		 819}
820
821static u32 avivo_get_post_div(struct radeon_pll *pll,
822 u32 target_clock)
823{
824 u32 vco, post_div, tmp;
825
826 if (pll->flags & RADEON_PLL_USE_POST_DIV)
827 return pll->post_div;
828
829 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
830 if (pll->flags & RADEON_PLL_IS_LCD)
831 vco = pll->lcd_pll_out_min;
832 else
833 vco = pll->pll_out_min;
834 } else {
835 if (pll->flags & RADEON_PLL_IS_LCD)
836 vco = pll->lcd_pll_out_max;
837 else
838 vco = pll->pll_out_max;
839 }
840
841 post_div = vco / target_clock;
842 tmp = vco % target_clock;
843
844 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
845 if (tmp)
846 post_div++;
847 } else {
848 if (!tmp)
849 post_div--;
850 }
851
a4b40d5d
AD		 852 if (post_div > pll->max_post_div)
853 post_div = pll->max_post_div;
854 else if (post_div < pll->min_post_div)
855 post_div = pll->min_post_div;
856
f523f74e
AD		 857 return post_div;
858}
859
860#define MAX_TOLERANCE 10
861
862void radeon_compute_pll_avivo(struct radeon_pll *pll,
863 u32 freq,
864 u32 *dot_clock_p,
865 u32 *fb_div_p,
866 u32 *frac_fb_div_p,
867 u32 *ref_div_p,
868 u32 *post_div_p)
869{
870 u32 target_clock = freq / 10;
871 u32 post_div = avivo_get_post_div(pll, target_clock);
872 u32 ref_div = pll->min_ref_div;
873 u32 fb_div = 0, frac_fb_div = 0, tmp;
874
875 if (pll->flags & RADEON_PLL_USE_REF_DIV)
876 ref_div = pll->reference_div;
877
878 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
879 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
880 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
881 if (frac_fb_div >= 5) {
882 frac_fb_div -= 5;
883 frac_fb_div = frac_fb_div / 10;
884 frac_fb_div++;
885 }
886 if (frac_fb_div >= 10) {
887 fb_div++;
888 frac_fb_div = 0;
889 }
890 } else {
891 while (ref_div <= pll->max_ref_div) {
892 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
893 &fb_div, &frac_fb_div);
894 if (frac_fb_div >= (pll->reference_freq / 2))
895 fb_div++;
896 frac_fb_div = 0;
897 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
898 tmp = (tmp * 10000) / target_clock;
899
900 if (tmp > (10000 + MAX_TOLERANCE))
901 ref_div++;
902 else if (tmp >= (10000 - MAX_TOLERANCE))
903 break;
904 else
905 ref_div++;
906 }
907 }
908
909 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
910 (ref_div * post_div * 10);
911 *fb_div_p = fb_div;
912 *frac_fb_div_p = frac_fb_div;
913 *ref_div_p = ref_div;
914 *post_div_p = post_div;
915 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
916 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
917}
918
919/* pre-avivo */
771fe6b9
JG		 920static inline uint32_t radeon_div(uint64_t n, uint32_t d)
921{
922 uint64_t mod;
923
924 n += d / 2;
925
926 mod = do_div(n, d);
927 return n;
928}
929
f523f74e
AD		 930void radeon_compute_pll_legacy(struct radeon_pll *pll,
931 uint64_t freq,
932 uint32_t *dot_clock_p,
933 uint32_t *fb_div_p,
934 uint32_t *frac_fb_div_p,
935 uint32_t *ref_div_p,
936 uint32_t *post_div_p)
771fe6b9
JG		 937{
938 uint32_t min_ref_div = pll->min_ref_div;
939 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 940 uint32_t min_post_div = pll->min_post_div;
941 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 942 uint32_t min_fractional_feed_div = 0;
943 uint32_t max_fractional_feed_div = 0;
944 uint32_t best_vco = pll->best_vco;
945 uint32_t best_post_div = 1;
946 uint32_t best_ref_div = 1;
947 uint32_t best_feedback_div = 1;
948 uint32_t best_frac_feedback_div = 0;
949 uint32_t best_freq = -1;
950 uint32_t best_error = 0xffffffff;
951 uint32_t best_vco_diff = 1;
952 uint32_t post_div;
86cb2bbf 953 u32 pll_out_min, pll_out_max;
771fe6b9 954
d9fdaafb 955 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 956 freq = freq * 1000;
957
86cb2bbf
AD		 958 if (pll->flags & RADEON_PLL_IS_LCD) {
959 pll_out_min = pll->lcd_pll_out_min;
960 pll_out_max = pll->lcd_pll_out_max;
961 } else {
962 pll_out_min = pll->pll_out_min;
963 pll_out_max = pll->pll_out_max;
964 }
965
619efb10
AD		 966 if (pll_out_min > 64800)
967 pll_out_min = 64800;
968
fc10332b 969 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 970 min_ref_div = max_ref_div = pll->reference_div;
971 else {
972 while (min_ref_div < max_ref_div-1) {
973 uint32_t mid = (min_ref_div + max_ref_div) / 2;
974 uint32_t pll_in = pll->reference_freq / mid;
975 if (pll_in < pll->pll_in_min)
976 max_ref_div = mid;
977 else if (pll_in > pll->pll_in_max)
978 min_ref_div = mid;
979 else
980 break;
981 }
982 }
983
fc10332b
AD		 984 if (pll->flags & RADEON_PLL_USE_POST_DIV)
985 min_post_div = max_post_div = pll->post_div;
986
987 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 988 min_fractional_feed_div = pll->min_frac_feedback_div;
989 max_fractional_feed_div = pll->max_frac_feedback_div;
990 }
991
bd6a60af 992 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 993 uint32_t ref_div;
994
fc10332b 995 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 996 continue;
997
998 /* legacy radeons only have a few post_divs */
fc10332b 999 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 1000 if ((post_div == 5) ||
1001 (post_div == 7) ||
1002 (post_div == 9) ||
1003 (post_div == 10) ||
1004 (post_div == 11) ||
1005 (post_div == 13) ||
1006 (post_div == 14) ||
1007 (post_div == 15))
1008 continue;
1009 }
1010
1011 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1012 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1013 uint32_t pll_in = pll->reference_freq / ref_div;
1014 uint32_t min_feed_div = pll->min_feedback_div;
1015 uint32_t max_feed_div = pll->max_feedback_div + 1;
1016
1017 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1018 continue;
1019
1020 while (min_feed_div < max_feed_div) {
1021 uint32_t vco;
1022 uint32_t min_frac_feed_div = min_fractional_feed_div;
1023 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1024 uint32_t frac_feedback_div;
1025 uint64_t tmp;
1026
1027 feedback_div = (min_feed_div + max_feed_div) / 2;
1028
1029 tmp = (uint64_t)pll->reference_freq * feedback_div;
1030 vco = radeon_div(tmp, ref_div);
1031
86cb2bbf 1032 if (vco < pll_out_min) {
771fe6b9
JG		 1033 min_feed_div = feedback_div + 1;
1034 continue;
86cb2bbf 1035 } else if (vco > pll_out_max) {
771fe6b9
JG		 1036 max_feed_div = feedback_div;
1037 continue;
1038 }
1039
1040 while (min_frac_feed_div < max_frac_feed_div) {
1041 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1042 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1043 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1044 current_freq = radeon_div(tmp, ref_div * post_div);
1045
fc10332b 1046 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 1047 if (freq < current_freq)
1048 error = 0xffffffff;
1049 else
1050 error = freq - current_freq;
d0e275a9
AD		 1051 } else
1052 error = abs(current_freq - freq);
771fe6b9
JG		 1053 vco_diff = abs(vco - best_vco);
1054
1055 if ((best_vco == 0 && error < best_error) ||
1056 (best_vco != 0 &&
167ffc44 1057 ((best_error > 100 && error < best_error - 100) ||
5480f727 1058 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1059 best_post_div = post_div;
1060 best_ref_div = ref_div;
1061 best_feedback_div = feedback_div;
1062 best_frac_feedback_div = frac_feedback_div;
1063 best_freq = current_freq;
1064 best_error = error;
1065 best_vco_diff = vco_diff;
5480f727
DA		 1066 } else if (current_freq == freq) {
1067 if (best_freq == -1) {
1068 best_post_div = post_div;
1069 best_ref_div = ref_div;
1070 best_feedback_div = feedback_div;
1071 best_frac_feedback_div = frac_feedback_div;
1072 best_freq = current_freq;
1073 best_error = error;
1074 best_vco_diff = vco_diff;
1075 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1076 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1077 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1078 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1079 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1080 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1081 best_post_div = post_div;
1082 best_ref_div = ref_div;
1083 best_feedback_div = feedback_div;
1084 best_frac_feedback_div = frac_feedback_div;
1085 best_freq = current_freq;
1086 best_error = error;
1087 best_vco_diff = vco_diff;
1088 }
771fe6b9
JG		 1089 }
1090 if (current_freq < freq)
1091 min_frac_feed_div = frac_feedback_div + 1;
1092 else
1093 max_frac_feed_div = frac_feedback_div;
1094 }
1095 if (current_freq < freq)
1096 min_feed_div = feedback_div + 1;
1097 else
1098 max_feed_div = feedback_div;
1099 }
1100 }
1101 }
1102
1103 *dot_clock_p = best_freq / 10000;
1104 *fb_div_p = best_feedback_div;
1105 *frac_fb_div_p = best_frac_feedback_div;
1106 *ref_div_p = best_ref_div;
1107 *post_div_p = best_post_div;
bbb0aef5
JP		 1108 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1109 (long long)freq,
1110 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1111 best_ref_div, best_post_div);
1112
771fe6b9
JG		 1113}
1114
1115static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1116{
1117 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1118
29d08b3e 1119 if (radeon_fb->obj) {
bc9025bd 1120 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1121 }
771fe6b9
JG		 1122 drm_framebuffer_cleanup(fb);
1123 kfree(radeon_fb);
1124}
1125
1126static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1127 struct drm_file *file_priv,
1128 unsigned int *handle)
1129{
1130 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1131
1132 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1133}
1134
1135static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1136 .destroy = radeon_user_framebuffer_destroy,
1137 .create_handle = radeon_user_framebuffer_create_handle,
1138};
1139
aaefcd42 1140int
38651674
DA		 1141radeon_framebuffer_init(struct drm_device *dev,
1142 struct radeon_framebuffer *rfb,
308e5bcb 1143 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1144 struct drm_gem_object *obj)
771fe6b9 1145{
aaefcd42 1146 int ret;
38651674 1147 rfb->obj = obj;
c7d73f6a 1148 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1149 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1150 if (ret) {
1151 rfb->obj = NULL;
1152 return ret;
1153 }
aaefcd42 1154 return 0;
771fe6b9
JG		 1155}
1156
1157static struct drm_framebuffer *
1158radeon_user_framebuffer_create(struct drm_device *dev,
1159 struct drm_file *file_priv,
308e5bcb 1160 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1161{
1162 struct drm_gem_object *obj;
38651674 1163 struct radeon_framebuffer *radeon_fb;
aaefcd42 1164 int ret;
771fe6b9 1165
308e5bcb 1166 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1167 if (obj == NULL) {
1168 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1169 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1170 return ERR_PTR(-ENOENT);
7e71c9e2 1171 }
38651674
DA		 1172
1173 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1174 if (radeon_fb == NULL) {
1175 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1176 return ERR_PTR(-ENOMEM);
f2d68cf4 1177 }
38651674 1178
aaefcd42
DA		 1179 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1180 if (ret) {
1181 kfree(radeon_fb);
1182 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1183 return ERR_PTR(ret);
aaefcd42 1184 }
38651674
DA		 1185
1186 return &radeon_fb->base;
771fe6b9
JG		 1187}
1188
eb1f8e4f
DA		 1189static void radeon_output_poll_changed(struct drm_device *dev)
1190{
1191 struct radeon_device *rdev = dev->dev_private;
1192 radeon_fb_output_poll_changed(rdev);
1193}
1194
771fe6b9
JG		 1195static const struct drm_mode_config_funcs radeon_mode_funcs = {
1196 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1197 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1198};
1199
445282db
DA		 1200static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1201{ { 0, "driver" },
1202 { 1, "bios" },
1203};
1204
1205static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1206{ { TV_STD_NTSC, "ntsc" },
1207 { TV_STD_PAL, "pal" },
1208 { TV_STD_PAL_M, "pal-m" },
1209 { TV_STD_PAL_60, "pal-60" },
1210 { TV_STD_NTSC_J, "ntsc-j" },
1211 { TV_STD_SCART_PAL, "scart-pal" },
1212 { TV_STD_PAL_CN, "pal-cn" },
1213 { TV_STD_SECAM, "secam" },
1214};
1215
5b1714d3
AD		 1216static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1217{ { UNDERSCAN_OFF, "off" },
1218 { UNDERSCAN_ON, "on" },
1219 { UNDERSCAN_AUTO, "auto" },
1220};
1221
8666c076
AD		 1222static struct drm_prop_enum_list radeon_audio_enum_list[] =
1223{ { RADEON_AUDIO_DISABLE, "off" },
1224 { RADEON_AUDIO_ENABLE, "on" },
1225 { RADEON_AUDIO_AUTO, "auto" },
1226};
1227
6214bb74
AD		 1228/* XXX support different dither options? spatial, temporal, both, etc. */
1229static struct drm_prop_enum_list radeon_dither_enum_list[] =
1230{ { RADEON_FMT_DITHER_DISABLE, "off" },
1231 { RADEON_FMT_DITHER_ENABLE, "on" },
1232};
1233
d79766fa 1234static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1235{
4a67d391 1236 int sz;
445282db
DA		 1237
1238 if (rdev->is_atom_bios) {
1239 rdev->mode_info.coherent_mode_property =
d9bc3c02 1240 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1241 if (!rdev->mode_info.coherent_mode_property)
1242 return -ENOMEM;
445282db
DA		 1243 }
1244
1245 if (!ASIC_IS_AVIVO(rdev)) {
1246 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1247 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1248 drm_property_create_enum(rdev->ddev, 0,
1249 "tmds_pll",
1250 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1251 }
1252
1253 rdev->mode_info.load_detect_property =
d9bc3c02 1254 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1255 if (!rdev->mode_info.load_detect_property)
1256 return -ENOMEM;
445282db
DA		 1257
1258 drm_mode_create_scaling_mode_property(rdev->ddev);
1259
1260 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1261 rdev->mode_info.tv_std_property =
4a67d391
SH		 1262 drm_property_create_enum(rdev->ddev, 0,
1263 "tv standard",
1264 radeon_tv_std_enum_list, sz);
445282db 1265
5b1714d3
AD		 1266 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1267 rdev->mode_info.underscan_property =
4a67d391
SH		 1268 drm_property_create_enum(rdev->ddev, 0,
1269 "underscan",
1270 radeon_underscan_enum_list, sz);
5b1714d3 1271
5bccf5e3 1272 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1273 drm_property_create_range(rdev->ddev, 0,
1274 "underscan hborder", 0, 128);
5bccf5e3
MG		 1275 if (!rdev->mode_info.underscan_hborder_property)
1276 return -ENOMEM;
5bccf5e3
MG		 1277
1278 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1279 drm_property_create_range(rdev->ddev, 0,
1280 "underscan vborder", 0, 128);
5bccf5e3
MG		 1281 if (!rdev->mode_info.underscan_vborder_property)
1282 return -ENOMEM;
5bccf5e3 1283
8666c076
AD		 1284 sz = ARRAY_SIZE(radeon_audio_enum_list);
1285 rdev->mode_info.audio_property =
1286 drm_property_create_enum(rdev->ddev, 0,
1287 "audio",
1288 radeon_audio_enum_list, sz);
1289
6214bb74
AD		 1290 sz = ARRAY_SIZE(radeon_dither_enum_list);
1291 rdev->mode_info.dither_property =
1292 drm_property_create_enum(rdev->ddev, 0,
1293 "dither",
1294 radeon_dither_enum_list, sz);
1295
445282db
DA		 1296 return 0;
1297}
1298
f46c0120
AD		 1299void radeon_update_display_priority(struct radeon_device *rdev)
1300{
1301 /* adjustment options for the display watermarks */
1302 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1303 /* set display priority to high for r3xx, rv515 chips
1304 * this avoids flickering due to underflow to the
1305 * display controllers during heavy acceleration.
45737447
AD		 1306 * Don't force high on rs4xx igp chips as it seems to
1307 * affect the sound card. See kernel bug 15982.
f46c0120 1308 */
45737447
AD		 1309 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1310 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1311 rdev->disp_priority = 2;
1312 else
1313 rdev->disp_priority = 0;
1314 } else
1315 rdev->disp_priority = radeon_disp_priority;
1316
1317}
1318
0783986a
AD		 1319/*
1320 * Allocate hdmi structs and determine register offsets
1321 */
1322static void radeon_afmt_init(struct radeon_device *rdev)
1323{
1324 int i;
1325
1326 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1327 rdev->mode_info.afmt[i] = NULL;
1328
b530602f
AD		 1329 if (ASIC_IS_NODCE(rdev)) {
1330 /* nothing to do */
0783986a 1331 } else if (ASIC_IS_DCE4(rdev)) {
a4d39e68
RM		 1332 static uint32_t eg_offsets[] = {
1333 EVERGREEN_CRTC0_REGISTER_OFFSET,
1334 EVERGREEN_CRTC1_REGISTER_OFFSET,
1335 EVERGREEN_CRTC2_REGISTER_OFFSET,
1336 EVERGREEN_CRTC3_REGISTER_OFFSET,
1337 EVERGREEN_CRTC4_REGISTER_OFFSET,
1338 EVERGREEN_CRTC5_REGISTER_OFFSET,
b530602f 1339 0x13830 - 0x7030,
a4d39e68
RM		 1340 };
1341 int num_afmt;
1342
b530602f
AD		 1343 /* DCE8 has 7 audio blocks tied to DIG encoders */
1344 /* DCE6 has 6 audio blocks tied to DIG encoders */
0783986a
AD		 1345 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1346 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
b530602f
AD		 1347 if (ASIC_IS_DCE8(rdev))
1348 num_afmt = 7;
1349 else if (ASIC_IS_DCE6(rdev))
1350 num_afmt = 6;
1351 else if (ASIC_IS_DCE5(rdev))
a4d39e68
RM		 1352 num_afmt = 6;
1353 else if (ASIC_IS_DCE41(rdev))
1354 num_afmt = 2;
1355 else /* DCE4 */
1356 num_afmt = 6;
1357
1358 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1359 for (i = 0; i < num_afmt; i++) {
1360 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1361 if (rdev->mode_info.afmt[i]) {
1362 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1363 rdev->mode_info.afmt[i]->id = i;
0783986a
AD		 1364 }
1365 }
1366 } else if (ASIC_IS_DCE3(rdev)) {
1367 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1368 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1369 if (rdev->mode_info.afmt[0]) {
1370 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1371 rdev->mode_info.afmt[0]->id = 0;
1372 }
1373 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1374 if (rdev->mode_info.afmt[1]) {
1375 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1376 rdev->mode_info.afmt[1]->id = 1;
1377 }
1378 } else if (ASIC_IS_DCE2(rdev)) {
1379 /* DCE2 has at least 1 routable audio block */
1380 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1381 if (rdev->mode_info.afmt[0]) {
1382 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1383 rdev->mode_info.afmt[0]->id = 0;
1384 }
1385 /* r6xx has 2 routable audio blocks */
1386 if (rdev->family >= CHIP_R600) {
1387 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1388 if (rdev->mode_info.afmt[1]) {
1389 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1390 rdev->mode_info.afmt[1]->id = 1;
1391 }
1392 }
1393 }
1394}
1395
1396static void radeon_afmt_fini(struct radeon_device *rdev)
1397{
1398 int i;
1399
1400 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1401 kfree(rdev->mode_info.afmt[i]);
1402 rdev->mode_info.afmt[i] = NULL;
1403 }
1404}
1405
771fe6b9
JG		 1406int radeon_modeset_init(struct radeon_device *rdev)
1407{
18917b60 1408 int i;
771fe6b9
JG		 1409 int ret;
1410
1411 drm_mode_config_init(rdev->ddev);
1412 rdev->mode_info.mode_config_initialized = true;
1413
e6ecefaa 1414 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1415
881dd74e
AD		 1416 if (ASIC_IS_DCE5(rdev)) {
1417 rdev->ddev->mode_config.max_width = 16384;
1418 rdev->ddev->mode_config.max_height = 16384;
1419 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1420 rdev->ddev->mode_config.max_width = 8192;
1421 rdev->ddev->mode_config.max_height = 8192;
1422 } else {
1423 rdev->ddev->mode_config.max_width = 4096;
1424 rdev->ddev->mode_config.max_height = 4096;
1425 }
1426
019d96cb
DA		 1427 rdev->ddev->mode_config.preferred_depth = 24;
1428 rdev->ddev->mode_config.prefer_shadow = 1;
1429
771fe6b9
JG		 1430 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1431
445282db
DA		 1432 ret = radeon_modeset_create_props(rdev);
1433 if (ret) {
1434 return ret;
1435 }
dfee5614 1436
f376b94f
AD		 1437 /* init i2c buses */
1438 radeon_i2c_init(rdev);
1439
3c537889
AD		 1440 /* check combios for a valid hardcoded EDID - Sun servers */
1441 if (!rdev->is_atom_bios) {
1442 /* check for hardcoded EDID in BIOS */
1443 radeon_combios_check_hardcoded_edid(rdev);
1444 }
1445
dfee5614 1446 /* allocate crtcs */
18917b60 1447 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1448 radeon_crtc_init(rdev->ddev, i);
1449 }
1450
1451 /* okay we should have all the bios connectors */
1452 ret = radeon_setup_enc_conn(rdev->ddev);
1453 if (!ret) {
1454 return ret;
1455 }
ac89af1e 1456
3fa47d9e
AD		 1457 /* init dig PHYs, disp eng pll */
1458 if (rdev->is_atom_bios) {
ac89af1e 1459 radeon_atom_encoder_init(rdev);
f3f1f03e 1460 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1461 }
ac89af1e 1462
d4877cf2
AD		 1463 /* initialize hpd */
1464 radeon_hpd_init(rdev);
38651674 1465
0783986a
AD		 1466 /* setup afmt */
1467 radeon_afmt_init(rdev);
1468
38651674 1469 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1470 drm_kms_helper_poll_init(rdev->ddev);
1471
6c7bccea
AD		 1472 if (rdev->pm.dpm_enabled) {
1473 /* do dpm late init */
1474 ret = radeon_pm_late_init(rdev);
1475 if (ret) {
1476 rdev->pm.dpm_enabled = false;
1477 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1478 }
1479 /* set the dpm state for PX since there won't be
1480 * a modeset to call this.
1481 */
1482 radeon_pm_compute_clocks(rdev);
1483 }
1484
771fe6b9
JG		 1485 return 0;
1486}
1487
1488void radeon_modeset_fini(struct radeon_device *rdev)
1489{
38651674 1490 radeon_fbdev_fini(rdev);
3c537889
AD		 1491 kfree(rdev->mode_info.bios_hardcoded_edid);
1492
771fe6b9 1493 if (rdev->mode_info.mode_config_initialized) {
0783986a 1494 radeon_afmt_fini(rdev);
eb1f8e4f 1495 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1496 radeon_hpd_fini(rdev);
771fe6b9
JG		 1497 drm_mode_config_cleanup(rdev->ddev);
1498 rdev->mode_info.mode_config_initialized = false;
1499 }
f376b94f
AD		 1500 /* free i2c buses */
1501 radeon_i2c_fini(rdev);
771fe6b9
JG		 1502}
1503
e811f5ae 1504static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1505{
1506 /* try and guess if this is a tv or a monitor */
1507 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1508 (mode->vdisplay == 576) || /* 576p */
1509 (mode->vdisplay == 720) || /* 720p */
1510 (mode->vdisplay == 1080)) /* 1080p */
1511 return true;
1512 else
1513 return false;
1514}
1515
c93bb85b 1516bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1517 const struct drm_display_mode *mode,
c93bb85b 1518 struct drm_display_mode *adjusted_mode)
771fe6b9 1519{
c93bb85b 1520 struct drm_device *dev = crtc->dev;
5b1714d3 1521 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1522 struct drm_encoder *encoder;
1523 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1524 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1525 struct drm_connector *connector;
1526 struct radeon_connector *radeon_connector;
c93bb85b 1527 bool first = true;
d65d65b1
AD		 1528 u32 src_v = 1, dst_v = 1;
1529 u32 src_h = 1, dst_h = 1;
771fe6b9 1530
5b1714d3
AD		 1531 radeon_crtc->h_border = 0;
1532 radeon_crtc->v_border = 0;
1533
c93bb85b 1534 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1535 if (encoder->crtc != crtc)
1536 continue;
d65d65b1 1537 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1538 connector = radeon_get_connector_for_encoder(encoder);
1539 radeon_connector = to_radeon_connector(connector);
1540
c93bb85b 1541 if (first) {
80297e87
AD		 1542 /* set scaling */
1543 if (radeon_encoder->rmx_type == RMX_OFF)
1544 radeon_crtc->rmx_type = RMX_OFF;
1545 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1546 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1547 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1548 else
1549 radeon_crtc->rmx_type = RMX_OFF;
1550 /* copy native mode */
c93bb85b 1551 memcpy(&radeon_crtc->native_mode,
80297e87 1552 &radeon_encoder->native_mode,
de2103e4 1553 sizeof(struct drm_display_mode));
ff32a59d
AD		 1554 src_v = crtc->mode.vdisplay;
1555 dst_v = radeon_crtc->native_mode.vdisplay;
1556 src_h = crtc->mode.hdisplay;
1557 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1558
1559 /* fix up for overscan on hdmi */
1560 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1561 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1562 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1563 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1564 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1565 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1566 if (radeon_encoder->underscan_hborder != 0)
1567 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1568 else
1569 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1570 if (radeon_encoder->underscan_vborder != 0)
1571 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1572 else
1573 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1574 radeon_crtc->rmx_type = RMX_FULL;
1575 src_v = crtc->mode.vdisplay;
1576 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1577 src_h = crtc->mode.hdisplay;
1578 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1579 }
c93bb85b
JG		 1580 first = false;
1581 } else {
1582 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1583 /* WARNING: Right now this can't happen but
1584 * in the future we need to check that scaling
d65d65b1 1585 * are consistent across different encoder
c93bb85b
JG		 1586 * (ie all encoder can work with the same
1587 * scaling).
1588 */
d65d65b1 1589 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1590 return false;
1591 }
771fe6b9
JG		 1592 }
1593 }
c93bb85b
JG		 1594 if (radeon_crtc->rmx_type != RMX_OFF) {
1595 fixed20_12 a, b;
d65d65b1
AD		 1596 a.full = dfixed_const(src_v);
1597 b.full = dfixed_const(dst_v);
68adac5e 1598 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1599 a.full = dfixed_const(src_h);
1600 b.full = dfixed_const(dst_h);
68adac5e 1601 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1602 } else {
68adac5e
BS		 1603 radeon_crtc->vsc.full = dfixed_const(1);
1604 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1605 }
c93bb85b 1606 return true;
771fe6b9 1607}
6383cf7d
MK		 1608
1609/*
d47abc58
MK		 1610 * Retrieve current video scanout position of crtc on a given gpu, and
1611 * an optional accurate timestamp of when query happened.
6383cf7d 1612 *
f5a80209 1613 * \param dev Device to query.
6383cf7d 1614 * \param crtc Crtc to query.
abca9e45 1615 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
6383cf7d
MK		 1616 * \param *vpos Location where vertical scanout position should be stored.
1617 * \param *hpos Location where horizontal scanout position should go.
d47abc58
MK		 1618 * \param *stime Target location for timestamp taken immediately before
1619 * scanout position query. Can be NULL to skip timestamp.
1620 * \param *etime Target location for timestamp taken immediately after
1621 * scanout position query. Can be NULL to skip timestamp.
6383cf7d
MK		 1622 *
1623 * Returns vpos as a positive number while in active scanout area.
1624 * Returns vpos as a negative number inside vblank, counting the number
1625 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1626 * until start of active scanout / end of vblank."
1627 *
1628 * \return Flags, or'ed together as follows:
1629 *
25985edc 1630 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1631 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1632 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1633 * this flag means that returned position may be offset by a constant but
1634 * unknown small number of scanlines wrt. real scanout position.
1635 *
1636 */
abca9e45
VS		 1637int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1638 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
6383cf7d
MK		 1639{
1640 u32 stat_crtc = 0, vbl = 0, position = 0;
1641 int vbl_start, vbl_end, vtotal, ret = 0;
1642 bool in_vbl = true;
1643
f5a80209
MK		 1644 struct radeon_device *rdev = dev->dev_private;
1645
d47abc58
MK		 1646 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1647
1648 /* Get optional system timestamp before query. */
1649 if (stime)
1650 *stime = ktime_get();
1651
6383cf7d
MK		 1652 if (ASIC_IS_DCE4(rdev)) {
1653 if (crtc == 0) {
1654 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1655 EVERGREEN_CRTC0_REGISTER_OFFSET);
1656 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1657 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1658 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1659 }
1660 if (crtc == 1) {
1661 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1662 EVERGREEN_CRTC1_REGISTER_OFFSET);
1663 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1664 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1665 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1666 }
1667 if (crtc == 2) {
1668 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1669 EVERGREEN_CRTC2_REGISTER_OFFSET);
1670 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1671 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1672 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1673 }
1674 if (crtc == 3) {
1675 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1676 EVERGREEN_CRTC3_REGISTER_OFFSET);
1677 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1678 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1679 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1680 }
1681 if (crtc == 4) {
1682 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1683 EVERGREEN_CRTC4_REGISTER_OFFSET);
1684 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1685 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1686 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1687 }
1688 if (crtc == 5) {
1689 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1690 EVERGREEN_CRTC5_REGISTER_OFFSET);
1691 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1692 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1693 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1694 }
1695 } else if (ASIC_IS_AVIVO(rdev)) {
1696 if (crtc == 0) {
1697 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1698 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1699 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1700 }
1701 if (crtc == 1) {
1702 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1703 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1704 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1705 }
1706 } else {
1707 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1708 if (crtc == 0) {
1709 /* Assume vbl_end == 0, get vbl_start from
1710 * upper 16 bits.
1711 */
1712 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1713 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1714 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1715 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1716 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1717 if (!(stat_crtc & 1))
1718 in_vbl = false;
1719
f5a80209 1720 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1721 }
1722 if (crtc == 1) {
1723 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1724 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1725 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1726 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1727 if (!(stat_crtc & 1))
1728 in_vbl = false;
1729
f5a80209 1730 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1731 }
1732 }
1733
d47abc58
MK		 1734 /* Get optional system timestamp after query. */
1735 if (etime)
1736 *etime = ktime_get();
1737
1738 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1739
6383cf7d
MK		 1740 /* Decode into vertical and horizontal scanout position. */
1741 *vpos = position & 0x1fff;
1742 *hpos = (position >> 16) & 0x1fff;
1743
1744 /* Valid vblank area boundaries from gpu retrieved? */
1745 if (vbl > 0) {
1746 /* Yes: Decode. */
f5a80209 1747 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1748 vbl_start = vbl & 0x1fff;
1749 vbl_end = (vbl >> 16) & 0x1fff;
1750 }
1751 else {
1752 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1753 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1754 vbl_end = 0;
1755 }
1756
1757 /* Test scanout position against vblank region. */
1758 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1759 in_vbl = false;
1760
1761 /* Check if inside vblank area and apply corrective offsets:
1762 * vpos will then be >=0 in video scanout area, but negative
1763 * within vblank area, counting down the number of lines until
1764 * start of scanout.
1765 */
1766
1767 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1768 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1769 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1770 *vpos = *vpos - vtotal;
1771 }
1772
1773 /* Correct for shifted end of vbl at vbl_end. */
1774 *vpos = *vpos - vbl_end;
1775
1776 /* In vblank? */
1777 if (in_vbl)
f5a80209 1778 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d 1779
8072bfa6
VS		 1780 /* Is vpos outside nominal vblank area, but less than
1781 * 1/100 of a frame height away from start of vblank?
1782 * If so, assume this isn't a massively delayed vblank
1783 * interrupt, but a vblank interrupt that fired a few
1784 * microseconds before true start of vblank. Compensate
1785 * by adding a full frame duration to the final timestamp.
1786 * Happens, e.g., on ATI R500, R600.
1787 *
1788 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1789 */
1790 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1791 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1792 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1793
1794 if (vbl_start - *vpos < vtotal / 100) {
1795 *vpos -= vtotal;
1796
1797 /* Signal this correction as "applied". */
1798 ret |= 0x8;
1799 }
1800 }
1801
6383cf7d
MK		 1802 return ret;
1803}
Linux kernel - Deliverables
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