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drm/radeon: Prevent too early kms-pageflips triggered by vblank.
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
771fe6b9
JG		 28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
10ebc0bc 33#include <linux/pm_runtime.h>
760285e7
DH		 34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_edid.h>
771fe6b9 36
32167016
CK		 37#include <linux/gcd.h>
38
771fe6b9
JG		 39static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40{
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
d9fdaafb 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
4366f3b5
MK		 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
771fe6b9
JG		 71}
72
fee298fd 73static void dce4_crtc_load_lut(struct drm_crtc *crtc)
bcc1c2a1
AD		 74{
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
78 int i;
79
d9fdaafb 80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90
677d0768
AD		 91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 93
677d0768 94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 95 for (i = 0; i < 256; i++) {
677d0768 96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
100 }
101}
102
fee298fd
AD		 103static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104{
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
108 int i;
109
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
142 }
143
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
9e05fa1d
AD		 160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
163 */
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
166 }
fee298fd
AD		 167}
168
771fe6b9
JG		 169static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int i;
175 uint32_t dac2_cntl;
176
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 else
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183
184 WREG8(RADEON_PALETTE_INDEX, 0);
185 for (i = 0; i < 256; i++) {
186 WREG32(RADEON_PALETTE_30_DATA,
187 (radeon_crtc->lut_r[i] << 20) |
188 (radeon_crtc->lut_g[i] << 10) |
189 (radeon_crtc->lut_b[i] << 0));
190 }
191}
192
193void radeon_crtc_load_lut(struct drm_crtc *crtc)
194{
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197
198 if (!crtc->enabled)
199 return;
200
fee298fd
AD		 201 if (ASIC_IS_DCE5(rdev))
202 dce5_crtc_load_lut(crtc);
203 else if (ASIC_IS_DCE4(rdev))
204 dce4_crtc_load_lut(crtc);
bcc1c2a1 205 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 206 avivo_crtc_load_lut(crtc);
207 else
208 legacy_crtc_load_lut(crtc);
209}
210
b8c00ac5 211/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 212void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
213 u16 blue, int regno)
214{
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216
771fe6b9
JG		 217 radeon_crtc->lut_r[regno] = red >> 6;
218 radeon_crtc->lut_g[regno] = green >> 6;
219 radeon_crtc->lut_b[regno] = blue >> 6;
220}
221
b8c00ac5
DA		 222/** Gets the color ramps on behalf of fbcon */
223void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, int regno)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227
228 *red = radeon_crtc->lut_r[regno] << 6;
229 *green = radeon_crtc->lut_g[regno] << 6;
230 *blue = radeon_crtc->lut_b[regno] << 6;
231}
232
771fe6b9 233static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 234 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 235{
236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 237 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 238
b8c00ac5 239 /* userspace palettes are always correct as is */
7203425a 240 for (i = start; i < end; i++) {
b8c00ac5
DA		 241 radeon_crtc->lut_r[i] = red[i] >> 6;
242 radeon_crtc->lut_g[i] = green[i] >> 6;
243 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 244 }
771fe6b9
JG		 245 radeon_crtc_load_lut(crtc);
246}
247
248static void radeon_crtc_destroy(struct drm_crtc *crtc)
249{
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251
771fe6b9 252 drm_crtc_cleanup(crtc);
fa7f517c 253 destroy_workqueue(radeon_crtc->flip_queue);
771fe6b9
JG		 254 kfree(radeon_crtc);
255}
256
fa7f517c
CK		 257/**
258 * radeon_unpin_work_func - unpin old buffer object
259 *
260 * @__work - kernel work item
261 *
262 * Unpin the old frame buffer object outside of the interrupt handler
6f34be50
AD		 263 */
264static void radeon_unpin_work_func(struct work_struct *__work)
265{
fa7f517c
CK		 266 struct radeon_flip_work *work =
267 container_of(__work, struct radeon_flip_work, unpin_work);
6f34be50
AD		 268 int r;
269
270 /* unpin of the old buffer */
271 r = radeon_bo_reserve(work->old_rbo, false);
272 if (likely(r == 0)) {
273 r = radeon_bo_unpin(work->old_rbo);
274 if (unlikely(r != 0)) {
275 DRM_ERROR("failed to unpin buffer after flip\n");
276 }
277 radeon_bo_unreserve(work->old_rbo);
278 } else
279 DRM_ERROR("failed to reserve buffer after flip\n");
498c555f
DA		 280
281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
6f34be50
AD		 282 kfree(work);
283}
284
1a0e7918 285void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
6f34be50
AD		 286{
287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
6f34be50
AD		 288 unsigned long flags;
289 u32 update_pending;
290 int vpos, hpos;
291
f5d636d2
CK		 292 /* can happen during initialization */
293 if (radeon_crtc == NULL)
294 return;
6f34be50
AD		 295
296 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
a2b6d3b3
MD		 297 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
298 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
299 "RADEON_FLIP_SUBMITTED(%d)\n",
300 radeon_crtc->flip_status,
301 RADEON_FLIP_SUBMITTED);
6f34be50
AD		 302 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
303 return;
304 }
fa7f517c
CK		 305
306 update_pending = radeon_page_flip_pending(rdev, crtc_id);
6f34be50
AD		 307
308 /* Has the pageflip already completed in crtc, or is it certain
309 * to complete in this vblank?
310 */
311 if (update_pending &&
abca9e45 312 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
d47abc58 313 &vpos, &hpos, NULL, NULL)) &&
81ffbbed
FK		 314 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
315 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
316 /* crtc didn't flip in this target vblank interval,
317 * but flip is pending in crtc. Based on the current
318 * scanout position we know that the current frame is
319 * (nearly) complete and the flip will (likely)
320 * complete before the start of the next frame.
321 */
322 update_pending = 0;
323 }
fa7f517c
CK		 324 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
325 if (!update_pending)
1a0e7918 326 radeon_crtc_handle_flip(rdev, crtc_id);
1a0e7918
CK		 327}
328
329/**
330 * radeon_crtc_handle_flip - page flip completed
331 *
332 * @rdev: radeon device pointer
333 * @crtc_id: crtc number this event is for
334 *
335 * Called when we are sure that a page flip for this crtc is completed.
336 */
337void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
338{
339 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
fa7f517c 340 struct radeon_flip_work *work;
1a0e7918
CK		 341 unsigned long flags;
342
343 /* this can happen at init */
344 if (radeon_crtc == NULL)
345 return;
346
347 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
fa7f517c 348 work = radeon_crtc->flip_work;
a2b6d3b3
MD		 349 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
350 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
351 "RADEON_FLIP_SUBMITTED(%d)\n",
352 radeon_crtc->flip_status,
353 RADEON_FLIP_SUBMITTED);
1a0e7918
CK		 354 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
355 return;
6f34be50
AD		 356 }
357
fa7f517c 358 /* Pageflip completed. Clean up. */
a2b6d3b3 359 radeon_crtc->flip_status = RADEON_FLIP_NONE;
fa7f517c 360 radeon_crtc->flip_work = NULL;
6f34be50
AD		 361
362 /* wakeup userspace */
26ae4667
RC		 363 if (work->event)
364 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
365
6f34be50
AD		 366 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
367
ca721b79 368 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
6f34be50 369 radeon_fence_unref(&work->fence);
46889d95 370 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
fa7f517c 371 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
6f34be50
AD		 372}
373
fa7f517c
CK		 374/**
375 * radeon_flip_work_func - page flip framebuffer
376 *
377 * @work - kernel work item
378 *
379 * Wait for the buffer object to become idle and do the actual page flip
380 */
381static void radeon_flip_work_func(struct work_struct *__work)
6f34be50 382{
fa7f517c
CK		 383 struct radeon_flip_work *work =
384 container_of(__work, struct radeon_flip_work, flip_work);
385 struct radeon_device *rdev = work->rdev;
386 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
6f34be50 387
fa7f517c
CK		 388 struct drm_crtc *crtc = &radeon_crtc->base;
389 struct drm_framebuffer *fb = work->fb;
6f34be50 390
fa7f517c
CK		 391 uint32_t tiling_flags, pitch_pixels;
392 uint64_t base;
9af20792 393
fa7f517c
CK		 394 unsigned long flags;
395 int r;
9af20792 396
fa7f517c
CK		 397 down_read(&rdev->exclusive_lock);
398 while (work->fence) {
399 r = radeon_fence_wait(work->fence, false);
400 if (r == -EDEADLK) {
401 up_read(&rdev->exclusive_lock);
402 r = radeon_gpu_reset(rdev);
403 down_read(&rdev->exclusive_lock);
404 }
6f34be50 405
fa7f517c
CK		 406 if (r) {
407 DRM_ERROR("failed to wait on page flip fence (%d)!\n",
408 r);
409 goto cleanup;
410 } else
411 radeon_fence_unref(&work->fence);
6f34be50 412 }
6f34be50
AD		 413
414 /* pin the new buffer */
6f34be50 415 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
fa7f517c 416 work->old_rbo, work->new_rbo);
6f34be50 417
fa7f517c 418 r = radeon_bo_reserve(work->new_rbo, false);
6f34be50
AD		 419 if (unlikely(r != 0)) {
420 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
fa7f517c 421 goto cleanup;
6f34be50 422 }
0349af70 423 /* Only 27 bit offset for legacy CRTC */
fa7f517c 424 r = radeon_bo_pin_restricted(work->new_rbo, RADEON_GEM_DOMAIN_VRAM,
0349af70 425 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
6f34be50 426 if (unlikely(r != 0)) {
fa7f517c 427 radeon_bo_unreserve(work->new_rbo);
6f34be50
AD		 428 r = -EINVAL;
429 DRM_ERROR("failed to pin new rbo buffer before flip\n");
fa7f517c 430 goto cleanup;
6f34be50 431 }
fa7f517c
CK		 432 radeon_bo_get_tiling_flags(work->new_rbo, &tiling_flags, NULL);
433 radeon_bo_unreserve(work->new_rbo);
6f34be50
AD		 434
435 if (!ASIC_IS_AVIVO(rdev)) {
436 /* crtc offset is from display base addr not FB location */
437 base -= radeon_crtc->legacy_display_base_addr;
01f2c773 438 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
6f34be50
AD		 439
440 if (tiling_flags & RADEON_TILING_MACRO) {
441 if (ASIC_IS_R300(rdev)) {
442 base &= ~0x7ff;
443 } else {
444 int byteshift = fb->bits_per_pixel >> 4;
445 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
446 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
447 }
448 } else {
449 int offset = crtc->y * pitch_pixels + crtc->x;
450 switch (fb->bits_per_pixel) {
451 case 8:
452 default:
453 offset *= 1;
454 break;
455 case 15:
456 case 16:
457 offset *= 2;
458 break;
459 case 24:
460 offset *= 3;
461 break;
462 case 32:
463 offset *= 4;
464 break;
465 }
466 base += offset;
467 }
468 base &= ~7;
469 }
470
ca721b79
MD		 471 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
472 if (r) {
473 DRM_ERROR("failed to get vblank before flip\n");
474 goto pflip_cleanup;
475 }
476
fa7f517c
CK		 477 /* We borrow the event spin lock for protecting flip_work */
478 spin_lock_irqsave(&crtc->dev->event_lock, flags);
b15eb4ea 479
6f34be50 480 /* set the proper interrupt */
e928c61a 481 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
6f34be50 482
fa7f517c
CK		 483 /* do the flip (mmio) */
484 radeon_page_flip(rdev, radeon_crtc->crtc_id, base);
485
a2b6d3b3 486 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
fa7f517c
CK		 487 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
488 up_read(&rdev->exclusive_lock);
489
490 return;
1aab5514 491
ca721b79
MD		 492pflip_cleanup:
493 if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) {
494 DRM_ERROR("failed to reserve new rbo in error path\n");
495 goto cleanup;
496 }
497 if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) {
498 DRM_ERROR("failed to unpin new rbo in error path\n");
499 }
500 radeon_bo_unreserve(work->new_rbo);
501
fa7f517c
CK		 502cleanup:
503 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
fcc485d6 504 radeon_fence_unref(&work->fence);
6f34be50 505 kfree(work);
fa7f517c
CK		 506 up_read(&rdev->exclusive_lock);
507}
508
509static int radeon_crtc_page_flip(struct drm_crtc *crtc,
510 struct drm_framebuffer *fb,
511 struct drm_pending_vblank_event *event,
512 uint32_t page_flip_flags)
513{
514 struct drm_device *dev = crtc->dev;
515 struct radeon_device *rdev = dev->dev_private;
516 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
517 struct radeon_framebuffer *old_radeon_fb;
518 struct radeon_framebuffer *new_radeon_fb;
519 struct drm_gem_object *obj;
520 struct radeon_flip_work *work;
521 unsigned long flags;
522
523 work = kzalloc(sizeof *work, GFP_KERNEL);
524 if (work == NULL)
525 return -ENOMEM;
526
527 INIT_WORK(&work->flip_work, radeon_flip_work_func);
528 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
529
530 work->rdev = rdev;
531 work->crtc_id = radeon_crtc->crtc_id;
532 work->fb = fb;
533 work->event = event;
534
535 /* schedule unpin of the old buffer */
536 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
537 obj = old_radeon_fb->obj;
538
539 /* take a reference to the old object */
540 drm_gem_object_reference(obj);
541 work->old_rbo = gem_to_radeon_bo(obj);
542
543 new_radeon_fb = to_radeon_framebuffer(fb);
544 obj = new_radeon_fb->obj;
545 work->new_rbo = gem_to_radeon_bo(obj);
546
547 spin_lock(&work->new_rbo->tbo.bdev->fence_lock);
548 if (work->new_rbo->tbo.sync_obj)
549 work->fence = radeon_fence_ref(work->new_rbo->tbo.sync_obj);
550 spin_unlock(&work->new_rbo->tbo.bdev->fence_lock);
551
552 /* We borrow the event spin lock for protecting flip_work */
553 spin_lock_irqsave(&crtc->dev->event_lock, flags);
6f34be50 554
a2b6d3b3 555 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
fa7f517c
CK		 556 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
557 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
558 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
559 radeon_fence_unref(&work->fence);
560 kfree(work);
561 return -EBUSY;
562 }
a2b6d3b3 563 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
fa7f517c
CK		 564 radeon_crtc->flip_work = work;
565
685d54b3
MD		 566 /* update crtc fb */
567 crtc->primary->fb = fb;
568
fa7f517c
CK		 569 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
570
571 queue_work(radeon_crtc->flip_queue, &work->flip_work);
572
573 return 0;
6f34be50
AD		 574}
575
10ebc0bc
DA		 576static int
577radeon_crtc_set_config(struct drm_mode_set *set)
578{
579 struct drm_device *dev;
580 struct radeon_device *rdev;
581 struct drm_crtc *crtc;
582 bool active = false;
583 int ret;
584
585 if (!set || !set->crtc)
586 return -EINVAL;
587
588 dev = set->crtc->dev;
589
590 ret = pm_runtime_get_sync(dev->dev);
591 if (ret < 0)
592 return ret;
593
594 ret = drm_crtc_helper_set_config(set);
595
596 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
597 if (crtc->enabled)
598 active = true;
599
600 pm_runtime_mark_last_busy(dev->dev);
601
602 rdev = dev->dev_private;
603 /* if we have active crtcs and we don't have a power ref,
604 take the current one */
605 if (active && !rdev->have_disp_power_ref) {
606 rdev->have_disp_power_ref = true;
607 return ret;
608 }
609 /* if we have no active crtcs, then drop the power ref
610 we got before */
611 if (!active && rdev->have_disp_power_ref) {
612 pm_runtime_put_autosuspend(dev->dev);
613 rdev->have_disp_power_ref = false;
614 }
615
616 /* drop the power reference we got coming in here */
617 pm_runtime_put_autosuspend(dev->dev);
618 return ret;
619}
771fe6b9
JG		 620static const struct drm_crtc_funcs radeon_crtc_funcs = {
621 .cursor_set = radeon_crtc_cursor_set,
622 .cursor_move = radeon_crtc_cursor_move,
623 .gamma_set = radeon_crtc_gamma_set,
10ebc0bc 624 .set_config = radeon_crtc_set_config,
771fe6b9 625 .destroy = radeon_crtc_destroy,
6f34be50 626 .page_flip = radeon_crtc_page_flip,
771fe6b9
JG		 627};
628
629static void radeon_crtc_init(struct drm_device *dev, int index)
630{
631 struct radeon_device *rdev = dev->dev_private;
632 struct radeon_crtc *radeon_crtc;
633 int i;
634
635 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
636 if (radeon_crtc == NULL)
637 return;
638
639 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
640
641 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
642 radeon_crtc->crtc_id = index;
fa7f517c 643 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
c93bb85b 644 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 645
9e05fa1d
AD		 646 if (rdev->family >= CHIP_BONAIRE) {
647 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
648 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
649 } else {
650 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
651 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
652 }
bea61c59
AD		 653 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
654 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
9e05fa1d 655
785b93ef 656#if 0
771fe6b9
JG		 657 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
658 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
659 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 660#endif
771fe6b9
JG		 661
662 for (i = 0; i < 256; i++) {
663 radeon_crtc->lut_r[i] = i << 2;
664 radeon_crtc->lut_g[i] = i << 2;
665 radeon_crtc->lut_b[i] = i << 2;
666 }
667
668 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
669 radeon_atombios_init_crtc(dev, radeon_crtc);
670 else
671 radeon_legacy_init_crtc(dev, radeon_crtc);
672}
673
e68adef8 674static const char *encoder_names[38] = {
771fe6b9
JG		 675 "NONE",
676 "INTERNAL_LVDS",
677 "INTERNAL_TMDS1",
678 "INTERNAL_TMDS2",
679 "INTERNAL_DAC1",
680 "INTERNAL_DAC2",
681 "INTERNAL_SDVOA",
682 "INTERNAL_SDVOB",
683 "SI170B",
684 "CH7303",
685 "CH7301",
686 "INTERNAL_DVO1",
687 "EXTERNAL_SDVOA",
688 "EXTERNAL_SDVOB",
689 "TITFP513",
690 "INTERNAL_LVTM1",
691 "VT1623",
692 "HDMI_SI1930",
693 "HDMI_INTERNAL",
694 "INTERNAL_KLDSCP_TMDS1",
695 "INTERNAL_KLDSCP_DVO1",
696 "INTERNAL_KLDSCP_DAC1",
697 "INTERNAL_KLDSCP_DAC2",
698 "SI178",
699 "MVPU_FPGA",
700 "INTERNAL_DDI",
701 "VT1625",
702 "HDMI_SI1932",
703 "DP_AN9801",
704 "DP_DP501",
705 "INTERNAL_UNIPHY",
706 "INTERNAL_KLDSCP_LVTMA",
707 "INTERNAL_UNIPHY1",
708 "INTERNAL_UNIPHY2",
bf982ebf
AD		 709 "NUTMEG",
710 "TRAVIS",
e68adef8
AD		 711 "INTERNAL_VCE",
712 "INTERNAL_UNIPHY3",
771fe6b9
JG		 713};
714
cbd4623d 715static const char *hpd_names[6] = {
eed45b30
AD		 716 "HPD1",
717 "HPD2",
718 "HPD3",
719 "HPD4",
720 "HPD5",
721 "HPD6",
722};
723
771fe6b9
JG		 724static void radeon_print_display_setup(struct drm_device *dev)
725{
726 struct drm_connector *connector;
727 struct radeon_connector *radeon_connector;
728 struct drm_encoder *encoder;
729 struct radeon_encoder *radeon_encoder;
730 uint32_t devices;
731 int i = 0;
732
733 DRM_INFO("Radeon Display Connectors\n");
734 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
735 radeon_connector = to_radeon_connector(connector);
736 DRM_INFO("Connector %d:\n", i);
72082093 737 DRM_INFO(" %s\n", connector->name);
eed45b30
AD		 738 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
739 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 740 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 741 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
742 radeon_connector->ddc_bus->rec.mask_clk_reg,
743 radeon_connector->ddc_bus->rec.mask_data_reg,
744 radeon_connector->ddc_bus->rec.a_clk_reg,
745 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 746 radeon_connector->ddc_bus->rec.en_clk_reg,
747 radeon_connector->ddc_bus->rec.en_data_reg,
748 radeon_connector->ddc_bus->rec.y_clk_reg,
749 radeon_connector->ddc_bus->rec.y_data_reg);
fb939dfc 750 if (radeon_connector->router.ddc_valid)
26b5bc98 751 DRM_INFO(" DDC Router 0x%x/0x%x\n",
fb939dfc
AD		 752 radeon_connector->router.ddc_mux_control_pin,
753 radeon_connector->router.ddc_mux_state);
754 if (radeon_connector->router.cd_valid)
755 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
756 radeon_connector->router.cd_mux_control_pin,
757 radeon_connector->router.cd_mux_state);
4b9d2a21
DA		 758 } else {
759 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
760 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
761 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
762 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
763 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
764 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
765 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
766 }
771fe6b9
JG		 767 DRM_INFO(" Encoders:\n");
768 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
769 radeon_encoder = to_radeon_encoder(encoder);
770 devices = radeon_encoder->devices & radeon_connector->devices;
771 if (devices) {
772 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
773 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
774 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
775 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
776 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
777 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
778 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
779 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
780 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
781 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
782 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
783 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
784 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
785 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
786 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
787 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 788 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
789 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 790 if (devices & ATOM_DEVICE_TV1_SUPPORT)
791 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
792 if (devices & ATOM_DEVICE_CV_SUPPORT)
793 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
794 }
795 }
796 i++;
797 }
798}
799
4ce001ab 800static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 801{
802 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 803 bool ret = false;
804
805 if (rdev->bios) {
806 if (rdev->is_atom_bios) {
a084e6ee
AD		 807 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
808 if (ret == false)
771fe6b9 809 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 810 } else {
771fe6b9 811 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 812 if (ret == false)
813 ret = radeon_get_legacy_connector_info_from_table(dev);
814 }
771fe6b9
JG		 815 } else {
816 if (!ASIC_IS_AVIVO(rdev))
817 ret = radeon_get_legacy_connector_info_from_table(dev);
818 }
819 if (ret) {
1f3b6a45 820 radeon_setup_encoder_clones(dev);
771fe6b9 821 radeon_print_display_setup(dev);
771fe6b9
JG		 822 }
823
824 return ret;
825}
826
827int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
828{
3c537889
AD		 829 struct drm_device *dev = radeon_connector->base.dev;
830 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 831 int ret = 0;
832
0ac66eff
AD		 833 /* don't leak the edid if we already fetched it in detect() */
834 if (radeon_connector->edid)
835 goto got_edid;
836
26b5bc98 837 /* on hw with routers, select right port */
fb939dfc
AD		 838 if (radeon_connector->router.ddc_valid)
839 radeon_router_select_ddc_port(radeon_connector);
26b5bc98 840
0a9069d3
NOS		 841 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
842 ENCODER_OBJECT_ID_NONE) {
379dfc25 843 if (radeon_connector->ddc_bus->has_aux)
0a9069d3 844 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
379dfc25 845 &radeon_connector->ddc_bus->aux.ddc);
0a9069d3
NOS		 846 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
847 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 848 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
b06947b5 849
7a15cbd4 850 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
379dfc25
AD		 851 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
852 radeon_connector->ddc_bus->has_aux)
b06947b5 853 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
379dfc25 854 &radeon_connector->ddc_bus->aux.ddc);
b06947b5
AD		 855 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
856 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
857 &radeon_connector->ddc_bus->adapter);
858 } else {
859 if (radeon_connector->ddc_bus && !radeon_connector->edid)
860 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
861 &radeon_connector->ddc_bus->adapter);
0294cf4f 862 }
c324acd5
AD		 863
864 if (!radeon_connector->edid) {
865 if (rdev->is_atom_bios) {
866 /* some laptops provide a hardcoded edid in rom for LCDs */
867 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
868 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
869 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
870 } else
871 /* some servers provide a hardcoded edid in rom for KVMs */
872 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
873 }
0294cf4f 874 if (radeon_connector->edid) {
0ac66eff 875got_edid:
0294cf4f
AD		 876 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
877 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
16086279 878 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 879 return ret;
880 }
881 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 882 return 0;
771fe6b9
JG		 883}
884
f523f74e 885/* avivo */
f523f74e 886
32167016
CK		 887/**
888 * avivo_reduce_ratio - fractional number reduction
889 *
890 * @nom: nominator
891 * @den: denominator
892 * @nom_min: minimum value for nominator
893 * @den_min: minimum value for denominator
894 *
895 * Find the greatest common divisor and apply it on both nominator and
896 * denominator, but make nominator and denominator are at least as large
897 * as their minimum values.
898 */
899static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
900 unsigned nom_min, unsigned den_min)
f523f74e 901{
32167016
CK		 902 unsigned tmp;
903
904 /* reduce the numbers to a simpler ratio */
905 tmp = gcd(*nom, *den);
906 *nom /= tmp;
907 *den /= tmp;
908
909 /* make sure nominator is large enough */
910 if (*nom < nom_min) {
3b333c55 911 tmp = DIV_ROUND_UP(nom_min, *nom);
32167016
CK		 912 *nom *= tmp;
913 *den *= tmp;
f523f74e
AD		 914 }
915
32167016
CK		 916 /* make sure the denominator is large enough */
917 if (*den < den_min) {
3b333c55 918 tmp = DIV_ROUND_UP(den_min, *den);
32167016
CK		 919 *nom *= tmp;
920 *den *= tmp;
f523f74e 921 }
f523f74e
AD		 922}
923
c2fb3094
CK		 924/**
925 * avivo_get_fb_ref_div - feedback and ref divider calculation
926 *
927 * @nom: nominator
928 * @den: denominator
929 * @post_div: post divider
930 * @fb_div_max: feedback divider maximum
931 * @ref_div_max: reference divider maximum
932 * @fb_div: resulting feedback divider
933 * @ref_div: resulting reference divider
934 *
935 * Calculate feedback and reference divider for a given post divider. Makes
936 * sure we stay within the limits.
937 */
938static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
939 unsigned fb_div_max, unsigned ref_div_max,
940 unsigned *fb_div, unsigned *ref_div)
941{
942 /* limit reference * post divider to a maximum */
4b21ce1b 943 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
c2fb3094
CK		 944
945 /* get matching reference and feedback divider */
946 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
947 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
948
949 /* limit fb divider to its maximum */
950 if (*fb_div > fb_div_max) {
951 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
952 *fb_div = fb_div_max;
953 }
954}
955
32167016
CK		 956/**
957 * radeon_compute_pll_avivo - compute PLL paramaters
958 *
959 * @pll: information about the PLL
960 * @dot_clock_p: resulting pixel clock
961 * fb_div_p: resulting feedback divider
962 * frac_fb_div_p: fractional part of the feedback divider
963 * ref_div_p: resulting reference divider
964 * post_div_p: resulting reference divider
965 *
966 * Try to calculate the PLL parameters to generate the given frequency:
967 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
968 */
f523f74e
AD		 969void radeon_compute_pll_avivo(struct radeon_pll *pll,
970 u32 freq,
971 u32 *dot_clock_p,
972 u32 *fb_div_p,
973 u32 *frac_fb_div_p,
974 u32 *ref_div_p,
975 u32 *post_div_p)
976{
c2fb3094
CK		 977 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
978 freq : freq / 10;
979
32167016
CK		 980 unsigned fb_div_min, fb_div_max, fb_div;
981 unsigned post_div_min, post_div_max, post_div;
982 unsigned ref_div_min, ref_div_max, ref_div;
983 unsigned post_div_best, diff_best;
f8a2645e 984 unsigned nom, den;
f523f74e 985
32167016
CK		 986 /* determine allowed feedback divider range */
987 fb_div_min = pll->min_feedback_div;
988 fb_div_max = pll->max_feedback_div;
f523f74e
AD		 989
990 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
32167016
CK		 991 fb_div_min *= 10;
992 fb_div_max *= 10;
993 }
994
995 /* determine allowed ref divider range */
996 if (pll->flags & RADEON_PLL_USE_REF_DIV)
997 ref_div_min = pll->reference_div;
998 else
999 ref_div_min = pll->min_ref_div;
24315814
CK		 1000
1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1002 pll->flags & RADEON_PLL_USE_REF_DIV)
1003 ref_div_max = pll->reference_div;
1004 else
1005 ref_div_max = pll->max_ref_div;
32167016
CK		 1006
1007 /* determine allowed post divider range */
1008 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1009 post_div_min = pll->post_div;
1010 post_div_max = pll->post_div;
1011 } else {
32167016
CK		 1012 unsigned vco_min, vco_max;
1013
1014 if (pll->flags & RADEON_PLL_IS_LCD) {
1015 vco_min = pll->lcd_pll_out_min;
1016 vco_max = pll->lcd_pll_out_max;
1017 } else {
1018 vco_min = pll->pll_out_min;
1019 vco_max = pll->pll_out_max;
f523f74e 1020 }
32167016 1021
c2fb3094
CK		 1022 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1023 vco_min *= 10;
1024 vco_max *= 10;
1025 }
1026
32167016
CK		 1027 post_div_min = vco_min / target_clock;
1028 if ((target_clock * post_div_min) < vco_min)
1029 ++post_div_min;
1030 if (post_div_min < pll->min_post_div)
1031 post_div_min = pll->min_post_div;
1032
1033 post_div_max = vco_max / target_clock;
1034 if ((target_clock * post_div_max) > vco_max)
1035 --post_div_max;
1036 if (post_div_max > pll->max_post_div)
1037 post_div_max = pll->max_post_div;
1038 }
1039
1040 /* represent the searched ratio as fractional number */
c2fb3094 1041 nom = target_clock;
32167016
CK		 1042 den = pll->reference_freq;
1043
1044 /* reduce the numbers to a simpler ratio */
1045 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1046
1047 /* now search for a post divider */
1048 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1049 post_div_best = post_div_min;
1050 else
1051 post_div_best = post_div_max;
1052 diff_best = ~0;
1053
1054 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
c2fb3094
CK		 1055 unsigned diff;
1056 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1057 ref_div_max, &fb_div, &ref_div);
1058 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1059 (ref_div * post_div));
1060
32167016
CK		 1061 if (diff < diff_best || (diff == diff_best &&
1062 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1063
1064 post_div_best = post_div;
1065 diff_best = diff;
f523f74e 1066 }
32167016
CK		 1067 }
1068 post_div = post_div_best;
1069
c2fb3094
CK		 1070 /* get the feedback and reference divider for the optimal value */
1071 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1072 &fb_div, &ref_div);
32167016
CK		 1073
1074 /* reduce the numbers to a simpler ratio once more */
1075 /* this also makes sure that the reference divider is large enough */
1076 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1077
3b333c55
CK		 1078 /* avoid high jitter with small fractional dividers */
1079 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
74ad54f2 1080 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
3b333c55
CK		 1081 if (fb_div < fb_div_min) {
1082 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1083 fb_div *= tmp;
1084 ref_div *= tmp;
1085 }
1086 }
1087
32167016
CK		 1088 /* and finally save the result */
1089 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1090 *fb_div_p = fb_div / 10;
1091 *frac_fb_div_p = fb_div % 10;
f523f74e 1092 } else {
32167016
CK		 1093 *fb_div_p = fb_div;
1094 *frac_fb_div_p = 0;
f523f74e
AD		 1095 }
1096
32167016
CK		 1097 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1098 (pll->reference_freq * *frac_fb_div_p)) /
1099 (ref_div * post_div * 10);
f523f74e
AD		 1100 *ref_div_p = ref_div;
1101 *post_div_p = post_div;
32167016
CK		 1102
1103 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
c2fb3094 1104 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
32167016 1105 ref_div, post_div);
f523f74e
AD		 1106}
1107
1108/* pre-avivo */
771fe6b9
JG		 1109static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1110{
1111 uint64_t mod;
1112
1113 n += d / 2;
1114
1115 mod = do_div(n, d);
1116 return n;
1117}
1118
f523f74e
AD		 1119void radeon_compute_pll_legacy(struct radeon_pll *pll,
1120 uint64_t freq,
1121 uint32_t *dot_clock_p,
1122 uint32_t *fb_div_p,
1123 uint32_t *frac_fb_div_p,
1124 uint32_t *ref_div_p,
1125 uint32_t *post_div_p)
771fe6b9
JG		 1126{
1127 uint32_t min_ref_div = pll->min_ref_div;
1128 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 1129 uint32_t min_post_div = pll->min_post_div;
1130 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 1131 uint32_t min_fractional_feed_div = 0;
1132 uint32_t max_fractional_feed_div = 0;
1133 uint32_t best_vco = pll->best_vco;
1134 uint32_t best_post_div = 1;
1135 uint32_t best_ref_div = 1;
1136 uint32_t best_feedback_div = 1;
1137 uint32_t best_frac_feedback_div = 0;
1138 uint32_t best_freq = -1;
1139 uint32_t best_error = 0xffffffff;
1140 uint32_t best_vco_diff = 1;
1141 uint32_t post_div;
86cb2bbf 1142 u32 pll_out_min, pll_out_max;
771fe6b9 1143
d9fdaafb 1144 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 1145 freq = freq * 1000;
1146
86cb2bbf
AD		 1147 if (pll->flags & RADEON_PLL_IS_LCD) {
1148 pll_out_min = pll->lcd_pll_out_min;
1149 pll_out_max = pll->lcd_pll_out_max;
1150 } else {
1151 pll_out_min = pll->pll_out_min;
1152 pll_out_max = pll->pll_out_max;
1153 }
1154
619efb10
AD		 1155 if (pll_out_min > 64800)
1156 pll_out_min = 64800;
1157
fc10332b 1158 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 1159 min_ref_div = max_ref_div = pll->reference_div;
1160 else {
1161 while (min_ref_div < max_ref_div-1) {
1162 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1163 uint32_t pll_in = pll->reference_freq / mid;
1164 if (pll_in < pll->pll_in_min)
1165 max_ref_div = mid;
1166 else if (pll_in > pll->pll_in_max)
1167 min_ref_div = mid;
1168 else
1169 break;
1170 }
1171 }
1172
fc10332b
AD		 1173 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1174 min_post_div = max_post_div = pll->post_div;
1175
1176 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 1177 min_fractional_feed_div = pll->min_frac_feedback_div;
1178 max_fractional_feed_div = pll->max_frac_feedback_div;
1179 }
1180
bd6a60af 1181 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
771fe6b9
JG		 1182 uint32_t ref_div;
1183
fc10332b 1184 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 1185 continue;
1186
1187 /* legacy radeons only have a few post_divs */
fc10332b 1188 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 1189 if ((post_div == 5) ||
1190 (post_div == 7) ||
1191 (post_div == 9) ||
1192 (post_div == 10) ||
1193 (post_div == 11) ||
1194 (post_div == 13) ||
1195 (post_div == 14) ||
1196 (post_div == 15))
1197 continue;
1198 }
1199
1200 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1201 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1202 uint32_t pll_in = pll->reference_freq / ref_div;
1203 uint32_t min_feed_div = pll->min_feedback_div;
1204 uint32_t max_feed_div = pll->max_feedback_div + 1;
1205
1206 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1207 continue;
1208
1209 while (min_feed_div < max_feed_div) {
1210 uint32_t vco;
1211 uint32_t min_frac_feed_div = min_fractional_feed_div;
1212 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1213 uint32_t frac_feedback_div;
1214 uint64_t tmp;
1215
1216 feedback_div = (min_feed_div + max_feed_div) / 2;
1217
1218 tmp = (uint64_t)pll->reference_freq * feedback_div;
1219 vco = radeon_div(tmp, ref_div);
1220
86cb2bbf 1221 if (vco < pll_out_min) {
771fe6b9
JG		 1222 min_feed_div = feedback_div + 1;
1223 continue;
86cb2bbf 1224 } else if (vco > pll_out_max) {
771fe6b9
JG		 1225 max_feed_div = feedback_div;
1226 continue;
1227 }
1228
1229 while (min_frac_feed_div < max_frac_feed_div) {
1230 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1231 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1232 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1233 current_freq = radeon_div(tmp, ref_div * post_div);
1234
fc10332b 1235 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 1236 if (freq < current_freq)
1237 error = 0xffffffff;
1238 else
1239 error = freq - current_freq;
d0e275a9
AD		 1240 } else
1241 error = abs(current_freq - freq);
771fe6b9
JG		 1242 vco_diff = abs(vco - best_vco);
1243
1244 if ((best_vco == 0 && error < best_error) ||
1245 (best_vco != 0 &&
167ffc44 1246 ((best_error > 100 && error < best_error - 100) ||
5480f727 1247 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
771fe6b9
JG		 1248 best_post_div = post_div;
1249 best_ref_div = ref_div;
1250 best_feedback_div = feedback_div;
1251 best_frac_feedback_div = frac_feedback_div;
1252 best_freq = current_freq;
1253 best_error = error;
1254 best_vco_diff = vco_diff;
5480f727
DA		 1255 } else if (current_freq == freq) {
1256 if (best_freq == -1) {
1257 best_post_div = post_div;
1258 best_ref_div = ref_div;
1259 best_feedback_div = feedback_div;
1260 best_frac_feedback_div = frac_feedback_div;
1261 best_freq = current_freq;
1262 best_error = error;
1263 best_vco_diff = vco_diff;
1264 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1265 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1266 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1267 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1268 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1269 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1270 best_post_div = post_div;
1271 best_ref_div = ref_div;
1272 best_feedback_div = feedback_div;
1273 best_frac_feedback_div = frac_feedback_div;
1274 best_freq = current_freq;
1275 best_error = error;
1276 best_vco_diff = vco_diff;
1277 }
771fe6b9
JG		 1278 }
1279 if (current_freq < freq)
1280 min_frac_feed_div = frac_feedback_div + 1;
1281 else
1282 max_frac_feed_div = frac_feedback_div;
1283 }
1284 if (current_freq < freq)
1285 min_feed_div = feedback_div + 1;
1286 else
1287 max_feed_div = feedback_div;
1288 }
1289 }
1290 }
1291
1292 *dot_clock_p = best_freq / 10000;
1293 *fb_div_p = best_feedback_div;
1294 *frac_fb_div_p = best_frac_feedback_div;
1295 *ref_div_p = best_ref_div;
1296 *post_div_p = best_post_div;
bbb0aef5
JP		 1297 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1298 (long long)freq,
1299 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
51d4bf84
AD		 1300 best_ref_div, best_post_div);
1301
771fe6b9
JG		 1302}
1303
1304static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1305{
1306 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 1307
29d08b3e 1308 if (radeon_fb->obj) {
bc9025bd 1309 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 1310 }
771fe6b9
JG		 1311 drm_framebuffer_cleanup(fb);
1312 kfree(radeon_fb);
1313}
1314
1315static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1316 struct drm_file *file_priv,
1317 unsigned int *handle)
1318{
1319 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1320
1321 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1322}
1323
1324static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1325 .destroy = radeon_user_framebuffer_destroy,
1326 .create_handle = radeon_user_framebuffer_create_handle,
1327};
1328
aaefcd42 1329int
38651674
DA		 1330radeon_framebuffer_init(struct drm_device *dev,
1331 struct radeon_framebuffer *rfb,
308e5bcb 1332 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 1333 struct drm_gem_object *obj)
771fe6b9 1334{
aaefcd42 1335 int ret;
38651674 1336 rfb->obj = obj;
c7d73f6a 1337 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
aaefcd42
DA		 1338 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1339 if (ret) {
1340 rfb->obj = NULL;
1341 return ret;
1342 }
aaefcd42 1343 return 0;
771fe6b9
JG		 1344}
1345
1346static struct drm_framebuffer *
1347radeon_user_framebuffer_create(struct drm_device *dev,
1348 struct drm_file *file_priv,
308e5bcb 1349 struct drm_mode_fb_cmd2 *mode_cmd)
771fe6b9
JG		 1350{
1351 struct drm_gem_object *obj;
38651674 1352 struct radeon_framebuffer *radeon_fb;
aaefcd42 1353 int ret;
771fe6b9 1354
308e5bcb 1355 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
7e71c9e2
JG		 1356 if (obj == NULL) {
1357 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
308e5bcb 1358 "can't create framebuffer\n", mode_cmd->handles[0]);
cce13ff7 1359 return ERR_PTR(-ENOENT);
7e71c9e2 1360 }
38651674
DA		 1361
1362 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
f2d68cf4 1363 if (radeon_fb == NULL) {
1364 drm_gem_object_unreference_unlocked(obj);
cce13ff7 1365 return ERR_PTR(-ENOMEM);
f2d68cf4 1366 }
38651674 1367
aaefcd42
DA		 1368 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1369 if (ret) {
1370 kfree(radeon_fb);
1371 drm_gem_object_unreference_unlocked(obj);
b2f4b03f 1372 return ERR_PTR(ret);
aaefcd42 1373 }
38651674
DA		 1374
1375 return &radeon_fb->base;
771fe6b9
JG		 1376}
1377
eb1f8e4f
DA		 1378static void radeon_output_poll_changed(struct drm_device *dev)
1379{
1380 struct radeon_device *rdev = dev->dev_private;
1381 radeon_fb_output_poll_changed(rdev);
1382}
1383
771fe6b9
JG		 1384static const struct drm_mode_config_funcs radeon_mode_funcs = {
1385 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 1386 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 1387};
1388
445282db
DA		 1389static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1390{ { 0, "driver" },
1391 { 1, "bios" },
1392};
1393
1394static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1395{ { TV_STD_NTSC, "ntsc" },
1396 { TV_STD_PAL, "pal" },
1397 { TV_STD_PAL_M, "pal-m" },
1398 { TV_STD_PAL_60, "pal-60" },
1399 { TV_STD_NTSC_J, "ntsc-j" },
1400 { TV_STD_SCART_PAL, "scart-pal" },
1401 { TV_STD_PAL_CN, "pal-cn" },
1402 { TV_STD_SECAM, "secam" },
1403};
1404
5b1714d3
AD		 1405static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1406{ { UNDERSCAN_OFF, "off" },
1407 { UNDERSCAN_ON, "on" },
1408 { UNDERSCAN_AUTO, "auto" },
1409};
1410
8666c076
AD		 1411static struct drm_prop_enum_list radeon_audio_enum_list[] =
1412{ { RADEON_AUDIO_DISABLE, "off" },
1413 { RADEON_AUDIO_ENABLE, "on" },
1414 { RADEON_AUDIO_AUTO, "auto" },
1415};
1416
6214bb74
AD		 1417/* XXX support different dither options? spatial, temporal, both, etc. */
1418static struct drm_prop_enum_list radeon_dither_enum_list[] =
1419{ { RADEON_FMT_DITHER_DISABLE, "off" },
1420 { RADEON_FMT_DITHER_ENABLE, "on" },
1421};
1422
d79766fa 1423static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db 1424{
4a67d391 1425 int sz;
445282db
DA		 1426
1427 if (rdev->is_atom_bios) {
1428 rdev->mode_info.coherent_mode_property =
d9bc3c02 1429 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
445282db
DA		 1430 if (!rdev->mode_info.coherent_mode_property)
1431 return -ENOMEM;
445282db
DA		 1432 }
1433
1434 if (!ASIC_IS_AVIVO(rdev)) {
1435 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1436 rdev->mode_info.tmds_pll_property =
4a67d391
SH		 1437 drm_property_create_enum(rdev->ddev, 0,
1438 "tmds_pll",
1439 radeon_tmds_pll_enum_list, sz);
445282db
DA		 1440 }
1441
1442 rdev->mode_info.load_detect_property =
d9bc3c02 1443 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
445282db
DA		 1444 if (!rdev->mode_info.load_detect_property)
1445 return -ENOMEM;
445282db
DA		 1446
1447 drm_mode_create_scaling_mode_property(rdev->ddev);
1448
1449 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1450 rdev->mode_info.tv_std_property =
4a67d391
SH		 1451 drm_property_create_enum(rdev->ddev, 0,
1452 "tv standard",
1453 radeon_tv_std_enum_list, sz);
445282db 1454
5b1714d3
AD		 1455 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1456 rdev->mode_info.underscan_property =
4a67d391
SH		 1457 drm_property_create_enum(rdev->ddev, 0,
1458 "underscan",
1459 radeon_underscan_enum_list, sz);
5b1714d3 1460
5bccf5e3 1461 rdev->mode_info.underscan_hborder_property =
d9bc3c02
SH		 1462 drm_property_create_range(rdev->ddev, 0,
1463 "underscan hborder", 0, 128);
5bccf5e3
MG		 1464 if (!rdev->mode_info.underscan_hborder_property)
1465 return -ENOMEM;
5bccf5e3
MG		 1466
1467 rdev->mode_info.underscan_vborder_property =
d9bc3c02
SH		 1468 drm_property_create_range(rdev->ddev, 0,
1469 "underscan vborder", 0, 128);
5bccf5e3
MG		 1470 if (!rdev->mode_info.underscan_vborder_property)
1471 return -ENOMEM;
5bccf5e3 1472
8666c076
AD		 1473 sz = ARRAY_SIZE(radeon_audio_enum_list);
1474 rdev->mode_info.audio_property =
1475 drm_property_create_enum(rdev->ddev, 0,
1476 "audio",
1477 radeon_audio_enum_list, sz);
1478
6214bb74
AD		 1479 sz = ARRAY_SIZE(radeon_dither_enum_list);
1480 rdev->mode_info.dither_property =
1481 drm_property_create_enum(rdev->ddev, 0,
1482 "dither",
1483 radeon_dither_enum_list, sz);
1484
445282db
DA		 1485 return 0;
1486}
1487
f46c0120
AD		 1488void radeon_update_display_priority(struct radeon_device *rdev)
1489{
1490 /* adjustment options for the display watermarks */
1491 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1492 /* set display priority to high for r3xx, rv515 chips
1493 * this avoids flickering due to underflow to the
1494 * display controllers during heavy acceleration.
45737447
AD		 1495 * Don't force high on rs4xx igp chips as it seems to
1496 * affect the sound card. See kernel bug 15982.
f46c0120 1497 */
45737447
AD		 1498 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1499 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1500 rdev->disp_priority = 2;
1501 else
1502 rdev->disp_priority = 0;
1503 } else
1504 rdev->disp_priority = radeon_disp_priority;
1505
1506}
1507
0783986a
AD		 1508/*
1509 * Allocate hdmi structs and determine register offsets
1510 */
1511static void radeon_afmt_init(struct radeon_device *rdev)
1512{
1513 int i;
1514
1515 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1516 rdev->mode_info.afmt[i] = NULL;
1517
b530602f
AD		 1518 if (ASIC_IS_NODCE(rdev)) {
1519 /* nothing to do */
0783986a 1520 } else if (ASIC_IS_DCE4(rdev)) {
a4d39e68
RM		 1521 static uint32_t eg_offsets[] = {
1522 EVERGREEN_CRTC0_REGISTER_OFFSET,
1523 EVERGREEN_CRTC1_REGISTER_OFFSET,
1524 EVERGREEN_CRTC2_REGISTER_OFFSET,
1525 EVERGREEN_CRTC3_REGISTER_OFFSET,
1526 EVERGREEN_CRTC4_REGISTER_OFFSET,
1527 EVERGREEN_CRTC5_REGISTER_OFFSET,
b530602f 1528 0x13830 - 0x7030,
a4d39e68
RM		 1529 };
1530 int num_afmt;
1531
b530602f
AD		 1532 /* DCE8 has 7 audio blocks tied to DIG encoders */
1533 /* DCE6 has 6 audio blocks tied to DIG encoders */
0783986a
AD		 1534 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1535 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
b530602f
AD		 1536 if (ASIC_IS_DCE8(rdev))
1537 num_afmt = 7;
1538 else if (ASIC_IS_DCE6(rdev))
1539 num_afmt = 6;
1540 else if (ASIC_IS_DCE5(rdev))
a4d39e68
RM		 1541 num_afmt = 6;
1542 else if (ASIC_IS_DCE41(rdev))
1543 num_afmt = 2;
1544 else /* DCE4 */
1545 num_afmt = 6;
1546
1547 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1548 for (i = 0; i < num_afmt; i++) {
1549 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1550 if (rdev->mode_info.afmt[i]) {
1551 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1552 rdev->mode_info.afmt[i]->id = i;
0783986a
AD		 1553 }
1554 }
1555 } else if (ASIC_IS_DCE3(rdev)) {
1556 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1557 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1558 if (rdev->mode_info.afmt[0]) {
1559 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1560 rdev->mode_info.afmt[0]->id = 0;
1561 }
1562 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1563 if (rdev->mode_info.afmt[1]) {
1564 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1565 rdev->mode_info.afmt[1]->id = 1;
1566 }
1567 } else if (ASIC_IS_DCE2(rdev)) {
1568 /* DCE2 has at least 1 routable audio block */
1569 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1570 if (rdev->mode_info.afmt[0]) {
1571 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1572 rdev->mode_info.afmt[0]->id = 0;
1573 }
1574 /* r6xx has 2 routable audio blocks */
1575 if (rdev->family >= CHIP_R600) {
1576 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1577 if (rdev->mode_info.afmt[1]) {
1578 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1579 rdev->mode_info.afmt[1]->id = 1;
1580 }
1581 }
1582 }
1583}
1584
1585static void radeon_afmt_fini(struct radeon_device *rdev)
1586{
1587 int i;
1588
1589 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1590 kfree(rdev->mode_info.afmt[i]);
1591 rdev->mode_info.afmt[i] = NULL;
1592 }
1593}
1594
771fe6b9
JG		 1595int radeon_modeset_init(struct radeon_device *rdev)
1596{
18917b60 1597 int i;
771fe6b9
JG		 1598 int ret;
1599
1600 drm_mode_config_init(rdev->ddev);
1601 rdev->mode_info.mode_config_initialized = true;
1602
e6ecefaa 1603 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
771fe6b9 1604
881dd74e
AD		 1605 if (ASIC_IS_DCE5(rdev)) {
1606 rdev->ddev->mode_config.max_width = 16384;
1607 rdev->ddev->mode_config.max_height = 16384;
1608 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 1609 rdev->ddev->mode_config.max_width = 8192;
1610 rdev->ddev->mode_config.max_height = 8192;
1611 } else {
1612 rdev->ddev->mode_config.max_width = 4096;
1613 rdev->ddev->mode_config.max_height = 4096;
1614 }
1615
019d96cb
DA		 1616 rdev->ddev->mode_config.preferred_depth = 24;
1617 rdev->ddev->mode_config.prefer_shadow = 1;
1618
771fe6b9
JG		 1619 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1620
445282db
DA		 1621 ret = radeon_modeset_create_props(rdev);
1622 if (ret) {
1623 return ret;
1624 }
dfee5614 1625
f376b94f
AD		 1626 /* init i2c buses */
1627 radeon_i2c_init(rdev);
1628
3c537889
AD		 1629 /* check combios for a valid hardcoded EDID - Sun servers */
1630 if (!rdev->is_atom_bios) {
1631 /* check for hardcoded EDID in BIOS */
1632 radeon_combios_check_hardcoded_edid(rdev);
1633 }
1634
dfee5614 1635 /* allocate crtcs */
18917b60 1636 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1637 radeon_crtc_init(rdev->ddev, i);
1638 }
1639
1640 /* okay we should have all the bios connectors */
1641 ret = radeon_setup_enc_conn(rdev->ddev);
1642 if (!ret) {
1643 return ret;
1644 }
ac89af1e 1645
3fa47d9e
AD		 1646 /* init dig PHYs, disp eng pll */
1647 if (rdev->is_atom_bios) {
ac89af1e 1648 radeon_atom_encoder_init(rdev);
f3f1f03e 1649 radeon_atom_disp_eng_pll_init(rdev);
3fa47d9e 1650 }
ac89af1e 1651
d4877cf2
AD		 1652 /* initialize hpd */
1653 radeon_hpd_init(rdev);
38651674 1654
0783986a
AD		 1655 /* setup afmt */
1656 radeon_afmt_init(rdev);
1657
38651674 1658 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1659 drm_kms_helper_poll_init(rdev->ddev);
1660
6c7bccea
AD		 1661 if (rdev->pm.dpm_enabled) {
1662 /* do dpm late init */
1663 ret = radeon_pm_late_init(rdev);
1664 if (ret) {
1665 rdev->pm.dpm_enabled = false;
1666 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1667 }
1668 /* set the dpm state for PX since there won't be
1669 * a modeset to call this.
1670 */
1671 radeon_pm_compute_clocks(rdev);
1672 }
1673
771fe6b9
JG		 1674 return 0;
1675}
1676
1677void radeon_modeset_fini(struct radeon_device *rdev)
1678{
38651674 1679 radeon_fbdev_fini(rdev);
3c537889
AD		 1680 kfree(rdev->mode_info.bios_hardcoded_edid);
1681
771fe6b9 1682 if (rdev->mode_info.mode_config_initialized) {
0783986a 1683 radeon_afmt_fini(rdev);
eb1f8e4f 1684 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1685 radeon_hpd_fini(rdev);
771fe6b9
JG		 1686 drm_mode_config_cleanup(rdev->ddev);
1687 rdev->mode_info.mode_config_initialized = false;
1688 }
f376b94f
AD		 1689 /* free i2c buses */
1690 radeon_i2c_fini(rdev);
771fe6b9
JG		 1691}
1692
e811f5ae 1693static bool is_hdtv_mode(const struct drm_display_mode *mode)
039ed2d9
AD		 1694{
1695 /* try and guess if this is a tv or a monitor */
1696 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1697 (mode->vdisplay == 576) || /* 576p */
1698 (mode->vdisplay == 720) || /* 720p */
1699 (mode->vdisplay == 1080)) /* 1080p */
1700 return true;
1701 else
1702 return false;
1703}
1704
c93bb85b 1705bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1706 const struct drm_display_mode *mode,
c93bb85b 1707 struct drm_display_mode *adjusted_mode)
771fe6b9 1708{
c93bb85b 1709 struct drm_device *dev = crtc->dev;
5b1714d3 1710 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1711 struct drm_encoder *encoder;
1712 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1713 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1714 struct drm_connector *connector;
1715 struct radeon_connector *radeon_connector;
c93bb85b 1716 bool first = true;
d65d65b1
AD		 1717 u32 src_v = 1, dst_v = 1;
1718 u32 src_h = 1, dst_h = 1;
771fe6b9 1719
5b1714d3
AD		 1720 radeon_crtc->h_border = 0;
1721 radeon_crtc->v_border = 0;
1722
c93bb85b 1723 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1724 if (encoder->crtc != crtc)
1725 continue;
d65d65b1 1726 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1727 connector = radeon_get_connector_for_encoder(encoder);
1728 radeon_connector = to_radeon_connector(connector);
1729
c93bb85b 1730 if (first) {
80297e87
AD		 1731 /* set scaling */
1732 if (radeon_encoder->rmx_type == RMX_OFF)
1733 radeon_crtc->rmx_type = RMX_OFF;
1734 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1735 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1736 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1737 else
1738 radeon_crtc->rmx_type = RMX_OFF;
1739 /* copy native mode */
c93bb85b 1740 memcpy(&radeon_crtc->native_mode,
80297e87 1741 &radeon_encoder->native_mode,
de2103e4 1742 sizeof(struct drm_display_mode));
ff32a59d
AD		 1743 src_v = crtc->mode.vdisplay;
1744 dst_v = radeon_crtc->native_mode.vdisplay;
1745 src_h = crtc->mode.hdisplay;
1746 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1747
1748 /* fix up for overscan on hdmi */
1749 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1750 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1751 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1752 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1753 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1754 is_hdtv_mode(mode)))) {
5bccf5e3
MG		 1755 if (radeon_encoder->underscan_hborder != 0)
1756 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1757 else
1758 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1759 if (radeon_encoder->underscan_vborder != 0)
1760 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1761 else
1762 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
5b1714d3
AD		 1763 radeon_crtc->rmx_type = RMX_FULL;
1764 src_v = crtc->mode.vdisplay;
1765 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1766 src_h = crtc->mode.hdisplay;
1767 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1768 }
c93bb85b
JG		 1769 first = false;
1770 } else {
1771 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1772 /* WARNING: Right now this can't happen but
1773 * in the future we need to check that scaling
d65d65b1 1774 * are consistent across different encoder
c93bb85b
JG		 1775 * (ie all encoder can work with the same
1776 * scaling).
1777 */
d65d65b1 1778 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1779 return false;
1780 }
771fe6b9
JG		 1781 }
1782 }
c93bb85b
JG		 1783 if (radeon_crtc->rmx_type != RMX_OFF) {
1784 fixed20_12 a, b;
d65d65b1
AD		 1785 a.full = dfixed_const(src_v);
1786 b.full = dfixed_const(dst_v);
68adac5e 1787 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1788 a.full = dfixed_const(src_h);
1789 b.full = dfixed_const(dst_h);
68adac5e 1790 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1791 } else {
68adac5e
BS		 1792 radeon_crtc->vsc.full = dfixed_const(1);
1793 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1794 }
c93bb85b 1795 return true;
771fe6b9 1796}
6383cf7d
MK		 1797
1798/*
d47abc58
MK		 1799 * Retrieve current video scanout position of crtc on a given gpu, and
1800 * an optional accurate timestamp of when query happened.
6383cf7d 1801 *
f5a80209 1802 * \param dev Device to query.
6383cf7d 1803 * \param crtc Crtc to query.
abca9e45 1804 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
6383cf7d
MK		 1805 * \param *vpos Location where vertical scanout position should be stored.
1806 * \param *hpos Location where horizontal scanout position should go.
d47abc58
MK		 1807 * \param *stime Target location for timestamp taken immediately before
1808 * scanout position query. Can be NULL to skip timestamp.
1809 * \param *etime Target location for timestamp taken immediately after
1810 * scanout position query. Can be NULL to skip timestamp.
6383cf7d
MK		 1811 *
1812 * Returns vpos as a positive number while in active scanout area.
1813 * Returns vpos as a negative number inside vblank, counting the number
1814 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1815 * until start of active scanout / end of vblank."
1816 *
1817 * \return Flags, or'ed together as follows:
1818 *
25985edc 1819 * DRM_SCANOUTPOS_VALID = Query successful.
f5a80209
MK		 1820 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1821 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
6383cf7d
MK		 1822 * this flag means that returned position may be offset by a constant but
1823 * unknown small number of scanlines wrt. real scanout position.
1824 *
1825 */
abca9e45
VS		 1826int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1827 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
6383cf7d
MK		 1828{
1829 u32 stat_crtc = 0, vbl = 0, position = 0;
1830 int vbl_start, vbl_end, vtotal, ret = 0;
1831 bool in_vbl = true;
1832
f5a80209
MK		 1833 struct radeon_device *rdev = dev->dev_private;
1834
d47abc58
MK		 1835 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1836
1837 /* Get optional system timestamp before query. */
1838 if (stime)
1839 *stime = ktime_get();
1840
6383cf7d
MK		 1841 if (ASIC_IS_DCE4(rdev)) {
1842 if (crtc == 0) {
1843 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1844 EVERGREEN_CRTC0_REGISTER_OFFSET);
1845 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1846 EVERGREEN_CRTC0_REGISTER_OFFSET);
f5a80209 1847 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1848 }
1849 if (crtc == 1) {
1850 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1851 EVERGREEN_CRTC1_REGISTER_OFFSET);
1852 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1853 EVERGREEN_CRTC1_REGISTER_OFFSET);
f5a80209 1854 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1855 }
1856 if (crtc == 2) {
1857 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1858 EVERGREEN_CRTC2_REGISTER_OFFSET);
1859 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1860 EVERGREEN_CRTC2_REGISTER_OFFSET);
f5a80209 1861 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1862 }
1863 if (crtc == 3) {
1864 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1865 EVERGREEN_CRTC3_REGISTER_OFFSET);
1866 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1867 EVERGREEN_CRTC3_REGISTER_OFFSET);
f5a80209 1868 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1869 }
1870 if (crtc == 4) {
1871 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1872 EVERGREEN_CRTC4_REGISTER_OFFSET);
1873 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1874 EVERGREEN_CRTC4_REGISTER_OFFSET);
f5a80209 1875 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1876 }
1877 if (crtc == 5) {
1878 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1879 EVERGREEN_CRTC5_REGISTER_OFFSET);
1880 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1881 EVERGREEN_CRTC5_REGISTER_OFFSET);
f5a80209 1882 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1883 }
1884 } else if (ASIC_IS_AVIVO(rdev)) {
1885 if (crtc == 0) {
1886 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1887 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
f5a80209 1888 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1889 }
1890 if (crtc == 1) {
1891 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1892 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
f5a80209 1893 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1894 }
1895 } else {
1896 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1897 if (crtc == 0) {
1898 /* Assume vbl_end == 0, get vbl_start from
1899 * upper 16 bits.
1900 */
1901 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1902 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1903 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1904 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1905 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1906 if (!(stat_crtc & 1))
1907 in_vbl = false;
1908
f5a80209 1909 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1910 }
1911 if (crtc == 1) {
1912 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1913 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1914 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1915 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1916 if (!(stat_crtc & 1))
1917 in_vbl = false;
1918
f5a80209 1919 ret |= DRM_SCANOUTPOS_VALID;
6383cf7d
MK		 1920 }
1921 }
1922
d47abc58
MK		 1923 /* Get optional system timestamp after query. */
1924 if (etime)
1925 *etime = ktime_get();
1926
1927 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1928
6383cf7d
MK		 1929 /* Decode into vertical and horizontal scanout position. */
1930 *vpos = position & 0x1fff;
1931 *hpos = (position >> 16) & 0x1fff;
1932
1933 /* Valid vblank area boundaries from gpu retrieved? */
1934 if (vbl > 0) {
1935 /* Yes: Decode. */
f5a80209 1936 ret |= DRM_SCANOUTPOS_ACCURATE;
6383cf7d
MK		 1937 vbl_start = vbl & 0x1fff;
1938 vbl_end = (vbl >> 16) & 0x1fff;
1939 }
1940 else {
1941 /* No: Fake something reasonable which gives at least ok results. */
f5a80209 1942 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
6383cf7d
MK		 1943 vbl_end = 0;
1944 }
1945
1946 /* Test scanout position against vblank region. */
1947 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1948 in_vbl = false;
1949
1950 /* Check if inside vblank area and apply corrective offsets:
1951 * vpos will then be >=0 in video scanout area, but negative
1952 * within vblank area, counting down the number of lines until
1953 * start of scanout.
1954 */
1955
1956 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1957 if (in_vbl && (*vpos >= vbl_start)) {
f5a80209 1958 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
6383cf7d
MK		 1959 *vpos = *vpos - vtotal;
1960 }
1961
1962 /* Correct for shifted end of vbl at vbl_end. */
1963 *vpos = *vpos - vbl_end;
1964
1965 /* In vblank? */
1966 if (in_vbl)
f5a80209 1967 ret |= DRM_SCANOUTPOS_INVBL;
6383cf7d 1968
8072bfa6
VS		 1969 /* Is vpos outside nominal vblank area, but less than
1970 * 1/100 of a frame height away from start of vblank?
1971 * If so, assume this isn't a massively delayed vblank
1972 * interrupt, but a vblank interrupt that fired a few
1973 * microseconds before true start of vblank. Compensate
1974 * by adding a full frame duration to the final timestamp.
1975 * Happens, e.g., on ATI R500, R600.
1976 *
1977 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1978 */
1979 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1980 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1981 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1982
1983 if (vbl_start - *vpos < vtotal / 100) {
1984 *vpos -= vtotal;
1985
1986 /* Signal this correction as "applied". */
1987 ret |= 0x8;
1988 }
1989 }
1990
6383cf7d
MK		 1991 return ret;
1992}
Linux kernel - Deliverables
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