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drm/radeon: convert to pmops
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
771fe6b9
JG		 39
40
771fe6b9
JG		 41/*
42 * KMS wrapper.
0de1a57b
DA		 43 * - 2.0.0 - initial interface
44 * - 2.1.0 - add square tiling interface
fdb43528 45 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 47 * - 2.4.0 - add crtc id query
148a03bc 48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 53 * 2.10.0 - fusion 2D tiling
54 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 55 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 56 * 2.13.0 - virtual memory support, streamout
285484e2 57 * 2.14.0 - add evergreen tiling informations
609c1e15 58 * 2.15.0 - add max_pipes query
d2609875 59 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 60 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 61 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 62 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 63 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 64 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 65 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 66 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 67 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 68 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 69 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 70 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 72 * 2.29.0 - R500 FP16 color clear registers
774c389f 73 * 2.30.0 - fix for FMASK texturing
a0a53aa8 74 * 2.31.0 - Add fastfb support for rs690
902aaef6 75 * 2.32.0 - new info request for rings working
64d7b8be 76 * 2.33.0 - Add SI tiling mode array query
39aee490 77 * 2.34.0 - Add CIK tiling mode array query
771fe6b9
JG		 78 */
79#define KMS_DRIVER_MAJOR 2
39aee490 80#define KMS_DRIVER_MINOR 34
771fe6b9
JG		 81#define KMS_DRIVER_PATCHLEVEL 0
82int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
83int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 84void radeon_driver_lastclose_kms(struct drm_device *dev);
85int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
86void radeon_driver_postclose_kms(struct drm_device *dev,
87 struct drm_file *file_priv);
88void radeon_driver_preclose_kms(struct drm_device *dev,
89 struct drm_file *file_priv);
7473e830
DA		 90int radeon_suspend_kms(struct drm_device *dev, bool suspend);
91int radeon_resume_kms(struct drm_device *dev, bool resume);
771fe6b9
JG		 92u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
93int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
94void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK		 95int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
96 int *max_error,
97 struct timeval *vblank_time,
98 unsigned flags);
771fe6b9
JG		 99void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
100int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
101void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
102irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
771fe6b9 103void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 104int radeon_gem_object_open(struct drm_gem_object *obj,
105 struct drm_file *file_priv);
106void radeon_gem_object_close(struct drm_gem_object *obj,
107 struct drm_file *file_priv);
f5a80209
MK		 108extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
109 int *vpos, int *hpos);
baa70943 110extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 111extern int radeon_max_kms_ioctl;
112int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 113int radeon_mode_dumb_mmap(struct drm_file *filp,
114 struct drm_device *dev,
115 uint32_t handle, uint64_t *offset_p);
116int radeon_mode_dumb_create(struct drm_file *file_priv,
117 struct drm_device *dev,
118 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 119struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
120struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
121 size_t size,
122 struct sg_table *sg);
123int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 124void radeon_gem_prime_unpin(struct drm_gem_object *obj);
1e6d17a5
AP		 125void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
126void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 127extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
128 unsigned long arg);
ff72145b 129
771fe6b9
JG		 130#if defined(CONFIG_DEBUG_FS)
131int radeon_debugfs_init(struct drm_minor *minor);
132void radeon_debugfs_cleanup(struct drm_minor *minor);
133#endif
771fe6b9 134
14adc892
CK		 135/* atpx handler */
136#if defined(CONFIG_VGA_SWITCHEROO)
137void radeon_register_atpx_handler(void);
138void radeon_unregister_atpx_handler(void);
139#else
140static inline void radeon_register_atpx_handler(void) {}
141static inline void radeon_unregister_atpx_handler(void) {}
142#endif
1da177e4 143
689b9d74 144int radeon_no_wb;
e9ced8e0 145int radeon_modeset = -1;
771fe6b9
JG		 146int radeon_dynclks = -1;
147int radeon_r4xx_atom = 0;
148int radeon_agpmode = 0;
149int radeon_vram_limit = 0;
edcd26e8 150int radeon_gart_size = -1; /* auto */
771fe6b9 151int radeon_benchmarking = 0;
ecc0b326 152int radeon_testing = 0;
771fe6b9 153int radeon_connector_table = 0;
4ce001ab 154int radeon_tv = 1;
8666c076 155int radeon_audio = 1;
f46c0120 156int radeon_disp_priority = 0;
e2b0a8e1 157int radeon_hw_i2c = 0;
197bbb3d 158int radeon_pcie_gen2 = -1;
a18cee15 159int radeon_msi = -1;
3368ff0c 160int radeon_lockup_timeout = 10000;
a0a53aa8 161int radeon_fastfb = 0;
da321c8a 162int radeon_dpm = -1;
1294d4a3 163int radeon_aspm = -1;
689b9d74 164
61a2d07d 165MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 166module_param_named(no_wb, radeon_no_wb, int, 0444);
167
771fe6b9
JG		 168MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
169module_param_named(modeset, radeon_modeset, int, 0400);
170
171MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
172module_param_named(dynclks, radeon_dynclks, int, 0444);
173
174MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
175module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
176
177MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
178module_param_named(vramlimit, radeon_vram_limit, int, 0600);
179
180MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
181module_param_named(agpmode, radeon_agpmode, int, 0444);
182
edcd26e8 183MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 184module_param_named(gartsize, radeon_gart_size, int, 0600);
185
186MODULE_PARM_DESC(benchmark, "Run benchmark");
187module_param_named(benchmark, radeon_benchmarking, int, 0444);
188
ecc0b326
MD		 189MODULE_PARM_DESC(test, "Run tests");
190module_param_named(test, radeon_testing, int, 0444);
191
771fe6b9
JG		 192MODULE_PARM_DESC(connector_table, "Force connector table");
193module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 194
195MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
196module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 197
805c2216 198MODULE_PARM_DESC(audio, "Audio enable (1 = enable)");
dafc3bd5
CK		 199module_param_named(audio, radeon_audio, int, 0444);
200
f46c0120
AD		 201MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
202module_param_named(disp_priority, radeon_disp_priority, int, 0444);
203
e2b0a8e1
AD		 204MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
205module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
206
197bbb3d 207MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 208module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
209
a18cee15
AD		 210MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
211module_param_named(msi, radeon_msi, int, 0444);
212
3368ff0c
CK		 213MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
214module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
215
a0a53aa8
SL		 216MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
217module_param_named(fastfb, radeon_fastfb, int, 0444);
218
da321c8a
AD		 219MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
220module_param_named(dpm, radeon_dpm, int, 0444);
221
1294d4a3
AD		 222MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
223module_param_named(aspm, radeon_aspm, int, 0444);
224
14adc892
CK		 225static struct pci_device_id pciidlist[] = {
226 radeon_PCI_IDS
227};
228
229MODULE_DEVICE_TABLE(pci, pciidlist);
230
231#ifdef CONFIG_DRM_RADEON_UMS
232
0a3e67a4
JB		 233static int radeon_suspend(struct drm_device *dev, pm_message_t state)
234{
235 drm_radeon_private_t *dev_priv = dev->dev_private;
236
03efb885
DA		 237 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
238 return 0;
239
0a3e67a4 240 /* Disable *all* interrupts */
800b6995 241 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 242 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
243 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
244 return 0;
245}
246
247static int radeon_resume(struct drm_device *dev)
248{
249 drm_radeon_private_t *dev_priv = dev->dev_private;
250
03efb885
DA		 251 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
252 return 0;
253
0a3e67a4 254 /* Restore interrupt registers */
800b6995 255 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 256 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
257 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
258 return 0;
259}
260
e08e96de
AV		 261static const struct file_operations radeon_driver_old_fops = {
262 .owner = THIS_MODULE,
263 .open = drm_open,
264 .release = drm_release,
265 .unlocked_ioctl = drm_ioctl,
266 .mmap = drm_mmap,
267 .poll = drm_poll,
e08e96de
AV		 268 .read = drm_read,
269#ifdef CONFIG_COMPAT
270 .compat_ioctl = radeon_compat_ioctl,
271#endif
272 .llseek = noop_llseek,
273};
274
771fe6b9 275static struct drm_driver driver_old = {
b5e89ed5 276 .driver_features =
28185647 277 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 278 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 279 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA		 280 .load = radeon_driver_load,
281 .firstopen = radeon_driver_firstopen,
282 .open = radeon_driver_open,
283 .preclose = radeon_driver_preclose,
284 .postclose = radeon_driver_postclose,
285 .lastclose = radeon_driver_lastclose,
286 .unload = radeon_driver_unload,
0a3e67a4
JB		 287 .suspend = radeon_suspend,
288 .resume = radeon_resume,
289 .get_vblank_counter = radeon_get_vblank_counter,
290 .enable_vblank = radeon_enable_vblank,
291 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA		 292 .master_create = radeon_master_create,
293 .master_destroy = radeon_master_destroy,
1da177e4
LT		 294 .irq_preinstall = radeon_driver_irq_preinstall,
295 .irq_postinstall = radeon_driver_irq_postinstall,
296 .irq_uninstall = radeon_driver_irq_uninstall,
297 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT		 298 .ioctls = radeon_ioctls,
299 .dma_ioctl = radeon_cp_buffers,
e08e96de 300 .fops = &radeon_driver_old_fops,
22eae947
DA		 301 .name = DRIVER_NAME,
302 .desc = DRIVER_DESC,
303 .date = DRIVER_DATE,
304 .major = DRIVER_MAJOR,
305 .minor = DRIVER_MINOR,
306 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 307};
308
14adc892
CK		 309#endif
310
771fe6b9
JG		 311static struct drm_driver kms_driver;
312
30238151 313static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 314{
315 struct apertures_struct *ap;
316 bool primary = false;
317
318 ap = alloc_apertures(1);
30238151
TR		 319 if (!ap)
320 return -ENOMEM;
321
a56f7428
BH		 322 ap->ranges[0].base = pci_resource_start(pdev, 0);
323 ap->ranges[0].size = pci_resource_len(pdev, 0);
324
325#ifdef CONFIG_X86
326 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
327#endif
328 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
329 kfree(ap);
30238151
TR		 330
331 return 0;
a56f7428
BH		 332}
333
56550d94
GKH		 334static int radeon_pci_probe(struct pci_dev *pdev,
335 const struct pci_device_id *ent)
771fe6b9 336{
30238151
TR		 337 int ret;
338
a56f7428 339 /* Get rid of things like offb */
30238151
TR		 340 ret = radeon_kick_out_firmware_fb(pdev);
341 if (ret)
342 return ret;
a56f7428 343
dcdb1674 344 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 345}
346
347static void
348radeon_pci_remove(struct pci_dev *pdev)
349{
350 struct drm_device *dev = pci_get_drvdata(pdev);
351
352 drm_put_dev(dev);
353}
354
7473e830 355static int radeon_pmops_suspend(struct device *dev)
771fe6b9 356{
7473e830
DA		 357 struct pci_dev *pdev = to_pci_dev(dev);
358 struct drm_device *drm_dev = pci_get_drvdata(pdev);
359 return radeon_suspend_kms(drm_dev, 1);
771fe6b9
JG		 360}
361
7473e830 362static int radeon_pmops_resume(struct device *dev)
771fe6b9 363{
7473e830
DA		 364 struct pci_dev *pdev = to_pci_dev(dev);
365 struct drm_device *drm_dev = pci_get_drvdata(pdev);
366 return radeon_resume_kms(drm_dev, 1);
367}
368
369static int radeon_pmops_freeze(struct device *dev)
370{
371 struct pci_dev *pdev = to_pci_dev(dev);
372 struct drm_device *drm_dev = pci_get_drvdata(pdev);
373 return radeon_suspend_kms(drm_dev, 0);
771fe6b9
JG		 374}
375
7473e830
DA		 376static int radeon_pmops_thaw(struct device *dev)
377{
378 struct pci_dev *pdev = to_pci_dev(dev);
379 struct drm_device *drm_dev = pci_get_drvdata(pdev);
380 return radeon_resume_kms(drm_dev, 0);
381}
382
383static const struct dev_pm_ops radeon_pm_ops = {
384 .suspend = radeon_pmops_suspend,
385 .resume = radeon_pmops_resume,
386 .freeze = radeon_pmops_freeze,
387 .thaw = radeon_pmops_thaw,
388 .poweroff = radeon_pmops_freeze,
389 .restore = radeon_pmops_resume,
390};
391
e08e96de
AV		 392static const struct file_operations radeon_driver_kms_fops = {
393 .owner = THIS_MODULE,
394 .open = drm_open,
395 .release = drm_release,
396 .unlocked_ioctl = drm_ioctl,
397 .mmap = radeon_mmap,
398 .poll = drm_poll,
e08e96de
AV		 399 .read = drm_read,
400#ifdef CONFIG_COMPAT
401 .compat_ioctl = radeon_kms_compat_ioctl,
402#endif
403};
404
771fe6b9
JG		 405static struct drm_driver kms_driver = {
406 .driver_features =
28185647 407 DRIVER_USE_AGP |
81e95697 408 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 409 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9
JG		 410 .dev_priv_size = 0,
411 .load = radeon_driver_load_kms,
771fe6b9
JG		 412 .open = radeon_driver_open_kms,
413 .preclose = radeon_driver_preclose_kms,
414 .postclose = radeon_driver_postclose_kms,
415 .lastclose = radeon_driver_lastclose_kms,
416 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 417 .get_vblank_counter = radeon_get_vblank_counter_kms,
418 .enable_vblank = radeon_enable_vblank_kms,
419 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 420 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
421 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 422#if defined(CONFIG_DEBUG_FS)
423 .debugfs_init = radeon_debugfs_init,
424 .debugfs_cleanup = radeon_debugfs_cleanup,
425#endif
426 .irq_preinstall = radeon_driver_irq_preinstall_kms,
427 .irq_postinstall = radeon_driver_irq_postinstall_kms,
428 .irq_uninstall = radeon_driver_irq_uninstall_kms,
429 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 430 .ioctls = radeon_ioctls_kms,
771fe6b9 431 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 432 .gem_open_object = radeon_gem_object_open,
433 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 434 .dumb_create = radeon_mode_dumb_create,
435 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 436 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 437 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 438
439 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
440 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1e6d17a5
AP		 441 .gem_prime_export = drm_gem_prime_export,
442 .gem_prime_import = drm_gem_prime_import,
443 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 444 .gem_prime_unpin = radeon_gem_prime_unpin,
1e6d17a5
AP		 445 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
446 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
447 .gem_prime_vmap = radeon_gem_prime_vmap,
448 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 449
771fe6b9
JG		 450 .name = DRIVER_NAME,
451 .desc = DRIVER_DESC,
452 .date = DRIVER_DATE,
453 .major = KMS_DRIVER_MAJOR,
454 .minor = KMS_DRIVER_MINOR,
455 .patchlevel = KMS_DRIVER_PATCHLEVEL,
456};
771fe6b9
JG		 457
458static struct drm_driver *driver;
8410ea3b
DA		 459static struct pci_driver *pdriver;
460
14adc892 461#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA		 462static struct pci_driver radeon_pci_driver = {
463 .name = DRIVER_NAME,
464 .id_table = pciidlist,
465};
14adc892 466#endif
8410ea3b
DA		 467
468static struct pci_driver radeon_kms_pci_driver = {
469 .name = DRIVER_NAME,
470 .id_table = pciidlist,
471 .probe = radeon_pci_probe,
472 .remove = radeon_pci_remove,
7473e830 473 .driver.pm = &radeon_pm_ops,
8410ea3b 474};
771fe6b9 475
1da177e4
LT		 476static int __init radeon_init(void)
477{
e9ced8e0
DA		 478#ifdef CONFIG_VGA_CONSOLE
479 if (vgacon_text_force() && radeon_modeset == -1) {
480 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
481 radeon_modeset = 0;
482 }
483#endif
484 /* set to modesetting by default if not nomodeset */
485 if (radeon_modeset == -1)
486 radeon_modeset = 1;
487
771fe6b9
JG		 488 if (radeon_modeset == 1) {
489 DRM_INFO("radeon kernel modesetting enabled.\n");
490 driver = &kms_driver;
8410ea3b 491 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 492 driver->driver_features |= DRIVER_MODESET;
493 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 494 radeon_register_atpx_handler();
14adc892
CK		 495
496 } else {
497#ifdef CONFIG_DRM_RADEON_UMS
498 DRM_INFO("radeon userspace modesetting enabled.\n");
499 driver = &driver_old;
500 pdriver = &radeon_pci_driver;
501 driver->driver_features &= ~DRIVER_MODESET;
502 driver->num_ioctls = radeon_max_ioctl;
503#else
504 DRM_ERROR("No UMS support in radeon module!\n");
505 return -EINVAL;
506#endif
771fe6b9 507 }
14adc892
CK		 508
509 /* let modprobe override vga console setting */
8410ea3b 510 return drm_pci_init(driver, pdriver);
1da177e4
LT		 511}
512
513static void __exit radeon_exit(void)
514{
8410ea3b 515 drm_pci_exit(driver, pdriver);
6a9ee8af 516 radeon_unregister_atpx_handler();
1da177e4
LT		 517}
518
176f613e 519module_init(radeon_init);
1da177e4
LT		 520module_exit(radeon_exit);
521
b5e89ed5
DA		 522MODULE_AUTHOR(DRIVER_AUTHOR);
523MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 524MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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