projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdkfd: Track when module's init is complete
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
14d20001 37#include <linux/apple-gmux.h>
771fe6b9 38#include <linux/console.h>
e0cd3608 39#include <linux/module.h>
10ebc0bc 40#include <linux/pm_runtime.h>
14d20001 41#include <linux/vgaarb.h>
10ebc0bc 42#include <linux/vga_switcheroo.h>
d9fc9413
DV		 43#include <drm/drm_gem.h>
44
10ebc0bc 45#include "drm_crtc_helper.h"
e28740ec
OG		 46#include "radeon_kfd.h"
47
771fe6b9
JG		 48/*
49 * KMS wrapper.
0de1a57b
DA		 50 * - 2.0.0 - initial interface
51 * - 2.1.0 - add square tiling interface
fdb43528 52 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 53 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 54 * - 2.4.0 - add crtc id query
148a03bc 55 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 56 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 57 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 58 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 59 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 60 * 2.10.0 - fusion 2D tiling
61 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 62 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 63 * 2.13.0 - virtual memory support, streamout
285484e2 64 * 2.14.0 - add evergreen tiling informations
609c1e15 65 * 2.15.0 - add max_pipes query
d2609875 66 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 67 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 68 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 69 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 70 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 71 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 72 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 73 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 74 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 75 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 76 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 77 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 78 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 79 * 2.29.0 - R500 FP16 color clear registers
774c389f 80 * 2.30.0 - fix for FMASK texturing
a0a53aa8 81 * 2.31.0 - Add fastfb support for rs690
902aaef6 82 * 2.32.0 - new info request for rings working
64d7b8be 83 * 2.33.0 - Add SI tiling mode array query
39aee490 84 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 85 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 86 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 87 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 88 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
89 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 90 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 91 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 92 * CS to GPU on >= r600
16613743 93 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 94 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 95 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
771fe6b9
JG		 96 */
97#define KMS_DRIVER_MAJOR 2
72b9076b 98#define KMS_DRIVER_MINOR 43
771fe6b9
JG		 99#define KMS_DRIVER_PATCHLEVEL 0
100int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
101int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 102void radeon_driver_lastclose_kms(struct drm_device *dev);
103int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
104void radeon_driver_postclose_kms(struct drm_device *dev,
105 struct drm_file *file_priv);
106void radeon_driver_preclose_kms(struct drm_device *dev,
107 struct drm_file *file_priv);
10ebc0bc
DA		 108int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
109int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 110u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
111int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
112void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
113int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
f5a80209
MK		 114 int *max_error,
115 struct timeval *vblank_time,
116 unsigned flags);
771fe6b9
JG		 117void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
118int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
119void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 120irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 121void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 122int radeon_gem_object_open(struct drm_gem_object *obj,
123 struct drm_file *file_priv);
124void radeon_gem_object_close(struct drm_gem_object *obj,
125 struct drm_file *file_priv);
f72a113a
CK		 126struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
127 struct drm_gem_object *gobj,
128 int flags);
88e72717
TR		 129extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
130 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 131 ktime_t *stime, ktime_t *etime,
132 const struct drm_display_mode *mode);
90c4cde9 133extern bool radeon_is_px(struct drm_device *dev);
baa70943 134extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 135extern int radeon_max_kms_ioctl;
136int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 137int radeon_mode_dumb_mmap(struct drm_file *filp,
138 struct drm_device *dev,
139 uint32_t handle, uint64_t *offset_p);
140int radeon_mode_dumb_create(struct drm_file *file_priv,
141 struct drm_device *dev,
142 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 143struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
144struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 145 struct dma_buf_attachment *,
1e6d17a5
AP		 146 struct sg_table *sg);
147int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 148void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 149struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 150void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
151void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 152extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
153 unsigned long arg);
ff72145b 154
771fe6b9
JG		 155#if defined(CONFIG_DEBUG_FS)
156int radeon_debugfs_init(struct drm_minor *minor);
157void radeon_debugfs_cleanup(struct drm_minor *minor);
158#endif
771fe6b9 159
14adc892
CK		 160/* atpx handler */
161#if defined(CONFIG_VGA_SWITCHEROO)
162void radeon_register_atpx_handler(void);
163void radeon_unregister_atpx_handler(void);
164#else
165static inline void radeon_register_atpx_handler(void) {}
166static inline void radeon_unregister_atpx_handler(void) {}
167#endif
1da177e4 168
689b9d74 169int radeon_no_wb;
e9ced8e0 170int radeon_modeset = -1;
771fe6b9
JG		 171int radeon_dynclks = -1;
172int radeon_r4xx_atom = 0;
173int radeon_agpmode = 0;
174int radeon_vram_limit = 0;
edcd26e8 175int radeon_gart_size = -1; /* auto */
771fe6b9 176int radeon_benchmarking = 0;
ecc0b326 177int radeon_testing = 0;
771fe6b9 178int radeon_connector_table = 0;
4ce001ab 179int radeon_tv = 1;
108dc8e8 180int radeon_audio = -1;
f46c0120 181int radeon_disp_priority = 0;
e2b0a8e1 182int radeon_hw_i2c = 0;
197bbb3d 183int radeon_pcie_gen2 = -1;
a18cee15 184int radeon_msi = -1;
3368ff0c 185int radeon_lockup_timeout = 10000;
a0a53aa8 186int radeon_fastfb = 0;
da321c8a 187int radeon_dpm = -1;
1294d4a3 188int radeon_aspm = -1;
10ebc0bc 189int radeon_runtime_pm = -1;
363eb0b4 190int radeon_hard_reset = 0;
dfc230f9
CK		 191int radeon_vm_size = 8;
192int radeon_vm_block_size = -1;
a624f429 193int radeon_deep_color = 0;
39dc5454 194int radeon_use_pflipirq = 2;
6e909f74 195int radeon_bapm = -1;
bc13018b 196int radeon_backlight = -1;
875711f0 197int radeon_auxch = -1;
9843ead0 198int radeon_mst = 0;
689b9d74 199
61a2d07d 200MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 201module_param_named(no_wb, radeon_no_wb, int, 0444);
202
771fe6b9
JG		 203MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
204module_param_named(modeset, radeon_modeset, int, 0400);
205
206MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
207module_param_named(dynclks, radeon_dynclks, int, 0444);
208
209MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
210module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
211
8902e6f2 212MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 213module_param_named(vramlimit, radeon_vram_limit, int, 0600);
214
215MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
216module_param_named(agpmode, radeon_agpmode, int, 0444);
217
edcd26e8 218MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 219module_param_named(gartsize, radeon_gart_size, int, 0600);
220
221MODULE_PARM_DESC(benchmark, "Run benchmark");
222module_param_named(benchmark, radeon_benchmarking, int, 0444);
223
ecc0b326
MD		 224MODULE_PARM_DESC(test, "Run tests");
225module_param_named(test, radeon_testing, int, 0444);
226
771fe6b9
JG		 227MODULE_PARM_DESC(connector_table, "Force connector table");
228module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 229
230MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
231module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 232
108dc8e8 233MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 234module_param_named(audio, radeon_audio, int, 0444);
235
f46c0120
AD		 236MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
237module_param_named(disp_priority, radeon_disp_priority, int, 0444);
238
e2b0a8e1
AD		 239MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
240module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
241
197bbb3d 242MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 243module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
244
a18cee15
AD		 245MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
246module_param_named(msi, radeon_msi, int, 0444);
247
b5c9ecab 248MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 249module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
250
a0a53aa8
SL		 251MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
252module_param_named(fastfb, radeon_fastfb, int, 0444);
253
da321c8a
AD		 254MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
255module_param_named(dpm, radeon_dpm, int, 0444);
256
1294d4a3
AD		 257MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
258module_param_named(aspm, radeon_aspm, int, 0444);
259
10ebc0bc
DA		 260MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
261module_param_named(runpm, radeon_runtime_pm, int, 0444);
262
363eb0b4
AD		 263MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
264module_param_named(hard_reset, radeon_hard_reset, int, 0444);
265
20b2656d 266MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 267module_param_named(vm_size, radeon_vm_size, int, 0444);
268
dfc230f9 269MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 270module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
271
a624f429
AD		 272MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
273module_param_named(deep_color, radeon_deep_color, int, 0444);
274
39dc5454
MK		 275MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
276module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
277
6e909f74
AD		 278MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
279module_param_named(bapm, radeon_bapm, int, 0444);
280
bc13018b
AD		 281MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
282module_param_named(backlight, radeon_backlight, int, 0444);
283
875711f0
DA		 284MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
285module_param_named(auxch, radeon_auxch, int, 0444);
286
9843ead0
DA		 287MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
288module_param_named(mst, radeon_mst, int, 0444);
289
14adc892
CK		 290static struct pci_device_id pciidlist[] = {
291 radeon_PCI_IDS
292};
293
294MODULE_DEVICE_TABLE(pci, pciidlist);
295
771fe6b9
JG		 296static struct drm_driver kms_driver;
297
30238151 298static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 299{
300 struct apertures_struct *ap;
301 bool primary = false;
302
303 ap = alloc_apertures(1);
30238151
TR		 304 if (!ap)
305 return -ENOMEM;
306
a56f7428
BH		 307 ap->ranges[0].base = pci_resource_start(pdev, 0);
308 ap->ranges[0].size = pci_resource_len(pdev, 0);
309
310#ifdef CONFIG_X86
311 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
312#endif
313 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
314 kfree(ap);
30238151
TR		 315
316 return 0;
a56f7428
BH		 317}
318
56550d94
GKH		 319static int radeon_pci_probe(struct pci_dev *pdev,
320 const struct pci_device_id *ent)
771fe6b9 321{
30238151
TR		 322 int ret;
323
14d20001
LW		 324 /*
325 * apple-gmux is needed on dual GPU MacBook Pro
326 * to probe the panel if we're the inactive GPU.
327 */
328 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
329 apple_gmux_present() && pdev != vga_default_device() &&
330 !vga_switcheroo_handler_flags())
331 return -EPROBE_DEFER;
332
a56f7428 333 /* Get rid of things like offb */
30238151
TR		 334 ret = radeon_kick_out_firmware_fb(pdev);
335 if (ret)
336 return ret;
a56f7428 337
dcdb1674 338 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 339}
340
341static void
342radeon_pci_remove(struct pci_dev *pdev)
343{
344 struct drm_device *dev = pci_get_drvdata(pdev);
345
346 drm_put_dev(dev);
347}
348
7473e830 349static int radeon_pmops_suspend(struct device *dev)
771fe6b9 350{
7473e830
DA		 351 struct pci_dev *pdev = to_pci_dev(dev);
352 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 353 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG		 354}
355
7473e830 356static int radeon_pmops_resume(struct device *dev)
771fe6b9 357{
7473e830
DA		 358 struct pci_dev *pdev = to_pci_dev(dev);
359 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 360 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 361}
362
363static int radeon_pmops_freeze(struct device *dev)
364{
365 struct pci_dev *pdev = to_pci_dev(dev);
366 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 367 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG		 368}
369
7473e830
DA		 370static int radeon_pmops_thaw(struct device *dev)
371{
372 struct pci_dev *pdev = to_pci_dev(dev);
373 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 374 return radeon_resume_kms(drm_dev, false, true);
375}
376
377static int radeon_pmops_runtime_suspend(struct device *dev)
378{
379 struct pci_dev *pdev = to_pci_dev(dev);
380 struct drm_device *drm_dev = pci_get_drvdata(pdev);
381 int ret;
382
90c4cde9 383 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 384 pm_runtime_forbid(dev);
385 return -EBUSY;
386 }
9babd35a 387
10ebc0bc
DA		 388 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
389 drm_kms_helper_poll_disable(drm_dev);
390 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
391
392 ret = radeon_suspend_kms(drm_dev, false, false);
393 pci_save_state(pdev);
394 pci_disable_device(pdev);
b440bde7 395 pci_ignore_hotplug(pdev);
10ebc0bc
DA		 396 pci_set_power_state(pdev, PCI_D3cold);
397 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
398
399 return 0;
400}
401
402static int radeon_pmops_runtime_resume(struct device *dev)
403{
404 struct pci_dev *pdev = to_pci_dev(dev);
405 struct drm_device *drm_dev = pci_get_drvdata(pdev);
406 int ret;
407
90c4cde9 408 if (!radeon_is_px(drm_dev))
9babd35a
AD		 409 return -EINVAL;
410
10ebc0bc
DA		 411 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
412
413 pci_set_power_state(pdev, PCI_D0);
414 pci_restore_state(pdev);
415 ret = pci_enable_device(pdev);
416 if (ret)
417 return ret;
418 pci_set_master(pdev);
419
420 ret = radeon_resume_kms(drm_dev, false, false);
421 drm_kms_helper_poll_enable(drm_dev);
422 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
423 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
424 return 0;
425}
426
427static int radeon_pmops_runtime_idle(struct device *dev)
428{
429 struct pci_dev *pdev = to_pci_dev(dev);
430 struct drm_device *drm_dev = pci_get_drvdata(pdev);
431 struct drm_crtc *crtc;
432
90c4cde9 433 if (!radeon_is_px(drm_dev)) {
1d8eec8b 434 pm_runtime_forbid(dev);
10ebc0bc
DA		 435 return -EBUSY;
436 }
437
438 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
439 if (crtc->enabled) {
440 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
441 return -EBUSY;
442 }
443 }
444
445 pm_runtime_mark_last_busy(dev);
446 pm_runtime_autosuspend(dev);
447 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
448 return 1;
449}
450
451long radeon_drm_ioctl(struct file *filp,
452 unsigned int cmd, unsigned long arg)
453{
454 struct drm_file *file_priv = filp->private_data;
455 struct drm_device *dev;
456 long ret;
457 dev = file_priv->minor->dev;
458 ret = pm_runtime_get_sync(dev->dev);
459 if (ret < 0)
460 return ret;
461
462 ret = drm_ioctl(filp, cmd, arg);
463
464 pm_runtime_mark_last_busy(dev->dev);
465 pm_runtime_put_autosuspend(dev->dev);
466 return ret;
7473e830
DA		 467}
468
469static const struct dev_pm_ops radeon_pm_ops = {
470 .suspend = radeon_pmops_suspend,
471 .resume = radeon_pmops_resume,
472 .freeze = radeon_pmops_freeze,
473 .thaw = radeon_pmops_thaw,
474 .poweroff = radeon_pmops_freeze,
475 .restore = radeon_pmops_resume,
10ebc0bc
DA		 476 .runtime_suspend = radeon_pmops_runtime_suspend,
477 .runtime_resume = radeon_pmops_runtime_resume,
478 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 479};
480
e08e96de
AV		 481static const struct file_operations radeon_driver_kms_fops = {
482 .owner = THIS_MODULE,
483 .open = drm_open,
484 .release = drm_release,
10ebc0bc 485 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 486 .mmap = radeon_mmap,
487 .poll = drm_poll,
e08e96de
AV		 488 .read = drm_read,
489#ifdef CONFIG_COMPAT
490 .compat_ioctl = radeon_kms_compat_ioctl,
491#endif
492};
493
771fe6b9
JG		 494static struct drm_driver kms_driver = {
495 .driver_features =
28185647 496 DRIVER_USE_AGP |
81e95697 497 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 498 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 499 .load = radeon_driver_load_kms,
771fe6b9
JG		 500 .open = radeon_driver_open_kms,
501 .preclose = radeon_driver_preclose_kms,
502 .postclose = radeon_driver_postclose_kms,
503 .lastclose = radeon_driver_lastclose_kms,
915b4d11 504 .set_busid = drm_pci_set_busid,
771fe6b9 505 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 506 .get_vblank_counter = radeon_get_vblank_counter_kms,
507 .enable_vblank = radeon_enable_vblank_kms,
508 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 509 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
510 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 511#if defined(CONFIG_DEBUG_FS)
512 .debugfs_init = radeon_debugfs_init,
513 .debugfs_cleanup = radeon_debugfs_cleanup,
514#endif
515 .irq_preinstall = radeon_driver_irq_preinstall_kms,
516 .irq_postinstall = radeon_driver_irq_postinstall_kms,
517 .irq_uninstall = radeon_driver_irq_uninstall_kms,
518 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 519 .ioctls = radeon_ioctls_kms,
771fe6b9 520 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 521 .gem_open_object = radeon_gem_object_open,
522 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 523 .dumb_create = radeon_mode_dumb_create,
524 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 525 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 526 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 527
528 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
529 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 530 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 531 .gem_prime_import = drm_gem_prime_import,
532 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 533 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 534 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 535 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
536 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
537 .gem_prime_vmap = radeon_gem_prime_vmap,
538 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 539
771fe6b9
JG		 540 .name = DRIVER_NAME,
541 .desc = DRIVER_DESC,
542 .date = DRIVER_DATE,
543 .major = KMS_DRIVER_MAJOR,
544 .minor = KMS_DRIVER_MINOR,
545 .patchlevel = KMS_DRIVER_PATCHLEVEL,
546};
771fe6b9
JG		 547
548static struct drm_driver *driver;
8410ea3b
DA		 549static struct pci_driver *pdriver;
550
8410ea3b
DA		 551static struct pci_driver radeon_kms_pci_driver = {
552 .name = DRIVER_NAME,
553 .id_table = pciidlist,
554 .probe = radeon_pci_probe,
555 .remove = radeon_pci_remove,
7473e830 556 .driver.pm = &radeon_pm_ops,
8410ea3b 557};
771fe6b9 558
1da177e4
LT		 559static int __init radeon_init(void)
560{
e9ced8e0
DA		 561#ifdef CONFIG_VGA_CONSOLE
562 if (vgacon_text_force() && radeon_modeset == -1) {
563 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
564 radeon_modeset = 0;
565 }
566#endif
567 /* set to modesetting by default if not nomodeset */
568 if (radeon_modeset == -1)
569 radeon_modeset = 1;
570
771fe6b9
JG		 571 if (radeon_modeset == 1) {
572 DRM_INFO("radeon kernel modesetting enabled.\n");
573 driver = &kms_driver;
8410ea3b 574 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 575 driver->driver_features |= DRIVER_MODESET;
576 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 577 radeon_register_atpx_handler();
14adc892
CK		 578
579 } else {
14adc892
CK		 580 DRM_ERROR("No UMS support in radeon module!\n");
581 return -EINVAL;
771fe6b9 582 }
14adc892 583
e28740ec
OG		 584 radeon_kfd_init();
585
14adc892 586 /* let modprobe override vga console setting */
8410ea3b 587 return drm_pci_init(driver, pdriver);
1da177e4
LT		 588}
589
590static void __exit radeon_exit(void)
591{
e28740ec 592 radeon_kfd_fini();
8410ea3b 593 drm_pci_exit(driver, pdriver);
6a9ee8af 594 radeon_unregister_atpx_handler();
1da177e4
LT		 595}
596
176f613e 597module_init(radeon_init);
1da177e4
LT		 598module_exit(radeon_exit);
599
b5e89ed5
DA		 600MODULE_AUTHOR(DRIVER_AUTHOR);
601MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 602MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
This page took 0.76152 seconds and 5 git commands to generate.