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drm: Extract <drm/drm_gem.h>
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
d9fc9413
DV		 41#include <drm/drm_gem.h>
42
10ebc0bc 43#include "drm_crtc_helper.h"
771fe6b9
JG		 44/*
45 * KMS wrapper.
0de1a57b
DA		 46 * - 2.0.0 - initial interface
47 * - 2.1.0 - add square tiling interface
fdb43528 48 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 49 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 50 * - 2.4.0 - add crtc id query
148a03bc 51 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 52 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 53 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 54 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 55 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 56 * 2.10.0 - fusion 2D tiling
57 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 58 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 59 * 2.13.0 - virtual memory support, streamout
285484e2 60 * 2.14.0 - add evergreen tiling informations
609c1e15 61 * 2.15.0 - add max_pipes query
d2609875 62 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 63 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 64 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 65 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 66 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 67 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 68 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 69 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 70 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 71 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 72 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 73 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 74 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 75 * 2.29.0 - R500 FP16 color clear registers
774c389f 76 * 2.30.0 - fix for FMASK texturing
a0a53aa8 77 * 2.31.0 - Add fastfb support for rs690
902aaef6 78 * 2.32.0 - new info request for rings working
64d7b8be 79 * 2.33.0 - Add SI tiling mode array query
39aee490 80 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 81 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 82 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 83 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 84 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
85 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 86 * 2.39.0 - Add INFO query for number of active CUs
72a9987e
MD		 87 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
88 * CS to GPU
771fe6b9
JG		 89 */
90#define KMS_DRIVER_MAJOR 2
72a9987e 91#define KMS_DRIVER_MINOR 40
771fe6b9
JG		 92#define KMS_DRIVER_PATCHLEVEL 0
93int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
94int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 95void radeon_driver_lastclose_kms(struct drm_device *dev);
96int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
97void radeon_driver_postclose_kms(struct drm_device *dev,
98 struct drm_file *file_priv);
99void radeon_driver_preclose_kms(struct drm_device *dev,
100 struct drm_file *file_priv);
10ebc0bc
DA		 101int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
102int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
771fe6b9
JG		 103u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
104int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
105void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
f5a80209
MK		 106int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
107 int *max_error,
108 struct timeval *vblank_time,
109 unsigned flags);
771fe6b9
JG		 110void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
111int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
112void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 113irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 114void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 115int radeon_gem_object_open(struct drm_gem_object *obj,
116 struct drm_file *file_priv);
117void radeon_gem_object_close(struct drm_gem_object *obj,
118 struct drm_file *file_priv);
f72a113a
CK		 119struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
120 struct drm_gem_object *gobj,
121 int flags);
f5a80209 122extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 123 unsigned int flags,
d47abc58
MK		 124 int *vpos, int *hpos, ktime_t *stime,
125 ktime_t *etime);
90c4cde9 126extern bool radeon_is_px(struct drm_device *dev);
baa70943 127extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 128extern int radeon_max_kms_ioctl;
129int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 130int radeon_mode_dumb_mmap(struct drm_file *filp,
131 struct drm_device *dev,
132 uint32_t handle, uint64_t *offset_p);
133int radeon_mode_dumb_create(struct drm_file *file_priv,
134 struct drm_device *dev,
135 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 136struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
137struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
138 size_t size,
139 struct sg_table *sg);
140int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 141void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 142struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 143void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
144void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 145extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
146 unsigned long arg);
ff72145b 147
771fe6b9
JG		 148#if defined(CONFIG_DEBUG_FS)
149int radeon_debugfs_init(struct drm_minor *minor);
150void radeon_debugfs_cleanup(struct drm_minor *minor);
151#endif
771fe6b9 152
14adc892
CK		 153/* atpx handler */
154#if defined(CONFIG_VGA_SWITCHEROO)
155void radeon_register_atpx_handler(void);
156void radeon_unregister_atpx_handler(void);
157#else
158static inline void radeon_register_atpx_handler(void) {}
159static inline void radeon_unregister_atpx_handler(void) {}
160#endif
1da177e4 161
689b9d74 162int radeon_no_wb;
e9ced8e0 163int radeon_modeset = -1;
771fe6b9
JG		 164int radeon_dynclks = -1;
165int radeon_r4xx_atom = 0;
166int radeon_agpmode = 0;
167int radeon_vram_limit = 0;
edcd26e8 168int radeon_gart_size = -1; /* auto */
771fe6b9 169int radeon_benchmarking = 0;
ecc0b326 170int radeon_testing = 0;
771fe6b9 171int radeon_connector_table = 0;
4ce001ab 172int radeon_tv = 1;
108dc8e8 173int radeon_audio = -1;
f46c0120 174int radeon_disp_priority = 0;
e2b0a8e1 175int radeon_hw_i2c = 0;
197bbb3d 176int radeon_pcie_gen2 = -1;
a18cee15 177int radeon_msi = -1;
3368ff0c 178int radeon_lockup_timeout = 10000;
a0a53aa8 179int radeon_fastfb = 0;
da321c8a 180int radeon_dpm = -1;
1294d4a3 181int radeon_aspm = -1;
10ebc0bc 182int radeon_runtime_pm = -1;
363eb0b4 183int radeon_hard_reset = 0;
dfc230f9
CK		 184int radeon_vm_size = 8;
185int radeon_vm_block_size = -1;
a624f429 186int radeon_deep_color = 0;
39dc5454 187int radeon_use_pflipirq = 2;
6e909f74 188int radeon_bapm = -1;
689b9d74 189
61a2d07d 190MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 191module_param_named(no_wb, radeon_no_wb, int, 0444);
192
771fe6b9
JG		 193MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
194module_param_named(modeset, radeon_modeset, int, 0400);
195
196MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
197module_param_named(dynclks, radeon_dynclks, int, 0444);
198
199MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
200module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
201
8902e6f2 202MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 203module_param_named(vramlimit, radeon_vram_limit, int, 0600);
204
205MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
206module_param_named(agpmode, radeon_agpmode, int, 0444);
207
edcd26e8 208MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 209module_param_named(gartsize, radeon_gart_size, int, 0600);
210
211MODULE_PARM_DESC(benchmark, "Run benchmark");
212module_param_named(benchmark, radeon_benchmarking, int, 0444);
213
ecc0b326
MD		 214MODULE_PARM_DESC(test, "Run tests");
215module_param_named(test, radeon_testing, int, 0444);
216
771fe6b9
JG		 217MODULE_PARM_DESC(connector_table, "Force connector table");
218module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 219
220MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
221module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 222
108dc8e8 223MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 224module_param_named(audio, radeon_audio, int, 0444);
225
f46c0120
AD		 226MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
227module_param_named(disp_priority, radeon_disp_priority, int, 0444);
228
e2b0a8e1
AD		 229MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
230module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
231
197bbb3d 232MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 233module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
234
a18cee15
AD		 235MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
236module_param_named(msi, radeon_msi, int, 0444);
237
3368ff0c
CK		 238MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
239module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
240
a0a53aa8
SL		 241MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
242module_param_named(fastfb, radeon_fastfb, int, 0444);
243
da321c8a
AD		 244MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
245module_param_named(dpm, radeon_dpm, int, 0444);
246
1294d4a3
AD		 247MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
248module_param_named(aspm, radeon_aspm, int, 0444);
249
10ebc0bc
DA		 250MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
251module_param_named(runpm, radeon_runtime_pm, int, 0444);
252
363eb0b4
AD		 253MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
254module_param_named(hard_reset, radeon_hard_reset, int, 0444);
255
20b2656d 256MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 257module_param_named(vm_size, radeon_vm_size, int, 0444);
258
dfc230f9 259MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 260module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
261
a624f429
AD		 262MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
263module_param_named(deep_color, radeon_deep_color, int, 0444);
264
39dc5454
MK		 265MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
266module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
267
6e909f74
AD		 268MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
269module_param_named(bapm, radeon_bapm, int, 0444);
270
14adc892
CK		 271static struct pci_device_id pciidlist[] = {
272 radeon_PCI_IDS
273};
274
275MODULE_DEVICE_TABLE(pci, pciidlist);
276
277#ifdef CONFIG_DRM_RADEON_UMS
278
0a3e67a4
JB		 279static int radeon_suspend(struct drm_device *dev, pm_message_t state)
280{
281 drm_radeon_private_t *dev_priv = dev->dev_private;
282
03efb885
DA		 283 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
284 return 0;
285
0a3e67a4 286 /* Disable *all* interrupts */
800b6995 287 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 288 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
289 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
290 return 0;
291}
292
293static int radeon_resume(struct drm_device *dev)
294{
295 drm_radeon_private_t *dev_priv = dev->dev_private;
296
03efb885
DA		 297 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
298 return 0;
299
0a3e67a4 300 /* Restore interrupt registers */
800b6995 301 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
0a3e67a4
JB		 302 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
303 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
304 return 0;
305}
306
10ebc0bc 307
e08e96de
AV		 308static const struct file_operations radeon_driver_old_fops = {
309 .owner = THIS_MODULE,
310 .open = drm_open,
311 .release = drm_release,
312 .unlocked_ioctl = drm_ioctl,
bfbf3c85 313 .mmap = drm_legacy_mmap,
e08e96de 314 .poll = drm_poll,
e08e96de
AV		 315 .read = drm_read,
316#ifdef CONFIG_COMPAT
317 .compat_ioctl = radeon_compat_ioctl,
318#endif
319 .llseek = noop_llseek,
320};
321
771fe6b9 322static struct drm_driver driver_old = {
b5e89ed5 323 .driver_features =
28185647 324 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
0a3e67a4 325 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
1da177e4 326 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
22eae947
DA		 327 .load = radeon_driver_load,
328 .firstopen = radeon_driver_firstopen,
329 .open = radeon_driver_open,
330 .preclose = radeon_driver_preclose,
331 .postclose = radeon_driver_postclose,
332 .lastclose = radeon_driver_lastclose,
915b4d11 333 .set_busid = drm_pci_set_busid,
22eae947 334 .unload = radeon_driver_unload,
0a3e67a4
JB		 335 .suspend = radeon_suspend,
336 .resume = radeon_resume,
337 .get_vblank_counter = radeon_get_vblank_counter,
338 .enable_vblank = radeon_enable_vblank,
339 .disable_vblank = radeon_disable_vblank,
60f2ee0b
DA		 340 .master_create = radeon_master_create,
341 .master_destroy = radeon_master_destroy,
1da177e4
LT		 342 .irq_preinstall = radeon_driver_irq_preinstall,
343 .irq_postinstall = radeon_driver_irq_postinstall,
344 .irq_uninstall = radeon_driver_irq_uninstall,
345 .irq_handler = radeon_driver_irq_handler,
1da177e4
LT		 346 .ioctls = radeon_ioctls,
347 .dma_ioctl = radeon_cp_buffers,
e08e96de 348 .fops = &radeon_driver_old_fops,
22eae947
DA		 349 .name = DRIVER_NAME,
350 .desc = DRIVER_DESC,
351 .date = DRIVER_DATE,
352 .major = DRIVER_MAJOR,
353 .minor = DRIVER_MINOR,
354 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 355};
356
14adc892
CK		 357#endif
358
771fe6b9
JG		 359static struct drm_driver kms_driver;
360
30238151 361static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 362{
363 struct apertures_struct *ap;
364 bool primary = false;
365
366 ap = alloc_apertures(1);
30238151
TR		 367 if (!ap)
368 return -ENOMEM;
369
a56f7428
BH		 370 ap->ranges[0].base = pci_resource_start(pdev, 0);
371 ap->ranges[0].size = pci_resource_len(pdev, 0);
372
373#ifdef CONFIG_X86
374 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
375#endif
376 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
377 kfree(ap);
30238151
TR		 378
379 return 0;
a56f7428
BH		 380}
381
56550d94
GKH		 382static int radeon_pci_probe(struct pci_dev *pdev,
383 const struct pci_device_id *ent)
771fe6b9 384{
30238151
TR		 385 int ret;
386
a56f7428 387 /* Get rid of things like offb */
30238151
TR		 388 ret = radeon_kick_out_firmware_fb(pdev);
389 if (ret)
390 return ret;
a56f7428 391
dcdb1674 392 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 393}
394
395static void
396radeon_pci_remove(struct pci_dev *pdev)
397{
398 struct drm_device *dev = pci_get_drvdata(pdev);
399
400 drm_put_dev(dev);
401}
402
7473e830 403static int radeon_pmops_suspend(struct device *dev)
771fe6b9 404{
7473e830
DA		 405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 407 return radeon_suspend_kms(drm_dev, true, true);
771fe6b9
JG		 408}
409
7473e830 410static int radeon_pmops_resume(struct device *dev)
771fe6b9 411{
7473e830
DA		 412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 414 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 415}
416
417static int radeon_pmops_freeze(struct device *dev)
418{
419 struct pci_dev *pdev = to_pci_dev(dev);
420 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 421 return radeon_suspend_kms(drm_dev, false, true);
771fe6b9
JG		 422}
423
7473e830
DA		 424static int radeon_pmops_thaw(struct device *dev)
425{
426 struct pci_dev *pdev = to_pci_dev(dev);
427 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 428 return radeon_resume_kms(drm_dev, false, true);
429}
430
431static int radeon_pmops_runtime_suspend(struct device *dev)
432{
433 struct pci_dev *pdev = to_pci_dev(dev);
434 struct drm_device *drm_dev = pci_get_drvdata(pdev);
435 int ret;
436
90c4cde9 437 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 438 pm_runtime_forbid(dev);
439 return -EBUSY;
440 }
9babd35a 441
10ebc0bc
DA		 442 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
443 drm_kms_helper_poll_disable(drm_dev);
444 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
445
446 ret = radeon_suspend_kms(drm_dev, false, false);
447 pci_save_state(pdev);
448 pci_disable_device(pdev);
449 pci_set_power_state(pdev, PCI_D3cold);
450 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
451
452 return 0;
453}
454
455static int radeon_pmops_runtime_resume(struct device *dev)
456{
457 struct pci_dev *pdev = to_pci_dev(dev);
458 struct drm_device *drm_dev = pci_get_drvdata(pdev);
459 int ret;
460
90c4cde9 461 if (!radeon_is_px(drm_dev))
9babd35a
AD		 462 return -EINVAL;
463
10ebc0bc
DA		 464 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
465
466 pci_set_power_state(pdev, PCI_D0);
467 pci_restore_state(pdev);
468 ret = pci_enable_device(pdev);
469 if (ret)
470 return ret;
471 pci_set_master(pdev);
472
473 ret = radeon_resume_kms(drm_dev, false, false);
474 drm_kms_helper_poll_enable(drm_dev);
475 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
476 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
477 return 0;
478}
479
480static int radeon_pmops_runtime_idle(struct device *dev)
481{
482 struct pci_dev *pdev = to_pci_dev(dev);
483 struct drm_device *drm_dev = pci_get_drvdata(pdev);
484 struct drm_crtc *crtc;
485
90c4cde9 486 if (!radeon_is_px(drm_dev)) {
1d8eec8b 487 pm_runtime_forbid(dev);
10ebc0bc
DA		 488 return -EBUSY;
489 }
490
491 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
492 if (crtc->enabled) {
493 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
494 return -EBUSY;
495 }
496 }
497
498 pm_runtime_mark_last_busy(dev);
499 pm_runtime_autosuspend(dev);
500 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
501 return 1;
502}
503
504long radeon_drm_ioctl(struct file *filp,
505 unsigned int cmd, unsigned long arg)
506{
507 struct drm_file *file_priv = filp->private_data;
508 struct drm_device *dev;
509 long ret;
510 dev = file_priv->minor->dev;
511 ret = pm_runtime_get_sync(dev->dev);
512 if (ret < 0)
513 return ret;
514
515 ret = drm_ioctl(filp, cmd, arg);
516
517 pm_runtime_mark_last_busy(dev->dev);
518 pm_runtime_put_autosuspend(dev->dev);
519 return ret;
7473e830
DA		 520}
521
522static const struct dev_pm_ops radeon_pm_ops = {
523 .suspend = radeon_pmops_suspend,
524 .resume = radeon_pmops_resume,
525 .freeze = radeon_pmops_freeze,
526 .thaw = radeon_pmops_thaw,
527 .poweroff = radeon_pmops_freeze,
528 .restore = radeon_pmops_resume,
10ebc0bc
DA		 529 .runtime_suspend = radeon_pmops_runtime_suspend,
530 .runtime_resume = radeon_pmops_runtime_resume,
531 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 532};
533
e08e96de
AV		 534static const struct file_operations radeon_driver_kms_fops = {
535 .owner = THIS_MODULE,
536 .open = drm_open,
537 .release = drm_release,
10ebc0bc 538 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 539 .mmap = radeon_mmap,
540 .poll = drm_poll,
e08e96de
AV		 541 .read = drm_read,
542#ifdef CONFIG_COMPAT
543 .compat_ioctl = radeon_kms_compat_ioctl,
544#endif
545};
546
771fe6b9
JG		 547static struct drm_driver kms_driver = {
548 .driver_features =
28185647 549 DRIVER_USE_AGP |
81e95697 550 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 551 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 552 .load = radeon_driver_load_kms,
771fe6b9
JG		 553 .open = radeon_driver_open_kms,
554 .preclose = radeon_driver_preclose_kms,
555 .postclose = radeon_driver_postclose_kms,
556 .lastclose = radeon_driver_lastclose_kms,
915b4d11 557 .set_busid = drm_pci_set_busid,
771fe6b9 558 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 559 .get_vblank_counter = radeon_get_vblank_counter_kms,
560 .enable_vblank = radeon_enable_vblank_kms,
561 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 562 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
563 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 564#if defined(CONFIG_DEBUG_FS)
565 .debugfs_init = radeon_debugfs_init,
566 .debugfs_cleanup = radeon_debugfs_cleanup,
567#endif
568 .irq_preinstall = radeon_driver_irq_preinstall_kms,
569 .irq_postinstall = radeon_driver_irq_postinstall_kms,
570 .irq_uninstall = radeon_driver_irq_uninstall_kms,
571 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 572 .ioctls = radeon_ioctls_kms,
771fe6b9 573 .gem_free_object = radeon_gem_object_free,
721604a1
JG		 574 .gem_open_object = radeon_gem_object_open,
575 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 576 .dumb_create = radeon_mode_dumb_create,
577 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 578 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 579 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 580
581 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
582 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 583 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 584 .gem_prime_import = drm_gem_prime_import,
585 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 586 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 587 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 588 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
589 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
590 .gem_prime_vmap = radeon_gem_prime_vmap,
591 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 592
771fe6b9
JG		 593 .name = DRIVER_NAME,
594 .desc = DRIVER_DESC,
595 .date = DRIVER_DATE,
596 .major = KMS_DRIVER_MAJOR,
597 .minor = KMS_DRIVER_MINOR,
598 .patchlevel = KMS_DRIVER_PATCHLEVEL,
599};
771fe6b9
JG		 600
601static struct drm_driver *driver;
8410ea3b
DA		 602static struct pci_driver *pdriver;
603
14adc892 604#ifdef CONFIG_DRM_RADEON_UMS
8410ea3b
DA		 605static struct pci_driver radeon_pci_driver = {
606 .name = DRIVER_NAME,
607 .id_table = pciidlist,
608};
14adc892 609#endif
8410ea3b
DA		 610
611static struct pci_driver radeon_kms_pci_driver = {
612 .name = DRIVER_NAME,
613 .id_table = pciidlist,
614 .probe = radeon_pci_probe,
615 .remove = radeon_pci_remove,
7473e830 616 .driver.pm = &radeon_pm_ops,
8410ea3b 617};
771fe6b9 618
1da177e4
LT		 619static int __init radeon_init(void)
620{
e9ced8e0
DA		 621#ifdef CONFIG_VGA_CONSOLE
622 if (vgacon_text_force() && radeon_modeset == -1) {
623 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
624 radeon_modeset = 0;
625 }
626#endif
627 /* set to modesetting by default if not nomodeset */
628 if (radeon_modeset == -1)
629 radeon_modeset = 1;
630
771fe6b9
JG		 631 if (radeon_modeset == 1) {
632 DRM_INFO("radeon kernel modesetting enabled.\n");
633 driver = &kms_driver;
8410ea3b 634 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 635 driver->driver_features |= DRIVER_MODESET;
636 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 637 radeon_register_atpx_handler();
14adc892
CK		 638
639 } else {
640#ifdef CONFIG_DRM_RADEON_UMS
641 DRM_INFO("radeon userspace modesetting enabled.\n");
642 driver = &driver_old;
643 pdriver = &radeon_pci_driver;
644 driver->driver_features &= ~DRIVER_MODESET;
645 driver->num_ioctls = radeon_max_ioctl;
646#else
647 DRM_ERROR("No UMS support in radeon module!\n");
648 return -EINVAL;
649#endif
771fe6b9 650 }
14adc892
CK		 651
652 /* let modprobe override vga console setting */
8410ea3b 653 return drm_pci_init(driver, pdriver);
1da177e4
LT		 654}
655
656static void __exit radeon_exit(void)
657{
8410ea3b 658 drm_pci_exit(driver, pdriver);
6a9ee8af 659 radeon_unregister_atpx_handler();
1da177e4
LT		 660}
661
176f613e 662module_init(radeon_init);
1da177e4
LT		 663module_exit(radeon_exit);
664
b5e89ed5
DA		 665MODULE_AUTHOR(DRIVER_AUTHOR);
666MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 667MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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