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drm: Use resource_size_t for drm_get_resource_{start, len}
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.h
CommitLineData
1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
c0beb2a7 41#define DRIVER_DATE "20080528"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
f2b04cd2
DA		 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
ddbee333 100 * 1.28- Add support for VBL on CRTC2
c0beb2a7 101 * 1.29- R500 3D cmd buffer support
1da177e4
LT		 102 */
103#define DRIVER_MAJOR 1
c0beb2a7 104#define DRIVER_MINOR 29
1da177e4
LT		 105#define DRIVER_PATCHLEVEL 0
106
1da177e4
LT		 107/*
108 * Radeon chip families
109 */
110enum radeon_family {
111 CHIP_R100,
1da177e4 112 CHIP_RV100,
dfab1154 113 CHIP_RS100,
1da177e4
LT		 114 CHIP_RV200,
115 CHIP_RS200,
dfab1154 116 CHIP_R200,
1da177e4 117 CHIP_RV250,
dfab1154 118 CHIP_RS300,
1da177e4
LT		 119 CHIP_RV280,
120 CHIP_R300,
414ed537 121 CHIP_R350,
1da177e4 122 CHIP_RV350,
dfab1154 123 CHIP_RV380,
414ed537 124 CHIP_R420,
edc6f389 125 CHIP_R423,
dfab1154 126 CHIP_RV410,
b2ceddfa 127 CHIP_RS400,
45e51905 128 CHIP_RS480,
60f92683 129 CHIP_RS690,
f0738e92 130 CHIP_RS740,
3d5e2c13
DA		 131 CHIP_RV515,
132 CHIP_R520,
133 CHIP_RV530,
134 CHIP_RV560,
135 CHIP_RV570,
136 CHIP_R580,
1da177e4
LT		 137 CHIP_LAST,
138};
139
140enum radeon_cp_microcode_version {
141 UCODE_R100,
142 UCODE_R200,
143 UCODE_R300,
144};
145
146/*
147 * Chip flags
148 */
149enum radeon_chip_flags {
54a56ac5
DA		 150 RADEON_FAMILY_MASK = 0x0000ffffUL,
151 RADEON_FLAGS_MASK = 0xffff0000UL,
152 RADEON_IS_MOBILITY = 0x00010000UL,
153 RADEON_IS_IGP = 0x00020000UL,
154 RADEON_SINGLE_CRTC = 0x00040000UL,
155 RADEON_IS_AGP = 0x00080000UL,
156 RADEON_HAS_HIERZ = 0x00100000UL,
157 RADEON_IS_PCIE = 0x00200000UL,
158 RADEON_NEW_MEMMAP = 0x00400000UL,
159 RADEON_IS_PCI = 0x00800000UL,
f2b04cd2 160 RADEON_IS_IGPGART = 0x01000000UL,
1da177e4
LT		 161};
162
d5ea702f
DA		 163#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
164 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 165#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
166
1da177e4 167typedef struct drm_radeon_freelist {
b5e89ed5 168 unsigned int age;
056219e2 169 struct drm_buf *buf;
b5e89ed5
DA		 170 struct drm_radeon_freelist *next;
171 struct drm_radeon_freelist *prev;
1da177e4
LT		 172} drm_radeon_freelist_t;
173
174typedef struct drm_radeon_ring_buffer {
175 u32 *start;
176 u32 *end;
177 int size;
178 int size_l2qw;
179
576cc458
RS		 180 int rptr_update; /* Double Words */
181 int rptr_update_l2qw; /* log2 Quad Words */
182
183 int fetch_size; /* Double Words */
184 int fetch_size_l2ow; /* log2 Oct Words */
185
1da177e4
LT		 186 u32 tail;
187 u32 tail_mask;
188 int space;
189
190 int high_mark;
191} drm_radeon_ring_buffer_t;
192
193typedef struct drm_radeon_depth_clear_t {
194 u32 rb3d_cntl;
195 u32 rb3d_zstencilcntl;
196 u32 se_cntl;
197} drm_radeon_depth_clear_t;
198
199struct drm_radeon_driver_file_fields {
200 int64_t radeon_fb_delta;
201};
202
203struct mem_block {
204 struct mem_block *next;
205 struct mem_block *prev;
206 int start;
207 int size;
6c340eac 208 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 209};
210
211struct radeon_surface {
212 int refcount;
213 u32 lower;
214 u32 upper;
215 u32 flags;
216};
217
218struct radeon_virt_surface {
219 int surface_index;
220 u32 lower;
221 u32 upper;
222 u32 flags;
6c340eac 223 struct drm_file *file_priv;
1da177e4
LT		 224};
225
54f961a6
JG		 226#define RADEON_FLUSH_EMITED (1 < 0)
227#define RADEON_PURGE_EMITED (1 < 1)
228
7c1c2871
DA		 229struct drm_radeon_master_private {
230 drm_local_map_t *sarea;
231 drm_radeon_sarea_t *sarea_priv;
232};
233
1da177e4
LT		 234typedef struct drm_radeon_private {
235 drm_radeon_ring_buffer_t ring;
1da177e4
LT		 236
237 u32 fb_location;
d5ea702f
DA		 238 u32 fb_size;
239 int new_memmap;
1da177e4
LT		 240
241 int gart_size;
242 u32 gart_vm_start;
243 unsigned long gart_buffers_offset;
244
245 int cp_mode;
246 int cp_running;
247
b5e89ed5
DA		 248 drm_radeon_freelist_t *head;
249 drm_radeon_freelist_t *tail;
1da177e4
LT		 250 int last_buf;
251 volatile u32 *scratch;
252 int writeback_works;
253
254 int usec_timeout;
255
256 int microcode_version;
257
1da177e4
LT		 258 struct {
259 u32 boxes;
260 int freelist_timeouts;
261 int freelist_loops;
262 int requested_bufs;
263 int last_frame_reads;
264 int last_clear_reads;
265 int clears;
266 int texture_uploads;
267 } stats;
268
269 int do_boxes;
270 int page_flipping;
1da177e4
LT		 271
272 u32 color_fmt;
273 unsigned int front_offset;
274 unsigned int front_pitch;
275 unsigned int back_offset;
276 unsigned int back_pitch;
277
278 u32 depth_fmt;
279 unsigned int depth_offset;
280 unsigned int depth_pitch;
281
282 u32 front_pitch_offset;
283 u32 back_pitch_offset;
284 u32 depth_pitch_offset;
285
286 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 287
1da177e4
LT		 288 unsigned long ring_offset;
289 unsigned long ring_rptr_offset;
290 unsigned long buffers_offset;
291 unsigned long gart_textures_offset;
292
293 drm_local_map_t *sarea;
1da177e4
LT		 294 drm_local_map_t *cp_ring;
295 drm_local_map_t *ring_rptr;
296 drm_local_map_t *gart_textures;
297
298 struct mem_block *gart_heap;
299 struct mem_block *fb_heap;
300
301 /* SW interrupt */
b5e89ed5
DA		 302 wait_queue_head_t swi_queue;
303 atomic_t swi_emitted;
ddbee333
DA		 304 int vblank_crtc;
305 uint32_t irq_enable_reg;
c0beb2a7 306 uint32_t r500_disp_irq_reg;
1da177e4
LT		 307
308 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 309 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 310
b5e89ed5 311 unsigned long pcigart_offset;
f2b04cd2 312 unsigned int pcigart_offset_set;
55910517 313 struct drm_ati_pcigart_info gart_info;
ea98a92f 314
ee4621f0
DA		 315 u32 scratch_ages[5];
316
1da177e4
LT		 317 /* starting from here on, data is preserved accross an open */
318 uint32_t flags; /* see radeon_chip_flags */
d883f7f1 319 resource_size_t fb_aper_offset;
5b92c404
AD		 320
321 int num_gb_pipes;
54f961a6 322 int track_flush;
78538bf1 323 drm_local_map_t *mmio;
1da177e4
LT		 324} drm_radeon_private_t;
325
326typedef struct drm_radeon_buf_priv {
327 u32 age;
328} drm_radeon_buf_priv_t;
329
b3a83639
DA		 330typedef struct drm_radeon_kcmd_buffer {
331 int bufsz;
332 char *buf;
333 int nbox;
c60ce623 334 struct drm_clip_rect __user *boxes;
b3a83639
DA		 335} drm_radeon_kcmd_buffer_t;
336
689b9d74 337extern int radeon_no_wb;
c153f45f 338extern struct drm_ioctl_desc radeon_ioctls[];
b3a83639
DA		 339extern int radeon_max_ioctl;
340
1d6bb8e5
MCA		 341/* Check whether the given hardware address is inside the framebuffer or the
342 * GART area.
343 */
344static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
345 u64 off)
346{
347 u32 fb_start = dev_priv->fb_location;
348 u32 fb_end = fb_start + dev_priv->fb_size - 1;
349 u32 gart_start = dev_priv->gart_vm_start;
350 u32 gart_end = gart_start + dev_priv->gart_size - 1;
351
352 return ((off >= fb_start && off <= fb_end) ||
353 (off >= gart_start && off <= gart_end));
354}
355
1da177e4 356 /* radeon_cp.c */
c153f45f
EA		 357extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
358extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
360extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
361extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
362extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
363extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
364extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
365extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
3d5e2c13 366extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
1da177e4 367
84b1fd10 368extern void radeon_freelist_reset(struct drm_device * dev);
056219e2 369extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
1da177e4 370
b5e89ed5 371extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 372
b5e89ed5 373extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 374
375extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 376extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 377extern int radeon_driver_postcleanup(struct drm_device *dev);
378
c153f45f
EA		 379extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
380extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
381extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 382extern void radeon_mem_takedown(struct mem_block **heap);
6c340eac
EA		 383extern void radeon_mem_release(struct drm_file *file_priv,
384 struct mem_block *heap);
1da177e4
LT		 385
386 /* radeon_irq.c */
0a3e67a4 387extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
c153f45f
EA		 388extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
389extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 390
84b1fd10 391extern void radeon_do_release(struct drm_device * dev);
0a3e67a4
JB		 392extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
393extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
394extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
b5e89ed5 395extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 396extern void radeon_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 397extern int radeon_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 398extern void radeon_driver_irq_uninstall(struct drm_device * dev);
7ecabc53 399extern void radeon_enable_interrupt(struct drm_device *dev);
84b1fd10
DA		 400extern int radeon_vblank_crtc_get(struct drm_device *dev);
401extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
1da177e4 402
22eae947
DA		 403extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
404extern int radeon_driver_unload(struct drm_device *dev);
405extern int radeon_driver_firstopen(struct drm_device *dev);
0a3e67a4
JB		 406extern void radeon_driver_preclose(struct drm_device *dev,
407 struct drm_file *file_priv);
408extern void radeon_driver_postclose(struct drm_device *dev,
409 struct drm_file *file_priv);
84b1fd10 410extern void radeon_driver_lastclose(struct drm_device * dev);
0a3e67a4
JB		 411extern int radeon_driver_open(struct drm_device *dev,
412 struct drm_file *file_priv);
9a186645
DA		 413extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
414 unsigned long arg);
415
7c1c2871
DA		 416extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
417extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
418extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
414ed537 419/* r300_cmdbuf.c */
3d5e2c13 420extern void r300_init_reg_flags(struct drm_device *dev);
414ed537 421
0a3e67a4 422extern int r300_do_cp_cmdbuf(struct drm_device *dev,
6c340eac 423 struct drm_file *file_priv,
0a3e67a4 424 drm_radeon_kcmd_buffer_t *cmdbuf);
414ed537 425
1da177e4
LT		 426/* Flags for stats.boxes
427 */
428#define RADEON_BOX_DMA_IDLE 0x1
429#define RADEON_BOX_RING_FULL 0x2
430#define RADEON_BOX_FLIP 0x4
431#define RADEON_BOX_WAIT_IDLE 0x8
432#define RADEON_BOX_TEXTURE_LOAD 0x10
433
1da177e4
LT		 434/* Register definitions, register access macros and drmAddMap constants
435 * for Radeon kernel driver.
436 */
437
438#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 439#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
440# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 441#define RADEON_AUX_SCISSOR_CNTL 0x26f0
442# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
443# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
444# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
445# define RADEON_SCISSOR_0_ENABLE (1 << 28)
446# define RADEON_SCISSOR_1_ENABLE (1 << 29)
447# define RADEON_SCISSOR_2_ENABLE (1 << 30)
448
edc6f389
AD		 449/*
450 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
451 * don't have an explicit bus mastering disable bit. It's handled
452 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
453 * handling, not bus mastering itself.
454 */
1da177e4 455#define RADEON_BUS_CNTL 0x0030
4e270e9b 456/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
1da177e4 457# define RADEON_BUS_MASTER_DIS (1 << 6)
4e270e9b
AD		 458/* rs600/rs690/rs740 */
459# define RS600_BUS_MASTER_DIS (1 << 14)
460# define RS600_MSI_REARM (1 << 20)
461/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
edc6f389
AD		 462
463#define RADEON_BUS_CNTL1 0x0034
464# define RADEON_PMI_BM_DIS (1 << 2)
465# define RADEON_PMI_INT_DIS (1 << 3)
466
467#define RV370_BUS_CNTL 0x004c
468# define RV370_PMI_BM_DIS (1 << 5)
469# define RV370_PMI_INT_DIS (1 << 6)
470
471#define RADEON_MSI_REARM_EN 0x0160
472/* rv370/rv380, rv410, r423/r430/r480, r5xx */
473# define RV370_MSI_REARM_EN (1 << 0)
1da177e4
LT		 474
475#define RADEON_CLOCK_CNTL_DATA 0x000c
476# define RADEON_PLL_WR_EN (1 << 7)
477#define RADEON_CLOCK_CNTL_INDEX 0x0008
478#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 479#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 480#define RADEON_CRTC_OFFSET 0x0224
481#define RADEON_CRTC_OFFSET_CNTL 0x0228
482# define RADEON_CRTC_TILE_EN (1 << 15)
483# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
484#define RADEON_CRTC2_OFFSET 0x0324
485#define RADEON_CRTC2_OFFSET_CNTL 0x0328
486
ea98a92f
DA		 487#define RADEON_PCIE_INDEX 0x0030
488#define RADEON_PCIE_DATA 0x0034
489#define RADEON_PCIE_TX_GART_CNTL 0x10
bc5f4523 490# define RADEON_PCIE_TX_GART_EN (1 << 0)
2735977b
AD		 491# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
492# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
493# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
494# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
495# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
496# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
497# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
ea98a92f
DA		 498#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
499#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
bc5f4523 500#define RADEON_PCIE_TX_GART_BASE 0x13
ea98a92f
DA		 501#define RADEON_PCIE_TX_GART_START_LO 0x14
502#define RADEON_PCIE_TX_GART_START_HI 0x15
503#define RADEON_PCIE_TX_GART_END_LO 0x16
504#define RADEON_PCIE_TX_GART_END_HI 0x17
505
45e51905
AD		 506#define RS480_NB_MC_INDEX 0x168
507# define RS480_NB_MC_IND_WR_EN (1 << 8)
508#define RS480_NB_MC_DATA 0x16c
f2b04cd2 509
60f92683
MC		 510#define RS690_MC_INDEX 0x78
511# define RS690_MC_INDEX_MASK 0x1ff
512# define RS690_MC_INDEX_WR_EN (1 << 9)
513# define RS690_MC_INDEX_WR_ACK 0x7f
514#define RS690_MC_DATA 0x7c
515
2735977b 516/* MC indirect registers */
45e51905
AD		 517#define RS480_MC_MISC_CNTL 0x18
518# define RS480_DISABLE_GTW (1 << 1)
2735977b 519/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
45e51905 520# define RS480_GART_INDEX_REG_EN (1 << 12)
2735977b 521# define RS690_BLOCK_GFX_D3_EN (1 << 14)
45e51905
AD		 522#define RS480_K8_FB_LOCATION 0x1e
523#define RS480_GART_FEATURE_ID 0x2b
524# define RS480_HANG_EN (1 << 11)
525# define RS480_TLB_ENABLE (1 << 18)
526# define RS480_P2P_ENABLE (1 << 19)
527# define RS480_GTW_LAC_EN (1 << 25)
528# define RS480_2LEVEL_GART (0 << 30)
529# define RS480_1LEVEL_GART (1 << 30)
530# define RS480_PDC_EN (1 << 31)
531#define RS480_GART_BASE 0x2c
532#define RS480_GART_CACHE_CNTRL 0x2e
533# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
534#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
535# define RS480_GART_EN (1 << 0)
536# define RS480_VA_SIZE_32MB (0 << 1)
537# define RS480_VA_SIZE_64MB (1 << 1)
538# define RS480_VA_SIZE_128MB (2 << 1)
539# define RS480_VA_SIZE_256MB (3 << 1)
540# define RS480_VA_SIZE_512MB (4 << 1)
541# define RS480_VA_SIZE_1GB (5 << 1)
542# define RS480_VA_SIZE_2GB (6 << 1)
543#define RS480_AGP_MODE_CNTL 0x39
544# define RS480_POST_GART_Q_SIZE (1 << 18)
545# define RS480_NONGART_SNOOP (1 << 19)
546# define RS480_AGP_RD_BUF_SIZE (1 << 20)
547# define RS480_REQ_TYPE_SNOOP_SHIFT 22
548# define RS480_REQ_TYPE_SNOOP_MASK 0x3
549# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
550#define RS480_MC_MISC_UMA_CNTL 0x5f
551#define RS480_MC_MCLK_CNTL 0x7a
552#define RS480_MC_UMA_DUALCH_CNTL 0x86
2735977b 553
60f92683
MC		 554#define RS690_MC_FB_LOCATION 0x100
555#define RS690_MC_AGP_LOCATION 0x101
556#define RS690_MC_AGP_BASE 0x102
3722bfc6 557#define RS690_MC_AGP_BASE_2 0x103
60f92683 558
3d5e2c13 559#define R520_MC_IND_INDEX 0x70
2735977b 560#define R520_MC_IND_WR_EN (1 << 24)
3d5e2c13
DA		 561#define R520_MC_IND_DATA 0x74
562
563#define RV515_MC_FB_LOCATION 0x01
564#define RV515_MC_AGP_LOCATION 0x02
70b13d51
DA		 565#define RV515_MC_AGP_BASE 0x03
566#define RV515_MC_AGP_BASE_2 0x04
3d5e2c13
DA		 567
568#define R520_MC_FB_LOCATION 0x04
569#define R520_MC_AGP_LOCATION 0x05
70b13d51
DA		 570#define R520_MC_AGP_BASE 0x06
571#define R520_MC_AGP_BASE_2 0x07
3d5e2c13 572
414ed537
DA		 573#define RADEON_MPP_TB_CONFIG 0x01c0
574#define RADEON_MEM_CNTL 0x0140
575#define RADEON_MEM_SDRAM_MODE_REG 0x0158
45e51905
AD		 576#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
577#define RS480_AGP_BASE_2 0x0164
414ed537
DA		 578#define RADEON_AGP_BASE 0x0170
579
5b92c404
AD		 580/* pipe config regs */
581#define R400_GB_PIPE_SELECT 0x402c
582#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
583#define R500_SU_REG_DEST 0x42c8
584#define R300_GB_TILE_CONFIG 0x4018
585# define R300_ENABLE_TILING (1 << 0)
586# define R300_PIPE_COUNT_RV350 (0 << 1)
587# define R300_PIPE_COUNT_R300 (3 << 1)
588# define R300_PIPE_COUNT_R420_3P (6 << 1)
589# define R300_PIPE_COUNT_R420 (7 << 1)
590# define R300_TILE_SIZE_8 (0 << 4)
591# define R300_TILE_SIZE_16 (1 << 4)
592# define R300_TILE_SIZE_32 (2 << 4)
593# define R300_SUBPIXEL_1_12 (0 << 16)
594# define R300_SUBPIXEL_1_16 (1 << 16)
595#define R300_DST_PIPE_CONFIG 0x170c
596# define R300_PIPE_AUTO_CONFIG (1 << 31)
597#define R300_RB2D_DSTCACHE_MODE 0x3428
598# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
599# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
600
1da177e4
LT		 601#define RADEON_RB3D_COLOROFFSET 0x1c40
602#define RADEON_RB3D_COLORPITCH 0x1c48
603
3e14a286
MD		 604#define RADEON_SRC_X_Y 0x1590
605
1da177e4
LT		 606#define RADEON_DP_GUI_MASTER_CNTL 0x146c
607# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
608# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
609# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
610# define RADEON_GMC_BRUSH_NONE (15 << 4)
611# define RADEON_GMC_DST_16BPP (4 << 8)
612# define RADEON_GMC_DST_24BPP (5 << 8)
613# define RADEON_GMC_DST_32BPP (6 << 8)
614# define RADEON_GMC_DST_DATATYPE_SHIFT 8
615# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
616# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
617# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
618# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
619# define RADEON_GMC_WR_MSK_DIS (1 << 30)
620# define RADEON_ROP3_S 0x00cc0000
621# define RADEON_ROP3_P 0x00f00000
622#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 623#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 624#define RADEON_DST_PITCH_OFFSET 0x142c
625#define RADEON_DST_PITCH_OFFSET_C 0x1c80
626# define RADEON_DST_TILE_LINEAR (0 << 30)
627# define RADEON_DST_TILE_MACRO (1 << 30)
628# define RADEON_DST_TILE_MICRO (2 << 30)
629# define RADEON_DST_TILE_BOTH (3 << 30)
630
631#define RADEON_SCRATCH_REG0 0x15e0
632#define RADEON_SCRATCH_REG1 0x15e4
633#define RADEON_SCRATCH_REG2 0x15e8
634#define RADEON_SCRATCH_REG3 0x15ec
635#define RADEON_SCRATCH_REG4 0x15f0
636#define RADEON_SCRATCH_REG5 0x15f4
637#define RADEON_SCRATCH_UMSK 0x0770
638#define RADEON_SCRATCH_ADDR 0x0774
639
640#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
641
642#define GET_SCRATCH( x ) (dev_priv->writeback_works \
643 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
644 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
645
1da177e4
LT		 646#define RADEON_GEN_INT_CNTL 0x0040
647# define RADEON_CRTC_VBLANK_MASK (1 << 0)
ddbee333 648# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
1da177e4
LT		 649# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
650# define RADEON_SW_INT_ENABLE (1 << 25)
651
652#define RADEON_GEN_INT_STATUS 0x0044
653# define RADEON_CRTC_VBLANK_STAT (1 << 0)
bc5f4523 654# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
ddbee333 655# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
bc5f4523 656# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
1da177e4
LT		 657# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
658# define RADEON_SW_INT_TEST (1 << 25)
bc5f4523 659# define RADEON_SW_INT_TEST_ACK (1 << 25)
1da177e4 660# define RADEON_SW_INT_FIRE (1 << 26)
0a3e67a4 661# define R500_DISPLAY_INT_STATUS (1 << 0)
1da177e4
LT		 662
663#define RADEON_HOST_PATH_CNTL 0x0130
664# define RADEON_HDP_SOFT_RESET (1 << 26)
665# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
666# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
667
668#define RADEON_ISYNC_CNTL 0x1724
669# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
670# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
671# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
672# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
673# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
674# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
675
676#define RADEON_RBBM_GUICNTL 0x172c
677# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
678# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
679# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
680# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
681
682#define RADEON_MC_AGP_LOCATION 0x014c
683#define RADEON_MC_FB_LOCATION 0x0148
684#define RADEON_MCLK_CNTL 0x0012
685# define RADEON_FORCEON_MCLKA (1 << 16)
686# define RADEON_FORCEON_MCLKB (1 << 17)
687# define RADEON_FORCEON_YCLKA (1 << 18)
688# define RADEON_FORCEON_YCLKB (1 << 19)
689# define RADEON_FORCEON_MC (1 << 20)
690# define RADEON_FORCEON_AIC (1 << 21)
691
692#define RADEON_PP_BORDER_COLOR_0 0x1d40
693#define RADEON_PP_BORDER_COLOR_1 0x1d44
694#define RADEON_PP_BORDER_COLOR_2 0x1d48
695#define RADEON_PP_CNTL 0x1c38
696# define RADEON_SCISSOR_ENABLE (1 << 1)
697#define RADEON_PP_LUM_MATRIX 0x1d00
698#define RADEON_PP_MISC 0x1c14
699#define RADEON_PP_ROT_MATRIX_0 0x1d58
700#define RADEON_PP_TXFILTER_0 0x1c54
701#define RADEON_PP_TXOFFSET_0 0x1c5c
702#define RADEON_PP_TXFILTER_1 0x1c6c
703#define RADEON_PP_TXFILTER_2 0x1c84
704
5e35eff1
AD		 705#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
706#define R300_DSTCACHE_CTLSTAT 0x1714
707# define R300_RB2D_DC_FLUSH (3 << 0)
708# define R300_RB2D_DC_FREE (3 << 2)
709# define R300_RB2D_DC_FLUSH_ALL 0xf
710# define R300_RB2D_DC_BUSY (1 << 31)
1da177e4
LT		 711#define RADEON_RB3D_CNTL 0x1c3c
712# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
713# define RADEON_PLANE_MASK_ENABLE (1 << 1)
714# define RADEON_DITHER_ENABLE (1 << 2)
715# define RADEON_ROUND_ENABLE (1 << 3)
716# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
717# define RADEON_DITHER_INIT (1 << 5)
718# define RADEON_ROP_ENABLE (1 << 6)
719# define RADEON_STENCIL_ENABLE (1 << 7)
720# define RADEON_Z_ENABLE (1 << 8)
721# define RADEON_ZBLOCK16 (1 << 15)
722#define RADEON_RB3D_DEPTHOFFSET 0x1c24
723#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
724#define RADEON_RB3D_DEPTHPITCH 0x1c28
725#define RADEON_RB3D_PLANEMASK 0x1d84
726#define RADEON_RB3D_STENCILREFMASK 0x1d7c
727#define RADEON_RB3D_ZCACHE_MODE 0x3250
728#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
729# define RADEON_RB3D_ZC_FLUSH (1 << 0)
730# define RADEON_RB3D_ZC_FREE (1 << 2)
731# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
732# define RADEON_RB3D_ZC_BUSY (1 << 31)
259434ac
AD		 733#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
734# define R300_ZC_FLUSH (1 << 0)
735# define R300_ZC_FREE (1 << 1)
259434ac 736# define R300_ZC_BUSY (1 << 31)
b9b603dd
MD		 737#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
738# define RADEON_RB3D_DC_FLUSH (3 << 0)
739# define RADEON_RB3D_DC_FREE (3 << 2)
740# define RADEON_RB3D_DC_FLUSH_ALL 0xf
741# define RADEON_RB3D_DC_BUSY (1 << 31)
259434ac 742#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
54f961a6
JG		 743# define R300_RB3D_DC_FLUSH (2 << 0)
744# define R300_RB3D_DC_FREE (2 << 2)
259434ac 745# define R300_RB3D_DC_FINISH (1 << 4)
1da177e4
LT		 746#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
747# define RADEON_Z_TEST_MASK (7 << 4)
748# define RADEON_Z_TEST_ALWAYS (7 << 4)
749# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
750# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
751# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
752# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
753# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
754# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
755# define RADEON_FORCE_Z_DIRTY (1 << 29)
756# define RADEON_Z_WRITE_ENABLE (1 << 30)
757# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
758#define RADEON_RBBM_SOFT_RESET 0x00f0
759# define RADEON_SOFT_RESET_CP (1 << 0)
760# define RADEON_SOFT_RESET_HI (1 << 1)
761# define RADEON_SOFT_RESET_SE (1 << 2)
762# define RADEON_SOFT_RESET_RE (1 << 3)
763# define RADEON_SOFT_RESET_PP (1 << 4)
764# define RADEON_SOFT_RESET_E2 (1 << 5)
765# define RADEON_SOFT_RESET_RB (1 << 6)
766# define RADEON_SOFT_RESET_HDP (1 << 7)
576cc458
RS		 767/*
768 * 6:0 Available slots in the FIFO
769 * 8 Host Interface active
770 * 9 CP request active
771 * 10 FIFO request active
772 * 11 Host Interface retry active
773 * 12 CP retry active
774 * 13 FIFO retry active
775 * 14 FIFO pipeline busy
776 * 15 Event engine busy
777 * 16 CP command stream busy
778 * 17 2D engine busy
779 * 18 2D portion of render backend busy
780 * 20 3D setup engine busy
781 * 26 GA engine busy
782 * 27 CBA 2D engine busy
783 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
784 * command stream queue not empty or Ring Buffer not empty
785 */
1da177e4 786#define RADEON_RBBM_STATUS 0x0e40
576cc458
RS		 787/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
788/* #define RADEON_RBBM_STATUS 0x1740 */
789/* bits 6:0 are dword slots available in the cmd fifo */
1da177e4 790# define RADEON_RBBM_FIFOCNT_MASK 0x007f
576cc458
RS		 791# define RADEON_HIRQ_ON_RBB (1 << 8)
792# define RADEON_CPRQ_ON_RBB (1 << 9)
793# define RADEON_CFRQ_ON_RBB (1 << 10)
794# define RADEON_HIRQ_IN_RTBUF (1 << 11)
795# define RADEON_CPRQ_IN_RTBUF (1 << 12)
796# define RADEON_CFRQ_IN_RTBUF (1 << 13)
797# define RADEON_PIPE_BUSY (1 << 14)
798# define RADEON_ENG_EV_BUSY (1 << 15)
799# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
800# define RADEON_E2_BUSY (1 << 17)
801# define RADEON_RB2D_BUSY (1 << 18)
802# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
803# define RADEON_VAP_BUSY (1 << 20)
804# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
805# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
806# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
807# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
808# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
809# define RADEON_GA_BUSY (1 << 26)
810# define RADEON_CBA2D_BUSY (1 << 27)
811# define RADEON_RBBM_ACTIVE (1 << 31)
1da177e4
LT		 812#define RADEON_RE_LINE_PATTERN 0x1cd0
813#define RADEON_RE_MISC 0x26c4
814#define RADEON_RE_TOP_LEFT 0x26c0
815#define RADEON_RE_WIDTH_HEIGHT 0x1c44
816#define RADEON_RE_STIPPLE_ADDR 0x1cc8
817#define RADEON_RE_STIPPLE_DATA 0x1ccc
818
819#define RADEON_SCISSOR_TL_0 0x1cd8
820#define RADEON_SCISSOR_BR_0 0x1cdc
821#define RADEON_SCISSOR_TL_1 0x1ce0
822#define RADEON_SCISSOR_BR_1 0x1ce4
823#define RADEON_SCISSOR_TL_2 0x1ce8
824#define RADEON_SCISSOR_BR_2 0x1cec
825#define RADEON_SE_COORD_FMT 0x1c50
826#define RADEON_SE_CNTL 0x1c4c
827# define RADEON_FFACE_CULL_CW (0 << 0)
828# define RADEON_BFACE_SOLID (3 << 1)
829# define RADEON_FFACE_SOLID (3 << 3)
830# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
831# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
832# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
833# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
834# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
835# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
836# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
837# define RADEON_FOG_SHADE_FLAT (1 << 14)
838# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
839# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
840# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
841# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
842# define RADEON_ROUND_MODE_TRUNC (0 << 28)
843# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
844#define RADEON_SE_CNTL_STATUS 0x2140
845#define RADEON_SE_LINE_WIDTH 0x1db8
846#define RADEON_SE_VPORT_XSCALE 0x1d98
847#define RADEON_SE_ZBIAS_FACTOR 0x1db0
848#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
849#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
850#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
851# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
852# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
853#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
854#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
855# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
856#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
857#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
858#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
859#define RADEON_SURFACE_CNTL 0x0b00
860# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
861# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
862# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
863# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
864# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
865# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
866# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
867# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
868# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
869#define RADEON_SURFACE0_INFO 0x0b0c
870# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
871# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
872# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
873# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
874# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
875# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
876#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
877#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
878# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
879#define RADEON_SURFACE1_INFO 0x0b1c
880#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
881#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
882#define RADEON_SURFACE2_INFO 0x0b2c
883#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
884#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
885#define RADEON_SURFACE3_INFO 0x0b3c
886#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
887#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
888#define RADEON_SURFACE4_INFO 0x0b4c
889#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
890#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
891#define RADEON_SURFACE5_INFO 0x0b5c
892#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
893#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
894#define RADEON_SURFACE6_INFO 0x0b6c
895#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
896#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
897#define RADEON_SURFACE7_INFO 0x0b7c
898#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
899#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
900#define RADEON_SW_SEMAPHORE 0x013c
901
902#define RADEON_WAIT_UNTIL 0x1720
903# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 904# define RADEON_WAIT_2D_IDLE (1 << 14)
905# define RADEON_WAIT_3D_IDLE (1 << 15)
1da177e4
LT		 906# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
907# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
908# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
909
910#define RADEON_RB3D_ZMASKOFFSET 0x3234
911#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
912# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
913# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
914
1da177e4
LT		 915/* CP registers */
916#define RADEON_CP_ME_RAM_ADDR 0x07d4
917#define RADEON_CP_ME_RAM_RADDR 0x07d8
918#define RADEON_CP_ME_RAM_DATAH 0x07dc
919#define RADEON_CP_ME_RAM_DATAL 0x07e0
920
921#define RADEON_CP_RB_BASE 0x0700
922#define RADEON_CP_RB_CNTL 0x0704
923# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 924# define RADEON_RB_NO_UPDATE (1 << 27)
1da177e4
LT		 925#define RADEON_CP_RB_RPTR_ADDR 0x070c
926#define RADEON_CP_RB_RPTR 0x0710
927#define RADEON_CP_RB_WPTR 0x0714
928
929#define RADEON_CP_RB_WPTR_DELAY 0x0718
930# define RADEON_PRE_WRITE_TIMER_SHIFT 0
931# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
932
933#define RADEON_CP_IB_BASE 0x0738
934
935#define RADEON_CP_CSQ_CNTL 0x0740
936# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
937# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
938# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
939# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
940# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
941# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
942# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
943
944#define RADEON_AIC_CNTL 0x01d0
945# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
4e270e9b 946# define RS400_MSI_REARM (1 << 3)
1da177e4
LT		 947#define RADEON_AIC_STAT 0x01d4
948#define RADEON_AIC_PT_BASE 0x01d8
949#define RADEON_AIC_LO_ADDR 0x01dc
950#define RADEON_AIC_HI_ADDR 0x01e0
951#define RADEON_AIC_TLB_ADDR 0x01e4
952#define RADEON_AIC_TLB_DATA 0x01e8
953
954/* CP command packets */
955#define RADEON_CP_PACKET0 0x00000000
956# define RADEON_ONE_REG_WR (1 << 15)
957#define RADEON_CP_PACKET1 0x40000000
958#define RADEON_CP_PACKET2 0x80000000
959#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 960# define RADEON_CP_NOP 0x00001000
961# define RADEON_CP_NEXT_CHAR 0x00001900
962# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
963# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 964 /* GEN_INDX_PRIM is unsupported starting with R300 */
1da177e4
LT		 965# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
966# define RADEON_WAIT_FOR_IDLE 0x00002600
967# define RADEON_3D_DRAW_VBUF 0x00002800
968# define RADEON_3D_DRAW_IMMD 0x00002900
969# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 970# define RADEON_CP_LOAD_PALETTE 0x00002C00
1da177e4
LT		 971# define RADEON_3D_LOAD_VBPNTR 0x00002F00
972# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
973# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
974# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 975# define RADEON_CP_INDX_BUFFER 0x00003300
976# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
977# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
978# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 979# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 980# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1da177e4
LT		 981# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
982# define RADEON_CNTL_PAINT_MULTI 0x00009A00
983# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
984# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
985
986#define RADEON_CP_PACKET_MASK 0xC0000000
987#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
988#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
989#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
990#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
991
992#define RADEON_VTX_Z_PRESENT (1 << 31)
993#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
994
995#define RADEON_PRIM_TYPE_NONE (0 << 0)
996#define RADEON_PRIM_TYPE_POINT (1 << 0)
997#define RADEON_PRIM_TYPE_LINE (2 << 0)
998#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
999#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1000#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1001#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1002#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1003#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1004#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1005#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1006#define RADEON_PRIM_TYPE_MASK 0xf
1007#define RADEON_PRIM_WALK_IND (1 << 4)
1008#define RADEON_PRIM_WALK_LIST (2 << 4)
1009#define RADEON_PRIM_WALK_RING (3 << 4)
1010#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1011#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1012#define RADEON_MAOS_ENABLE (1 << 7)
1013#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1014#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1015#define RADEON_NUM_VERTICES_SHIFT 16
1016
1017#define RADEON_COLOR_FORMAT_CI8 2
1018#define RADEON_COLOR_FORMAT_ARGB1555 3
1019#define RADEON_COLOR_FORMAT_RGB565 4
1020#define RADEON_COLOR_FORMAT_ARGB8888 6
1021#define RADEON_COLOR_FORMAT_RGB332 7
1022#define RADEON_COLOR_FORMAT_RGB8 9
1023#define RADEON_COLOR_FORMAT_ARGB4444 15
1024
1025#define RADEON_TXFORMAT_I8 0
1026#define RADEON_TXFORMAT_AI88 1
1027#define RADEON_TXFORMAT_RGB332 2
1028#define RADEON_TXFORMAT_ARGB1555 3
1029#define RADEON_TXFORMAT_RGB565 4
1030#define RADEON_TXFORMAT_ARGB4444 5
1031#define RADEON_TXFORMAT_ARGB8888 6
1032#define RADEON_TXFORMAT_RGBA8888 7
1033#define RADEON_TXFORMAT_Y8 8
1034#define RADEON_TXFORMAT_VYUY422 10
1035#define RADEON_TXFORMAT_YVYU422 11
1036#define RADEON_TXFORMAT_DXT1 12
1037#define RADEON_TXFORMAT_DXT23 14
1038#define RADEON_TXFORMAT_DXT45 15
1039
1040#define R200_PP_TXCBLEND_0 0x2f00
1041#define R200_PP_TXCBLEND_1 0x2f10
1042#define R200_PP_TXCBLEND_2 0x2f20
1043#define R200_PP_TXCBLEND_3 0x2f30
1044#define R200_PP_TXCBLEND_4 0x2f40
1045#define R200_PP_TXCBLEND_5 0x2f50
1046#define R200_PP_TXCBLEND_6 0x2f60
1047#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 1048#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 1049#define R200_PP_TFACTOR_0 0x2ee0
1050#define R200_SE_VTX_FMT_0 0x2088
1051#define R200_SE_VAP_CNTL 0x2080
1052#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 1053#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1054#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1055#define R200_PP_TXFILTER_5 0x2ca0
1056#define R200_PP_TXFILTER_4 0x2c80
1057#define R200_PP_TXFILTER_3 0x2c60
1058#define R200_PP_TXFILTER_2 0x2c40
1059#define R200_PP_TXFILTER_1 0x2c20
1060#define R200_PP_TXFILTER_0 0x2c00
1da177e4
LT		 1061#define R200_PP_TXOFFSET_5 0x2d78
1062#define R200_PP_TXOFFSET_4 0x2d60
1063#define R200_PP_TXOFFSET_3 0x2d48
1064#define R200_PP_TXOFFSET_2 0x2d30
1065#define R200_PP_TXOFFSET_1 0x2d18
1066#define R200_PP_TXOFFSET_0 0x2d00
1067
1068#define R200_PP_CUBIC_FACES_0 0x2c18
1069#define R200_PP_CUBIC_FACES_1 0x2c38
1070#define R200_PP_CUBIC_FACES_2 0x2c58
1071#define R200_PP_CUBIC_FACES_3 0x2c78
1072#define R200_PP_CUBIC_FACES_4 0x2c98
1073#define R200_PP_CUBIC_FACES_5 0x2cb8
1074#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1075#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1076#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1077#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1078#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1079#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1080#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1081#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1082#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1083#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1084#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1085#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1086#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1087#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1088#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1089#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1090#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1091#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1092#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1093#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1094#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1095#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1096#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1097#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1098#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1099#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1100#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1101#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1102#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1103#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1104
1105#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1106#define R200_SE_VTE_CNTL 0x20b0
1107#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1108#define R200_PP_TAM_DEBUG3 0x2d9c
1109#define R200_PP_CNTL_X 0x2cc4
1110#define R200_SE_VAP_CNTL_STATUS 0x2140
1111#define R200_RE_SCISSOR_TL_0 0x1cd8
1112#define R200_RE_SCISSOR_TL_1 0x1ce0
1113#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 1114#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 1115#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1116#define R200_SE_VTX_STATE_CNTL 0x2180
1117#define R200_RE_POINTSIZE 0x2648
1118#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1119
b5e89ed5 1120#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1da177e4
LT		 1121#define RADEON_PP_TEX_SIZE_1 0x1d0c
1122#define RADEON_PP_TEX_SIZE_2 0x1d14
1123
1124#define RADEON_PP_CUBIC_FACES_0 0x1d24
1125#define RADEON_PP_CUBIC_FACES_1 0x1d28
1126#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1127#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1128#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1129#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1130
f2a2279f
DA		 1131#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1132
1da177e4
LT		 1133#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1134#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1135#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1136#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1137#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1138#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1139#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1140#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1141#define R200_3D_DRAW_IMMD_2 0xC0003500
1142#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 1143#define R200_RE_CNTL 0x1c50
1da177e4
LT		 1144
1145#define R200_RB3D_BLENDCOLOR 0x3218
1146
1147#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1148
1149#define R200_PP_TRI_PERF 0x2cf8
1150
9d17601c 1151#define R200_PP_AFS_0 0x2f80
b5e89ed5 1152#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 1153
d6fece05
DA		 1154#define R200_VAP_PVS_CNTL_1 0x22D0
1155
0a3e67a4
JB		 1156#define RADEON_CRTC_CRNT_FRAME 0x0214
1157#define RADEON_CRTC2_CRNT_FRAME 0x0314
1158
c0beb2a7
DA		 1159#define R500_D1CRTC_STATUS 0x609c
1160#define R500_D2CRTC_STATUS 0x689c
1161#define R500_CRTC_V_BLANK (1<<0)
1162
1163#define R500_D1CRTC_FRAME_COUNT 0x60a4
1164#define R500_D2CRTC_FRAME_COUNT 0x68a4
1165
1166#define R500_D1MODE_V_COUNTER 0x6530
1167#define R500_D2MODE_V_COUNTER 0x6d30
1168
1169#define R500_D1MODE_VBLANK_STATUS 0x6534
1170#define R500_D2MODE_VBLANK_STATUS 0x6d34
1171#define R500_VBLANK_OCCURED (1<<0)
1172#define R500_VBLANK_ACK (1<<4)
1173#define R500_VBLANK_STAT (1<<12)
1174#define R500_VBLANK_INT (1<<16)
1175
1176#define R500_DxMODE_INT_MASK 0x6540
1177#define R500_D1MODE_INT_MASK (1<<0)
1178#define R500_D2MODE_INT_MASK (1<<8)
1179
1180#define R500_DISP_INTERRUPT_STATUS 0x7edc
1181#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1182#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1183
1da177e4
LT		 1184/* Constants */
1185#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1186
1187#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1188#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1189#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1190#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1191#define RADEON_LAST_DISPATCH 1
1192
1193#define RADEON_MAX_VB_AGE 0x7fffffff
1194#define RADEON_MAX_VB_VERTS (0xffff)
1195
1196#define RADEON_RING_HIGH_MARK 128
1197
ea98a92f
DA		 1198#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1199
1da177e4
LT		 1200#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1201#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1202#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1203#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1204
2735977b 1205#define RADEON_WRITE_PLL(addr, val) \
1da177e4 1206do { \
2735977b 1207 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1da177e4 1208 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
2735977b 1209 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1da177e4
LT		 1210} while (0)
1211
2735977b 1212#define RADEON_WRITE_PCIE(addr, val) \
ea98a92f 1213do { \
2735977b 1214 RADEON_WRITE8(RADEON_PCIE_INDEX, \
ea98a92f 1215 ((addr) & 0xff)); \
2735977b 1216 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
ea98a92f
DA		 1217} while (0)
1218
45e51905
AD		 1219#define R500_WRITE_MCIND(addr, val) \
1220do { \
1221 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1222 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1223 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1224} while (0)
1225
1226#define RS480_WRITE_MCIND(addr, val) \
1227do { \
1228 RADEON_WRITE(RS480_NB_MC_INDEX, \
1229 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1230 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1231 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1232} while (0)
3d5e2c13 1233
2735977b 1234#define RS690_WRITE_MCIND(addr, val) \
60f92683
MC		 1235do { \
1236 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1237 RADEON_WRITE(RS690_MC_DATA, val); \
1238 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1239} while (0)
1240
45e51905
AD		 1241#define IGP_WRITE_MCIND(addr, val) \
1242do { \
f0738e92
AD		 1243 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
45e51905
AD		 1245 RS690_WRITE_MCIND(addr, val); \
1246 else \
1247 RS480_WRITE_MCIND(addr, val); \
1248} while (0)
1249
1da177e4
LT		 1250#define CP_PACKET0( reg, n ) \
1251 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1252#define CP_PACKET0_TABLE( reg, n ) \
1253 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1254#define CP_PACKET1( reg0, reg1 ) \
1255 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1256#define CP_PACKET2() \
1257 (RADEON_CP_PACKET2)
1258#define CP_PACKET3( pkt, n ) \
1259 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1260
1da177e4
LT		 1261/* ================================================================
1262 * Engine control helper macros
1263 */
1264
1265#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1266 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1267 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1268 RADEON_WAIT_HOST_IDLECLEAN) ); \
1269} while (0)
1270
1271#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1272 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1273 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1274 RADEON_WAIT_HOST_IDLECLEAN) ); \
1275} while (0)
1276
1277#define RADEON_WAIT_UNTIL_IDLE() do { \
1278 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1279 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1280 RADEON_WAIT_3D_IDLECLEAN | \
1281 RADEON_WAIT_HOST_IDLECLEAN) ); \
1282} while (0)
1283
1284#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1285 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1286 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1287} while (0)
1288
1289#define RADEON_FLUSH_CACHE() do { \
259434ac
AD		 1290 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1291 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1292 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1293 } else { \
1294 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1295 OUT_RING(R300_RB3D_DC_FLUSH); \
259434ac 1296 } \
1da177e4
LT		 1297} while (0)
1298
1299#define RADEON_PURGE_CACHE() do { \
259434ac
AD		 1300 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1301 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1302 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
259434ac
AD		 1303 } else { \
1304 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1305 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
259434ac 1306 } \
1da177e4
LT		 1307} while (0)
1308
1309#define RADEON_FLUSH_ZCACHE() do { \
259434ac
AD		 1310 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1311 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1312 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1313 } else { \
1314 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1315 OUT_RING(R300_ZC_FLUSH); \
1316 } \
1da177e4
LT		 1317} while (0)
1318
1319#define RADEON_PURGE_ZCACHE() do { \
259434ac
AD		 1320 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1321 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
54f961a6 1322 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
259434ac 1323 } else { \
54f961a6
JG		 1324 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1325 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
259434ac 1326 } \
1da177e4
LT		 1327} while (0)
1328
1da177e4
LT		 1329/* ================================================================
1330 * Misc helper macros
1331 */
1332
b5e89ed5 1333/* Perfbox functionality only.
1da177e4
LT		 1334 */
1335#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1336do { \
1337 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1338 u32 head = GET_RING_HEAD( dev_priv ); \
1339 if (head == dev_priv->ring.tail) \
1340 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1341 } \
1342} while (0)
1343
1344#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
7c1c2871
DA		 1345do { \
1346 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1347 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1da177e4
LT		 1348 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1349 int __ret = radeon_do_cp_idle( dev_priv ); \
1350 if ( __ret ) return __ret; \
1351 sarea_priv->last_dispatch = 0; \
1352 radeon_freelist_reset( dev ); \
1353 } \
1354} while (0)
1355
1356#define RADEON_DISPATCH_AGE( age ) do { \
1357 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1358 OUT_RING( age ); \
1359} while (0)
1360
1361#define RADEON_FRAME_AGE( age ) do { \
1362 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1363 OUT_RING( age ); \
1364} while (0)
1365
1366#define RADEON_CLEAR_AGE( age ) do { \
1367 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1368 OUT_RING( age ); \
1369} while (0)
1370
1da177e4
LT		 1371/* ================================================================
1372 * Ring control
1373 */
1374
1375#define RADEON_VERBOSE 0
1376
1377#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1378
1379#define BEGIN_RING( n ) do { \
1380 if ( RADEON_VERBOSE ) { \
3e684eae 1381 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1da177e4
LT		 1382 } \
1383 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1384 COMMIT_RING(); \
1385 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1386 } \
1387 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1388 ring = dev_priv->ring.start; \
1389 write = dev_priv->ring.tail; \
1390 mask = dev_priv->ring.tail_mask; \
1391} while (0)
1392
1393#define ADVANCE_RING() do { \
1394 if ( RADEON_VERBOSE ) { \
1395 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1396 write, dev_priv->ring.tail ); \
1397 } \
1398 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
bc5f4523 1399 DRM_ERROR( \
1da177e4
LT		 1400 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1401 ((dev_priv->ring.tail + _nr) & mask), \
1402 write, __LINE__); \
1403 } else \
1404 dev_priv->ring.tail = write; \
1405} while (0)
1406
1407#define COMMIT_RING() do { \
1408 /* Flush writes to ring */ \
1409 DRM_MEMORYBARRIER(); \
1410 GET_RING_HEAD( dev_priv ); \
1411 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1412 /* read from PCI bus to ensure correct posting */ \
1413 RADEON_READ( RADEON_CP_RB_RPTR ); \
1414} while (0)
1415
1416#define OUT_RING( x ) do { \
1417 if ( RADEON_VERBOSE ) { \
1418 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1419 (unsigned int)(x), write ); \
1420 } \
1421 ring[write++] = (x); \
1422 write &= mask; \
1423} while (0)
1424
1425#define OUT_RING_REG( reg, val ) do { \
1426 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1427 OUT_RING( val ); \
1428} while (0)
1429
1da177e4
LT		 1430#define OUT_RING_TABLE( tab, sz ) do { \
1431 int _size = (sz); \
1432 int *_tab = (int *)(tab); \
1433 \
1434 if (write + _size > mask) { \
1435 int _i = (mask+1) - write; \
1436 _size -= _i; \
1437 while (_i > 0 ) { \
1438 *(int *)(ring + write) = *_tab++; \
1439 write++; \
1440 _i--; \
1441 } \
1442 write = 0; \
1443 _tab += _i; \
1444 } \
1da177e4
LT		 1445 while (_size > 0) { \
1446 *(ring + write) = *_tab++; \
1447 write++; \
1448 _size--; \
1449 } \
1450 write &= mask; \
1451} while (0)
1452
b5e89ed5 1453#endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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