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drm/radeon/kms: make sure eDP panel is on for modesetting
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
1f3b6a45
DA		 38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
bcc1c2a1 56
1f3b6a45
DA		 57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72}
73
74void radeon_setup_encoder_clones(struct drm_device *dev)
75{
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81}
82
771fe6b9 83uint32_t
5137ee94 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
771fe6b9
JG		 85{
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
5137ee94 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9 101 else if (ASIC_IS_AVIVO(rdev))
5137ee94 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
771fe6b9 103 else
5137ee94 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
771fe6b9
JG		 105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
5137ee94 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
771fe6b9
JG		 109 else {
110 /*if (rdev->family == CHIP_R200)
5137ee94 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 112 else*/
5137ee94 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9
JG		 114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
5137ee94 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 119 else
5137ee94 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
5137ee94 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9 127 else
5137ee94 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
771fe6b9
JG		 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
5137ee94 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 135 else if (ASIC_IS_AVIVO(rdev))
5137ee94 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
771fe6b9 137 else
5137ee94 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
771fe6b9
JG		 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
5137ee94 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
771fe6b9 146 else if (ASIC_IS_AVIVO(rdev))
5137ee94 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 148 else
5137ee94 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
5137ee94 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9
JG		 153 break;
154 }
155
156 return ret;
157}
158
f28cf339
DA		 159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
99999aaa 179
771fe6b9
JG		 180void
181radeon_link_encoder_connector(struct drm_device *dev)
182{
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197}
198
4ce001ab
DA		 199void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200{
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
d9fdaafb 209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
f641e51e
DA		 210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 212 }
213 }
214}
215
5b1714d3 216struct drm_connector *
771fe6b9
JG		 217radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218{
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
43c33ed8 226 if (radeon_encoder->active_device & radeon_connector->devices)
771fe6b9
JG		 227 return connector;
228 }
229 return NULL;
230}
231
3e4b9982
AD		 232struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233{
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
238
239 if (radeon_encoder->is_ext_encoder)
240 return NULL;
241
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
244 continue;
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
249 }
250 return NULL;
251}
252
3515387b
AD		 253void radeon_panel_mode_fixup(struct drm_encoder *encoder,
254 struct drm_display_mode *adjusted_mode)
255{
256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
257 struct drm_device *dev = encoder->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
260 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
261 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
262 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
263 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
264 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
265 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
266
267 adjusted_mode->clock = native_mode->clock;
268 adjusted_mode->flags = native_mode->flags;
269
270 if (ASIC_IS_AVIVO(rdev)) {
271 adjusted_mode->hdisplay = native_mode->hdisplay;
272 adjusted_mode->vdisplay = native_mode->vdisplay;
273 }
274
275 adjusted_mode->htotal = native_mode->hdisplay + hblank;
276 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
277 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
278
279 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
280 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
281 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
282
283 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
284
285 if (ASIC_IS_AVIVO(rdev)) {
286 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
287 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
288 }
289
290 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
291 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
292 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
293
294 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
295 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
296 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
297
298}
299
771fe6b9
JG		 300static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
301 struct drm_display_mode *mode,
302 struct drm_display_mode *adjusted_mode)
303{
771fe6b9 304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 305 struct drm_device *dev = encoder->dev;
306 struct radeon_device *rdev = dev->dev_private;
771fe6b9 307
8c2a6d73
AD		 308 /* set the active encoder to connector routing */
309 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 310 drm_mode_set_crtcinfo(adjusted_mode, 0);
311
771fe6b9
JG		 312 /* hw bug */
313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
314 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
315 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
316
80297e87 317 /* get the native mode for LVDS */
3515387b
AD		 318 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
319 radeon_panel_mode_fixup(encoder, adjusted_mode);
80297e87
AD		 320
321 /* get the native mode for TV */
ceefedd8 322 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
5a9bcacc
AD		 323 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
324 if (tv_dac) {
325 if (tv_dac->tv_std == TV_STD_NTSC ||
326 tv_dac->tv_std == TV_STD_NTSC_J ||
327 tv_dac->tv_std == TV_STD_PAL_M)
328 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
329 else
330 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
331 }
332 }
333
5801ead6 334 if (ASIC_IS_DCE3(rdev) &&
9f998ad7 335 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
5801ead6
AD		 336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337 radeon_dp_set_link_config(connector, mode);
338 }
339
771fe6b9
JG		 340 return true;
341}
342
343static void
344atombios_dac_setup(struct drm_encoder *encoder, int action)
345{
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
affd8589 350 int index = 0;
445282db 351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 352
771fe6b9
JG		 353 memset(&args, 0, sizeof(args));
354
355 switch (radeon_encoder->encoder_id) {
356 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
771fe6b9
JG		 359 break;
360 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
771fe6b9
JG		 363 break;
364 }
365
366 args.ucAction = action;
367
4ce001ab 368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 369 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 371 args.ucDacStandard = ATOM_DAC1_CV;
372 else {
affd8589 373 switch (dac_info->tv_std) {
771fe6b9
JG		 374 case TV_STD_PAL:
375 case TV_STD_PAL_M:
376 case TV_STD_SCART_PAL:
377 case TV_STD_SECAM:
378 case TV_STD_PAL_CN:
379 args.ucDacStandard = ATOM_DAC1_PAL;
380 break;
381 case TV_STD_NTSC:
382 case TV_STD_NTSC_J:
383 case TV_STD_PAL_60:
384 default:
385 args.ucDacStandard = ATOM_DAC1_NTSC;
386 break;
387 }
388 }
389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
390
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392
393}
394
395static void
396atombios_tv_setup(struct drm_encoder *encoder, int action)
397{
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args;
402 int index = 0;
445282db 403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 404
771fe6b9
JG		 405 memset(&args, 0, sizeof(args));
406
407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
408
409 args.sTVEncoder.ucAction = action;
410
4ce001ab 411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
413 else {
affd8589 414 switch (dac_info->tv_std) {
771fe6b9
JG		 415 case TV_STD_NTSC:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
417 break;
418 case TV_STD_PAL:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
420 break;
421 case TV_STD_PAL_M:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
423 break;
424 case TV_STD_PAL_60:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
426 break;
427 case TV_STD_NTSC_J:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
429 break;
430 case TV_STD_SCART_PAL:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
432 break;
433 case TV_STD_SECAM:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
435 break;
436 case TV_STD_PAL_CN:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
438 break;
439 default:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441 break;
442 }
443 }
444
445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
446
447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
448
449}
450
99999aaa
AD		 451union dvo_encoder_control {
452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
455};
771fe6b9 456
99999aaa
AD		 457void
458atombios_dvo_setup(struct drm_encoder *encoder, int action)
771fe6b9
JG		 459{
460 struct drm_device *dev = encoder->dev;
461 struct radeon_device *rdev = dev->dev_private;
462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99999aaa
AD		 463 union dvo_encoder_control args;
464 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
771fe6b9
JG		 465
466 memset(&args, 0, sizeof(args));
467
99999aaa
AD		 468 if (ASIC_IS_DCE3(rdev)) {
469 /* DCE3+ */
470 args.dvo_v3.ucAction = action;
471 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 args.dvo_v3.ucDVOConfig = 0; /* XXX */
473 } else if (ASIC_IS_DCE2(rdev)) {
474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475 args.dvo.sDVOEncoder.ucAction = action;
476 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
477 /* DFP1, CRT1, TV1 depending on the type of port */
478 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
479
480 if (radeon_encoder->pixel_clock > 165000)
481 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
482 } else {
483 /* R4xx, R5xx */
484 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
771fe6b9 485
99999aaa
AD		 486 if (radeon_encoder->pixel_clock > 165000)
487 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
771fe6b9 488
99999aaa
AD		 489 /*if (pScrn->rgbBits == 8)*/
490 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
491 }
771fe6b9
JG		 492
493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 494}
495
496union lvds_encoder_control {
497 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
498 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
499};
500
32f48ffe 501void
771fe6b9
JG		 502atombios_digital_setup(struct drm_encoder *encoder, int action)
503{
504 struct drm_device *dev = encoder->dev;
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
771fe6b9
JG		 508 union lvds_encoder_control args;
509 int index = 0;
dafc3bd5 510 int hdmi_detected = 0;
771fe6b9 511 uint8_t frev, crev;
771fe6b9 512
4aab97e8 513 if (!dig)
771fe6b9
JG		 514 return;
515
9ae47867 516 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dafc3bd5
CK		 517 hdmi_detected = 1;
518
771fe6b9
JG		 519 memset(&args, 0, sizeof(args));
520
521 switch (radeon_encoder->encoder_id) {
522 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
523 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
524 break;
525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
527 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
528 break;
529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
530 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
531 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
532 else
533 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
534 break;
535 }
536
a084e6ee
AD		 537 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
538 return;
771fe6b9
JG		 539
540 switch (frev) {
541 case 1:
542 case 2:
543 switch (crev) {
544 case 1:
545 args.v1.ucMisc = 0;
546 args.v1.ucAction = action;
dafc3bd5 547 if (hdmi_detected)
771fe6b9
JG		 548 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
549 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 551 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 552 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 553 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
99999aaa 554 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
771fe6b9 555 } else {
5137ee94 556 if (dig->linkb)
771fe6b9
JG		 557 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
558 if (radeon_encoder->pixel_clock > 165000)
559 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
560 /*if (pScrn->rgbBits == 8) */
99999aaa 561 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
771fe6b9
JG		 562 }
563 break;
564 case 2:
565 case 3:
566 args.v2.ucMisc = 0;
567 args.v2.ucAction = action;
568 if (crev == 3) {
569 if (dig->coherent_mode)
570 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
571 }
dafc3bd5 572 if (hdmi_detected)
771fe6b9
JG		 573 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
574 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
575 args.v2.ucTruncate = 0;
576 args.v2.ucSpatial = 0;
577 args.v2.ucTemporal = 0;
578 args.v2.ucFRC = 0;
579 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 580 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 581 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 582 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
771fe6b9 583 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
ba032a58 584 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 585 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
586 }
ba032a58 587 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
771fe6b9 588 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
ba032a58 589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9 590 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
ba032a58 591 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
771fe6b9
JG		 592 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
593 }
594 } else {
5137ee94 595 if (dig->linkb)
771fe6b9
JG		 596 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
597 if (radeon_encoder->pixel_clock > 165000)
598 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
599 }
600 break;
601 default:
602 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
603 break;
604 }
605 break;
606 default:
607 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
608 break;
609 }
610
611 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 612}
613
614int
615atombios_get_encoder_mode(struct drm_encoder *encoder)
616{
c7a71fc7 617 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
d033af87
AD		 618 struct drm_device *dev = encoder->dev;
619 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 620 struct drm_connector *connector;
621 struct radeon_connector *radeon_connector;
9ae47867 622 struct radeon_connector_atom_dig *dig_connector;
771fe6b9
JG		 623
624 connector = radeon_get_connector_for_encoder(encoder);
c7a71fc7
AD		 625 if (!connector) {
626 switch (radeon_encoder->encoder_id) {
627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
632 return ATOM_ENCODER_MODE_DVI;
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
635 default:
636 return ATOM_ENCODER_MODE_CRT;
637 }
638 }
771fe6b9
JG		 639 radeon_connector = to_radeon_connector(connector);
640
641 switch (connector->connector_type) {
642 case DRM_MODE_CONNECTOR_DVII:
705af9c7 643 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
9453d621 644 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 645 /* fix me */
646 if (ASIC_IS_DCE4(rdev))
647 return ATOM_ENCODER_MODE_DVI;
648 else
649 return ATOM_ENCODER_MODE_HDMI;
650 } else if (radeon_connector->use_digital)
771fe6b9
JG		 651 return ATOM_ENCODER_MODE_DVI;
652 else
653 return ATOM_ENCODER_MODE_CRT;
654 break;
655 case DRM_MODE_CONNECTOR_DVID:
656 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9 657 default:
9453d621 658 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 659 /* fix me */
660 if (ASIC_IS_DCE4(rdev))
661 return ATOM_ENCODER_MODE_DVI;
662 else
663 return ATOM_ENCODER_MODE_HDMI;
664 } else
771fe6b9
JG		 665 return ATOM_ENCODER_MODE_DVI;
666 break;
667 case DRM_MODE_CONNECTOR_LVDS:
668 return ATOM_ENCODER_MODE_LVDS;
669 break;
670 case DRM_MODE_CONNECTOR_DisplayPort:
9ae47867
AD		 671 dig_connector = radeon_connector->con_priv;
672 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
673 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
f92a8b67 674 return ATOM_ENCODER_MODE_DP;
9453d621 675 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 676 /* fix me */
677 if (ASIC_IS_DCE4(rdev))
678 return ATOM_ENCODER_MODE_DVI;
679 else
680 return ATOM_ENCODER_MODE_HDMI;
681 } else
771fe6b9
JG		 682 return ATOM_ENCODER_MODE_DVI;
683 break;
3a5f4a21
AD		 684 case DRM_MODE_CONNECTOR_eDP:
685 return ATOM_ENCODER_MODE_DP;
a5899fcc
AD		 686 case DRM_MODE_CONNECTOR_DVIA:
687 case DRM_MODE_CONNECTOR_VGA:
771fe6b9
JG		 688 return ATOM_ENCODER_MODE_CRT;
689 break;
a5899fcc
AD		 690 case DRM_MODE_CONNECTOR_Composite:
691 case DRM_MODE_CONNECTOR_SVIDEO:
692 case DRM_MODE_CONNECTOR_9PinDIN:
771fe6b9
JG		 693 /* fix me */
694 return ATOM_ENCODER_MODE_TV;
695 /*return ATOM_ENCODER_MODE_CV;*/
696 break;
697 }
698}
699
1a66c95a
AD		 700/*
701 * DIG Encoder/Transmitter Setup
702 *
703 * DCE 3.0/3.1
704 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
705 * Supports up to 3 digital outputs
706 * - 2 DIG encoder blocks.
707 * DIG1 can drive UNIPHY link A or link B
708 * DIG2 can drive UNIPHY link B or LVTMA
709 *
710 * DCE 3.2
711 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
712 * Supports up to 5 digital outputs
713 * - 2 DIG encoder blocks.
714 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
715 *
a001182a 716 * DCE 4.0/5.0
4e8c65a1 717 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
bcc1c2a1
AD		 718 * Supports up to 6 digital outputs
719 * - 6 DIG encoder blocks.
720 * - DIG to PHY mapping is hardcoded
721 * DIG1 drives UNIPHY0 link A, A+B
722 * DIG2 drives UNIPHY0 link B
723 * DIG3 drives UNIPHY1 link A, A+B
724 * DIG4 drives UNIPHY1 link B
725 * DIG5 drives UNIPHY2 link A, A+B
726 * DIG6 drives UNIPHY2 link B
727 *
4e8c65a1
AD		 728 * DCE 4.1
729 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
730 * Supports up to 6 digital outputs
731 * - 2 DIG encoder blocks.
732 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
733 *
1a66c95a
AD		 734 * Routing
735 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
736 * Examples:
737 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
738 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
739 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
740 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
741 */
bcc1c2a1
AD		 742
743union dig_encoder_control {
744 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
745 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
746 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
badbb57b 747 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
bcc1c2a1
AD		 748};
749
750void
771fe6b9
JG		 751atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
752{
753 struct drm_device *dev = encoder->dev;
754 struct radeon_device *rdev = dev->dev_private;
755 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 756 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 757 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
bcc1c2a1 758 union dig_encoder_control args;
d9c9fe36 759 int index = 0;
771fe6b9 760 uint8_t frev, crev;
4aab97e8
AD		 761 int dp_clock = 0;
762 int dp_lane_count = 0;
badbb57b 763 int hpd_id = RADEON_HPD_NONE;
df271bec 764 int bpc = 8;
4aab97e8
AD		 765
766 if (connector) {
767 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
768 struct radeon_connector_atom_dig *dig_connector =
769 radeon_connector->con_priv;
771fe6b9 770
4aab97e8
AD		 771 dp_clock = dig_connector->dp_clock;
772 dp_lane_count = dig_connector->dp_lane_count;
badbb57b 773 hpd_id = radeon_connector->hpd.hpd;
df271bec 774 bpc = connector->display_info.bpc;
4aab97e8
AD		 775 }
776
777 /* no dig encoder assigned */
778 if (dig->dig_encoder == -1)
771fe6b9
JG		 779 return;
780
771fe6b9
JG		 781 memset(&args, 0, sizeof(args));
782
bcc1c2a1
AD		 783 if (ASIC_IS_DCE4(rdev))
784 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
785 else {
786 if (dig->dig_encoder)
787 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
788 else
789 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
790 }
771fe6b9 791
a084e6ee
AD		 792 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
793 return;
771fe6b9 794
bcc1c2a1
AD		 795 args.v1.ucAction = action;
796 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
797 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
771fe6b9 798
badbb57b
AD		 799 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
800 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
4aab97e8 801 args.v1.ucLaneNum = dp_lane_count;
badbb57b 802 else if (radeon_encoder->pixel_clock > 165000)
bcc1c2a1
AD		 803 args.v1.ucLaneNum = 8;
804 else
805 args.v1.ucLaneNum = 4;
806
badbb57b
AD		 807 if (ASIC_IS_DCE5(rdev)) {
808 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
809 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
810 if (dp_clock == 270000)
811 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
812 else if (dp_clock == 540000)
813 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
814 }
815 args.v4.acConfig.ucDigSel = dig->dig_encoder;
df271bec
AD		 816 switch (bpc) {
817 case 0:
818 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
819 break;
820 case 6:
821 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
822 break;
823 case 8:
824 default:
825 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
826 break;
827 case 10:
828 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
829 break;
830 case 12:
831 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
832 break;
833 case 16:
834 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
835 break;
836 }
badbb57b
AD		 837 if (hpd_id == RADEON_HPD_NONE)
838 args.v4.ucHPD_ID = 0;
839 else
840 args.v4.ucHPD_ID = hpd_id + 1;
841 } else if (ASIC_IS_DCE4(rdev)) {
842 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
843 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
bcc1c2a1 844 args.v3.acConfig.ucDigSel = dig->dig_encoder;
df271bec
AD		 845 switch (bpc) {
846 case 0:
847 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
848 break;
849 case 6:
850 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
851 break;
852 case 8:
853 default:
854 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
855 break;
856 case 10:
857 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
858 break;
859 case 12:
860 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
861 break;
862 case 16:
863 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
864 break;
865 }
bcc1c2a1 866 } else {
badbb57b
AD		 867 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
868 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
771fe6b9
JG		 869 switch (radeon_encoder->encoder_id) {
870 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
bcc1c2a1 871 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
771fe6b9
JG		 872 break;
873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
bcc1c2a1
AD		 874 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
875 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
771fe6b9
JG		 876 break;
877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
bcc1c2a1 878 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
771fe6b9
JG		 879 break;
880 }
5137ee94 881 if (dig->linkb)
bcc1c2a1
AD		 882 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
883 else
884 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
771fe6b9
JG		 885 }
886
771fe6b9
JG		 887 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
888
889}
890
891union dig_transmitter_control {
892 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
893 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
bcc1c2a1 894 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
a001182a 895 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
771fe6b9
JG		 896};
897
5801ead6 898void
1a66c95a 899atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
771fe6b9
JG		 900{
901 struct drm_device *dev = encoder->dev;
902 struct radeon_device *rdev = dev->dev_private;
903 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 904 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 905 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
771fe6b9 906 union dig_transmitter_control args;
d9c9fe36 907 int index = 0;
771fe6b9 908 uint8_t frev, crev;
f92a8b67 909 bool is_dp = false;
bcc1c2a1 910 int pll_id = 0;
4aab97e8
AD		 911 int dp_clock = 0;
912 int dp_lane_count = 0;
913 int connector_object_id = 0;
914 int igp_lane_info = 0;
915
916 if (connector) {
917 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
918 struct radeon_connector_atom_dig *dig_connector =
919 radeon_connector->con_priv;
920
921 dp_clock = dig_connector->dp_clock;
922 dp_lane_count = dig_connector->dp_lane_count;
923 connector_object_id =
924 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
925 igp_lane_info = dig_connector->igp_lane_info;
926 }
771fe6b9 927
4aab97e8
AD		 928 /* no dig encoder assigned */
929 if (dig->dig_encoder == -1)
771fe6b9
JG		 930 return;
931
f92a8b67
AD		 932 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
933 is_dp = true;
934
771fe6b9
JG		 935 memset(&args, 0, sizeof(args));
936
4aab97e8 937 switch (radeon_encoder->encoder_id) {
99999aaa
AD		 938 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
939 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
940 break;
4aab97e8
AD		 941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
771fe6b9 944 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
4aab97e8
AD		 945 break;
946 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
947 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
948 break;
771fe6b9
JG		 949 }
950
a084e6ee
AD		 951 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
952 return;
771fe6b9
JG		 953
954 args.v1.ucAction = action;
f95a9f0b 955 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
4589433c 956 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1a66c95a
AD		 957 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
958 args.v1.asMode.ucLaneSel = lane_num;
959 args.v1.asMode.ucLaneSet = lane_set;
f95a9f0b 960 } else {
f92a8b67
AD		 961 if (is_dp)
962 args.v1.usPixelClock =
4aab97e8 963 cpu_to_le16(dp_clock / 10);
f92a8b67 964 else if (radeon_encoder->pixel_clock > 165000)
f95a9f0b
AD		 965 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
966 else
967 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
968 }
bcc1c2a1
AD		 969 if (ASIC_IS_DCE4(rdev)) {
970 if (is_dp)
4aab97e8 971 args.v3.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 972 else if (radeon_encoder->pixel_clock > 165000)
973 args.v3.ucLaneNum = 8;
974 else
975 args.v3.ucLaneNum = 4;
976
96b3bef8 977 if (dig->linkb)
b61c99de 978 args.v3.acConfig.ucLinkSel = 1;
96b3bef8 979 if (dig->dig_encoder & 1)
b61c99de 980 args.v3.acConfig.ucEncoderSel = 1;
bcc1c2a1
AD		 981
982 /* Select the PLL for the PHY
983 * DP PHY should be clocked from external src if there is
984 * one.
985 */
986 if (encoder->crtc) {
987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
988 pll_id = radeon_crtc->pll_id;
989 }
a001182a
AD		 990
991 if (ASIC_IS_DCE5(rdev)) {
86a94def
AD		 992 /* On DCE5 DCPLL usually generates the DP ref clock */
993 if (is_dp) {
994 if (rdev->clock.dp_extclk)
995 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
996 else
997 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
998 } else
a001182a
AD		 999 args.v4.acConfig.ucRefClkSource = pll_id;
1000 } else {
86a94def 1001 /* On DCE4, if there is an external clock, it generates the DP ref clock */
a001182a
AD		 1002 if (is_dp && rdev->clock.dp_extclk)
1003 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1004 else
1005 args.v3.acConfig.ucRefClkSource = pll_id;
1006 }
bcc1c2a1
AD		 1007
1008 switch (radeon_encoder->encoder_id) {
1009 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1010 args.v3.acConfig.ucTransmitterSel = 0;
bcc1c2a1
AD		 1011 break;
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1013 args.v3.acConfig.ucTransmitterSel = 1;
bcc1c2a1
AD		 1014 break;
1015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1016 args.v3.acConfig.ucTransmitterSel = 2;
bcc1c2a1
AD		 1017 break;
1018 }
1019
1020 if (is_dp)
1021 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1022 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1023 if (dig->coherent_mode)
1024 args.v3.acConfig.fCoherentMode = 1;
b317a9ce
AD		 1025 if (radeon_encoder->pixel_clock > 165000)
1026 args.v3.acConfig.fDualLinkConnector = 1;
bcc1c2a1
AD		 1027 }
1028 } else if (ASIC_IS_DCE32(rdev)) {
d9c9fe36 1029 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
5137ee94 1030 if (dig->linkb)
1a66c95a 1031 args.v2.acConfig.ucLinkSel = 1;
771fe6b9
JG		 1032
1033 switch (radeon_encoder->encoder_id) {
1034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1035 args.v2.acConfig.ucTransmitterSel = 0;
771fe6b9
JG		 1036 break;
1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1038 args.v2.acConfig.ucTransmitterSel = 1;
771fe6b9
JG		 1039 break;
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1041 args.v2.acConfig.ucTransmitterSel = 2;
771fe6b9
JG		 1042 break;
1043 }
1044
f92a8b67
AD		 1045 if (is_dp)
1046 args.v2.acConfig.fCoherentMode = 1;
1047 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 1048 if (dig->coherent_mode)
1049 args.v2.acConfig.fCoherentMode = 1;
b317a9ce
AD		 1050 if (radeon_encoder->pixel_clock > 165000)
1051 args.v2.acConfig.fDualLinkConnector = 1;
771fe6b9
JG		 1052 }
1053 } else {
1054 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
771fe6b9 1055
f28cf339
DA		 1056 if (dig->dig_encoder)
1057 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1058 else
1059 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1060
d9c9fe36
AD		 1061 if ((rdev->flags & RADEON_IS_IGP) &&
1062 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1063 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
4aab97e8 1064 if (igp_lane_info & 0x1)
d9c9fe36 1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
4aab97e8 1066 else if (igp_lane_info & 0x2)
d9c9fe36 1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
4aab97e8 1068 else if (igp_lane_info & 0x4)
d9c9fe36 1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
4aab97e8 1070 else if (igp_lane_info & 0x8)
d9c9fe36
AD		 1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1072 } else {
4aab97e8 1073 if (igp_lane_info & 0x3)
d9c9fe36 1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
4aab97e8 1075 else if (igp_lane_info & 0xc)
d9c9fe36 1076 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
771fe6b9 1077 }
771fe6b9
JG		 1078 }
1079
5137ee94 1080 if (dig->linkb)
1a66c95a
AD		 1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1082 else
1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1084
f92a8b67
AD		 1085 if (is_dp)
1086 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1087 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 1088 if (dig->coherent_mode)
1089 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
d9c9fe36
AD		 1090 if (radeon_encoder->pixel_clock > 165000)
1091 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
771fe6b9
JG		 1092 }
1093 }
1094
1095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 1096}
1097
2dafb74d 1098bool
8b834852
AD		 1099atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1100{
1101 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1102 struct drm_device *dev = radeon_connector->base.dev;
1103 struct radeon_device *rdev = dev->dev_private;
1104 union dig_transmitter_control args;
1105 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1106 uint8_t frev, crev;
1107
1108 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
2dafb74d 1109 goto done;
8b834852
AD		 1110
1111 if (!ASIC_IS_DCE4(rdev))
2dafb74d 1112 goto done;
8b834852 1113
e468e001 1114 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
8b834852 1115 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
2dafb74d 1116 goto done;
8b834852
AD		 1117
1118 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2dafb74d 1119 goto done;
8b834852
AD		 1120
1121 memset(&args, 0, sizeof(args));
1122
1123 args.v1.ucAction = action;
1124
1125 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2dafb74d
AD		 1126
1127 /* wait for the panel to power up */
1128 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1129 int i;
1130
1131 for (i = 0; i < 300; i++) {
1132 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1133 return true;
1134 mdelay(1);
1135 }
1136 return false;
1137 }
1138done:
1139 return true;
8b834852
AD		 1140}
1141
3e4b9982
AD		 1142union external_encoder_control {
1143 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
bf982ebf 1144 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
3e4b9982
AD		 1145};
1146
1147static void
1148atombios_external_encoder_setup(struct drm_encoder *encoder,
1149 struct drm_encoder *ext_encoder,
1150 int action)
1151{
1152 struct drm_device *dev = encoder->dev;
1153 struct radeon_device *rdev = dev->dev_private;
1154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
bf982ebf 1155 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
3e4b9982
AD		 1156 union external_encoder_control args;
1157 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1158 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1159 u8 frev, crev;
1160 int dp_clock = 0;
1161 int dp_lane_count = 0;
1162 int connector_object_id = 0;
bf982ebf 1163 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
df271bec 1164 int bpc = 8;
3e4b9982
AD		 1165
1166 if (connector) {
1167 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1168 struct radeon_connector_atom_dig *dig_connector =
1169 radeon_connector->con_priv;
1170
1171 dp_clock = dig_connector->dp_clock;
1172 dp_lane_count = dig_connector->dp_lane_count;
1173 connector_object_id =
1174 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
df271bec 1175 bpc = connector->display_info.bpc;
3e4b9982
AD		 1176 }
1177
1178 memset(&args, 0, sizeof(args));
1179
1180 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1181 return;
1182
1183 switch (frev) {
1184 case 1:
1185 /* no params on frev 1 */
1186 break;
1187 case 2:
1188 switch (crev) {
1189 case 1:
1190 case 2:
1191 args.v1.sDigEncoder.ucAction = action;
1192 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1193 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1194
1195 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1196 if (dp_clock == 270000)
1197 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1198 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1199 } else if (radeon_encoder->pixel_clock > 165000)
1200 args.v1.sDigEncoder.ucLaneNum = 8;
1201 else
1202 args.v1.sDigEncoder.ucLaneNum = 4;
1203 break;
bf982ebf
AD		 1204 case 3:
1205 args.v3.sExtEncoder.ucAction = action;
1206 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
4589433c 1207 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
bf982ebf
AD		 1208 else
1209 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1210 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1211
1212 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1213 if (dp_clock == 270000)
1214 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1215 else if (dp_clock == 540000)
1216 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1217 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1218 } else if (radeon_encoder->pixel_clock > 165000)
1219 args.v3.sExtEncoder.ucLaneNum = 8;
1220 else
1221 args.v3.sExtEncoder.ucLaneNum = 4;
1222 switch (ext_enum) {
1223 case GRAPH_OBJECT_ENUM_ID1:
1224 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1225 break;
1226 case GRAPH_OBJECT_ENUM_ID2:
1227 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1228 break;
1229 case GRAPH_OBJECT_ENUM_ID3:
1230 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1231 break;
1232 }
df271bec
AD		 1233 switch (bpc) {
1234 case 0:
1235 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1236 break;
1237 case 6:
1238 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1239 break;
1240 case 8:
1241 default:
1242 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1243 break;
1244 case 10:
1245 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1246 break;
1247 case 12:
1248 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1249 break;
1250 case 16:
1251 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1252 break;
1253 }
bf982ebf 1254 break;
3e4b9982
AD		 1255 default:
1256 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1257 return;
1258 }
1259 break;
1260 default:
1261 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1262 return;
1263 }
1264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1265}
1266
771fe6b9
JG		 1267static void
1268atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1269{
1270 struct drm_device *dev = encoder->dev;
1271 struct radeon_device *rdev = dev->dev_private;
1272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1273 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1274 ENABLE_YUV_PS_ALLOCATION args;
1275 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1276 uint32_t temp, reg;
1277
1278 memset(&args, 0, sizeof(args));
1279
1280 if (rdev->family >= CHIP_R600)
1281 reg = R600_BIOS_3_SCRATCH;
1282 else
1283 reg = RADEON_BIOS_3_SCRATCH;
1284
1285 /* XXX: fix up scratch reg handling */
1286 temp = RREG32(reg);
4ce001ab 1287 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1288 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1289 (radeon_crtc->crtc_id << 18)));
4ce001ab 1290 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1291 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1292 else
1293 WREG32(reg, 0);
1294
1295 if (enable)
1296 args.ucEnable = ATOM_ENABLE;
1297 args.ucCRTC = radeon_crtc->crtc_id;
1298
1299 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1300
1301 WREG32(reg, temp);
1302}
1303
771fe6b9
JG		 1304static void
1305radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1306{
1307 struct drm_device *dev = encoder->dev;
1308 struct radeon_device *rdev = dev->dev_private;
1309 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3e4b9982 1310 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
771fe6b9
JG		 1311 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1312 int index = 0;
1313 bool is_dig = false;
69c74525 1314 bool is_dce5_dac = false;
d07f4e83 1315 bool is_dce5_dvo = false;
771fe6b9
JG		 1316
1317 memset(&args, 0, sizeof(args));
1318
d9fdaafb 1319 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
f641e51e
DA		 1320 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1321 radeon_encoder->active_device);
771fe6b9
JG		 1322 switch (radeon_encoder->encoder_id) {
1323 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1324 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1325 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1326 break;
1327 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1328 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1330 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1331 is_dig = true;
1332 break;
1333 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1334 case ENCODER_OBJECT_ID_INTERNAL_DDI:
771fe6b9
JG		 1335 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1336 break;
99999aaa 1337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
d07f4e83
AD		 1338 if (ASIC_IS_DCE5(rdev))
1339 is_dce5_dvo = true;
1340 else if (ASIC_IS_DCE3(rdev))
99999aaa
AD		 1341 is_dig = true;
1342 else
1343 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1344 break;
771fe6b9
JG		 1345 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1346 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1347 break;
1348 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1349 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1350 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1351 else
1352 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1353 break;
1354 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1355 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
69c74525
AD		 1356 if (ASIC_IS_DCE5(rdev))
1357 is_dce5_dac = true;
1358 else {
1359 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1360 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1361 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1362 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1363 else
1364 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1365 }
771fe6b9
JG		 1366 break;
1367 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
8c2a6d73 1369 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1370 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1371 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1372 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1373 else
1374 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1375 break;
1376 }
1377
1378 if (is_dig) {
1379 switch (mode) {
1380 case DRM_MODE_DPMS_ON:
e13b2ac1 1381 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fb668c2f 1382 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
58682f10 1383 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
fb668c2f 1384
8b834852
AD		 1385 if (connector &&
1386 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1387 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1388 struct radeon_connector_atom_dig *radeon_dig_connector =
1389 radeon_connector->con_priv;
1390 atombios_set_edp_panel_power(connector,
1391 ATOM_TRANSMITTER_ACTION_POWER_ON);
1392 radeon_dig_connector->edp_on = true;
1393 }
58682f10 1394 dp_link_train(encoder, connector);
fb668c2f
AD		 1395 if (ASIC_IS_DCE4(rdev))
1396 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
58682f10 1397 }
ba251bde
AD		 1398 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1399 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
771fe6b9
JG		 1400 break;
1401 case DRM_MODE_DPMS_STANDBY:
1402 case DRM_MODE_DPMS_SUSPEND:
1403 case DRM_MODE_DPMS_OFF:
e13b2ac1 1404 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
fb668c2f 1405 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
8b834852
AD		 1406 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1407
fb668c2f
AD		 1408 if (ASIC_IS_DCE4(rdev))
1409 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
8b834852
AD		 1410 if (connector &&
1411 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1412 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1413 struct radeon_connector_atom_dig *radeon_dig_connector =
1414 radeon_connector->con_priv;
1415 atombios_set_edp_panel_power(connector,
1416 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1417 radeon_dig_connector->edp_on = false;
1418 }
fb668c2f 1419 }
ba251bde
AD		 1420 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1421 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
771fe6b9
JG		 1422 break;
1423 }
69c74525
AD		 1424 } else if (is_dce5_dac) {
1425 switch (mode) {
1426 case DRM_MODE_DPMS_ON:
1427 atombios_dac_setup(encoder, ATOM_ENABLE);
1428 break;
1429 case DRM_MODE_DPMS_STANDBY:
1430 case DRM_MODE_DPMS_SUSPEND:
1431 case DRM_MODE_DPMS_OFF:
1432 atombios_dac_setup(encoder, ATOM_DISABLE);
1433 break;
1434 }
d07f4e83
AD		 1435 } else if (is_dce5_dvo) {
1436 switch (mode) {
1437 case DRM_MODE_DPMS_ON:
1438 atombios_dvo_setup(encoder, ATOM_ENABLE);
1439 break;
1440 case DRM_MODE_DPMS_STANDBY:
1441 case DRM_MODE_DPMS_SUSPEND:
1442 case DRM_MODE_DPMS_OFF:
1443 atombios_dvo_setup(encoder, ATOM_DISABLE);
1444 break;
1445 }
771fe6b9
JG		 1446 } else {
1447 switch (mode) {
1448 case DRM_MODE_DPMS_ON:
1449 args.ucAction = ATOM_ENABLE;
ba251bde
AD		 1450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1451 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1452 args.ucAction = ATOM_LCD_BLON;
1453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1454 }
771fe6b9
JG		 1455 break;
1456 case DRM_MODE_DPMS_STANDBY:
1457 case DRM_MODE_DPMS_SUSPEND:
1458 case DRM_MODE_DPMS_OFF:
1459 args.ucAction = ATOM_DISABLE;
ba251bde
AD		 1460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1461 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1462 args.ucAction = ATOM_LCD_BLOFF;
1463 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1464 }
771fe6b9
JG		 1465 break;
1466 }
771fe6b9 1467 }
3e4b9982
AD		 1468
1469 if (ext_encoder) {
1470 int action;
1471
1472 switch (mode) {
1473 case DRM_MODE_DPMS_ON:
1474 default:
633b9164 1475 if (ASIC_IS_DCE41(rdev))
bf982ebf
AD		 1476 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1477 else
1478 action = ATOM_ENABLE;
3e4b9982
AD		 1479 break;
1480 case DRM_MODE_DPMS_STANDBY:
1481 case DRM_MODE_DPMS_SUSPEND:
1482 case DRM_MODE_DPMS_OFF:
633b9164 1483 if (ASIC_IS_DCE41(rdev))
bf982ebf
AD		 1484 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1485 else
1486 action = ATOM_DISABLE;
3e4b9982
AD		 1487 break;
1488 }
1489 atombios_external_encoder_setup(encoder, ext_encoder, action);
1490 }
1491
771fe6b9 1492 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1493
771fe6b9
JG		 1494}
1495
9ae47867 1496union crtc_source_param {
771fe6b9
JG		 1497 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1498 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1499};
1500
1501static void
1502atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1503{
1504 struct drm_device *dev = encoder->dev;
1505 struct radeon_device *rdev = dev->dev_private;
1506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1507 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9ae47867 1508 union crtc_source_param args;
771fe6b9
JG		 1509 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1510 uint8_t frev, crev;
f28cf339 1511 struct radeon_encoder_atom_dig *dig;
771fe6b9
JG		 1512
1513 memset(&args, 0, sizeof(args));
1514
a084e6ee
AD		 1515 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1516 return;
771fe6b9
JG		 1517
1518 switch (frev) {
1519 case 1:
1520 switch (crev) {
1521 case 1:
1522 default:
1523 if (ASIC_IS_AVIVO(rdev))
1524 args.v1.ucCRTC = radeon_crtc->crtc_id;
1525 else {
1526 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1527 args.v1.ucCRTC = radeon_crtc->crtc_id;
1528 } else {
1529 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1530 }
1531 }
1532 switch (radeon_encoder->encoder_id) {
1533 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1534 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1535 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1536 break;
1537 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1538 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1539 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1540 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1541 else
1542 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1543 break;
1544 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1545 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1546 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1547 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1548 break;
1549 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1551 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1552 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1553 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1554 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1555 else
1556 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1557 break;
1558 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1559 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1560 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1561 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1562 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1563 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1564 else
1565 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1566 break;
1567 }
1568 break;
1569 case 2:
1570 args.v2.ucCRTC = radeon_crtc->crtc_id;
1571 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1572 switch (radeon_encoder->encoder_id) {
1573 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1574 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1575 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
f28cf339
DA		 1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1577 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1578 switch (dig->dig_encoder) {
1579 case 0:
f28cf339 1580 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
bcc1c2a1
AD		 1581 break;
1582 case 1:
1583 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1584 break;
1585 case 2:
1586 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1587 break;
1588 case 3:
1589 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1590 break;
1591 case 4:
1592 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1593 break;
1594 case 5:
1595 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1596 break;
1597 }
771fe6b9
JG		 1598 break;
1599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1600 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1601 break;
771fe6b9 1602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1603 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1604 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1605 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1606 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1607 else
1608 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1609 break;
1610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1611 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1612 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1613 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1614 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1615 else
1616 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1617 break;
1618 }
1619 break;
1620 }
1621 break;
1622 default:
1623 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
99999aaa 1624 return;
771fe6b9
JG		 1625 }
1626
1627 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
267364ac
AD		 1628
1629 /* update scratch regs with new routing */
1630 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1631}
1632
1633static void
1634atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1635 struct drm_display_mode *mode)
1636{
1637 struct drm_device *dev = encoder->dev;
1638 struct radeon_device *rdev = dev->dev_private;
1639 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1640 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1641
1642 /* Funky macbooks */
1643 if ((dev->pdev->device == 0x71C5) &&
1644 (dev->pdev->subsystem_vendor == 0x106b) &&
1645 (dev->pdev->subsystem_device == 0x0080)) {
1646 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1647 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1648
1649 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1650 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1651
1652 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1653 }
1654 }
1655
1656 /* set scaler clears this on some chips */
c9417bdd
AD		 1657 if (ASIC_IS_AVIVO(rdev) &&
1658 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1659 if (ASIC_IS_DCE4(rdev)) {
1660 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1661 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1662 EVERGREEN_INTERLEAVE_EN);
1663 else
1664 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1665 } else {
1666 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1667 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1668 AVIVO_D1MODE_INTERLEAVE_EN);
1669 else
1670 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1671 }
ceefedd8 1672 }
771fe6b9
JG		 1673}
1674
f28cf339
DA		 1675static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1676{
1677 struct drm_device *dev = encoder->dev;
1678 struct radeon_device *rdev = dev->dev_private;
1679 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1681 struct drm_encoder *test_encoder;
1682 struct radeon_encoder_atom_dig *dig;
1683 uint32_t dig_enc_in_use = 0;
bcc1c2a1 1684
badbb57b 1685 /* DCE4/5 */
bcc1c2a1 1686 if (ASIC_IS_DCE4(rdev)) {
5137ee94 1687 dig = radeon_encoder->enc_priv;
96b3bef8
AD		 1688 if (ASIC_IS_DCE41(rdev))
1689 return radeon_crtc->crtc_id;
1690 else {
b61c99de
AD		 1691 switch (radeon_encoder->encoder_id) {
1692 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1693 if (dig->linkb)
1694 return 1;
1695 else
1696 return 0;
1697 break;
1698 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1699 if (dig->linkb)
1700 return 3;
1701 else
1702 return 2;
1703 break;
1704 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1705 if (dig->linkb)
1706 return 5;
1707 else
1708 return 4;
1709 break;
1710 }
bcc1c2a1
AD		 1711 }
1712 }
1713
f28cf339
DA		 1714 /* on DCE32 and encoder can driver any block so just crtc id */
1715 if (ASIC_IS_DCE32(rdev)) {
1716 return radeon_crtc->crtc_id;
1717 }
1718
1719 /* on DCE3 - LVTMA can only be driven by DIGB */
1720 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1721 struct radeon_encoder *radeon_test_encoder;
1722
1723 if (encoder == test_encoder)
1724 continue;
1725
1726 if (!radeon_encoder_is_digital(test_encoder))
1727 continue;
1728
1729 radeon_test_encoder = to_radeon_encoder(test_encoder);
1730 dig = radeon_test_encoder->enc_priv;
1731
1732 if (dig->dig_encoder >= 0)
1733 dig_enc_in_use |= (1 << dig->dig_encoder);
1734 }
1735
1736 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1737 if (dig_enc_in_use & 0x2)
1738 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1739 return 1;
1740 }
1741 if (!(dig_enc_in_use & 1))
1742 return 0;
1743 return 1;
1744}
1745
771fe6b9
JG		 1746static void
1747radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1748 struct drm_display_mode *mode,
1749 struct drm_display_mode *adjusted_mode)
1750{
1751 struct drm_device *dev = encoder->dev;
1752 struct radeon_device *rdev = dev->dev_private;
1753 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3e4b9982 1754 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
771fe6b9 1755
771fe6b9
JG		 1756 radeon_encoder->pixel_clock = adjusted_mode->clock;
1757
c6f8505e 1758 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
4ce001ab 1759 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1760 atombios_yuv_setup(encoder, true);
1761 else
1762 atombios_yuv_setup(encoder, false);
1763 }
1764
1765 switch (radeon_encoder->encoder_id) {
1766 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1767 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1768 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1769 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1770 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1771 break;
1772 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
bcc1c2a1
AD		 1776 if (ASIC_IS_DCE4(rdev)) {
1777 /* disable the transmitter */
1778 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1779 /* setup and enable the encoder */
1780 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1781
1782 /* init and enable the transmitter */
1783 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1784 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1785 } else {
1786 /* disable the encoder and transmitter */
1787 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1788 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1789
1790 /* setup and enable the encoder and transmitter */
1791 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1792 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1793 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1794 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1795 }
771fe6b9
JG		 1796 break;
1797 case ENCODER_OBJECT_ID_INTERNAL_DDI:
771fe6b9
JG		 1798 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
99999aaa 1800 atombios_dvo_setup(encoder, ATOM_ENABLE);
771fe6b9
JG		 1801 break;
1802 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1803 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1804 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1806 atombios_dac_setup(encoder, ATOM_ENABLE);
d3a67a43
AD		 1807 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1808 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1809 atombios_tv_setup(encoder, ATOM_ENABLE);
1810 else
1811 atombios_tv_setup(encoder, ATOM_DISABLE);
1812 }
771fe6b9
JG		 1813 break;
1814 }
3e4b9982
AD		 1815
1816 if (ext_encoder) {
633b9164 1817 if (ASIC_IS_DCE41(rdev)) {
bf982ebf
AD		 1818 atombios_external_encoder_setup(encoder, ext_encoder,
1819 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1820 atombios_external_encoder_setup(encoder, ext_encoder,
1821 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1822 } else
1823 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
3e4b9982
AD		 1824 }
1825
771fe6b9 1826 atombios_apply_encoder_quirks(encoder, adjusted_mode);
dafc3bd5 1827
2cd6218c
RM		 1828 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1829 r600_hdmi_enable(encoder);
bcc1c2a1 1830 r600_hdmi_setmode(encoder, adjusted_mode);
2cd6218c 1831 }
771fe6b9
JG		 1832}
1833
1834static bool
4ce001ab 1835atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1836{
1837 struct drm_device *dev = encoder->dev;
1838 struct radeon_device *rdev = dev->dev_private;
1839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1840 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1841
1842 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1843 ATOM_DEVICE_CV_SUPPORT |
1844 ATOM_DEVICE_CRT_SUPPORT)) {
1845 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1846 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1847 uint8_t frev, crev;
1848
1849 memset(&args, 0, sizeof(args));
1850
a084e6ee
AD		 1851 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1852 return false;
771fe6b9
JG		 1853
1854 args.sDacload.ucMisc = 0;
1855
1856 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1857 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1858 args.sDacload.ucDacType = ATOM_DAC_A;
1859 else
1860 args.sDacload.ucDacType = ATOM_DAC_B;
1861
4ce001ab 1862 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1863 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1864 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1865 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1866 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1867 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1868 if (crev >= 3)
1869 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1870 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1871 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1872 if (crev >= 3)
1873 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1874 }
1875
1876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1877
1878 return true;
1879 } else
1880 return false;
1881}
1882
1883static enum drm_connector_status
1884radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1885{
1886 struct drm_device *dev = encoder->dev;
1887 struct radeon_device *rdev = dev->dev_private;
1888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1889 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1890 uint32_t bios_0_scratch;
1891
4ce001ab 1892 if (!atombios_dac_load_detect(encoder, connector)) {
d9fdaafb 1893 DRM_DEBUG_KMS("detect returned false \n");
771fe6b9
JG		 1894 return connector_status_unknown;
1895 }
1896
1897 if (rdev->family >= CHIP_R600)
1898 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1899 else
1900 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1901
d9fdaafb 1902 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
4ce001ab 1903 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1904 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1905 return connector_status_connected;
4ce001ab
DA		 1906 }
1907 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1908 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1909 return connector_status_connected;
4ce001ab
DA		 1910 }
1911 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1912 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1913 return connector_status_connected;
4ce001ab
DA		 1914 }
1915 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1916 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1917 return connector_status_connected; /* CTV */
1918 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1919 return connector_status_connected; /* STV */
1920 }
1921 return connector_status_disconnected;
1922}
1923
1924static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1925{
267364ac 1926 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
fb939dfc 1927 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
267364ac
AD		 1928
1929 if (radeon_encoder->active_device &
1930 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1931 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1932 if (dig)
1933 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1934 }
1935
771fe6b9
JG		 1936 radeon_atom_output_lock(encoder, true);
1937 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
267364ac 1938
fb939dfc
AD		 1939 if (connector) {
1940 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
4e633939
AD		 1941
1942 /* select the clock/data port if it uses a router */
fb939dfc
AD		 1943 if (radeon_connector->router.cd_valid)
1944 radeon_router_select_cd_port(radeon_connector);
4e633939
AD		 1945
1946 /* turn eDP panel on for mode set */
1947 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1948 atombios_set_edp_panel_power(connector,
1949 ATOM_TRANSMITTER_ACTION_POWER_ON);
fb939dfc
AD		 1950 }
1951
267364ac
AD		 1952 /* this is needed for the pll/ss setup to work correctly in some cases */
1953 atombios_set_encoder_crtc_source(encoder);
771fe6b9
JG		 1954}
1955
1956static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1957{
1958 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1959 radeon_atom_output_lock(encoder, false);
1960}
1961
4ce001ab
DA		 1962static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1963{
aa961391
AD		 1964 struct drm_device *dev = encoder->dev;
1965 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1966 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f28cf339 1967 struct radeon_encoder_atom_dig *dig;
a0ae5864
AD		 1968
1969 /* check for pre-DCE3 cards with shared encoders;
1970 * can't really use the links individually, so don't disable
1971 * the encoder if it's in use by another connector
1972 */
1973 if (!ASIC_IS_DCE3(rdev)) {
1974 struct drm_encoder *other_encoder;
1975 struct radeon_encoder *other_radeon_encoder;
1976
1977 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1978 other_radeon_encoder = to_radeon_encoder(other_encoder);
1979 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1980 drm_helper_encoder_in_use(other_encoder))
1981 goto disable_done;
1982 }
1983 }
1984
4ce001ab 1985 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
f28cf339 1986
aa961391
AD		 1987 switch (radeon_encoder->encoder_id) {
1988 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1989 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1990 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1991 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1992 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1993 break;
1994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1995 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1997 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1998 if (ASIC_IS_DCE4(rdev))
1999 /* disable the transmitter */
2000 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2001 else {
2002 /* disable the encoder and transmitter */
2003 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2004 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
2005 }
2006 break;
2007 case ENCODER_OBJECT_ID_INTERNAL_DDI:
aa961391
AD		 2008 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
99999aaa 2010 atombios_dvo_setup(encoder, ATOM_DISABLE);
aa961391
AD		 2011 break;
2012 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2013 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2014 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2015 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2016 atombios_dac_setup(encoder, ATOM_DISABLE);
8bf3aae6 2017 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
aa961391
AD		 2018 atombios_tv_setup(encoder, ATOM_DISABLE);
2019 break;
2020 }
2021
a0ae5864 2022disable_done:
f28cf339 2023 if (radeon_encoder_is_digital(encoder)) {
2cd6218c
RM		 2024 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2025 r600_hdmi_disable(encoder);
f28cf339
DA		 2026 dig = radeon_encoder->enc_priv;
2027 dig->dig_encoder = -1;
2028 }
4ce001ab
DA		 2029 radeon_encoder->active_device = 0;
2030}
2031
3e4b9982
AD		 2032/* these are handled by the primary encoders */
2033static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2034{
2035
2036}
2037
2038static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2039{
2040
2041}
2042
2043static void
2044radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2045 struct drm_display_mode *mode,
2046 struct drm_display_mode *adjusted_mode)
2047{
2048
2049}
2050
2051static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2052{
2053
2054}
2055
2056static void
2057radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2058{
2059
2060}
2061
2062static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2063 struct drm_display_mode *mode,
2064 struct drm_display_mode *adjusted_mode)
2065{
2066 return true;
2067}
2068
2069static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2070 .dpms = radeon_atom_ext_dpms,
2071 .mode_fixup = radeon_atom_ext_mode_fixup,
2072 .prepare = radeon_atom_ext_prepare,
2073 .mode_set = radeon_atom_ext_mode_set,
2074 .commit = radeon_atom_ext_commit,
2075 .disable = radeon_atom_ext_disable,
2076 /* no detect for TMDS/LVDS yet */
2077};
2078
771fe6b9
JG		 2079static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2080 .dpms = radeon_atom_encoder_dpms,
2081 .mode_fixup = radeon_atom_mode_fixup,
2082 .prepare = radeon_atom_encoder_prepare,
2083 .mode_set = radeon_atom_encoder_mode_set,
2084 .commit = radeon_atom_encoder_commit,
4ce001ab 2085 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 2086 /* no detect for TMDS/LVDS yet */
2087};
2088
2089static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2090 .dpms = radeon_atom_encoder_dpms,
2091 .mode_fixup = radeon_atom_mode_fixup,
2092 .prepare = radeon_atom_encoder_prepare,
2093 .mode_set = radeon_atom_encoder_mode_set,
2094 .commit = radeon_atom_encoder_commit,
2095 .detect = radeon_atom_dac_detect,
2096};
2097
2098void radeon_enc_destroy(struct drm_encoder *encoder)
2099{
2100 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2101 kfree(radeon_encoder->enc_priv);
2102 drm_encoder_cleanup(encoder);
2103 kfree(radeon_encoder);
2104}
2105
2106static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2107 .destroy = radeon_enc_destroy,
2108};
2109
4ce001ab
DA		 2110struct radeon_encoder_atom_dac *
2111radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2112{
affd8589
AD		 2113 struct drm_device *dev = radeon_encoder->base.dev;
2114 struct radeon_device *rdev = dev->dev_private;
4ce001ab
DA		 2115 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2116
2117 if (!dac)
2118 return NULL;
2119
affd8589 2120 dac->tv_std = radeon_atombios_get_tv_info(rdev);
4ce001ab
DA		 2121 return dac;
2122}
2123
771fe6b9
JG		 2124struct radeon_encoder_atom_dig *
2125radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2126{
5137ee94 2127 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9
JG		 2128 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2129
2130 if (!dig)
2131 return NULL;
2132
2133 /* coherent mode by default */
2134 dig->coherent_mode = true;
f28cf339 2135 dig->dig_encoder = -1;
771fe6b9 2136
5137ee94
AD		 2137 if (encoder_enum == 2)
2138 dig->linkb = true;
2139 else
2140 dig->linkb = false;
2141
771fe6b9
JG		 2142 return dig;
2143}
2144
2145void
36868bda
AD		 2146radeon_add_atom_encoder(struct drm_device *dev,
2147 uint32_t encoder_enum,
2148 uint32_t supported_device,
2149 u16 caps)
771fe6b9 2150{
dfee5614 2151 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 2152 struct drm_encoder *encoder;
2153 struct radeon_encoder *radeon_encoder;
2154
2155 /* see if we already added it */
2156 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2157 radeon_encoder = to_radeon_encoder(encoder);
5137ee94 2158 if (radeon_encoder->encoder_enum == encoder_enum) {
771fe6b9
JG		 2159 radeon_encoder->devices |= supported_device;
2160 return;
2161 }
2162
2163 }
2164
2165 /* add a new one */
2166 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2167 if (!radeon_encoder)
2168 return;
2169
2170 encoder = &radeon_encoder->base;
bcc1c2a1
AD		 2171 switch (rdev->num_crtc) {
2172 case 1:
dfee5614 2173 encoder->possible_crtcs = 0x1;
bcc1c2a1
AD		 2174 break;
2175 case 2:
2176 default:
dfee5614 2177 encoder->possible_crtcs = 0x3;
bcc1c2a1
AD		 2178 break;
2179 case 6:
2180 encoder->possible_crtcs = 0x3f;
2181 break;
2182 }
771fe6b9
JG		 2183
2184 radeon_encoder->enc_priv = NULL;
2185
5137ee94
AD		 2186 radeon_encoder->encoder_enum = encoder_enum;
2187 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
771fe6b9 2188 radeon_encoder->devices = supported_device;
c93bb85b 2189 radeon_encoder->rmx_type = RMX_OFF;
5b1714d3 2190 radeon_encoder->underscan_type = UNDERSCAN_OFF;
3e4b9982 2191 radeon_encoder->is_ext_encoder = false;
36868bda 2192 radeon_encoder->caps = caps;
771fe6b9
JG		 2193
2194 switch (radeon_encoder->encoder_id) {
2195 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2196 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2198 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2199 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2200 radeon_encoder->rmx_type = RMX_FULL;
2201 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2202 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2203 } else {
2204 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2205 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2206 }
2207 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2208 break;
2209 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2210 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
affd8589 2211 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 2212 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2213 break;
2214 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2215 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2216 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2217 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 2218 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 2219 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2220 break;
2221 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2222 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2223 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2225 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 2228 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2229 radeon_encoder->rmx_type = RMX_FULL;
2230 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2231 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
3e4b9982
AD		 2232 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2233 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2234 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
60d15f55
AD		 2235 } else {
2236 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2237 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2238 }
771fe6b9
JG		 2239 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2240 break;
3e4b9982
AD		 2241 case ENCODER_OBJECT_ID_SI170B:
2242 case ENCODER_OBJECT_ID_CH7303:
2243 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2244 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2245 case ENCODER_OBJECT_ID_TITFP513:
2246 case ENCODER_OBJECT_ID_VT1623:
2247 case ENCODER_OBJECT_ID_HDMI_SI1930:
bf982ebf
AD		 2248 case ENCODER_OBJECT_ID_TRAVIS:
2249 case ENCODER_OBJECT_ID_NUTMEG:
3e4b9982
AD		 2250 /* these are handled by the primary encoders */
2251 radeon_encoder->is_ext_encoder = true;
2252 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2253 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2254 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2255 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2256 else
2257 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2258 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2259 break;
771fe6b9
JG		 2260 }
2261}
Linux kernel - Deliverables
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