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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "drm_crtc_helper.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
31 | ||
32 | extern int atom_debug; | |
33 | ||
5a9bcacc AD |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
36 | struct drm_display_mode *mode); | |
37 | ||
1f3b6a45 DA |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { | |
40 | struct drm_device *dev = encoder->dev; | |
41 | struct radeon_device *rdev = dev->dev_private; | |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
43 | struct drm_encoder *clone_encoder; | |
44 | uint32_t index_mask = 0; | |
45 | int count; | |
46 | ||
47 | /* DIG routing gets problematic */ | |
48 | if (rdev->family >= CHIP_R600) | |
49 | return index_mask; | |
50 | /* LVDS/TV are too wacky */ | |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
52 | return index_mask; | |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ | |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
55 | return index_mask; | |
bcc1c2a1 | 56 | |
1f3b6a45 DA |
57 | count = -1; |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { | |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); | |
60 | count++; | |
61 | ||
62 | if (clone_encoder == encoder) | |
63 | continue; | |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
65 | continue; | |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
67 | continue; | |
68 | else | |
69 | index_mask |= (1 << count); | |
70 | } | |
71 | return index_mask; | |
72 | } | |
73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) | |
75 | { | |
76 | struct drm_encoder *encoder; | |
77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); | |
80 | } | |
81 | } | |
82 | ||
771fe6b9 JG |
83 | uint32_t |
84 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) | |
85 | { | |
86 | struct radeon_device *rdev = dev->dev_private; | |
87 | uint32_t ret = 0; | |
88 | ||
89 | switch (supported_device) { | |
90 | case ATOM_DEVICE_CRT1_SUPPORT: | |
91 | case ATOM_DEVICE_TV1_SUPPORT: | |
92 | case ATOM_DEVICE_TV2_SUPPORT: | |
93 | case ATOM_DEVICE_CRT2_SUPPORT: | |
94 | case ATOM_DEVICE_CV_SUPPORT: | |
95 | switch (dac) { | |
96 | case 1: /* dac a */ | |
97 | if ((rdev->family == CHIP_RS300) || | |
98 | (rdev->family == CHIP_RS400) || | |
99 | (rdev->family == CHIP_RS480)) | |
100 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | |
101 | else if (ASIC_IS_AVIVO(rdev)) | |
102 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; | |
103 | else | |
104 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; | |
105 | break; | |
106 | case 2: /* dac b */ | |
107 | if (ASIC_IS_AVIVO(rdev)) | |
108 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; | |
109 | else { | |
110 | /*if (rdev->family == CHIP_R200) | |
111 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
112 | else*/ | |
113 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | |
114 | } | |
115 | break; | |
116 | case 3: /* external dac */ | |
117 | if (ASIC_IS_AVIVO(rdev)) | |
118 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | |
119 | else | |
120 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
121 | break; | |
122 | } | |
123 | break; | |
124 | case ATOM_DEVICE_LCD1_SUPPORT: | |
125 | if (ASIC_IS_AVIVO(rdev)) | |
126 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | |
127 | else | |
128 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; | |
129 | break; | |
130 | case ATOM_DEVICE_DFP1_SUPPORT: | |
131 | if ((rdev->family == CHIP_RS300) || | |
132 | (rdev->family == CHIP_RS400) || | |
133 | (rdev->family == CHIP_RS480)) | |
134 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
135 | else if (ASIC_IS_AVIVO(rdev)) | |
136 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; | |
137 | else | |
138 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; | |
139 | break; | |
140 | case ATOM_DEVICE_LCD2_SUPPORT: | |
141 | case ATOM_DEVICE_DFP2_SUPPORT: | |
142 | if ((rdev->family == CHIP_RS600) || | |
143 | (rdev->family == CHIP_RS690) || | |
144 | (rdev->family == CHIP_RS740)) | |
145 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; | |
146 | else if (ASIC_IS_AVIVO(rdev)) | |
147 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | |
148 | else | |
149 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | |
150 | break; | |
151 | case ATOM_DEVICE_DFP3_SUPPORT: | |
152 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | |
153 | break; | |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
f28cf339 DA |
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
160 | { | |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
162 | switch (radeon_encoder->encoder_id) { | |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
174 | return true; | |
175 | default: | |
176 | return false; | |
177 | } | |
178 | } | |
771fe6b9 JG |
179 | void |
180 | radeon_link_encoder_connector(struct drm_device *dev) | |
181 | { | |
182 | struct drm_connector *connector; | |
183 | struct radeon_connector *radeon_connector; | |
184 | struct drm_encoder *encoder; | |
185 | struct radeon_encoder *radeon_encoder; | |
186 | ||
187 | /* walk the list and link encoders to connectors */ | |
188 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
189 | radeon_connector = to_radeon_connector(connector); | |
190 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
191 | radeon_encoder = to_radeon_encoder(encoder); | |
192 | if (radeon_encoder->devices & radeon_connector->devices) | |
193 | drm_mode_connector_attach_encoder(connector, encoder); | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
4ce001ab DA |
198 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
199 | { | |
200 | struct drm_device *dev = encoder->dev; | |
201 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
202 | struct drm_connector *connector; | |
203 | ||
204 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
205 | if (connector->encoder == encoder) { | |
206 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
207 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; | |
f641e51e DA |
208 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
209 | radeon_encoder->active_device, radeon_encoder->devices, | |
210 | radeon_connector->devices, encoder->encoder_type); | |
4ce001ab DA |
211 | } |
212 | } | |
213 | } | |
214 | ||
771fe6b9 JG |
215 | static struct drm_connector * |
216 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) | |
217 | { | |
218 | struct drm_device *dev = encoder->dev; | |
219 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
220 | struct drm_connector *connector; | |
221 | struct radeon_connector *radeon_connector; | |
222 | ||
223 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
224 | radeon_connector = to_radeon_connector(connector); | |
43c33ed8 | 225 | if (radeon_encoder->active_device & radeon_connector->devices) |
771fe6b9 JG |
226 | return connector; |
227 | } | |
228 | return NULL; | |
229 | } | |
230 | ||
9ae47867 AD |
231 | static struct radeon_connector_atom_dig * |
232 | radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) | |
233 | { | |
234 | struct drm_device *dev = encoder->dev; | |
235 | struct radeon_device *rdev = dev->dev_private; | |
236 | struct drm_connector *connector; | |
237 | struct radeon_connector *radeon_connector; | |
238 | struct radeon_connector_atom_dig *dig_connector; | |
239 | ||
240 | if (!rdev->is_atom_bios) | |
241 | return NULL; | |
242 | ||
243 | connector = radeon_get_connector_for_encoder(encoder); | |
244 | if (!connector) | |
245 | return NULL; | |
246 | ||
247 | radeon_connector = to_radeon_connector(connector); | |
248 | ||
249 | if (!radeon_connector->con_priv) | |
250 | return NULL; | |
251 | ||
252 | dig_connector = radeon_connector->con_priv; | |
253 | ||
254 | return dig_connector; | |
255 | } | |
256 | ||
3515387b AD |
257 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
258 | struct drm_display_mode *adjusted_mode) | |
259 | { | |
260 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
261 | struct drm_device *dev = encoder->dev; | |
262 | struct radeon_device *rdev = dev->dev_private; | |
263 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
264 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; | |
265 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; | |
266 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; | |
267 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; | |
268 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; | |
269 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; | |
270 | ||
271 | adjusted_mode->clock = native_mode->clock; | |
272 | adjusted_mode->flags = native_mode->flags; | |
273 | ||
274 | if (ASIC_IS_AVIVO(rdev)) { | |
275 | adjusted_mode->hdisplay = native_mode->hdisplay; | |
276 | adjusted_mode->vdisplay = native_mode->vdisplay; | |
277 | } | |
278 | ||
279 | adjusted_mode->htotal = native_mode->hdisplay + hblank; | |
280 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; | |
281 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; | |
282 | ||
283 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; | |
284 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; | |
285 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; | |
286 | ||
287 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
288 | ||
289 | if (ASIC_IS_AVIVO(rdev)) { | |
290 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; | |
291 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; | |
292 | } | |
293 | ||
294 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; | |
295 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; | |
296 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; | |
297 | ||
298 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; | |
299 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; | |
300 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; | |
301 | ||
302 | } | |
303 | ||
771fe6b9 JG |
304 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
305 | struct drm_display_mode *mode, | |
306 | struct drm_display_mode *adjusted_mode) | |
307 | { | |
771fe6b9 | 308 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
5a9bcacc AD |
309 | struct drm_device *dev = encoder->dev; |
310 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 311 | |
c913e23a RM |
312 | /* adjust pm to upcoming mode change */ |
313 | radeon_pm_compute_clocks(rdev); | |
314 | ||
8c2a6d73 AD |
315 | /* set the active encoder to connector routing */ |
316 | radeon_encoder_set_active_device(encoder); | |
771fe6b9 JG |
317 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
318 | ||
771fe6b9 JG |
319 | /* hw bug */ |
320 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
321 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
322 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
323 | ||
80297e87 | 324 | /* get the native mode for LVDS */ |
3515387b AD |
325 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
326 | radeon_panel_mode_fixup(encoder, adjusted_mode); | |
80297e87 AD |
327 | |
328 | /* get the native mode for TV */ | |
ceefedd8 | 329 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
5a9bcacc AD |
330 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
331 | if (tv_dac) { | |
332 | if (tv_dac->tv_std == TV_STD_NTSC || | |
333 | tv_dac->tv_std == TV_STD_NTSC_J || | |
334 | tv_dac->tv_std == TV_STD_PAL_M) | |
335 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
336 | else | |
337 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
338 | } | |
339 | } | |
340 | ||
5801ead6 | 341 | if (ASIC_IS_DCE3(rdev) && |
9f998ad7 | 342 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { |
5801ead6 AD |
343 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
344 | radeon_dp_set_link_config(connector, mode); | |
345 | } | |
346 | ||
771fe6b9 JG |
347 | return true; |
348 | } | |
349 | ||
350 | static void | |
351 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
352 | { | |
353 | struct drm_device *dev = encoder->dev; | |
354 | struct radeon_device *rdev = dev->dev_private; | |
355 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
356 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
affd8589 | 357 | int index = 0; |
445282db | 358 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 359 | |
771fe6b9 JG |
360 | memset(&args, 0, sizeof(args)); |
361 | ||
362 | switch (radeon_encoder->encoder_id) { | |
363 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
364 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
365 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
771fe6b9 JG |
366 | break; |
367 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
368 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
369 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
771fe6b9 JG |
370 | break; |
371 | } | |
372 | ||
373 | args.ucAction = action; | |
374 | ||
4ce001ab | 375 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
771fe6b9 | 376 | args.ucDacStandard = ATOM_DAC1_PS2; |
4ce001ab | 377 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
378 | args.ucDacStandard = ATOM_DAC1_CV; |
379 | else { | |
affd8589 | 380 | switch (dac_info->tv_std) { |
771fe6b9 JG |
381 | case TV_STD_PAL: |
382 | case TV_STD_PAL_M: | |
383 | case TV_STD_SCART_PAL: | |
384 | case TV_STD_SECAM: | |
385 | case TV_STD_PAL_CN: | |
386 | args.ucDacStandard = ATOM_DAC1_PAL; | |
387 | break; | |
388 | case TV_STD_NTSC: | |
389 | case TV_STD_NTSC_J: | |
390 | case TV_STD_PAL_60: | |
391 | default: | |
392 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
393 | break; | |
394 | } | |
395 | } | |
396 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
397 | ||
398 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
399 | ||
400 | } | |
401 | ||
402 | static void | |
403 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
404 | { | |
405 | struct drm_device *dev = encoder->dev; | |
406 | struct radeon_device *rdev = dev->dev_private; | |
407 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
408 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
409 | int index = 0; | |
445282db | 410 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 411 | |
771fe6b9 JG |
412 | memset(&args, 0, sizeof(args)); |
413 | ||
414 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
415 | ||
416 | args.sTVEncoder.ucAction = action; | |
417 | ||
4ce001ab | 418 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
419 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
420 | else { | |
affd8589 | 421 | switch (dac_info->tv_std) { |
771fe6b9 JG |
422 | case TV_STD_NTSC: |
423 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
424 | break; | |
425 | case TV_STD_PAL: | |
426 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
427 | break; | |
428 | case TV_STD_PAL_M: | |
429 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
430 | break; | |
431 | case TV_STD_PAL_60: | |
432 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
433 | break; | |
434 | case TV_STD_NTSC_J: | |
435 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
436 | break; | |
437 | case TV_STD_SCART_PAL: | |
438 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
439 | break; | |
440 | case TV_STD_SECAM: | |
441 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
442 | break; | |
443 | case TV_STD_PAL_CN: | |
444 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
445 | break; | |
446 | default: | |
447 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
448 | break; | |
449 | } | |
450 | } | |
451 | ||
452 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
453 | ||
454 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
455 | ||
456 | } | |
457 | ||
458 | void | |
459 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) | |
460 | { | |
461 | struct drm_device *dev = encoder->dev; | |
462 | struct radeon_device *rdev = dev->dev_private; | |
463 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
464 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; | |
465 | int index = 0; | |
466 | ||
467 | memset(&args, 0, sizeof(args)); | |
468 | ||
469 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
470 | ||
471 | args.sXTmdsEncoder.ucEnable = action; | |
472 | ||
473 | if (radeon_encoder->pixel_clock > 165000) | |
474 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; | |
475 | ||
476 | /*if (pScrn->rgbBits == 8)*/ | |
477 | args.sXTmdsEncoder.ucMisc |= (1 << 1); | |
478 | ||
479 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
480 | ||
481 | } | |
482 | ||
483 | static void | |
484 | atombios_ddia_setup(struct drm_encoder *encoder, int action) | |
485 | { | |
486 | struct drm_device *dev = encoder->dev; | |
487 | struct radeon_device *rdev = dev->dev_private; | |
488 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
489 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; | |
490 | int index = 0; | |
491 | ||
492 | memset(&args, 0, sizeof(args)); | |
493 | ||
494 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
495 | ||
496 | args.sDVOEncoder.ucAction = action; | |
497 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
498 | ||
499 | if (radeon_encoder->pixel_clock > 165000) | |
500 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; | |
501 | ||
502 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
503 | ||
504 | } | |
505 | ||
506 | union lvds_encoder_control { | |
507 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
508 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
509 | }; | |
510 | ||
32f48ffe | 511 | void |
771fe6b9 JG |
512 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
513 | { | |
514 | struct drm_device *dev = encoder->dev; | |
515 | struct radeon_device *rdev = dev->dev_private; | |
516 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
517 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
518 | struct radeon_connector_atom_dig *dig_connector = | |
519 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
771fe6b9 JG |
520 | union lvds_encoder_control args; |
521 | int index = 0; | |
dafc3bd5 | 522 | int hdmi_detected = 0; |
771fe6b9 | 523 | uint8_t frev, crev; |
771fe6b9 | 524 | |
9ae47867 | 525 | if (!dig || !dig_connector) |
771fe6b9 JG |
526 | return; |
527 | ||
9ae47867 | 528 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
dafc3bd5 CK |
529 | hdmi_detected = 1; |
530 | ||
771fe6b9 JG |
531 | memset(&args, 0, sizeof(args)); |
532 | ||
533 | switch (radeon_encoder->encoder_id) { | |
534 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
535 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
536 | break; | |
537 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
538 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
539 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
540 | break; | |
541 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
542 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
543 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
544 | else | |
545 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
546 | break; | |
547 | } | |
548 | ||
a084e6ee AD |
549 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
550 | return; | |
771fe6b9 JG |
551 | |
552 | switch (frev) { | |
553 | case 1: | |
554 | case 2: | |
555 | switch (crev) { | |
556 | case 1: | |
557 | args.v1.ucMisc = 0; | |
558 | args.v1.ucAction = action; | |
dafc3bd5 | 559 | if (hdmi_detected) |
771fe6b9 JG |
560 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
561 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
562 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
edc664e3 | 563 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 564 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
edc664e3 | 565 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 JG |
566 | args.v1.ucMisc |= (1 << 1); |
567 | } else { | |
568 | if (dig_connector->linkb) | |
569 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
570 | if (radeon_encoder->pixel_clock > 165000) | |
571 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
572 | /*if (pScrn->rgbBits == 8) */ | |
573 | args.v1.ucMisc |= (1 << 1); | |
574 | } | |
575 | break; | |
576 | case 2: | |
577 | case 3: | |
578 | args.v2.ucMisc = 0; | |
579 | args.v2.ucAction = action; | |
580 | if (crev == 3) { | |
581 | if (dig->coherent_mode) | |
582 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
583 | } | |
dafc3bd5 | 584 | if (hdmi_detected) |
771fe6b9 JG |
585 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
586 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
587 | args.v2.ucTruncate = 0; | |
588 | args.v2.ucSpatial = 0; | |
589 | args.v2.ucTemporal = 0; | |
590 | args.v2.ucFRC = 0; | |
591 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
edc664e3 | 592 | if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 593 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
edc664e3 | 594 | if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { |
771fe6b9 | 595 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
edc664e3 | 596 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 JG |
597 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
598 | } | |
edc664e3 | 599 | if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { |
771fe6b9 | 600 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
edc664e3 | 601 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 | 602 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
edc664e3 | 603 | if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
771fe6b9 JG |
604 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
605 | } | |
606 | } else { | |
607 | if (dig_connector->linkb) | |
608 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
609 | if (radeon_encoder->pixel_clock > 165000) | |
610 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
611 | } | |
612 | break; | |
613 | default: | |
614 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
615 | break; | |
616 | } | |
617 | break; | |
618 | default: | |
619 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
620 | break; | |
621 | } | |
622 | ||
623 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
624 | } |
625 | ||
626 | int | |
627 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
628 | { | |
629 | struct drm_connector *connector; | |
630 | struct radeon_connector *radeon_connector; | |
9ae47867 | 631 | struct radeon_connector_atom_dig *dig_connector; |
771fe6b9 JG |
632 | |
633 | connector = radeon_get_connector_for_encoder(encoder); | |
634 | if (!connector) | |
635 | return 0; | |
636 | ||
637 | radeon_connector = to_radeon_connector(connector); | |
638 | ||
639 | switch (connector->connector_type) { | |
640 | case DRM_MODE_CONNECTOR_DVII: | |
705af9c7 | 641 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
0294cf4f | 642 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
643 | return ATOM_ENCODER_MODE_HDMI; |
644 | else if (radeon_connector->use_digital) | |
645 | return ATOM_ENCODER_MODE_DVI; | |
646 | else | |
647 | return ATOM_ENCODER_MODE_CRT; | |
648 | break; | |
649 | case DRM_MODE_CONNECTOR_DVID: | |
650 | case DRM_MODE_CONNECTOR_HDMIA: | |
771fe6b9 | 651 | default: |
0294cf4f | 652 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
771fe6b9 JG |
653 | return ATOM_ENCODER_MODE_HDMI; |
654 | else | |
655 | return ATOM_ENCODER_MODE_DVI; | |
656 | break; | |
657 | case DRM_MODE_CONNECTOR_LVDS: | |
658 | return ATOM_ENCODER_MODE_LVDS; | |
659 | break; | |
660 | case DRM_MODE_CONNECTOR_DisplayPort: | |
196c58d2 | 661 | case DRM_MODE_CONNECTOR_eDP: |
9ae47867 AD |
662 | dig_connector = radeon_connector->con_priv; |
663 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
664 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | |
f92a8b67 AD |
665 | return ATOM_ENCODER_MODE_DP; |
666 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) | |
771fe6b9 JG |
667 | return ATOM_ENCODER_MODE_HDMI; |
668 | else | |
669 | return ATOM_ENCODER_MODE_DVI; | |
670 | break; | |
a5899fcc AD |
671 | case DRM_MODE_CONNECTOR_DVIA: |
672 | case DRM_MODE_CONNECTOR_VGA: | |
771fe6b9 JG |
673 | return ATOM_ENCODER_MODE_CRT; |
674 | break; | |
a5899fcc AD |
675 | case DRM_MODE_CONNECTOR_Composite: |
676 | case DRM_MODE_CONNECTOR_SVIDEO: | |
677 | case DRM_MODE_CONNECTOR_9PinDIN: | |
771fe6b9 JG |
678 | /* fix me */ |
679 | return ATOM_ENCODER_MODE_TV; | |
680 | /*return ATOM_ENCODER_MODE_CV;*/ | |
681 | break; | |
682 | } | |
683 | } | |
684 | ||
1a66c95a AD |
685 | /* |
686 | * DIG Encoder/Transmitter Setup | |
687 | * | |
688 | * DCE 3.0/3.1 | |
689 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
690 | * Supports up to 3 digital outputs | |
691 | * - 2 DIG encoder blocks. | |
692 | * DIG1 can drive UNIPHY link A or link B | |
693 | * DIG2 can drive UNIPHY link B or LVTMA | |
694 | * | |
695 | * DCE 3.2 | |
696 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
697 | * Supports up to 5 digital outputs | |
698 | * - 2 DIG encoder blocks. | |
699 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
700 | * | |
bcc1c2a1 AD |
701 | * DCE 4.0 |
702 | * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). | |
703 | * Supports up to 6 digital outputs | |
704 | * - 6 DIG encoder blocks. | |
705 | * - DIG to PHY mapping is hardcoded | |
706 | * DIG1 drives UNIPHY0 link A, A+B | |
707 | * DIG2 drives UNIPHY0 link B | |
708 | * DIG3 drives UNIPHY1 link A, A+B | |
709 | * DIG4 drives UNIPHY1 link B | |
710 | * DIG5 drives UNIPHY2 link A, A+B | |
711 | * DIG6 drives UNIPHY2 link B | |
712 | * | |
1a66c95a AD |
713 | * Routing |
714 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
715 | * Examples: | |
716 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
717 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
718 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
719 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
720 | */ | |
bcc1c2a1 AD |
721 | |
722 | union dig_encoder_control { | |
723 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | |
724 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | |
725 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | |
726 | }; | |
727 | ||
728 | void | |
771fe6b9 JG |
729 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
730 | { | |
731 | struct drm_device *dev = encoder->dev; | |
732 | struct radeon_device *rdev = dev->dev_private; | |
733 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
734 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
735 | struct radeon_connector_atom_dig *dig_connector = | |
736 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
bcc1c2a1 | 737 | union dig_encoder_control args; |
d9c9fe36 | 738 | int index = 0; |
771fe6b9 | 739 | uint8_t frev, crev; |
771fe6b9 | 740 | |
9ae47867 | 741 | if (!dig || !dig_connector) |
771fe6b9 JG |
742 | return; |
743 | ||
771fe6b9 JG |
744 | memset(&args, 0, sizeof(args)); |
745 | ||
bcc1c2a1 AD |
746 | if (ASIC_IS_DCE4(rdev)) |
747 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); | |
748 | else { | |
749 | if (dig->dig_encoder) | |
750 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
751 | else | |
752 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
753 | } | |
771fe6b9 | 754 | |
a084e6ee AD |
755 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
756 | return; | |
771fe6b9 | 757 | |
bcc1c2a1 AD |
758 | args.v1.ucAction = action; |
759 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
760 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
771fe6b9 | 761 | |
bcc1c2a1 AD |
762 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
763 | if (dig_connector->dp_clock == 270000) | |
764 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
765 | args.v1.ucLaneNum = dig_connector->dp_lane_count; | |
766 | } else if (radeon_encoder->pixel_clock > 165000) | |
767 | args.v1.ucLaneNum = 8; | |
768 | else | |
769 | args.v1.ucLaneNum = 4; | |
770 | ||
771 | if (ASIC_IS_DCE4(rdev)) { | |
772 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | |
773 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
774 | } else { | |
771fe6b9 JG |
775 | switch (radeon_encoder->encoder_id) { |
776 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
bcc1c2a1 | 777 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
771fe6b9 JG |
778 | break; |
779 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
bcc1c2a1 AD |
780 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
781 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
771fe6b9 JG |
782 | break; |
783 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
bcc1c2a1 | 784 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
771fe6b9 JG |
785 | break; |
786 | } | |
bcc1c2a1 AD |
787 | if (dig_connector->linkb) |
788 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; | |
789 | else | |
790 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
771fe6b9 JG |
791 | } |
792 | ||
771fe6b9 JG |
793 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
794 | ||
795 | } | |
796 | ||
797 | union dig_transmitter_control { | |
798 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
799 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
bcc1c2a1 | 800 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
771fe6b9 JG |
801 | }; |
802 | ||
5801ead6 | 803 | void |
1a66c95a | 804 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
771fe6b9 JG |
805 | { |
806 | struct drm_device *dev = encoder->dev; | |
807 | struct radeon_device *rdev = dev->dev_private; | |
808 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 AD |
809 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
810 | struct radeon_connector_atom_dig *dig_connector = | |
811 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
812 | struct drm_connector *connector; | |
813 | struct radeon_connector *radeon_connector; | |
771fe6b9 | 814 | union dig_transmitter_control args; |
d9c9fe36 | 815 | int index = 0; |
771fe6b9 | 816 | uint8_t frev, crev; |
f92a8b67 | 817 | bool is_dp = false; |
bcc1c2a1 | 818 | int pll_id = 0; |
771fe6b9 | 819 | |
9ae47867 | 820 | if (!dig || !dig_connector) |
771fe6b9 JG |
821 | return; |
822 | ||
9ae47867 | 823 | connector = radeon_get_connector_for_encoder(encoder); |
771fe6b9 JG |
824 | radeon_connector = to_radeon_connector(connector); |
825 | ||
f92a8b67 AD |
826 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
827 | is_dp = true; | |
828 | ||
771fe6b9 JG |
829 | memset(&args, 0, sizeof(args)); |
830 | ||
bcc1c2a1 | 831 | if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) |
771fe6b9 JG |
832 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
833 | else { | |
834 | switch (radeon_encoder->encoder_id) { | |
835 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
836 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); | |
837 | break; | |
838 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
839 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); | |
840 | break; | |
841 | } | |
842 | } | |
843 | ||
a084e6ee AD |
844 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
845 | return; | |
771fe6b9 JG |
846 | |
847 | args.v1.ucAction = action; | |
f95a9f0b AD |
848 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
849 | args.v1.usInitInfo = radeon_connector->connector_object_id; | |
1a66c95a AD |
850 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
851 | args.v1.asMode.ucLaneSel = lane_num; | |
852 | args.v1.asMode.ucLaneSet = lane_set; | |
f95a9f0b | 853 | } else { |
f92a8b67 AD |
854 | if (is_dp) |
855 | args.v1.usPixelClock = | |
5801ead6 | 856 | cpu_to_le16(dig_connector->dp_clock / 10); |
f92a8b67 | 857 | else if (radeon_encoder->pixel_clock > 165000) |
f95a9f0b AD |
858 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
859 | else | |
860 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
861 | } | |
bcc1c2a1 AD |
862 | if (ASIC_IS_DCE4(rdev)) { |
863 | if (is_dp) | |
864 | args.v3.ucLaneNum = dig_connector->dp_lane_count; | |
865 | else if (radeon_encoder->pixel_clock > 165000) | |
866 | args.v3.ucLaneNum = 8; | |
867 | else | |
868 | args.v3.ucLaneNum = 4; | |
869 | ||
870 | if (dig_connector->linkb) { | |
871 | args.v3.acConfig.ucLinkSel = 1; | |
872 | args.v3.acConfig.ucEncoderSel = 1; | |
873 | } | |
874 | ||
875 | /* Select the PLL for the PHY | |
876 | * DP PHY should be clocked from external src if there is | |
877 | * one. | |
878 | */ | |
879 | if (encoder->crtc) { | |
880 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
881 | pll_id = radeon_crtc->pll_id; | |
882 | } | |
883 | if (is_dp && rdev->clock.dp_extclk) | |
884 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | |
885 | else | |
886 | args.v3.acConfig.ucRefClkSource = pll_id; | |
887 | ||
888 | switch (radeon_encoder->encoder_id) { | |
889 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
890 | args.v3.acConfig.ucTransmitterSel = 0; | |
bcc1c2a1 AD |
891 | break; |
892 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
893 | args.v3.acConfig.ucTransmitterSel = 1; | |
bcc1c2a1 AD |
894 | break; |
895 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
896 | args.v3.acConfig.ucTransmitterSel = 2; | |
bcc1c2a1 AD |
897 | break; |
898 | } | |
899 | ||
900 | if (is_dp) | |
901 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
902 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
903 | if (dig->coherent_mode) | |
904 | args.v3.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
905 | if (radeon_encoder->pixel_clock > 165000) |
906 | args.v3.acConfig.fDualLinkConnector = 1; | |
bcc1c2a1 AD |
907 | } |
908 | } else if (ASIC_IS_DCE32(rdev)) { | |
d9c9fe36 | 909 | args.v2.acConfig.ucEncoderSel = dig->dig_encoder; |
1a66c95a AD |
910 | if (dig_connector->linkb) |
911 | args.v2.acConfig.ucLinkSel = 1; | |
771fe6b9 JG |
912 | |
913 | switch (radeon_encoder->encoder_id) { | |
914 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
915 | args.v2.acConfig.ucTransmitterSel = 0; | |
771fe6b9 JG |
916 | break; |
917 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
918 | args.v2.acConfig.ucTransmitterSel = 1; | |
771fe6b9 JG |
919 | break; |
920 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
921 | args.v2.acConfig.ucTransmitterSel = 2; | |
771fe6b9 JG |
922 | break; |
923 | } | |
924 | ||
f92a8b67 AD |
925 | if (is_dp) |
926 | args.v2.acConfig.fCoherentMode = 1; | |
927 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
928 | if (dig->coherent_mode) |
929 | args.v2.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
930 | if (radeon_encoder->pixel_clock > 165000) |
931 | args.v2.acConfig.fDualLinkConnector = 1; | |
771fe6b9 JG |
932 | } |
933 | } else { | |
934 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; | |
771fe6b9 | 935 | |
f28cf339 DA |
936 | if (dig->dig_encoder) |
937 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
938 | else | |
939 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
940 | ||
d9c9fe36 AD |
941 | if ((rdev->flags & RADEON_IS_IGP) && |
942 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | |
943 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { | |
944 | if (dig_connector->igp_lane_info & 0x1) | |
945 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | |
946 | else if (dig_connector->igp_lane_info & 0x2) | |
947 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | |
948 | else if (dig_connector->igp_lane_info & 0x4) | |
949 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | |
950 | else if (dig_connector->igp_lane_info & 0x8) | |
951 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | |
952 | } else { | |
953 | if (dig_connector->igp_lane_info & 0x3) | |
954 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | |
955 | else if (dig_connector->igp_lane_info & 0xc) | |
956 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | |
771fe6b9 | 957 | } |
771fe6b9 JG |
958 | } |
959 | ||
1a66c95a AD |
960 | if (dig_connector->linkb) |
961 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; | |
962 | else | |
963 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
964 | ||
f92a8b67 AD |
965 | if (is_dp) |
966 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
967 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
968 | if (dig->coherent_mode) |
969 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
d9c9fe36 AD |
970 | if (radeon_encoder->pixel_clock > 165000) |
971 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; | |
771fe6b9 JG |
972 | } |
973 | } | |
974 | ||
975 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
976 | } |
977 | ||
771fe6b9 JG |
978 | static void |
979 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
980 | { | |
981 | struct drm_device *dev = encoder->dev; | |
982 | struct radeon_device *rdev = dev->dev_private; | |
983 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
984 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
985 | ENABLE_YUV_PS_ALLOCATION args; | |
986 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
987 | uint32_t temp, reg; | |
988 | ||
989 | memset(&args, 0, sizeof(args)); | |
990 | ||
991 | if (rdev->family >= CHIP_R600) | |
992 | reg = R600_BIOS_3_SCRATCH; | |
993 | else | |
994 | reg = RADEON_BIOS_3_SCRATCH; | |
995 | ||
996 | /* XXX: fix up scratch reg handling */ | |
997 | temp = RREG32(reg); | |
4ce001ab | 998 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
999 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1000 | (radeon_crtc->crtc_id << 18))); | |
4ce001ab | 1001 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1002 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1003 | else | |
1004 | WREG32(reg, 0); | |
1005 | ||
1006 | if (enable) | |
1007 | args.ucEnable = ATOM_ENABLE; | |
1008 | args.ucCRTC = radeon_crtc->crtc_id; | |
1009 | ||
1010 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1011 | ||
1012 | WREG32(reg, temp); | |
1013 | } | |
1014 | ||
771fe6b9 JG |
1015 | static void |
1016 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
1017 | { | |
1018 | struct drm_device *dev = encoder->dev; | |
1019 | struct radeon_device *rdev = dev->dev_private; | |
1020 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1021 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
1022 | int index = 0; | |
1023 | bool is_dig = false; | |
1024 | ||
1025 | memset(&args, 0, sizeof(args)); | |
1026 | ||
f641e51e DA |
1027 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1028 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | |
1029 | radeon_encoder->active_device); | |
771fe6b9 JG |
1030 | switch (radeon_encoder->encoder_id) { |
1031 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1032 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1033 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
1034 | break; | |
1035 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1036 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1037 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1038 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1039 | is_dig = true; | |
1040 | break; | |
1041 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1042 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1043 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1044 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1045 | break; | |
1046 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1047 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1048 | break; | |
1049 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1050 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1051 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1052 | else | |
1053 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
1054 | break; | |
1055 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1056 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
8c2a6d73 | 1057 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1058 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 1059 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1060 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1061 | else | |
1062 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
1063 | break; | |
1064 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1065 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
8c2a6d73 | 1066 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1067 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 1068 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1069 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1070 | else | |
1071 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
1072 | break; | |
1073 | } | |
1074 | ||
1075 | if (is_dig) { | |
1076 | switch (mode) { | |
1077 | case DRM_MODE_DPMS_ON: | |
fb668c2f | 1078 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
58682f10 | 1079 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
fb668c2f | 1080 | |
58682f10 | 1081 | dp_link_train(encoder, connector); |
fb668c2f AD |
1082 | if (ASIC_IS_DCE4(rdev)) |
1083 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); | |
58682f10 | 1084 | } |
fb668c2f AD |
1085 | if (!ASIC_IS_DCE4(rdev)) |
1086 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | |
771fe6b9 JG |
1087 | break; |
1088 | case DRM_MODE_DPMS_STANDBY: | |
1089 | case DRM_MODE_DPMS_SUSPEND: | |
1090 | case DRM_MODE_DPMS_OFF: | |
fb668c2f AD |
1091 | if (!ASIC_IS_DCE4(rdev)) |
1092 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | |
1093 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { | |
1094 | if (ASIC_IS_DCE4(rdev)) | |
1095 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); | |
1096 | } | |
771fe6b9 JG |
1097 | break; |
1098 | } | |
1099 | } else { | |
1100 | switch (mode) { | |
1101 | case DRM_MODE_DPMS_ON: | |
1102 | args.ucAction = ATOM_ENABLE; | |
1103 | break; | |
1104 | case DRM_MODE_DPMS_STANDBY: | |
1105 | case DRM_MODE_DPMS_SUSPEND: | |
1106 | case DRM_MODE_DPMS_OFF: | |
1107 | args.ucAction = ATOM_DISABLE; | |
1108 | break; | |
1109 | } | |
1110 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1111 | } | |
1112 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); | |
c913e23a RM |
1113 | |
1114 | /* adjust pm to dpms change */ | |
1115 | radeon_pm_compute_clocks(rdev); | |
771fe6b9 JG |
1116 | } |
1117 | ||
9ae47867 | 1118 | union crtc_source_param { |
771fe6b9 JG |
1119 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1120 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1121 | }; | |
1122 | ||
1123 | static void | |
1124 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1125 | { | |
1126 | struct drm_device *dev = encoder->dev; | |
1127 | struct radeon_device *rdev = dev->dev_private; | |
1128 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1129 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
9ae47867 | 1130 | union crtc_source_param args; |
771fe6b9 JG |
1131 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1132 | uint8_t frev, crev; | |
f28cf339 | 1133 | struct radeon_encoder_atom_dig *dig; |
771fe6b9 JG |
1134 | |
1135 | memset(&args, 0, sizeof(args)); | |
1136 | ||
a084e6ee AD |
1137 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1138 | return; | |
771fe6b9 JG |
1139 | |
1140 | switch (frev) { | |
1141 | case 1: | |
1142 | switch (crev) { | |
1143 | case 1: | |
1144 | default: | |
1145 | if (ASIC_IS_AVIVO(rdev)) | |
1146 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1147 | else { | |
1148 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1149 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1150 | } else { | |
1151 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1152 | } | |
1153 | } | |
1154 | switch (radeon_encoder->encoder_id) { | |
1155 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1156 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1157 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1158 | break; | |
1159 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1160 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1161 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1162 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1163 | else | |
1164 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1165 | break; | |
1166 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1167 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1169 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1170 | break; | |
1171 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1172 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
4ce001ab | 1173 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1174 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1175 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1176 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1177 | else | |
1178 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1179 | break; | |
1180 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1181 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1182 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1183 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1184 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1185 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1186 | else | |
1187 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1188 | break; | |
1189 | } | |
1190 | break; | |
1191 | case 2: | |
1192 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1193 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1194 | switch (radeon_encoder->encoder_id) { | |
1195 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1196 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1197 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
f28cf339 DA |
1198 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1199 | dig = radeon_encoder->enc_priv; | |
bcc1c2a1 AD |
1200 | switch (dig->dig_encoder) { |
1201 | case 0: | |
f28cf339 | 1202 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
bcc1c2a1 AD |
1203 | break; |
1204 | case 1: | |
1205 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1206 | break; | |
1207 | case 2: | |
1208 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
1209 | break; | |
1210 | case 3: | |
1211 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
1212 | break; | |
1213 | case 4: | |
1214 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
1215 | break; | |
1216 | case 5: | |
1217 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
1218 | break; | |
1219 | } | |
771fe6b9 JG |
1220 | break; |
1221 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1222 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1223 | break; | |
771fe6b9 | 1224 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
4ce001ab | 1225 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1226 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1227 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1228 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1229 | else | |
1230 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1231 | break; | |
1232 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1233 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1234 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1235 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1236 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1237 | else | |
1238 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1239 | break; | |
1240 | } | |
1241 | break; | |
1242 | } | |
1243 | break; | |
1244 | default: | |
1245 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1246 | break; | |
1247 | } | |
1248 | ||
1249 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
267364ac AD |
1250 | |
1251 | /* update scratch regs with new routing */ | |
1252 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
771fe6b9 JG |
1253 | } |
1254 | ||
1255 | static void | |
1256 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
1257 | struct drm_display_mode *mode) | |
1258 | { | |
1259 | struct drm_device *dev = encoder->dev; | |
1260 | struct radeon_device *rdev = dev->dev_private; | |
1261 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1262 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1263 | ||
1264 | /* Funky macbooks */ | |
1265 | if ((dev->pdev->device == 0x71C5) && | |
1266 | (dev->pdev->subsystem_vendor == 0x106b) && | |
1267 | (dev->pdev->subsystem_device == 0x0080)) { | |
1268 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
1269 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
1270 | ||
1271 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
1272 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
1273 | ||
1274 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | /* set scaler clears this on some chips */ | |
bcc1c2a1 | 1279 | /* XXX check DCE4 */ |
ceefedd8 AD |
1280 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
1281 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) | |
1282 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1283 | AVIVO_D1MODE_INTERLEAVE_EN); | |
1284 | } | |
771fe6b9 JG |
1285 | } |
1286 | ||
f28cf339 DA |
1287 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1288 | { | |
1289 | struct drm_device *dev = encoder->dev; | |
1290 | struct radeon_device *rdev = dev->dev_private; | |
1291 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1292 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1293 | struct drm_encoder *test_encoder; | |
1294 | struct radeon_encoder_atom_dig *dig; | |
1295 | uint32_t dig_enc_in_use = 0; | |
bcc1c2a1 AD |
1296 | |
1297 | if (ASIC_IS_DCE4(rdev)) { | |
1298 | struct radeon_connector_atom_dig *dig_connector = | |
1299 | radeon_get_atom_connector_priv_from_encoder(encoder); | |
1300 | ||
1301 | switch (radeon_encoder->encoder_id) { | |
1302 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1303 | if (dig_connector->linkb) | |
1304 | return 1; | |
1305 | else | |
1306 | return 0; | |
1307 | break; | |
1308 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1309 | if (dig_connector->linkb) | |
1310 | return 3; | |
1311 | else | |
1312 | return 2; | |
1313 | break; | |
1314 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1315 | if (dig_connector->linkb) | |
1316 | return 5; | |
1317 | else | |
1318 | return 4; | |
1319 | break; | |
1320 | } | |
1321 | } | |
1322 | ||
f28cf339 DA |
1323 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1324 | if (ASIC_IS_DCE32(rdev)) { | |
1325 | return radeon_crtc->crtc_id; | |
1326 | } | |
1327 | ||
1328 | /* on DCE3 - LVTMA can only be driven by DIGB */ | |
1329 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1330 | struct radeon_encoder *radeon_test_encoder; | |
1331 | ||
1332 | if (encoder == test_encoder) | |
1333 | continue; | |
1334 | ||
1335 | if (!radeon_encoder_is_digital(test_encoder)) | |
1336 | continue; | |
1337 | ||
1338 | radeon_test_encoder = to_radeon_encoder(test_encoder); | |
1339 | dig = radeon_test_encoder->enc_priv; | |
1340 | ||
1341 | if (dig->dig_encoder >= 0) | |
1342 | dig_enc_in_use |= (1 << dig->dig_encoder); | |
1343 | } | |
1344 | ||
1345 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { | |
1346 | if (dig_enc_in_use & 0x2) | |
1347 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); | |
1348 | return 1; | |
1349 | } | |
1350 | if (!(dig_enc_in_use & 1)) | |
1351 | return 0; | |
1352 | return 1; | |
1353 | } | |
1354 | ||
771fe6b9 JG |
1355 | static void |
1356 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
1357 | struct drm_display_mode *mode, | |
1358 | struct drm_display_mode *adjusted_mode) | |
1359 | { | |
1360 | struct drm_device *dev = encoder->dev; | |
1361 | struct radeon_device *rdev = dev->dev_private; | |
1362 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
771fe6b9 | 1363 | |
771fe6b9 JG |
1364 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1365 | ||
c6f8505e | 1366 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
4ce001ab | 1367 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
1368 | atombios_yuv_setup(encoder, true); |
1369 | else | |
1370 | atombios_yuv_setup(encoder, false); | |
1371 | } | |
1372 | ||
1373 | switch (radeon_encoder->encoder_id) { | |
1374 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1375 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1376 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1377 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1378 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
1379 | break; | |
1380 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1381 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1382 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1383 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
bcc1c2a1 AD |
1384 | if (ASIC_IS_DCE4(rdev)) { |
1385 | /* disable the transmitter */ | |
1386 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1387 | /* setup and enable the encoder */ | |
1388 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); | |
1389 | ||
1390 | /* init and enable the transmitter */ | |
1391 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1392 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1393 | } else { | |
1394 | /* disable the encoder and transmitter */ | |
1395 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1396 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); | |
1397 | ||
1398 | /* setup and enable the encoder and transmitter */ | |
1399 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); | |
1400 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1401 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
1402 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1403 | } | |
771fe6b9 JG |
1404 | break; |
1405 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1406 | atombios_ddia_setup(encoder, ATOM_ENABLE); | |
1407 | break; | |
1408 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1409 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1410 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); | |
1411 | break; | |
1412 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1413 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1414 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1415 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1416 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
d3a67a43 AD |
1417 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
1418 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1419 | atombios_tv_setup(encoder, ATOM_ENABLE); | |
1420 | else | |
1421 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
1422 | } | |
771fe6b9 JG |
1423 | break; |
1424 | } | |
1425 | atombios_apply_encoder_quirks(encoder, adjusted_mode); | |
dafc3bd5 | 1426 | |
2cd6218c RM |
1427 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1428 | r600_hdmi_enable(encoder); | |
bcc1c2a1 | 1429 | r600_hdmi_setmode(encoder, adjusted_mode); |
2cd6218c | 1430 | } |
771fe6b9 JG |
1431 | } |
1432 | ||
1433 | static bool | |
4ce001ab | 1434 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
771fe6b9 JG |
1435 | { |
1436 | struct drm_device *dev = encoder->dev; | |
1437 | struct radeon_device *rdev = dev->dev_private; | |
1438 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1439 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1440 | |
1441 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
1442 | ATOM_DEVICE_CV_SUPPORT | | |
1443 | ATOM_DEVICE_CRT_SUPPORT)) { | |
1444 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
1445 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
1446 | uint8_t frev, crev; | |
1447 | ||
1448 | memset(&args, 0, sizeof(args)); | |
1449 | ||
a084e6ee AD |
1450 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1451 | return false; | |
771fe6b9 JG |
1452 | |
1453 | args.sDacload.ucMisc = 0; | |
1454 | ||
1455 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
1456 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
1457 | args.sDacload.ucDacType = ATOM_DAC_A; | |
1458 | else | |
1459 | args.sDacload.ucDacType = ATOM_DAC_B; | |
1460 | ||
4ce001ab | 1461 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
771fe6b9 | 1462 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
4ce001ab | 1463 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
771fe6b9 | 1464 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
4ce001ab | 1465 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
771fe6b9 JG |
1466 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1467 | if (crev >= 3) | |
1468 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
4ce001ab | 1469 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
771fe6b9 JG |
1470 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1471 | if (crev >= 3) | |
1472 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
1473 | } | |
1474 | ||
1475 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1476 | ||
1477 | return true; | |
1478 | } else | |
1479 | return false; | |
1480 | } | |
1481 | ||
1482 | static enum drm_connector_status | |
1483 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
1484 | { | |
1485 | struct drm_device *dev = encoder->dev; | |
1486 | struct radeon_device *rdev = dev->dev_private; | |
1487 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1488 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1489 | uint32_t bios_0_scratch; |
1490 | ||
4ce001ab | 1491 | if (!atombios_dac_load_detect(encoder, connector)) { |
771fe6b9 JG |
1492 | DRM_DEBUG("detect returned false \n"); |
1493 | return connector_status_unknown; | |
1494 | } | |
1495 | ||
1496 | if (rdev->family >= CHIP_R600) | |
1497 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
1498 | else | |
1499 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
1500 | ||
4ce001ab DA |
1501 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1502 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
771fe6b9 JG |
1503 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1504 | return connector_status_connected; | |
4ce001ab DA |
1505 | } |
1506 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
771fe6b9 JG |
1507 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1508 | return connector_status_connected; | |
4ce001ab DA |
1509 | } |
1510 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
771fe6b9 JG |
1511 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1512 | return connector_status_connected; | |
4ce001ab DA |
1513 | } |
1514 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
771fe6b9 JG |
1515 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1516 | return connector_status_connected; /* CTV */ | |
1517 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
1518 | return connector_status_connected; /* STV */ | |
1519 | } | |
1520 | return connector_status_disconnected; | |
1521 | } | |
1522 | ||
1523 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
1524 | { | |
267364ac AD |
1525 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1526 | ||
1527 | if (radeon_encoder->active_device & | |
1528 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { | |
1529 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
1530 | if (dig) | |
1531 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); | |
1532 | } | |
1533 | ||
771fe6b9 JG |
1534 | radeon_atom_output_lock(encoder, true); |
1535 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
267364ac AD |
1536 | |
1537 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
1538 | atombios_set_encoder_crtc_source(encoder); | |
771fe6b9 JG |
1539 | } |
1540 | ||
1541 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
1542 | { | |
1543 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
1544 | radeon_atom_output_lock(encoder, false); | |
1545 | } | |
1546 | ||
4ce001ab DA |
1547 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1548 | { | |
1549 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
f28cf339 | 1550 | struct radeon_encoder_atom_dig *dig; |
4ce001ab | 1551 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
f28cf339 DA |
1552 | |
1553 | if (radeon_encoder_is_digital(encoder)) { | |
2cd6218c RM |
1554 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
1555 | r600_hdmi_disable(encoder); | |
f28cf339 DA |
1556 | dig = radeon_encoder->enc_priv; |
1557 | dig->dig_encoder = -1; | |
1558 | } | |
4ce001ab DA |
1559 | radeon_encoder->active_device = 0; |
1560 | } | |
1561 | ||
771fe6b9 JG |
1562 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1563 | .dpms = radeon_atom_encoder_dpms, | |
1564 | .mode_fixup = radeon_atom_mode_fixup, | |
1565 | .prepare = radeon_atom_encoder_prepare, | |
1566 | .mode_set = radeon_atom_encoder_mode_set, | |
1567 | .commit = radeon_atom_encoder_commit, | |
4ce001ab | 1568 | .disable = radeon_atom_encoder_disable, |
771fe6b9 JG |
1569 | /* no detect for TMDS/LVDS yet */ |
1570 | }; | |
1571 | ||
1572 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
1573 | .dpms = radeon_atom_encoder_dpms, | |
1574 | .mode_fixup = radeon_atom_mode_fixup, | |
1575 | .prepare = radeon_atom_encoder_prepare, | |
1576 | .mode_set = radeon_atom_encoder_mode_set, | |
1577 | .commit = radeon_atom_encoder_commit, | |
1578 | .detect = radeon_atom_dac_detect, | |
1579 | }; | |
1580 | ||
1581 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
1582 | { | |
1583 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1584 | kfree(radeon_encoder->enc_priv); | |
1585 | drm_encoder_cleanup(encoder); | |
1586 | kfree(radeon_encoder); | |
1587 | } | |
1588 | ||
1589 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
1590 | .destroy = radeon_enc_destroy, | |
1591 | }; | |
1592 | ||
4ce001ab DA |
1593 | struct radeon_encoder_atom_dac * |
1594 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |
1595 | { | |
affd8589 AD |
1596 | struct drm_device *dev = radeon_encoder->base.dev; |
1597 | struct radeon_device *rdev = dev->dev_private; | |
4ce001ab DA |
1598 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
1599 | ||
1600 | if (!dac) | |
1601 | return NULL; | |
1602 | ||
affd8589 | 1603 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
4ce001ab DA |
1604 | return dac; |
1605 | } | |
1606 | ||
771fe6b9 JG |
1607 | struct radeon_encoder_atom_dig * |
1608 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |
1609 | { | |
1610 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
1611 | ||
1612 | if (!dig) | |
1613 | return NULL; | |
1614 | ||
1615 | /* coherent mode by default */ | |
1616 | dig->coherent_mode = true; | |
f28cf339 | 1617 | dig->dig_encoder = -1; |
771fe6b9 JG |
1618 | |
1619 | return dig; | |
1620 | } | |
1621 | ||
1622 | void | |
1623 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) | |
1624 | { | |
dfee5614 | 1625 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
1626 | struct drm_encoder *encoder; |
1627 | struct radeon_encoder *radeon_encoder; | |
1628 | ||
1629 | /* see if we already added it */ | |
1630 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1631 | radeon_encoder = to_radeon_encoder(encoder); | |
1632 | if (radeon_encoder->encoder_id == encoder_id) { | |
1633 | radeon_encoder->devices |= supported_device; | |
1634 | return; | |
1635 | } | |
1636 | ||
1637 | } | |
1638 | ||
1639 | /* add a new one */ | |
1640 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
1641 | if (!radeon_encoder) | |
1642 | return; | |
1643 | ||
1644 | encoder = &radeon_encoder->base; | |
bcc1c2a1 AD |
1645 | switch (rdev->num_crtc) { |
1646 | case 1: | |
dfee5614 | 1647 | encoder->possible_crtcs = 0x1; |
bcc1c2a1 AD |
1648 | break; |
1649 | case 2: | |
1650 | default: | |
dfee5614 | 1651 | encoder->possible_crtcs = 0x3; |
bcc1c2a1 AD |
1652 | break; |
1653 | case 6: | |
1654 | encoder->possible_crtcs = 0x3f; | |
1655 | break; | |
1656 | } | |
771fe6b9 JG |
1657 | |
1658 | radeon_encoder->enc_priv = NULL; | |
1659 | ||
1660 | radeon_encoder->encoder_id = encoder_id; | |
1661 | radeon_encoder->devices = supported_device; | |
c93bb85b | 1662 | radeon_encoder->rmx_type = RMX_OFF; |
771fe6b9 JG |
1663 | |
1664 | switch (radeon_encoder->encoder_id) { | |
1665 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1666 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1667 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1668 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1669 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1670 | radeon_encoder->rmx_type = RMX_FULL; | |
1671 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1672 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1673 | } else { | |
1674 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1675 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
1676 | } | |
1677 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
1678 | break; | |
1679 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1680 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
affd8589 | 1681 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
1682 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1683 | break; | |
1684 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1685 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1686 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1687 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); | |
4ce001ab | 1688 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
1689 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1690 | break; | |
1691 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1692 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1693 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1694 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1695 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1696 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1697 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
60d15f55 AD |
1698 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
1699 | radeon_encoder->rmx_type = RMX_FULL; | |
1700 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
1701 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
1702 | } else { | |
1703 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
1704 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
1705 | } | |
771fe6b9 JG |
1706 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1707 | break; | |
1708 | } | |
1709 | } |