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drm/radeon/kms/atom: fix PHY init
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
1f3b6a45
DA		 38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
bcc1c2a1 56
1f3b6a45
DA		 57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72}
73
74void radeon_setup_encoder_clones(struct drm_device *dev)
75{
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81}
82
771fe6b9 83uint32_t
5137ee94 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
771fe6b9
JG		 85{
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
5137ee94 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9 101 else if (ASIC_IS_AVIVO(rdev))
5137ee94 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
771fe6b9 103 else
5137ee94 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
771fe6b9
JG		 105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
5137ee94 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
771fe6b9
JG		 109 else {
110 /*if (rdev->family == CHIP_R200)
5137ee94 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 112 else*/
5137ee94 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9
JG		 114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
5137ee94 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 119 else
5137ee94 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
5137ee94 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9 127 else
5137ee94 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
771fe6b9
JG		 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
5137ee94 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 135 else if (ASIC_IS_AVIVO(rdev))
5137ee94 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
771fe6b9 137 else
5137ee94 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
771fe6b9
JG		 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
5137ee94 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
771fe6b9 146 else if (ASIC_IS_AVIVO(rdev))
5137ee94 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 148 else
5137ee94 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
5137ee94 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9
JG		 153 break;
154 }
155
156 return ret;
157}
158
f28cf339
DA		 159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
99999aaa 179
771fe6b9
JG		 180void
181radeon_link_encoder_connector(struct drm_device *dev)
182{
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197}
198
4ce001ab
DA		 199void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200{
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
d9fdaafb 209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
f641e51e
DA		 210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 212 }
213 }
214}
215
5b1714d3 216struct drm_connector *
771fe6b9
JG		 217radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218{
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
43c33ed8 226 if (radeon_encoder->active_device & radeon_connector->devices)
771fe6b9
JG		 227 return connector;
228 }
229 return NULL;
230}
231
ac89af1e
AD		 232static struct drm_connector *
233radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234{
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246}
247
3e4b9982
AD		 248struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
249{
250 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 struct drm_encoder *other_encoder;
253 struct radeon_encoder *other_radeon_encoder;
254
255 if (radeon_encoder->is_ext_encoder)
256 return NULL;
257
258 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
259 if (other_encoder == encoder)
260 continue;
261 other_radeon_encoder = to_radeon_encoder(other_encoder);
262 if (other_radeon_encoder->is_ext_encoder &&
263 (radeon_encoder->devices & other_radeon_encoder->devices))
264 return other_encoder;
265 }
266 return NULL;
267}
268
d7fa8bb3
AD		 269bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
270{
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
272
273 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
275
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
279 return true;
280 default:
281 return false;
282 }
283 }
284
285 return false;
286}
287
3515387b
AD		 288void radeon_panel_mode_fixup(struct drm_encoder *encoder,
289 struct drm_display_mode *adjusted_mode)
290{
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
295 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
296 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
297 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
298 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
299 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
300 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
301
302 adjusted_mode->clock = native_mode->clock;
303 adjusted_mode->flags = native_mode->flags;
304
305 if (ASIC_IS_AVIVO(rdev)) {
306 adjusted_mode->hdisplay = native_mode->hdisplay;
307 adjusted_mode->vdisplay = native_mode->vdisplay;
308 }
309
310 adjusted_mode->htotal = native_mode->hdisplay + hblank;
311 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
312 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
313
314 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
315 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
316 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
317
318 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
319
320 if (ASIC_IS_AVIVO(rdev)) {
321 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
322 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
323 }
324
325 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
326 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
327 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
328
329 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
330 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
331 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
332
333}
334
771fe6b9
JG		 335static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
338{
771fe6b9 339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
771fe6b9 342
8c2a6d73
AD		 343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 345 drm_mode_set_crtcinfo(adjusted_mode, 0);
346
771fe6b9
JG		 347 /* hw bug */
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
351
80297e87 352 /* get the native mode for LVDS */
3515387b
AD		 353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
80297e87
AD		 355
356 /* get the native mode for TV */
ceefedd8 357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
5a9bcacc
AD		 358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
359 if (tv_dac) {
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
364 else
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
366 }
367 }
368
5801ead6 369 if (ASIC_IS_DCE3(rdev) &&
9f998ad7 370 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
5801ead6
AD		 371 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
372 radeon_dp_set_link_config(connector, mode);
373 }
374
771fe6b9
JG		 375 return true;
376}
377
378static void
379atombios_dac_setup(struct drm_encoder *encoder, int action)
380{
381 struct drm_device *dev = encoder->dev;
382 struct radeon_device *rdev = dev->dev_private;
383 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
384 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
affd8589 385 int index = 0;
445282db 386 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 387
771fe6b9
JG		 388 memset(&args, 0, sizeof(args));
389
390 switch (radeon_encoder->encoder_id) {
391 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
392 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
393 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
771fe6b9
JG		 394 break;
395 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
397 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
771fe6b9
JG		 398 break;
399 }
400
401 args.ucAction = action;
402
4ce001ab 403 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 404 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 405 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 406 args.ucDacStandard = ATOM_DAC1_CV;
407 else {
affd8589 408 switch (dac_info->tv_std) {
771fe6b9
JG		 409 case TV_STD_PAL:
410 case TV_STD_PAL_M:
411 case TV_STD_SCART_PAL:
412 case TV_STD_SECAM:
413 case TV_STD_PAL_CN:
414 args.ucDacStandard = ATOM_DAC1_PAL;
415 break;
416 case TV_STD_NTSC:
417 case TV_STD_NTSC_J:
418 case TV_STD_PAL_60:
419 default:
420 args.ucDacStandard = ATOM_DAC1_NTSC;
421 break;
422 }
423 }
424 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
425
426 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
427
428}
429
430static void
431atombios_tv_setup(struct drm_encoder *encoder, int action)
432{
433 struct drm_device *dev = encoder->dev;
434 struct radeon_device *rdev = dev->dev_private;
435 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
436 TV_ENCODER_CONTROL_PS_ALLOCATION args;
437 int index = 0;
445282db 438 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 439
771fe6b9
JG		 440 memset(&args, 0, sizeof(args));
441
442 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
443
444 args.sTVEncoder.ucAction = action;
445
4ce001ab 446 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 447 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
448 else {
affd8589 449 switch (dac_info->tv_std) {
771fe6b9
JG		 450 case TV_STD_NTSC:
451 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
452 break;
453 case TV_STD_PAL:
454 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
455 break;
456 case TV_STD_PAL_M:
457 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
458 break;
459 case TV_STD_PAL_60:
460 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
461 break;
462 case TV_STD_NTSC_J:
463 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
464 break;
465 case TV_STD_SCART_PAL:
466 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
467 break;
468 case TV_STD_SECAM:
469 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
470 break;
471 case TV_STD_PAL_CN:
472 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
473 break;
474 default:
475 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
476 break;
477 }
478 }
479
480 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
481
482 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
483
484}
485
99999aaa
AD		 486union dvo_encoder_control {
487 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
488 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
490};
771fe6b9 491
99999aaa
AD		 492void
493atombios_dvo_setup(struct drm_encoder *encoder, int action)
771fe6b9
JG		 494{
495 struct drm_device *dev = encoder->dev;
496 struct radeon_device *rdev = dev->dev_private;
497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99999aaa
AD		 498 union dvo_encoder_control args;
499 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
771fe6b9
JG		 500
501 memset(&args, 0, sizeof(args));
502
99999aaa
AD		 503 if (ASIC_IS_DCE3(rdev)) {
504 /* DCE3+ */
505 args.dvo_v3.ucAction = action;
506 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
507 args.dvo_v3.ucDVOConfig = 0; /* XXX */
508 } else if (ASIC_IS_DCE2(rdev)) {
509 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
510 args.dvo.sDVOEncoder.ucAction = action;
511 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
512 /* DFP1, CRT1, TV1 depending on the type of port */
513 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
514
515 if (radeon_encoder->pixel_clock > 165000)
516 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
517 } else {
518 /* R4xx, R5xx */
519 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
771fe6b9 520
99999aaa
AD		 521 if (radeon_encoder->pixel_clock > 165000)
522 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
771fe6b9 523
99999aaa
AD		 524 /*if (pScrn->rgbBits == 8)*/
525 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
526 }
771fe6b9
JG		 527
528 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 529}
530
531union lvds_encoder_control {
532 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
534};
535
32f48ffe 536void
771fe6b9
JG		 537atombios_digital_setup(struct drm_encoder *encoder, int action)
538{
539 struct drm_device *dev = encoder->dev;
540 struct radeon_device *rdev = dev->dev_private;
541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 542 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
771fe6b9
JG		 543 union lvds_encoder_control args;
544 int index = 0;
dafc3bd5 545 int hdmi_detected = 0;
771fe6b9 546 uint8_t frev, crev;
771fe6b9 547
4aab97e8 548 if (!dig)
771fe6b9
JG		 549 return;
550
9ae47867 551 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dafc3bd5
CK		 552 hdmi_detected = 1;
553
771fe6b9
JG		 554 memset(&args, 0, sizeof(args));
555
556 switch (radeon_encoder->encoder_id) {
557 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
558 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
559 break;
560 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
562 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
563 break;
564 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
565 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
566 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
567 else
568 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
569 break;
570 }
571
a084e6ee
AD		 572 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
573 return;
771fe6b9
JG		 574
575 switch (frev) {
576 case 1:
577 case 2:
578 switch (crev) {
579 case 1:
580 args.v1.ucMisc = 0;
581 args.v1.ucAction = action;
dafc3bd5 582 if (hdmi_detected)
771fe6b9
JG		 583 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
584 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
585 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 586 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 587 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 588 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
99999aaa 589 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
771fe6b9 590 } else {
5137ee94 591 if (dig->linkb)
771fe6b9
JG		 592 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
593 if (radeon_encoder->pixel_clock > 165000)
594 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
595 /*if (pScrn->rgbBits == 8) */
99999aaa 596 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
771fe6b9
JG		 597 }
598 break;
599 case 2:
600 case 3:
601 args.v2.ucMisc = 0;
602 args.v2.ucAction = action;
603 if (crev == 3) {
604 if (dig->coherent_mode)
605 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
606 }
dafc3bd5 607 if (hdmi_detected)
771fe6b9
JG		 608 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
609 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 args.v2.ucTruncate = 0;
611 args.v2.ucSpatial = 0;
612 args.v2.ucTemporal = 0;
613 args.v2.ucFRC = 0;
614 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 615 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 616 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 617 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
771fe6b9 618 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
ba032a58 619 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 620 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
621 }
ba032a58 622 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
771fe6b9 623 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
ba032a58 624 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9 625 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
ba032a58 626 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
771fe6b9
JG		 627 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
628 }
629 } else {
5137ee94 630 if (dig->linkb)
771fe6b9
JG		 631 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
632 if (radeon_encoder->pixel_clock > 165000)
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
634 }
635 break;
636 default:
637 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
638 break;
639 }
640 break;
641 default:
642 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
643 break;
644 }
645
646 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 647}
648
649int
650atombios_get_encoder_mode(struct drm_encoder *encoder)
651{
c7a71fc7 652 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
d033af87
AD		 653 struct drm_device *dev = encoder->dev;
654 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 655 struct drm_connector *connector;
656 struct radeon_connector *radeon_connector;
9ae47867 657 struct radeon_connector_atom_dig *dig_connector;
771fe6b9 658
d7fa8bb3
AD		 659 /* dp bridges are always DP */
660 if (radeon_encoder_is_dp_bridge(encoder))
661 return ATOM_ENCODER_MODE_DP;
662
771fe6b9 663 connector = radeon_get_connector_for_encoder(encoder);
c7a71fc7
AD		 664 if (!connector) {
665 switch (radeon_encoder->encoder_id) {
666 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
668 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
670 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
671 return ATOM_ENCODER_MODE_DVI;
672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
674 default:
675 return ATOM_ENCODER_MODE_CRT;
676 }
677 }
771fe6b9
JG		 678 radeon_connector = to_radeon_connector(connector);
679
680 switch (connector->connector_type) {
681 case DRM_MODE_CONNECTOR_DVII:
705af9c7 682 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
9453d621 683 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 684 /* fix me */
685 if (ASIC_IS_DCE4(rdev))
686 return ATOM_ENCODER_MODE_DVI;
687 else
688 return ATOM_ENCODER_MODE_HDMI;
689 } else if (radeon_connector->use_digital)
771fe6b9
JG		 690 return ATOM_ENCODER_MODE_DVI;
691 else
692 return ATOM_ENCODER_MODE_CRT;
693 break;
694 case DRM_MODE_CONNECTOR_DVID:
695 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9 696 default:
9453d621 697 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 698 /* fix me */
699 if (ASIC_IS_DCE4(rdev))
700 return ATOM_ENCODER_MODE_DVI;
701 else
702 return ATOM_ENCODER_MODE_HDMI;
703 } else
771fe6b9
JG		 704 return ATOM_ENCODER_MODE_DVI;
705 break;
706 case DRM_MODE_CONNECTOR_LVDS:
707 return ATOM_ENCODER_MODE_LVDS;
708 break;
709 case DRM_MODE_CONNECTOR_DisplayPort:
9ae47867
AD		 710 dig_connector = radeon_connector->con_priv;
711 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
712 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
f92a8b67 713 return ATOM_ENCODER_MODE_DP;
9453d621 714 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
d033af87
AD		 715 /* fix me */
716 if (ASIC_IS_DCE4(rdev))
717 return ATOM_ENCODER_MODE_DVI;
718 else
719 return ATOM_ENCODER_MODE_HDMI;
720 } else
771fe6b9
JG		 721 return ATOM_ENCODER_MODE_DVI;
722 break;
3a5f4a21
AD		 723 case DRM_MODE_CONNECTOR_eDP:
724 return ATOM_ENCODER_MODE_DP;
a5899fcc
AD		 725 case DRM_MODE_CONNECTOR_DVIA:
726 case DRM_MODE_CONNECTOR_VGA:
771fe6b9
JG		 727 return ATOM_ENCODER_MODE_CRT;
728 break;
a5899fcc
AD		 729 case DRM_MODE_CONNECTOR_Composite:
730 case DRM_MODE_CONNECTOR_SVIDEO:
731 case DRM_MODE_CONNECTOR_9PinDIN:
771fe6b9
JG		 732 /* fix me */
733 return ATOM_ENCODER_MODE_TV;
734 /*return ATOM_ENCODER_MODE_CV;*/
735 break;
736 }
737}
738
1a66c95a
AD		 739/*
740 * DIG Encoder/Transmitter Setup
741 *
742 * DCE 3.0/3.1
743 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
744 * Supports up to 3 digital outputs
745 * - 2 DIG encoder blocks.
746 * DIG1 can drive UNIPHY link A or link B
747 * DIG2 can drive UNIPHY link B or LVTMA
748 *
749 * DCE 3.2
750 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
751 * Supports up to 5 digital outputs
752 * - 2 DIG encoder blocks.
753 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
754 *
a001182a 755 * DCE 4.0/5.0
4e8c65a1 756 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
bcc1c2a1
AD		 757 * Supports up to 6 digital outputs
758 * - 6 DIG encoder blocks.
759 * - DIG to PHY mapping is hardcoded
760 * DIG1 drives UNIPHY0 link A, A+B
761 * DIG2 drives UNIPHY0 link B
762 * DIG3 drives UNIPHY1 link A, A+B
763 * DIG4 drives UNIPHY1 link B
764 * DIG5 drives UNIPHY2 link A, A+B
765 * DIG6 drives UNIPHY2 link B
766 *
4e8c65a1
AD		 767 * DCE 4.1
768 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
769 * Supports up to 6 digital outputs
770 * - 2 DIG encoder blocks.
771 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
772 *
1a66c95a
AD		 773 * Routing
774 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
775 * Examples:
776 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
777 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
778 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
779 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
780 */
bcc1c2a1
AD		 781
782union dig_encoder_control {
783 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
784 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
785 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
badbb57b 786 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
bcc1c2a1
AD		 787};
788
789void
558e27db 790atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
771fe6b9
JG		 791{
792 struct drm_device *dev = encoder->dev;
793 struct radeon_device *rdev = dev->dev_private;
794 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 795 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 796 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
bcc1c2a1 797 union dig_encoder_control args;
d9c9fe36 798 int index = 0;
771fe6b9 799 uint8_t frev, crev;
4aab97e8
AD		 800 int dp_clock = 0;
801 int dp_lane_count = 0;
badbb57b 802 int hpd_id = RADEON_HPD_NONE;
df271bec 803 int bpc = 8;
4aab97e8
AD		 804
805 if (connector) {
806 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
807 struct radeon_connector_atom_dig *dig_connector =
808 radeon_connector->con_priv;
771fe6b9 809
4aab97e8
AD		 810 dp_clock = dig_connector->dp_clock;
811 dp_lane_count = dig_connector->dp_lane_count;
badbb57b 812 hpd_id = radeon_connector->hpd.hpd;
df271bec 813 bpc = connector->display_info.bpc;
4aab97e8
AD		 814 }
815
816 /* no dig encoder assigned */
817 if (dig->dig_encoder == -1)
771fe6b9
JG		 818 return;
819
771fe6b9
JG		 820 memset(&args, 0, sizeof(args));
821
bcc1c2a1
AD		 822 if (ASIC_IS_DCE4(rdev))
823 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
824 else {
825 if (dig->dig_encoder)
826 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
827 else
828 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
829 }
771fe6b9 830
a084e6ee
AD		 831 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
832 return;
771fe6b9 833
bcc1c2a1
AD		 834 args.v1.ucAction = action;
835 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
558e27db
AD		 836 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
837 args.v3.ucPanelMode = panel_mode;
838 else
839 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
771fe6b9 840
badbb57b
AD		 841 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
842 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
4aab97e8 843 args.v1.ucLaneNum = dp_lane_count;
badbb57b 844 else if (radeon_encoder->pixel_clock > 165000)
bcc1c2a1
AD		 845 args.v1.ucLaneNum = 8;
846 else
847 args.v1.ucLaneNum = 4;
848
badbb57b
AD		 849 if (ASIC_IS_DCE5(rdev)) {
850 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
851 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
852 if (dp_clock == 270000)
853 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
854 else if (dp_clock == 540000)
855 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
856 }
857 args.v4.acConfig.ucDigSel = dig->dig_encoder;
df271bec
AD		 858 switch (bpc) {
859 case 0:
860 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
861 break;
862 case 6:
863 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
864 break;
865 case 8:
866 default:
867 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
868 break;
869 case 10:
870 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
871 break;
872 case 12:
873 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
874 break;
875 case 16:
876 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
877 break;
878 }
badbb57b
AD		 879 if (hpd_id == RADEON_HPD_NONE)
880 args.v4.ucHPD_ID = 0;
881 else
882 args.v4.ucHPD_ID = hpd_id + 1;
883 } else if (ASIC_IS_DCE4(rdev)) {
884 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
885 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
bcc1c2a1 886 args.v3.acConfig.ucDigSel = dig->dig_encoder;
df271bec
AD		 887 switch (bpc) {
888 case 0:
889 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
890 break;
891 case 6:
892 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
893 break;
894 case 8:
895 default:
896 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
897 break;
898 case 10:
899 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
900 break;
901 case 12:
902 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
903 break;
904 case 16:
905 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
906 break;
907 }
bcc1c2a1 908 } else {
badbb57b
AD		 909 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
771fe6b9
JG		 911 switch (radeon_encoder->encoder_id) {
912 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
bcc1c2a1 913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
771fe6b9
JG		 914 break;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
bcc1c2a1
AD		 916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
917 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
771fe6b9
JG		 918 break;
919 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
bcc1c2a1 920 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
771fe6b9
JG		 921 break;
922 }
5137ee94 923 if (dig->linkb)
bcc1c2a1
AD		 924 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
925 else
926 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
771fe6b9
JG		 927 }
928
771fe6b9
JG		 929 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
930
931}
932
933union dig_transmitter_control {
934 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
935 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
bcc1c2a1 936 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
a001182a 937 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
771fe6b9
JG		 938};
939
5801ead6 940void
1a66c95a 941atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
771fe6b9
JG		 942{
943 struct drm_device *dev = encoder->dev;
944 struct radeon_device *rdev = dev->dev_private;
945 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 946 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
ac89af1e 947 struct drm_connector *connector;
771fe6b9 948 union dig_transmitter_control args;
d9c9fe36 949 int index = 0;
771fe6b9 950 uint8_t frev, crev;
f92a8b67 951 bool is_dp = false;
bcc1c2a1 952 int pll_id = 0;
4aab97e8
AD		 953 int dp_clock = 0;
954 int dp_lane_count = 0;
955 int connector_object_id = 0;
956 int igp_lane_info = 0;
f3aeceac 957 int dig_encoder = dig->dig_encoder;
4aab97e8 958
f3aeceac 959 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
ac89af1e 960 connector = radeon_get_connector_for_encoder_init(encoder);
f3aeceac
AD		 961 /* just needed to avoid bailing in the encoder check. the encoder
962 * isn't used for init
963 */
964 dig_encoder = 0;
965 } else
ac89af1e
AD		 966 connector = radeon_get_connector_for_encoder(encoder);
967
4aab97e8
AD		 968 if (connector) {
969 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
970 struct radeon_connector_atom_dig *dig_connector =
971 radeon_connector->con_priv;
972
973 dp_clock = dig_connector->dp_clock;
974 dp_lane_count = dig_connector->dp_lane_count;
975 connector_object_id =
976 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
977 igp_lane_info = dig_connector->igp_lane_info;
978 }
771fe6b9 979
4aab97e8 980 /* no dig encoder assigned */
f3aeceac 981 if (dig_encoder == -1)
771fe6b9
JG		 982 return;
983
f92a8b67
AD		 984 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
985 is_dp = true;
986
771fe6b9
JG		 987 memset(&args, 0, sizeof(args));
988
4aab97e8 989 switch (radeon_encoder->encoder_id) {
99999aaa
AD		 990 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
991 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
992 break;
4aab97e8
AD		 993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
995 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
771fe6b9 996 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
4aab97e8
AD		 997 break;
998 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
999 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1000 break;
771fe6b9
JG		 1001 }
1002
a084e6ee
AD		 1003 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1004 return;
771fe6b9
JG		 1005
1006 args.v1.ucAction = action;
f95a9f0b 1007 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
4589433c 1008 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1a66c95a
AD		 1009 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1010 args.v1.asMode.ucLaneSel = lane_num;
1011 args.v1.asMode.ucLaneSet = lane_set;
f95a9f0b 1012 } else {
f92a8b67
AD		 1013 if (is_dp)
1014 args.v1.usPixelClock =
4aab97e8 1015 cpu_to_le16(dp_clock / 10);
f92a8b67 1016 else if (radeon_encoder->pixel_clock > 165000)
f95a9f0b
AD		 1017 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1018 else
1019 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1020 }
bcc1c2a1
AD		 1021 if (ASIC_IS_DCE4(rdev)) {
1022 if (is_dp)
4aab97e8 1023 args.v3.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 1024 else if (radeon_encoder->pixel_clock > 165000)
1025 args.v3.ucLaneNum = 8;
1026 else
1027 args.v3.ucLaneNum = 4;
1028
96b3bef8 1029 if (dig->linkb)
b61c99de 1030 args.v3.acConfig.ucLinkSel = 1;
f3aeceac 1031 if (dig_encoder & 1)
b61c99de 1032 args.v3.acConfig.ucEncoderSel = 1;
bcc1c2a1
AD		 1033
1034 /* Select the PLL for the PHY
1035 * DP PHY should be clocked from external src if there is
1036 * one.
1037 */
1038 if (encoder->crtc) {
1039 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1040 pll_id = radeon_crtc->pll_id;
1041 }
a001182a
AD		 1042
1043 if (ASIC_IS_DCE5(rdev)) {
86a94def
AD		 1044 /* On DCE5 DCPLL usually generates the DP ref clock */
1045 if (is_dp) {
1046 if (rdev->clock.dp_extclk)
1047 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1048 else
1049 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1050 } else
a001182a
AD		 1051 args.v4.acConfig.ucRefClkSource = pll_id;
1052 } else {
86a94def 1053 /* On DCE4, if there is an external clock, it generates the DP ref clock */
a001182a
AD		 1054 if (is_dp && rdev->clock.dp_extclk)
1055 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1056 else
1057 args.v3.acConfig.ucRefClkSource = pll_id;
1058 }
bcc1c2a1
AD		 1059
1060 switch (radeon_encoder->encoder_id) {
1061 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1062 args.v3.acConfig.ucTransmitterSel = 0;
bcc1c2a1
AD		 1063 break;
1064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1065 args.v3.acConfig.ucTransmitterSel = 1;
bcc1c2a1
AD		 1066 break;
1067 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1068 args.v3.acConfig.ucTransmitterSel = 2;
bcc1c2a1
AD		 1069 break;
1070 }
1071
1072 if (is_dp)
1073 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1074 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1075 if (dig->coherent_mode)
1076 args.v3.acConfig.fCoherentMode = 1;
b317a9ce
AD		 1077 if (radeon_encoder->pixel_clock > 165000)
1078 args.v3.acConfig.fDualLinkConnector = 1;
bcc1c2a1
AD		 1079 }
1080 } else if (ASIC_IS_DCE32(rdev)) {
f3aeceac 1081 args.v2.acConfig.ucEncoderSel = dig_encoder;
5137ee94 1082 if (dig->linkb)
1a66c95a 1083 args.v2.acConfig.ucLinkSel = 1;
771fe6b9
JG		 1084
1085 switch (radeon_encoder->encoder_id) {
1086 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1087 args.v2.acConfig.ucTransmitterSel = 0;
771fe6b9
JG		 1088 break;
1089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1090 args.v2.acConfig.ucTransmitterSel = 1;
771fe6b9
JG		 1091 break;
1092 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1093 args.v2.acConfig.ucTransmitterSel = 2;
771fe6b9
JG		 1094 break;
1095 }
1096
f92a8b67
AD		 1097 if (is_dp)
1098 args.v2.acConfig.fCoherentMode = 1;
1099 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 1100 if (dig->coherent_mode)
1101 args.v2.acConfig.fCoherentMode = 1;
b317a9ce
AD		 1102 if (radeon_encoder->pixel_clock > 165000)
1103 args.v2.acConfig.fDualLinkConnector = 1;
771fe6b9
JG		 1104 }
1105 } else {
1106 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
771fe6b9 1107
f3aeceac 1108 if (dig_encoder)
f28cf339
DA		 1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1110 else
1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1112
d9c9fe36
AD		 1113 if ((rdev->flags & RADEON_IS_IGP) &&
1114 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1115 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
4aab97e8 1116 if (igp_lane_info & 0x1)
d9c9fe36 1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
4aab97e8 1118 else if (igp_lane_info & 0x2)
d9c9fe36 1119 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
4aab97e8 1120 else if (igp_lane_info & 0x4)
d9c9fe36 1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
4aab97e8 1122 else if (igp_lane_info & 0x8)
d9c9fe36
AD		 1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1124 } else {
4aab97e8 1125 if (igp_lane_info & 0x3)
d9c9fe36 1126 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
4aab97e8 1127 else if (igp_lane_info & 0xc)
d9c9fe36 1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
771fe6b9 1129 }
771fe6b9
JG		 1130 }
1131
5137ee94 1132 if (dig->linkb)
1a66c95a
AD		 1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1134 else
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1136
f92a8b67
AD		 1137 if (is_dp)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 1140 if (dig->coherent_mode)
1141 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
d9c9fe36
AD		 1142 if (radeon_encoder->pixel_clock > 165000)
1143 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
771fe6b9
JG		 1144 }
1145 }
1146
1147 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 1148}
1149
2dafb74d 1150bool
8b834852
AD		 1151atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1152{
1153 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1154 struct drm_device *dev = radeon_connector->base.dev;
1155 struct radeon_device *rdev = dev->dev_private;
1156 union dig_transmitter_control args;
1157 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1158 uint8_t frev, crev;
1159
1160 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
2dafb74d 1161 goto done;
8b834852
AD		 1162
1163 if (!ASIC_IS_DCE4(rdev))
2dafb74d 1164 goto done;
8b834852 1165
e468e001 1166 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
8b834852 1167 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
2dafb74d 1168 goto done;
8b834852
AD		 1169
1170 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2dafb74d 1171 goto done;
8b834852
AD		 1172
1173 memset(&args, 0, sizeof(args));
1174
1175 args.v1.ucAction = action;
1176
1177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2dafb74d
AD		 1178
1179 /* wait for the panel to power up */
1180 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1181 int i;
1182
1183 for (i = 0; i < 300; i++) {
1184 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1185 return true;
1186 mdelay(1);
1187 }
1188 return false;
1189 }
1190done:
1191 return true;
8b834852
AD		 1192}
1193
3e4b9982
AD		 1194union external_encoder_control {
1195 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
bf982ebf 1196 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
3e4b9982
AD		 1197};
1198
1199static void
1200atombios_external_encoder_setup(struct drm_encoder *encoder,
1201 struct drm_encoder *ext_encoder,
1202 int action)
1203{
1204 struct drm_device *dev = encoder->dev;
1205 struct radeon_device *rdev = dev->dev_private;
1206 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
bf982ebf 1207 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
3e4b9982 1208 union external_encoder_control args;
ac89af1e 1209 struct drm_connector *connector;
3e4b9982
AD		 1210 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1211 u8 frev, crev;
1212 int dp_clock = 0;
1213 int dp_lane_count = 0;
1214 int connector_object_id = 0;
bf982ebf 1215 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
df271bec 1216 int bpc = 8;
3e4b9982 1217
ac89af1e
AD		 1218 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1219 connector = radeon_get_connector_for_encoder_init(encoder);
1220 else
1221 connector = radeon_get_connector_for_encoder(encoder);
1222
3e4b9982
AD		 1223 if (connector) {
1224 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1225 struct radeon_connector_atom_dig *dig_connector =
1226 radeon_connector->con_priv;
1227
1228 dp_clock = dig_connector->dp_clock;
1229 dp_lane_count = dig_connector->dp_lane_count;
1230 connector_object_id =
1231 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
df271bec 1232 bpc = connector->display_info.bpc;
3e4b9982
AD		 1233 }
1234
1235 memset(&args, 0, sizeof(args));
1236
1237 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1238 return;
1239
1240 switch (frev) {
1241 case 1:
1242 /* no params on frev 1 */
1243 break;
1244 case 2:
1245 switch (crev) {
1246 case 1:
1247 case 2:
1248 args.v1.sDigEncoder.ucAction = action;
1249 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1250 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1251
1252 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1253 if (dp_clock == 270000)
1254 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1255 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1256 } else if (radeon_encoder->pixel_clock > 165000)
1257 args.v1.sDigEncoder.ucLaneNum = 8;
1258 else
1259 args.v1.sDigEncoder.ucLaneNum = 4;
1260 break;
bf982ebf
AD		 1261 case 3:
1262 args.v3.sExtEncoder.ucAction = action;
1263 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
4589433c 1264 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
bf982ebf
AD		 1265 else
1266 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1267 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1268
1269 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1270 if (dp_clock == 270000)
1271 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1272 else if (dp_clock == 540000)
1273 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1274 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1275 } else if (radeon_encoder->pixel_clock > 165000)
1276 args.v3.sExtEncoder.ucLaneNum = 8;
1277 else
1278 args.v3.sExtEncoder.ucLaneNum = 4;
1279 switch (ext_enum) {
1280 case GRAPH_OBJECT_ENUM_ID1:
1281 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1282 break;
1283 case GRAPH_OBJECT_ENUM_ID2:
1284 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1285 break;
1286 case GRAPH_OBJECT_ENUM_ID3:
1287 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1288 break;
1289 }
df271bec
AD		 1290 switch (bpc) {
1291 case 0:
1292 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1293 break;
1294 case 6:
1295 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1296 break;
1297 case 8:
1298 default:
1299 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1300 break;
1301 case 10:
1302 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1303 break;
1304 case 12:
1305 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1306 break;
1307 case 16:
1308 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1309 break;
1310 }
bf982ebf 1311 break;
3e4b9982
AD		 1312 default:
1313 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1314 return;
1315 }
1316 break;
1317 default:
1318 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1319 return;
1320 }
1321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322}
1323
771fe6b9
JG		 1324static void
1325atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1326{
1327 struct drm_device *dev = encoder->dev;
1328 struct radeon_device *rdev = dev->dev_private;
1329 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1330 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1331 ENABLE_YUV_PS_ALLOCATION args;
1332 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1333 uint32_t temp, reg;
1334
1335 memset(&args, 0, sizeof(args));
1336
1337 if (rdev->family >= CHIP_R600)
1338 reg = R600_BIOS_3_SCRATCH;
1339 else
1340 reg = RADEON_BIOS_3_SCRATCH;
1341
1342 /* XXX: fix up scratch reg handling */
1343 temp = RREG32(reg);
4ce001ab 1344 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1345 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1346 (radeon_crtc->crtc_id << 18)));
4ce001ab 1347 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1348 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1349 else
1350 WREG32(reg, 0);
1351
1352 if (enable)
1353 args.ucEnable = ATOM_ENABLE;
1354 args.ucCRTC = radeon_crtc->crtc_id;
1355
1356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1357
1358 WREG32(reg, temp);
1359}
1360
771fe6b9
JG		 1361static void
1362radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1363{
1364 struct drm_device *dev = encoder->dev;
1365 struct radeon_device *rdev = dev->dev_private;
1366 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3e4b9982 1367 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
771fe6b9
JG		 1368 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1369 int index = 0;
1370 bool is_dig = false;
69c74525 1371 bool is_dce5_dac = false;
d07f4e83 1372 bool is_dce5_dvo = false;
771fe6b9
JG		 1373
1374 memset(&args, 0, sizeof(args));
1375
d9fdaafb 1376 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
f641e51e
DA		 1377 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1378 radeon_encoder->active_device);
771fe6b9
JG		 1379 switch (radeon_encoder->encoder_id) {
1380 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1381 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1382 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1383 break;
1384 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1388 is_dig = true;
1389 break;
1390 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1391 case ENCODER_OBJECT_ID_INTERNAL_DDI:
771fe6b9
JG		 1392 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1393 break;
99999aaa 1394 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
d07f4e83
AD		 1395 if (ASIC_IS_DCE5(rdev))
1396 is_dce5_dvo = true;
1397 else if (ASIC_IS_DCE3(rdev))
99999aaa
AD		 1398 is_dig = true;
1399 else
1400 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1401 break;
771fe6b9
JG		 1402 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1403 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1404 break;
1405 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1406 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1407 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1408 else
1409 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1410 break;
1411 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
69c74525
AD		 1413 if (ASIC_IS_DCE5(rdev))
1414 is_dce5_dac = true;
1415 else {
1416 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1417 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1418 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1419 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1420 else
1421 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1422 }
771fe6b9
JG		 1423 break;
1424 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1425 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
8c2a6d73 1426 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1427 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1428 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1429 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1430 else
1431 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1432 break;
1433 }
1434
1435 if (is_dig) {
1436 switch (mode) {
1437 case DRM_MODE_DPMS_ON:
e13b2ac1 1438 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fb668c2f 1439 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
58682f10 1440 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
fb668c2f 1441
8b834852
AD		 1442 if (connector &&
1443 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1444 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1445 struct radeon_connector_atom_dig *radeon_dig_connector =
1446 radeon_connector->con_priv;
1447 atombios_set_edp_panel_power(connector,
1448 ATOM_TRANSMITTER_ACTION_POWER_ON);
1449 radeon_dig_connector->edp_on = true;
1450 }
224d94b1
AD		 1451 if (ASIC_IS_DCE4(rdev))
1452 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1453 radeon_dp_link_train(encoder, connector);
fb668c2f 1454 if (ASIC_IS_DCE4(rdev))
558e27db 1455 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
58682f10 1456 }
ba251bde
AD		 1457 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
771fe6b9
JG		 1459 break;
1460 case DRM_MODE_DPMS_STANDBY:
1461 case DRM_MODE_DPMS_SUSPEND:
1462 case DRM_MODE_DPMS_OFF:
e13b2ac1 1463 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
fb668c2f 1464 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
8b834852
AD		 1465 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1466
fb668c2f 1467 if (ASIC_IS_DCE4(rdev))
558e27db 1468 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
8b834852
AD		 1469 if (connector &&
1470 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1471 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1472 struct radeon_connector_atom_dig *radeon_dig_connector =
1473 radeon_connector->con_priv;
1474 atombios_set_edp_panel_power(connector,
1475 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1476 radeon_dig_connector->edp_on = false;
1477 }
fb668c2f 1478 }
ba251bde
AD		 1479 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1480 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
771fe6b9
JG		 1481 break;
1482 }
69c74525
AD		 1483 } else if (is_dce5_dac) {
1484 switch (mode) {
1485 case DRM_MODE_DPMS_ON:
1486 atombios_dac_setup(encoder, ATOM_ENABLE);
1487 break;
1488 case DRM_MODE_DPMS_STANDBY:
1489 case DRM_MODE_DPMS_SUSPEND:
1490 case DRM_MODE_DPMS_OFF:
1491 atombios_dac_setup(encoder, ATOM_DISABLE);
1492 break;
1493 }
d07f4e83
AD		 1494 } else if (is_dce5_dvo) {
1495 switch (mode) {
1496 case DRM_MODE_DPMS_ON:
1497 atombios_dvo_setup(encoder, ATOM_ENABLE);
1498 break;
1499 case DRM_MODE_DPMS_STANDBY:
1500 case DRM_MODE_DPMS_SUSPEND:
1501 case DRM_MODE_DPMS_OFF:
1502 atombios_dvo_setup(encoder, ATOM_DISABLE);
1503 break;
1504 }
771fe6b9
JG		 1505 } else {
1506 switch (mode) {
1507 case DRM_MODE_DPMS_ON:
1508 args.ucAction = ATOM_ENABLE;
ba251bde
AD		 1509 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1510 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1511 args.ucAction = ATOM_LCD_BLON;
1512 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1513 }
771fe6b9
JG		 1514 break;
1515 case DRM_MODE_DPMS_STANDBY:
1516 case DRM_MODE_DPMS_SUSPEND:
1517 case DRM_MODE_DPMS_OFF:
1518 args.ucAction = ATOM_DISABLE;
ba251bde
AD		 1519 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1520 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1521 args.ucAction = ATOM_LCD_BLOFF;
1522 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1523 }
771fe6b9
JG		 1524 break;
1525 }
771fe6b9 1526 }
3e4b9982
AD		 1527
1528 if (ext_encoder) {
1529 int action;
1530
1531 switch (mode) {
1532 case DRM_MODE_DPMS_ON:
1533 default:
633b9164 1534 if (ASIC_IS_DCE41(rdev))
bf982ebf
AD		 1535 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1536 else
1537 action = ATOM_ENABLE;
3e4b9982
AD		 1538 break;
1539 case DRM_MODE_DPMS_STANDBY:
1540 case DRM_MODE_DPMS_SUSPEND:
1541 case DRM_MODE_DPMS_OFF:
633b9164 1542 if (ASIC_IS_DCE41(rdev))
bf982ebf
AD		 1543 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1544 else
1545 action = ATOM_DISABLE;
3e4b9982
AD		 1546 break;
1547 }
1548 atombios_external_encoder_setup(encoder, ext_encoder, action);
1549 }
1550
771fe6b9 1551 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1552
771fe6b9
JG		 1553}
1554
9ae47867 1555union crtc_source_param {
771fe6b9
JG		 1556 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1557 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1558};
1559
1560static void
1561atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1562{
1563 struct drm_device *dev = encoder->dev;
1564 struct radeon_device *rdev = dev->dev_private;
1565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1566 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9ae47867 1567 union crtc_source_param args;
771fe6b9
JG		 1568 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1569 uint8_t frev, crev;
f28cf339 1570 struct radeon_encoder_atom_dig *dig;
771fe6b9
JG		 1571
1572 memset(&args, 0, sizeof(args));
1573
a084e6ee
AD		 1574 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1575 return;
771fe6b9
JG		 1576
1577 switch (frev) {
1578 case 1:
1579 switch (crev) {
1580 case 1:
1581 default:
1582 if (ASIC_IS_AVIVO(rdev))
1583 args.v1.ucCRTC = radeon_crtc->crtc_id;
1584 else {
1585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1586 args.v1.ucCRTC = radeon_crtc->crtc_id;
1587 } else {
1588 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1589 }
1590 }
1591 switch (radeon_encoder->encoder_id) {
1592 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1593 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1594 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1595 break;
1596 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1598 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1599 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1600 else
1601 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1602 break;
1603 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1604 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1606 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1607 break;
1608 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1610 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1611 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1612 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1613 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1614 else
1615 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1616 break;
1617 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1618 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1619 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1620 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1621 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1622 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1623 else
1624 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1625 break;
1626 }
1627 break;
1628 case 2:
1629 args.v2.ucCRTC = radeon_crtc->crtc_id;
1630 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1631 switch (radeon_encoder->encoder_id) {
1632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1633 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1634 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
f28cf339
DA		 1635 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1636 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1637 switch (dig->dig_encoder) {
1638 case 0:
f28cf339 1639 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
bcc1c2a1
AD		 1640 break;
1641 case 1:
1642 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1643 break;
1644 case 2:
1645 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1646 break;
1647 case 3:
1648 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1649 break;
1650 case 4:
1651 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1652 break;
1653 case 5:
1654 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1655 break;
1656 }
771fe6b9
JG		 1657 break;
1658 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1659 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1660 break;
771fe6b9 1661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1662 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1663 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1664 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1665 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1666 else
1667 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1668 break;
1669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1670 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1671 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1672 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1673 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1674 else
1675 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1676 break;
1677 }
1678 break;
1679 }
1680 break;
1681 default:
1682 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
99999aaa 1683 return;
771fe6b9
JG		 1684 }
1685
1686 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
267364ac
AD		 1687
1688 /* update scratch regs with new routing */
1689 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1690}
1691
1692static void
1693atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1694 struct drm_display_mode *mode)
1695{
1696 struct drm_device *dev = encoder->dev;
1697 struct radeon_device *rdev = dev->dev_private;
1698 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1699 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1700
1701 /* Funky macbooks */
1702 if ((dev->pdev->device == 0x71C5) &&
1703 (dev->pdev->subsystem_vendor == 0x106b) &&
1704 (dev->pdev->subsystem_device == 0x0080)) {
1705 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1706 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1707
1708 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1709 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1710
1711 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1712 }
1713 }
1714
1715 /* set scaler clears this on some chips */
c9417bdd
AD		 1716 if (ASIC_IS_AVIVO(rdev) &&
1717 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1718 if (ASIC_IS_DCE4(rdev)) {
1719 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1720 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1721 EVERGREEN_INTERLEAVE_EN);
1722 else
1723 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1724 } else {
1725 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1726 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1727 AVIVO_D1MODE_INTERLEAVE_EN);
1728 else
1729 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1730 }
ceefedd8 1731 }
771fe6b9
JG		 1732}
1733
f28cf339
DA		 1734static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1735{
1736 struct drm_device *dev = encoder->dev;
1737 struct radeon_device *rdev = dev->dev_private;
1738 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1739 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1740 struct drm_encoder *test_encoder;
1741 struct radeon_encoder_atom_dig *dig;
1742 uint32_t dig_enc_in_use = 0;
bcc1c2a1 1743
badbb57b 1744 /* DCE4/5 */
bcc1c2a1 1745 if (ASIC_IS_DCE4(rdev)) {
5137ee94 1746 dig = radeon_encoder->enc_priv;
96b3bef8
AD		 1747 if (ASIC_IS_DCE41(rdev))
1748 return radeon_crtc->crtc_id;
1749 else {
b61c99de
AD		 1750 switch (radeon_encoder->encoder_id) {
1751 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1752 if (dig->linkb)
1753 return 1;
1754 else
1755 return 0;
1756 break;
1757 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1758 if (dig->linkb)
1759 return 3;
1760 else
1761 return 2;
1762 break;
1763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1764 if (dig->linkb)
1765 return 5;
1766 else
1767 return 4;
1768 break;
1769 }
bcc1c2a1
AD		 1770 }
1771 }
1772
f28cf339
DA		 1773 /* on DCE32 and encoder can driver any block so just crtc id */
1774 if (ASIC_IS_DCE32(rdev)) {
1775 return radeon_crtc->crtc_id;
1776 }
1777
1778 /* on DCE3 - LVTMA can only be driven by DIGB */
1779 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1780 struct radeon_encoder *radeon_test_encoder;
1781
1782 if (encoder == test_encoder)
1783 continue;
1784
1785 if (!radeon_encoder_is_digital(test_encoder))
1786 continue;
1787
1788 radeon_test_encoder = to_radeon_encoder(test_encoder);
1789 dig = radeon_test_encoder->enc_priv;
1790
1791 if (dig->dig_encoder >= 0)
1792 dig_enc_in_use |= (1 << dig->dig_encoder);
1793 }
1794
1795 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1796 if (dig_enc_in_use & 0x2)
1797 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1798 return 1;
1799 }
1800 if (!(dig_enc_in_use & 1))
1801 return 0;
1802 return 1;
1803}
1804
ac89af1e
AD		 1805/* This only needs to be called once at startup */
1806void
1807radeon_atom_encoder_init(struct radeon_device *rdev)
1808{
1809 struct drm_device *dev = rdev->ddev;
1810 struct drm_encoder *encoder;
1811
1812 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1813 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1814 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1815
1816 switch (radeon_encoder->encoder_id) {
1817 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1818 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1819 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1820 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1821 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1822 break;
1823 default:
1824 break;
1825 }
1826
1827 if (ext_encoder && ASIC_IS_DCE41(rdev))
1828 atombios_external_encoder_setup(encoder, ext_encoder,
1829 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1830 }
1831}
1832
771fe6b9
JG		 1833static void
1834radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1835 struct drm_display_mode *mode,
1836 struct drm_display_mode *adjusted_mode)
1837{
1838 struct drm_device *dev = encoder->dev;
1839 struct radeon_device *rdev = dev->dev_private;
1840 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3e4b9982 1841 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
771fe6b9 1842
771fe6b9
JG		 1843 radeon_encoder->pixel_clock = adjusted_mode->clock;
1844
c6f8505e 1845 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
4ce001ab 1846 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1847 atombios_yuv_setup(encoder, true);
1848 else
1849 atombios_yuv_setup(encoder, false);
1850 }
1851
1852 switch (radeon_encoder->encoder_id) {
1853 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1855 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1856 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1857 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1858 break;
1859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1860 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1861 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1862 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
bcc1c2a1
AD		 1863 if (ASIC_IS_DCE4(rdev)) {
1864 /* disable the transmitter */
1865 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1866 /* setup and enable the encoder */
558e27db 1867 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
bcc1c2a1 1868
ac89af1e 1869 /* enable the transmitter */
bcc1c2a1
AD		 1870 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1871 } else {
1872 /* disable the encoder and transmitter */
1873 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
558e27db 1874 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
bcc1c2a1
AD		 1875
1876 /* setup and enable the encoder and transmitter */
558e27db 1877 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
bcc1c2a1
AD		 1878 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1879 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1880 }
771fe6b9
JG		 1881 break;
1882 case ENCODER_OBJECT_ID_INTERNAL_DDI:
771fe6b9
JG		 1883 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
99999aaa 1885 atombios_dvo_setup(encoder, ATOM_ENABLE);
771fe6b9
JG		 1886 break;
1887 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1889 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1890 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1891 atombios_dac_setup(encoder, ATOM_ENABLE);
d3a67a43
AD		 1892 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1893 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1894 atombios_tv_setup(encoder, ATOM_ENABLE);
1895 else
1896 atombios_tv_setup(encoder, ATOM_DISABLE);
1897 }
771fe6b9
JG		 1898 break;
1899 }
3e4b9982
AD		 1900
1901 if (ext_encoder) {
ac89af1e 1902 if (ASIC_IS_DCE41(rdev))
bf982ebf
AD		 1903 atombios_external_encoder_setup(encoder, ext_encoder,
1904 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
ac89af1e 1905 else
bf982ebf 1906 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
3e4b9982
AD		 1907 }
1908
771fe6b9 1909 atombios_apply_encoder_quirks(encoder, adjusted_mode);
dafc3bd5 1910
2cd6218c
RM		 1911 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1912 r600_hdmi_enable(encoder);
bcc1c2a1 1913 r600_hdmi_setmode(encoder, adjusted_mode);
2cd6218c 1914 }
771fe6b9
JG		 1915}
1916
1917static bool
4ce001ab 1918atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1919{
1920 struct drm_device *dev = encoder->dev;
1921 struct radeon_device *rdev = dev->dev_private;
1922 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1923 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1924
1925 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1926 ATOM_DEVICE_CV_SUPPORT |
1927 ATOM_DEVICE_CRT_SUPPORT)) {
1928 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1929 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1930 uint8_t frev, crev;
1931
1932 memset(&args, 0, sizeof(args));
1933
a084e6ee
AD		 1934 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1935 return false;
771fe6b9
JG		 1936
1937 args.sDacload.ucMisc = 0;
1938
1939 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1940 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1941 args.sDacload.ucDacType = ATOM_DAC_A;
1942 else
1943 args.sDacload.ucDacType = ATOM_DAC_B;
1944
4ce001ab 1945 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1946 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1947 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1948 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1949 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1950 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1951 if (crev >= 3)
1952 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1953 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1954 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1955 if (crev >= 3)
1956 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1957 }
1958
1959 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1960
1961 return true;
1962 } else
1963 return false;
1964}
1965
1966static enum drm_connector_status
1967radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1968{
1969 struct drm_device *dev = encoder->dev;
1970 struct radeon_device *rdev = dev->dev_private;
1971 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1972 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1973 uint32_t bios_0_scratch;
1974
4ce001ab 1975 if (!atombios_dac_load_detect(encoder, connector)) {
d9fdaafb 1976 DRM_DEBUG_KMS("detect returned false \n");
771fe6b9
JG		 1977 return connector_status_unknown;
1978 }
1979
1980 if (rdev->family >= CHIP_R600)
1981 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1982 else
1983 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1984
d9fdaafb 1985 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
4ce001ab 1986 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1987 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1988 return connector_status_connected;
4ce001ab
DA		 1989 }
1990 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1991 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1992 return connector_status_connected;
4ce001ab
DA		 1993 }
1994 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1995 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1996 return connector_status_connected;
4ce001ab
DA		 1997 }
1998 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1999 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2000 return connector_status_connected; /* CTV */
2001 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2002 return connector_status_connected; /* STV */
2003 }
2004 return connector_status_disconnected;
2005}
2006
2007static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2008{
267364ac 2009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
fb939dfc 2010 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
267364ac 2011
eac4dff6
AD		 2012 if ((radeon_encoder->active_device &
2013 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2014 radeon_encoder_is_dp_bridge(encoder)) {
267364ac
AD		 2015 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2016 if (dig)
2017 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2018 }
2019
771fe6b9
JG		 2020 radeon_atom_output_lock(encoder, true);
2021 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
267364ac 2022
fb939dfc
AD		 2023 if (connector) {
2024 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
4e633939
AD		 2025
2026 /* select the clock/data port if it uses a router */
fb939dfc
AD		 2027 if (radeon_connector->router.cd_valid)
2028 radeon_router_select_cd_port(radeon_connector);
4e633939
AD		 2029
2030 /* turn eDP panel on for mode set */
2031 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2032 atombios_set_edp_panel_power(connector,
2033 ATOM_TRANSMITTER_ACTION_POWER_ON);
fb939dfc
AD		 2034 }
2035
267364ac
AD		 2036 /* this is needed for the pll/ss setup to work correctly in some cases */
2037 atombios_set_encoder_crtc_source(encoder);
771fe6b9
JG		 2038}
2039
2040static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2041{
2042 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2043 radeon_atom_output_lock(encoder, false);
2044}
2045
4ce001ab
DA		 2046static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2047{
aa961391
AD		 2048 struct drm_device *dev = encoder->dev;
2049 struct radeon_device *rdev = dev->dev_private;
4ce001ab 2050 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f28cf339 2051 struct radeon_encoder_atom_dig *dig;
a0ae5864
AD		 2052
2053 /* check for pre-DCE3 cards with shared encoders;
2054 * can't really use the links individually, so don't disable
2055 * the encoder if it's in use by another connector
2056 */
2057 if (!ASIC_IS_DCE3(rdev)) {
2058 struct drm_encoder *other_encoder;
2059 struct radeon_encoder *other_radeon_encoder;
2060
2061 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2062 other_radeon_encoder = to_radeon_encoder(other_encoder);
2063 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2064 drm_helper_encoder_in_use(other_encoder))
2065 goto disable_done;
2066 }
2067 }
2068
4ce001ab 2069 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
f28cf339 2070
aa961391
AD		 2071 switch (radeon_encoder->encoder_id) {
2072 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2073 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2074 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2075 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2076 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2077 break;
2078 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2079 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2081 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2082 if (ASIC_IS_DCE4(rdev))
2083 /* disable the transmitter */
2084 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2085 else {
2086 /* disable the encoder and transmitter */
2087 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
558e27db 2088 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
aa961391
AD		 2089 }
2090 break;
2091 case ENCODER_OBJECT_ID_INTERNAL_DDI:
aa961391
AD		 2092 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2093 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
99999aaa 2094 atombios_dvo_setup(encoder, ATOM_DISABLE);
aa961391
AD		 2095 break;
2096 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2097 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2098 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2099 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2100 atombios_dac_setup(encoder, ATOM_DISABLE);
8bf3aae6 2101 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
aa961391
AD		 2102 atombios_tv_setup(encoder, ATOM_DISABLE);
2103 break;
2104 }
2105
a0ae5864 2106disable_done:
f28cf339 2107 if (radeon_encoder_is_digital(encoder)) {
2cd6218c
RM		 2108 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2109 r600_hdmi_disable(encoder);
f28cf339
DA		 2110 dig = radeon_encoder->enc_priv;
2111 dig->dig_encoder = -1;
2112 }
4ce001ab
DA		 2113 radeon_encoder->active_device = 0;
2114}
2115
3e4b9982
AD		 2116/* these are handled by the primary encoders */
2117static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2118{
2119
2120}
2121
2122static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2123{
2124
2125}
2126
2127static void
2128radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2129 struct drm_display_mode *mode,
2130 struct drm_display_mode *adjusted_mode)
2131{
2132
2133}
2134
2135static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2136{
2137
2138}
2139
2140static void
2141radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2142{
2143
2144}
2145
2146static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2147 struct drm_display_mode *mode,
2148 struct drm_display_mode *adjusted_mode)
2149{
2150 return true;
2151}
2152
2153static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2154 .dpms = radeon_atom_ext_dpms,
2155 .mode_fixup = radeon_atom_ext_mode_fixup,
2156 .prepare = radeon_atom_ext_prepare,
2157 .mode_set = radeon_atom_ext_mode_set,
2158 .commit = radeon_atom_ext_commit,
2159 .disable = radeon_atom_ext_disable,
2160 /* no detect for TMDS/LVDS yet */
2161};
2162
771fe6b9
JG		 2163static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2164 .dpms = radeon_atom_encoder_dpms,
2165 .mode_fixup = radeon_atom_mode_fixup,
2166 .prepare = radeon_atom_encoder_prepare,
2167 .mode_set = radeon_atom_encoder_mode_set,
2168 .commit = radeon_atom_encoder_commit,
4ce001ab 2169 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 2170 /* no detect for TMDS/LVDS yet */
2171};
2172
2173static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2174 .dpms = radeon_atom_encoder_dpms,
2175 .mode_fixup = radeon_atom_mode_fixup,
2176 .prepare = radeon_atom_encoder_prepare,
2177 .mode_set = radeon_atom_encoder_mode_set,
2178 .commit = radeon_atom_encoder_commit,
2179 .detect = radeon_atom_dac_detect,
2180};
2181
2182void radeon_enc_destroy(struct drm_encoder *encoder)
2183{
2184 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2185 kfree(radeon_encoder->enc_priv);
2186 drm_encoder_cleanup(encoder);
2187 kfree(radeon_encoder);
2188}
2189
2190static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2191 .destroy = radeon_enc_destroy,
2192};
2193
4ce001ab
DA		 2194struct radeon_encoder_atom_dac *
2195radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2196{
affd8589
AD		 2197 struct drm_device *dev = radeon_encoder->base.dev;
2198 struct radeon_device *rdev = dev->dev_private;
4ce001ab
DA		 2199 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2200
2201 if (!dac)
2202 return NULL;
2203
affd8589 2204 dac->tv_std = radeon_atombios_get_tv_info(rdev);
4ce001ab
DA		 2205 return dac;
2206}
2207
771fe6b9
JG		 2208struct radeon_encoder_atom_dig *
2209radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2210{
5137ee94 2211 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9
JG		 2212 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2213
2214 if (!dig)
2215 return NULL;
2216
2217 /* coherent mode by default */
2218 dig->coherent_mode = true;
f28cf339 2219 dig->dig_encoder = -1;
771fe6b9 2220
5137ee94
AD		 2221 if (encoder_enum == 2)
2222 dig->linkb = true;
2223 else
2224 dig->linkb = false;
2225
771fe6b9
JG		 2226 return dig;
2227}
2228
2229void
36868bda
AD		 2230radeon_add_atom_encoder(struct drm_device *dev,
2231 uint32_t encoder_enum,
2232 uint32_t supported_device,
2233 u16 caps)
771fe6b9 2234{
dfee5614 2235 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 2236 struct drm_encoder *encoder;
2237 struct radeon_encoder *radeon_encoder;
2238
2239 /* see if we already added it */
2240 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2241 radeon_encoder = to_radeon_encoder(encoder);
5137ee94 2242 if (radeon_encoder->encoder_enum == encoder_enum) {
771fe6b9
JG		 2243 radeon_encoder->devices |= supported_device;
2244 return;
2245 }
2246
2247 }
2248
2249 /* add a new one */
2250 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2251 if (!radeon_encoder)
2252 return;
2253
2254 encoder = &radeon_encoder->base;
bcc1c2a1
AD		 2255 switch (rdev->num_crtc) {
2256 case 1:
dfee5614 2257 encoder->possible_crtcs = 0x1;
bcc1c2a1
AD		 2258 break;
2259 case 2:
2260 default:
dfee5614 2261 encoder->possible_crtcs = 0x3;
bcc1c2a1
AD		 2262 break;
2263 case 6:
2264 encoder->possible_crtcs = 0x3f;
2265 break;
2266 }
771fe6b9
JG		 2267
2268 radeon_encoder->enc_priv = NULL;
2269
5137ee94
AD		 2270 radeon_encoder->encoder_enum = encoder_enum;
2271 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
771fe6b9 2272 radeon_encoder->devices = supported_device;
c93bb85b 2273 radeon_encoder->rmx_type = RMX_OFF;
5b1714d3 2274 radeon_encoder->underscan_type = UNDERSCAN_OFF;
3e4b9982 2275 radeon_encoder->is_ext_encoder = false;
36868bda 2276 radeon_encoder->caps = caps;
771fe6b9
JG		 2277
2278 switch (radeon_encoder->encoder_id) {
2279 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2280 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2281 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2282 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2283 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2284 radeon_encoder->rmx_type = RMX_FULL;
2285 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2286 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2287 } else {
2288 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2289 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2290 }
2291 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2292 break;
2293 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2294 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
affd8589 2295 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 2296 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2297 break;
2298 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2299 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2301 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 2302 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 2303 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2304 break;
2305 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2306 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2307 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2309 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 2312 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2313 radeon_encoder->rmx_type = RMX_FULL;
2314 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2315 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
3e4b9982
AD		 2316 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2317 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2318 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
60d15f55
AD		 2319 } else {
2320 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2321 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2322 }
771fe6b9
JG		 2323 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2324 break;
3e4b9982
AD		 2325 case ENCODER_OBJECT_ID_SI170B:
2326 case ENCODER_OBJECT_ID_CH7303:
2327 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2328 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2329 case ENCODER_OBJECT_ID_TITFP513:
2330 case ENCODER_OBJECT_ID_VT1623:
2331 case ENCODER_OBJECT_ID_HDMI_SI1930:
bf982ebf
AD		 2332 case ENCODER_OBJECT_ID_TRAVIS:
2333 case ENCODER_OBJECT_ID_NUTMEG:
3e4b9982
AD		 2334 /* these are handled by the primary encoders */
2335 radeon_encoder->is_ext_encoder = true;
2336 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2337 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2338 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2339 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2340 else
2341 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2342 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2343 break;
771fe6b9
JG		 2344 }
2345}
Linux kernel - Deliverables
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