Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
771fe6b9 | 26 | #include <linux/module.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
771fe6b9 | 28 | #include <linux/fb.h> |
771fe6b9 | 29 | |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
34 | #include "radeon.h" |
35 | ||
760285e7 | 36 | #include <drm/drm_fb_helper.h> |
785b93ef | 37 | |
6a9ee8af DA |
38 | #include <linux/vga_switcheroo.h> |
39 | ||
38651674 | 40 | /* object hierarchy - |
3cf8bb1a JG |
41 | * this contains a helper + a radeon fb |
42 | * the helper contains a pointer to radeon framebuffer baseclass. | |
43 | */ | |
8be48d92 | 44 | struct radeon_fbdev { |
785b93ef | 45 | struct drm_fb_helper helper; |
38651674 | 46 | struct radeon_framebuffer rfb; |
38651674 | 47 | struct radeon_device *rdev; |
771fe6b9 JG |
48 | }; |
49 | ||
771fe6b9 JG |
50 | static struct fb_ops radeonfb_ops = { |
51 | .owner = THIS_MODULE, | |
c88f9f0c | 52 | .fb_check_var = drm_fb_helper_check_var, |
0c6dadbe | 53 | .fb_set_par = drm_fb_helper_set_par, |
00450052 AT |
54 | .fb_fillrect = drm_fb_helper_cfb_fillrect, |
55 | .fb_copyarea = drm_fb_helper_cfb_copyarea, | |
56 | .fb_imageblit = drm_fb_helper_cfb_imageblit, | |
785b93ef DA |
57 | .fb_pan_display = drm_fb_helper_pan_display, |
58 | .fb_blank = drm_fb_helper_blank, | |
068143d3 | 59 | .fb_setcmap = drm_fb_helper_setcmap, |
4dd19b0d CB |
60 | .fb_debug_enter = drm_fb_helper_debug_enter, |
61 | .fb_debug_leave = drm_fb_helper_debug_leave, | |
771fe6b9 JG |
62 | }; |
63 | ||
771fe6b9 | 64 | |
ff72145b | 65 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
771fe6b9 JG |
66 | { |
67 | int aligned = width; | |
e024e110 | 68 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
771fe6b9 JG |
69 | int pitch_mask = 0; |
70 | ||
71 | switch (bpp / 8) { | |
72 | case 1: | |
73 | pitch_mask = align_large ? 255 : 127; | |
74 | break; | |
75 | case 2: | |
76 | pitch_mask = align_large ? 127 : 31; | |
77 | break; | |
78 | case 3: | |
79 | case 4: | |
80 | pitch_mask = align_large ? 63 : 15; | |
81 | break; | |
82 | } | |
83 | ||
84 | aligned += pitch_mask; | |
85 | aligned &= ~pitch_mask; | |
86 | return aligned; | |
87 | } | |
88 | ||
8be48d92 | 89 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
771fe6b9 | 90 | { |
7e4d15d9 | 91 | struct radeon_bo *rbo = gem_to_radeon_bo(gobj); |
8be48d92 DA |
92 | int ret; |
93 | ||
94 | ret = radeon_bo_reserve(rbo, false); | |
95 | if (likely(ret == 0)) { | |
96 | radeon_bo_kunmap(rbo); | |
29d08b3e | 97 | radeon_bo_unpin(rbo); |
8be48d92 DA |
98 | radeon_bo_unreserve(rbo); |
99 | } | |
100 | drm_gem_object_unreference_unlocked(gobj); | |
101 | } | |
785b93ef | 102 | |
8be48d92 | 103 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, |
308e5bcb | 104 | struct drm_mode_fb_cmd2 *mode_cmd, |
8be48d92 | 105 | struct drm_gem_object **gobj_p) |
771fe6b9 | 106 | { |
8be48d92 | 107 | struct radeon_device *rdev = rfbdev->rdev; |
771fe6b9 | 108 | struct drm_gem_object *gobj = NULL; |
4c788679 | 109 | struct radeon_bo *rbo = NULL; |
e024e110 | 110 | bool fb_tiled = false; /* useful for testing */ |
c88f9f0c | 111 | u32 tiling_flags = 0; |
8be48d92 DA |
112 | int ret; |
113 | int aligned_size, size; | |
e40b6fc8 | 114 | int height = mode_cmd->height; |
308e5bcb JB |
115 | u32 bpp, depth; |
116 | ||
248dbc23 | 117 | drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); |
771fe6b9 | 118 | |
771fe6b9 | 119 | /* need to align pitch with crtc limits */ |
308e5bcb JB |
120 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, |
121 | fb_tiled) * ((bpp + 1) / 8); | |
771fe6b9 | 122 | |
e40b6fc8 DA |
123 | if (rdev->family >= CHIP_R600) |
124 | height = ALIGN(mode_cmd->height, 8); | |
308e5bcb | 125 | size = mode_cmd->pitches[0] * height; |
771fe6b9 | 126 | aligned_size = ALIGN(size, PAGE_SIZE); |
771fe6b9 | 127 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
8be48d92 | 128 | RADEON_GEM_DOMAIN_VRAM, |
ed5cb43f | 129 | 0, true, &gobj); |
771fe6b9 | 130 | if (ret) { |
8be48d92 DA |
131 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
132 | aligned_size); | |
133 | return -ENOMEM; | |
771fe6b9 | 134 | } |
7e4d15d9 | 135 | rbo = gem_to_radeon_bo(gobj); |
771fe6b9 | 136 | |
e024e110 | 137 | if (fb_tiled) |
c88f9f0c MD |
138 | tiling_flags = RADEON_TILING_MACRO; |
139 | ||
140 | #ifdef __BIG_ENDIAN | |
435ddd92 | 141 | switch (bpp) { |
c88f9f0c MD |
142 | case 32: |
143 | tiling_flags |= RADEON_TILING_SWAP_32BIT; | |
144 | break; | |
145 | case 16: | |
146 | tiling_flags |= RADEON_TILING_SWAP_16BIT; | |
147 | default: | |
148 | break; | |
149 | } | |
150 | #endif | |
151 | ||
4c788679 JG |
152 | if (tiling_flags) { |
153 | ret = radeon_bo_set_tiling_flags(rbo, | |
8be48d92 | 154 | tiling_flags | RADEON_TILING_SURFACE, |
308e5bcb | 155 | mode_cmd->pitches[0]); |
4c788679 JG |
156 | if (ret) |
157 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); | |
158 | } | |
8be48d92 | 159 | |
38651674 | 160 | |
4c788679 JG |
161 | ret = radeon_bo_reserve(rbo, false); |
162 | if (unlikely(ret != 0)) | |
163 | goto out_unref; | |
0349af70 MD |
164 | /* Only 27 bit offset for legacy CRTC */ |
165 | ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, | |
166 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, | |
167 | NULL); | |
4c788679 JG |
168 | if (ret) { |
169 | radeon_bo_unreserve(rbo); | |
170 | goto out_unref; | |
171 | } | |
172 | if (fb_tiled) | |
173 | radeon_bo_check_tiling(rbo, 0, 0); | |
8be48d92 | 174 | ret = radeon_bo_kmap(rbo, NULL); |
4c788679 | 175 | radeon_bo_unreserve(rbo); |
f92e93eb | 176 | if (ret) { |
f92e93eb JG |
177 | goto out_unref; |
178 | } | |
771fe6b9 | 179 | |
8be48d92 DA |
180 | *gobj_p = gobj; |
181 | return 0; | |
182 | out_unref: | |
183 | radeonfb_destroy_pinned_object(gobj); | |
184 | *gobj_p = NULL; | |
185 | return ret; | |
186 | } | |
187 | ||
cd5428a5 | 188 | static int radeonfb_create(struct drm_fb_helper *helper, |
8be48d92 DA |
189 | struct drm_fb_helper_surface_size *sizes) |
190 | { | |
a1d0280e FF |
191 | struct radeon_fbdev *rfbdev = |
192 | container_of(helper, struct radeon_fbdev, helper); | |
8be48d92 DA |
193 | struct radeon_device *rdev = rfbdev->rdev; |
194 | struct fb_info *info; | |
195 | struct drm_framebuffer *fb = NULL; | |
308e5bcb | 196 | struct drm_mode_fb_cmd2 mode_cmd; |
8be48d92 DA |
197 | struct drm_gem_object *gobj = NULL; |
198 | struct radeon_bo *rbo = NULL; | |
8be48d92 DA |
199 | int ret; |
200 | unsigned long tmp; | |
201 | ||
202 | mode_cmd.width = sizes->surface_width; | |
203 | mode_cmd.height = sizes->surface_height; | |
204 | ||
205 | /* avivo can't scanout real 24bpp */ | |
206 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) | |
207 | sizes->surface_bpp = 32; | |
208 | ||
308e5bcb JB |
209 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, |
210 | sizes->surface_depth); | |
771fe6b9 | 211 | |
8be48d92 | 212 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); |
aaefcd42 DA |
213 | if (ret) { |
214 | DRM_ERROR("failed to create fbcon object %d\n", ret); | |
215 | return ret; | |
216 | } | |
217 | ||
7e4d15d9 | 218 | rbo = gem_to_radeon_bo(gobj); |
771fe6b9 | 219 | |
8be48d92 | 220 | /* okay we have an object now allocate the framebuffer */ |
00450052 AT |
221 | info = drm_fb_helper_alloc_fbi(helper); |
222 | if (IS_ERR(info)) { | |
223 | ret = PTR_ERR(info); | |
771fe6b9 JG |
224 | goto out_unref; |
225 | } | |
785b93ef | 226 | |
8be48d92 | 227 | info->par = rfbdev; |
d57c0edf | 228 | info->skip_vt_switch = true; |
771fe6b9 | 229 | |
aaefcd42 DA |
230 | ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); |
231 | if (ret) { | |
8b513d0c | 232 | DRM_ERROR("failed to initialize framebuffer %d\n", ret); |
00450052 | 233 | goto out_destroy_fbi; |
aaefcd42 | 234 | } |
8be48d92 | 235 | |
38651674 DA |
236 | fb = &rfbdev->rfb.base; |
237 | ||
238 | /* setup helper */ | |
239 | rfbdev->helper.fb = fb; | |
38651674 | 240 | |
8be48d92 | 241 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
bf8e828b | 242 | |
771fe6b9 | 243 | strcpy(info->fix.id, "radeondrmfb"); |
785b93ef | 244 | |
01f2c773 | 245 | drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); |
3632ef89 | 246 | |
8fd4bd22 | 247 | info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; |
771fe6b9 | 248 | info->fbops = &radeonfb_ops; |
785b93ef | 249 | |
8be48d92 | 250 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
f92e93eb | 251 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
8be48d92 DA |
252 | info->fix.smem_len = radeon_bo_size(rbo); |
253 | info->screen_base = rbo->kptr; | |
254 | info->screen_size = radeon_bo_size(rbo); | |
785b93ef | 255 | |
38651674 | 256 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
ed8f0d9e DA |
257 | |
258 | /* setup aperture base/size for vesafb takeover */ | |
1471ca9a | 259 | info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; |
68d30596 | 260 | info->apertures->ranges[0].size = rdev->mc.aper_size; |
ed8f0d9e | 261 | |
fb2a99e1 | 262 | /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ |
4abe3520 | 263 | |
771fe6b9 JG |
264 | if (info->screen_base == NULL) { |
265 | ret = -ENOSPC; | |
00450052 | 266 | goto out_destroy_fbi; |
4abe3520 DA |
267 | } |
268 | ||
771fe6b9 JG |
269 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
270 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); | |
8be48d92 | 271 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
771fe6b9 | 272 | DRM_INFO("fb depth is %d\n", fb->depth); |
01f2c773 | 273 | DRM_INFO(" pitch is %d\n", fb->pitches[0]); |
771fe6b9 | 274 | |
6a9ee8af | 275 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
771fe6b9 JG |
276 | return 0; |
277 | ||
00450052 AT |
278 | out_destroy_fbi: |
279 | drm_fb_helper_release_fbi(helper); | |
771fe6b9 | 280 | out_unref: |
4c788679 | 281 | if (rbo) { |
8be48d92 | 282 | |
771fe6b9 | 283 | } |
f92e93eb | 284 | if (fb && ret) { |
623fc3b7 | 285 | drm_gem_object_unreference_unlocked(gobj); |
36206361 | 286 | drm_framebuffer_unregister_private(fb); |
771fe6b9 JG |
287 | drm_framebuffer_cleanup(fb); |
288 | kfree(fb); | |
289 | } | |
771fe6b9 JG |
290 | return ret; |
291 | } | |
292 | ||
eb1f8e4f | 293 | void radeon_fb_output_poll_changed(struct radeon_device *rdev) |
771fe6b9 | 294 | { |
e5f243bd AD |
295 | if (rdev->mode_info.rfbdev) |
296 | drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); | |
771fe6b9 | 297 | } |
771fe6b9 | 298 | |
8be48d92 | 299 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
771fe6b9 | 300 | { |
38651674 | 301 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
771fe6b9 | 302 | |
00450052 AT |
303 | drm_fb_helper_unregister_fbi(&rfbdev->helper); |
304 | drm_fb_helper_release_fbi(&rfbdev->helper); | |
771fe6b9 | 305 | |
8be48d92 | 306 | if (rfb->obj) { |
29d08b3e DA |
307 | radeonfb_destroy_pinned_object(rfb->obj); |
308 | rfb->obj = NULL; | |
771fe6b9 | 309 | } |
4abe3520 | 310 | drm_fb_helper_fini(&rfbdev->helper); |
36206361 | 311 | drm_framebuffer_unregister_private(&rfb->base); |
38651674 | 312 | drm_framebuffer_cleanup(&rfb->base); |
771fe6b9 | 313 | |
771fe6b9 JG |
314 | return 0; |
315 | } | |
785b93ef | 316 | |
3a493879 | 317 | static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
4abe3520 DA |
318 | .gamma_set = radeon_crtc_fb_gamma_set, |
319 | .gamma_get = radeon_crtc_fb_gamma_get, | |
cd5428a5 | 320 | .fb_probe = radeonfb_create, |
4abe3520 | 321 | }; |
38651674 DA |
322 | |
323 | int radeon_fbdev_init(struct radeon_device *rdev) | |
324 | { | |
8be48d92 | 325 | struct radeon_fbdev *rfbdev; |
4abe3520 | 326 | int bpp_sel = 32; |
5a79395b | 327 | int ret; |
4abe3520 | 328 | |
e5f243bd AD |
329 | /* don't enable fbdev if no connectors */ |
330 | if (list_empty(&rdev->ddev->mode_config.connector_list)) | |
331 | return 0; | |
332 | ||
4abe3520 DA |
333 | /* select 8 bpp console on RN50 or 16MB cards */ |
334 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) | |
335 | bpp_sel = 8; | |
8be48d92 DA |
336 | |
337 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); | |
338 | if (!rfbdev) | |
339 | return -ENOMEM; | |
340 | ||
341 | rfbdev->rdev = rdev; | |
342 | rdev->mode_info.rfbdev = rfbdev; | |
10a23102 TR |
343 | |
344 | drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper, | |
345 | &radeon_fb_helper_funcs); | |
8be48d92 | 346 | |
5a79395b CW |
347 | ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper, |
348 | rdev->num_crtc, | |
349 | RADEONFB_CONN_LIMIT); | |
01934c2a TR |
350 | if (ret) |
351 | goto free; | |
5a79395b | 352 | |
01934c2a TR |
353 | ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper); |
354 | if (ret) | |
355 | goto fini; | |
76a39dbf DV |
356 | |
357 | /* disable all the possible outputs/crtcs before entering KMS mode */ | |
358 | drm_helper_disable_unused_functions(rdev->ddev); | |
359 | ||
01934c2a TR |
360 | ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
361 | if (ret) | |
362 | goto fini; | |
363 | ||
771fe6b9 | 364 | return 0; |
01934c2a TR |
365 | |
366 | fini: | |
367 | drm_fb_helper_fini(&rfbdev->helper); | |
368 | free: | |
369 | kfree(rfbdev); | |
370 | return ret; | |
38651674 DA |
371 | } |
372 | ||
373 | void radeon_fbdev_fini(struct radeon_device *rdev) | |
374 | { | |
8be48d92 DA |
375 | if (!rdev->mode_info.rfbdev) |
376 | return; | |
377 | ||
38651674 | 378 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
8be48d92 | 379 | kfree(rdev->mode_info.rfbdev); |
38651674 DA |
380 | rdev->mode_info.rfbdev = NULL; |
381 | } | |
382 | ||
383 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) | |
384 | { | |
e5f243bd AD |
385 | if (rdev->mode_info.rfbdev) |
386 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); | |
38651674 DA |
387 | } |
388 | ||
38651674 DA |
389 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) |
390 | { | |
e5f243bd AD |
391 | if (!rdev->mode_info.rfbdev) |
392 | return false; | |
393 | ||
7e4d15d9 | 394 | if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj)) |
38651674 DA |
395 | return true; |
396 | return false; | |
771fe6b9 | 397 | } |
bb26270e DA |
398 | |
399 | void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector) | |
400 | { | |
e5f243bd AD |
401 | if (rdev->mode_info.rfbdev) |
402 | drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector); | |
bb26270e DA |
403 | } |
404 | ||
405 | void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector) | |
406 | { | |
e5f243bd AD |
407 | if (rdev->mode_info.rfbdev) |
408 | drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector); | |
bb26270e | 409 | } |
8c70e1cd AD |
410 | |
411 | void radeon_fbdev_restore_mode(struct radeon_device *rdev) | |
412 | { | |
413 | struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev; | |
414 | struct drm_fb_helper *fb_helper; | |
415 | int ret; | |
416 | ||
417 | if (!rfbdev) | |
418 | return; | |
419 | ||
420 | fb_helper = &rfbdev->helper; | |
421 | ||
422 | ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); | |
423 | if (ret) | |
424 | DRM_DEBUG("failed to restore crtc mode\n"); | |
425 | } |