[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
    /*
     *  Modularization
     */

#include <linux/module.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

struct radeon_fb_device {
	struct drm_fb_helper helper;
	struct radeon_framebuffer	*rfb;
	struct radeon_device		*rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};

/**
 * Currently it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
 *
 */
int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct fb_info *info;
	struct drm_framebuffer *fb;
	struct drm_display_mode *mode = crtc->desired_mode;

	fb = crtc->fb;
	if (fb == NULL) {
		return 1;
	}
	info = fb->fbdev;
	if (info == NULL) {
		return 1;
	}
	if (mode == NULL) {
		return 1;
	}
	info->var.xres = mode->hdisplay;
	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	info->var.left_margin = mode->htotal - mode->hsync_end;
	info->var.yres = mode->vdisplay;
	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	/* avoid overflow */
	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;

	return 0;
}
EXPORT_SYMBOL(radeonfb_resize);

static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
};

int radeonfb_create(struct drm_device *dev,
		    uint32_t fb_width, uint32_t fb_height,
		    uint32_t surface_width, uint32_t surface_height,
		    uint32_t surface_depth, uint32_t surface_bpp,
		    struct drm_framebuffer **fb_p)
{
	struct radeon_device *rdev = dev->dev_private;
	struct fb_info *info;
	struct radeon_fb_device *rfbdev;
	struct drm_framebuffer *fb = NULL;
	struct radeon_framebuffer *rfb;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int size, aligned_size, ret;
	u64 fb_gpuaddr;
	void *fbptr = NULL;
	unsigned long tmp;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;

	mode_cmd.width = surface_width;
	mode_cmd.height = surface_height;

	/* avivo can't scanout real 24bpp */
	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		surface_bpp = 32;

	mode_cmd.bpp = surface_bpp;
	/* need to align pitch with crtc limits */
	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
	mode_cmd.depth = surface_depth;

	size = mode_cmd.pitch * mode_cmd.height;
	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = radeon_gem_object_create(rdev, aligned_size, 0,
			RADEON_GEM_DOMAIN_VRAM,
			false, ttm_bo_type_kernel,
			&gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
		       surface_width, surface_height);
		ret = -ENOMEM;
		goto out;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd.bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
					tiling_flags | RADEON_TILING_SURFACE,
					mode_cmd.pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}
	mutex_lock(&rdev->ddev->struct_mutex);
	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	if (fb == NULL) {
		DRM_ERROR("failed to allocate fb.\n");
		ret = -ENOMEM;
		goto out_unref;
	}
	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, &fbptr);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);

	*fb_p = fb;
	rfb = to_radeon_framebuffer(fb);
	rdev->fbdev_rfb = rfb;
	rdev->fbdev_rbo = rbo;

	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	rdev->fbdev_info = info;
	rfbdev = info->par;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	rfbdev->helper.dev = dev;
	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
					    RADEONFB_CONN_LIMIT);
	if (ret)
		goto out_unref;

	memset_io(fbptr, 0x0, aligned_size);

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = fb_gpuaddr - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = size;
	info->screen_base = fbptr;
	info->screen_size = size;

	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)size);
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	fb->fbdev = info;
	rfbdev->rfb = rfb;
	rfbdev->rdev = rdev;

	mutex_unlock(&rdev->ddev->struct_mutex);
	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {
		ret = radeon_bo_reserve(rbo, false);
		if (likely(ret == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unreserve(rbo);
		}
	}
	if (fb && ret) {
		list_del(&fb->filp_head);
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	drm_gem_object_unreference(gobj);
	mutex_unlock(&rdev->ddev->struct_mutex);
out:
	return ret;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

int radeonfb_probe(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int bpp_sel = 32;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create);
}

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	struct radeon_bo *rbo;
	int r;

	if (!fb) {
		return -EINVAL;
	}
	info = fb->fbdev;
	if (info) {
		struct radeon_fb_device *rfbdev = info->par;
		rbo = rfb->obj->driver_private;
		unregister_framebuffer(info);
		r = radeon_bo_reserve(rbo, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unpin(rbo);
			radeon_bo_unreserve(rbo);
		}
		drm_fb_helper_free(&rfbdev->helper);
		framebuffer_release(info);
	}

	printk(KERN_INFO "unregistered panic notifier\n");

	return 0;
}
EXPORT_SYMBOL(radeonfb_remove);
MODULE_LICENSE("GPL");
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	/*
	27	* Modularization
	28	*/
	29
	30	#include <linux/module.h>
771fe6b9	31	#include <linux/fb.h>
771fe6b9 JG	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_crtc.h"
	36	#include "drm_crtc_helper.h"
	37	#include "radeon_drm.h"
	38	#include "radeon.h"
	39
785b93ef DA	40	#include "drm_fb_helper.h"
785b93ef DA	41
6a9ee8af DA	42	#include <linux/vga_switcheroo.h>
6a9ee8af DA	43
771fe6b9	44	struct radeon_fb_device {
785b93ef	45	struct drm_fb_helper helper;
771fe6b9	46	struct radeon_framebuffer *rfb;
785b93ef	47	struct radeon_device *rdev;
771fe6b9 JG	48	};
771fe6b9 JG	49
771fe6b9 JG	50	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	51	.owner = THIS_MODULE,
c88f9f0c	52	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	53	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	54	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	55	.fb_fillrect = cfb_fillrect,
	56	.fb_copyarea = cfb_copyarea,
	57	.fb_imageblit = cfb_imageblit,
785b93ef DA	58	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	59	.fb_blank = drm_fb_helper_blank,
068143d3	60	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	61	};
	62
	63	/**
af901ca1	64	* Currently it is assumed that the old framebuffer is reused.
771fe6b9 JG	65	*
	66	* LOCKING
	67	* caller should hold the mode config lock.
	68	*
	69	*/
	70	int radeonfb_resize(struct drm_device dev, struct drm_crtc crtc)
	71	{
	72	struct fb_info *info;
	73	struct drm_framebuffer *fb;
	74	struct drm_display_mode *mode = crtc->desired_mode;
	75
	76	fb = crtc->fb;
	77	if (fb == NULL) {
	78	return 1;
	79	}
	80	info = fb->fbdev;
	81	if (info == NULL) {
	82	return 1;
	83	}
	84	if (mode == NULL) {
	85	return 1;
	86	}
	87	info->var.xres = mode->hdisplay;
	88	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	89	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	90	info->var.left_margin = mode->htotal - mode->hsync_end;
	91	info->var.yres = mode->vdisplay;
	92	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	93	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	94	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	95	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	96	/* avoid overflow */
	97	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
	98
	99	return 0;
	100	}
	101	EXPORT_SYMBOL(radeonfb_resize);
	102
e024e110	103	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	104	{
771fe6b9 JG	105	int aligned = width;
e024e110	106	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	107	int pitch_mask = 0;
	108
	109	switch (bpp / 8) {
	110	case 1:
	111	pitch_mask = align_large ? 255 : 127;
	112	break;
	113	case 2:
	114	pitch_mask = align_large ? 127 : 31;
	115	break;
	116	case 3:
	117	case 4:
	118	pitch_mask = align_large ? 63 : 15;
	119	break;
	120	}
	121
	122	aligned += pitch_mask;
	123	aligned &= ~pitch_mask;
	124	return aligned;
	125	}
	126
785b93ef DA	127	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
785b93ef DA	128	.gamma_set = radeon_crtc_fb_gamma_set,
b8c00ac5	129	.gamma_get = radeon_crtc_fb_gamma_get,
785b93ef DA	130	};
	131
	132	int radeonfb_create(struct drm_device *dev,
771fe6b9 JG	133	uint32_t fb_width, uint32_t fb_height,
771fe6b9 JG	134	uint32_t surface_width, uint32_t surface_height,
d50ba256	135	uint32_t surface_depth, uint32_t surface_bpp,
785b93ef	136	struct drm_framebuffer **fb_p)
771fe6b9	137	{
785b93ef	138	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	139	struct fb_info *info;
771fe6b9 JG	140	struct radeon_fb_device *rfbdev;
f92e93eb	141	struct drm_framebuffer *fb = NULL;
771fe6b9 JG	142	struct radeon_framebuffer *rfb;
	143	struct drm_mode_fb_cmd mode_cmd;
	144	struct drm_gem_object *gobj = NULL;
4c788679	145	struct radeon_bo *rbo = NULL;
771fe6b9 JG	146	struct device *device = &rdev->pdev->dev;
771fe6b9 JG	147	int size, aligned_size, ret;
f92e93eb	148	u64 fb_gpuaddr;
771fe6b9	149	void *fbptr = NULL;
f92e93eb	150	unsigned long tmp;
e024e110	151	bool fb_tiled = false; /* useful for testing */
c88f9f0c	152	u32 tiling_flags = 0;
771fe6b9 JG	153
	154	mode_cmd.width = surface_width;
	155	mode_cmd.height = surface_height;
b8c00ac5 DA	156
	157	/* avivo can't scanout real 24bpp */
	158	if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	159	surface_bpp = 32;
	160
d50ba256	161	mode_cmd.bpp = surface_bpp;
771fe6b9	162	/* need to align pitch with crtc limits */
e024e110	163	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
d50ba256	164	mode_cmd.depth = surface_depth;
771fe6b9 JG	165
	166	size = mode_cmd.pitch * mode_cmd.height;
	167	aligned_size = ALIGN(size, PAGE_SIZE);
	168
	169	ret = radeon_gem_object_create(rdev, aligned_size, 0,
f92e93eb JG	170	RADEON_GEM_DOMAIN_VRAM,
f92e93eb JG	171	false, ttm_bo_type_kernel,
4c788679	172	&gobj);
771fe6b9	173	if (ret) {
f92e93eb JG	174	printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
f92e93eb JG	175	surface_width, surface_height);
771fe6b9 JG	176	ret = -ENOMEM;
	177	goto out;
	178	}
4c788679	179	rbo = gobj->driver_private;
771fe6b9	180
e024e110	181	if (fb_tiled)
c88f9f0c MD	182	tiling_flags = RADEON_TILING_MACRO;
	183
	184	#ifdef __BIG_ENDIAN
	185	switch (mode_cmd.bpp) {
	186	case 32:
	187	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	188	break;
	189	case 16:
	190	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	191	default:
	192	break;
	193	}
	194	#endif
	195
4c788679 JG	196	if (tiling_flags) {
	197	ret = radeon_bo_set_tiling_flags(rbo,
	198	tiling_flags \| RADEON_TILING_SURFACE,
	199	mode_cmd.pitch);
	200	if (ret)
	201	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	202	}
771fe6b9 JG	203	mutex_lock(&rdev->ddev->struct_mutex);
	204	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	205	if (fb == NULL) {
	206	DRM_ERROR("failed to allocate fb.\n");
	207	ret = -ENOMEM;
	208	goto out_unref;
	209	}
4c788679 JG	210	ret = radeon_bo_reserve(rbo, false);
	211	if (unlikely(ret != 0))
	212	goto out_unref;
	213	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	214	if (ret) {
	215	radeon_bo_unreserve(rbo);
	216	goto out_unref;
	217	}
	218	if (fb_tiled)
	219	radeon_bo_check_tiling(rbo, 0, 0);
	220	ret = radeon_bo_kmap(rbo, &fbptr);
	221	radeon_bo_unreserve(rbo);
f92e93eb	222	if (ret) {
f92e93eb JG	223	goto out_unref;
f92e93eb JG	224	}
771fe6b9 JG	225
	226	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
	227
785b93ef	228	*fb_p = fb;
771fe6b9	229	rfb = to_radeon_framebuffer(fb);
771fe6b9	230	rdev->fbdev_rfb = rfb;
4c788679	231	rdev->fbdev_rbo = rbo;
771fe6b9 JG	232
	233	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	234	if (info == NULL) {
	235	ret = -ENOMEM;
	236	goto out_unref;
	237	}
785b93ef	238
2f9a60d7	239	rdev->fbdev_info = info;
771fe6b9	240	rfbdev = info->par;
785b93ef DA	241	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
785b93ef DA	242	rfbdev->helper.dev = dev;
18917b60	243	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
785b93ef DA	244	RADEONFB_CONN_LIMIT);
	245	if (ret)
	246	goto out_unref;
771fe6b9	247
6719fc66	248	memset_io(fbptr, 0x0, aligned_size);
bf8e828b	249
771fe6b9	250	strcpy(info->fix.id, "radeondrmfb");
785b93ef	251
068143d3	252	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	253
771fe6b9 JG	254	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	255	info->fbops = &radeonfb_ops;
785b93ef	256
d594e46a	257	tmp = fb_gpuaddr - rdev->mc.vram_start;
f92e93eb	258	info->fix.smem_start = rdev->mc.aper_base + tmp;
771fe6b9 JG	259	info->fix.smem_len = size;
	260	info->screen_base = fbptr;
	261	info->screen_size = size;
785b93ef DA	262
785b93ef DA	263	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
ed8f0d9e DA	264
	265	/* setup aperture base/size for vesafb takeover */
	266	info->aperture_base = rdev->ddev->mode_config.fb_base;
	267	info->aperture_size = rdev->mc.real_vram_size;
	268
696d4df1 MD	269	info->fix.mmio_start = 0;
696d4df1 MD	270	info->fix.mmio_len = 0;
771fe6b9 JG	271	info->pixmap.size = 64*1024;
	272	info->pixmap.buf_align = 8;
	273	info->pixmap.access_align = 32;
	274	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	275	info->pixmap.scan_align = 1;
	276	if (info->screen_base == NULL) {
	277	ret = -ENOSPC;
	278	goto out_unref;
	279	}
	280	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	281	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
	282	DRM_INFO("size %lu\n", (unsigned long)size);
	283	DRM_INFO("fb depth is %d\n", fb->depth);
	284	DRM_INFO(" pitch is %d\n", fb->pitch);
	285
771fe6b9 JG	286	fb->fbdev = info;
	287	rfbdev->rfb = rfb;
	288	rfbdev->rdev = rdev;
	289
	290	mutex_unlock(&rdev->ddev->struct_mutex);
6a9ee8af	291	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	292	return 0;
	293
	294	out_unref:
4c788679 JG	295	if (rbo) {
	296	ret = radeon_bo_reserve(rbo, false);
	297	if (likely(ret == 0)) {
	298	radeon_bo_kunmap(rbo);
	299	radeon_bo_unreserve(rbo);
	300	}
771fe6b9	301	}
f92e93eb	302	if (fb && ret) {
771fe6b9 JG	303	list_del(&fb->filp_head);
	304	drm_gem_object_unreference(gobj);
	305	drm_framebuffer_cleanup(fb);
	306	kfree(fb);
	307	}
	308	drm_gem_object_unreference(gobj);
	309	mutex_unlock(&rdev->ddev->struct_mutex);
	310	out:
	311	return ret;
	312	}
	313
d50ba256 DA	314	static char *mode_option;
	315	int radeon_parse_options(char *options)
	316	{
	317	char *this_opt;
	318
	319	if (!options \|\| !*options)
	320	return 0;
	321
	322	while ((this_opt = strsep(&options, ",")) != NULL) {
	323	if (!*this_opt)
	324	continue;
	325	mode_option = this_opt;
	326	}
	327	return 0;
	328	}
	329
771fe6b9 JG	330	int radeonfb_probe(struct drm_device *dev)
771fe6b9 JG	331	{
47381156 DA	332	struct radeon_device *rdev = dev->dev_private;
	333	int bpp_sel = 32;
	334
	335	/* select 8 bpp console on RN50 or 16MB cards */
	336	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	337	bpp_sel = 8;
	338
	339	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create);
771fe6b9	340	}
771fe6b9 JG	341
	342	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb)
	343	{
	344	struct fb_info *info;
	345	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
4c788679 JG	346	struct radeon_bo *rbo;
4c788679 JG	347	int r;
771fe6b9 JG	348
	349	if (!fb) {
	350	return -EINVAL;
	351	}
	352	info = fb->fbdev;
	353	if (info) {
785b93ef	354	struct radeon_fb_device *rfbdev = info->par;
4c788679	355	rbo = rfb->obj->driver_private;
771fe6b9	356	unregister_framebuffer(info);
4c788679 JG	357	r = radeon_bo_reserve(rbo, false);
	358	if (likely(r == 0)) {
	359	radeon_bo_kunmap(rbo);
	360	radeon_bo_unpin(rbo);
	361	radeon_bo_unreserve(rbo);
	362	}
785b93ef	363	drm_fb_helper_free(&rfbdev->helper);
771fe6b9 JG	364	framebuffer_release(info);
	365	}
	366
	367	printk(KERN_INFO "unregistered panic notifier\n");
785b93ef	368
771fe6b9 JG	369	return 0;
	370	}
	371	EXPORT_SYMBOL(radeonfb_remove);
	372	MODULE_LICENSE("GPL");